K7I163682B-EC200_技术文档

K7I163682B

K7I161882B

512Kx36 & 1Mx18 DDRII CIO b2 SRAM

18Mb DDRII SRAM Specification

165FBGA with Pb & Pb-Free

(RoHS compliant)

INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS,

AND IS SUBJECT TO CHANGE WITHOUT NOTICE.

NOTHING IN THIS DOCUMENT SHALL BE CONSTRUED AS GRANTING ANY LICENSE,

EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE,

TO ANY INTELLECTUAL PROPERTY RIGHTS IN SAMSUNG PRODUCTS OR TECHNOLOGY.

ALL INFORMATION IN THIS DOCUMENT IS PROVIDED

ON AS "AS IS" BASIS WITHOUT GUARANTEE OR WARRANTY OF ANY KIND.

1. For updates or additional information about Samsung products, contact your nearest Samsung office.

2. Samsung products are not intended for use in life support, critical care, medical, safety equipment, or simi-

lar applications where Product failure could result in loss of life or personal or physical harm, or any military

or defense application, or any governmental procurement to which special terms or provisions may apply.

* Samsung Electronics reserves the right to change products or specification without notice.

Rev. 5.0 July 2006

- 1 -

K7I163682B

K7I161882B

512Kx36 & 1Mx18 DDRII CIO b2 SRAM

Document Title

512Kx36-bit, 1Mx18-bit DDRII CIO b2 SRAM

Revision History

Rev. No.

History

Draft Date

Remark

Advance

Preliminary

0.0

1. Initial document.

Oct. 23. 2002

Oct. 24. 2002

0.1

1. Add the speed bin (-33, -30)

2. Delete the speed bin (-25, -13)

0.2

1. Change the Boundary scan exit order.

2. Correct the Overshoot and Undershoot timing diagram.

Preliminary

Dec. 16, 2002

0.3

0.4

1. Add the speed bin (-25)

Preliminary

Jan. 27, 2003

Mar. 20, 2003

1. Correct the JTAG ID register definition

2. Correct the AC timing parameter (delete the tKHKH Max value)

0.5

0.6

1. Change the Maximum Clock cycle time.

2. Correct the 165FBGA package ball size.

Preliminary

April. 4, 2003

1. Add the power up/down sequencing comment.

2. Update the DC current parameter (Icc and Isb).

3. Change the Max. speed bin from -33 to -30.

June. 20, 2003

0.7

1. Change the ISB1.

Preliminary

Oct. 20. 2003

Speed Bin

From

To

-30

-25

-20

-16

200

180

160

140

230

210

190

170

1.0

2.0

1. Final spec release

1. Delete the x8 Org.

Final

Oct. 31, 2003

Nov. 28, 2003

2. Delete the 300MHz speed bin

3.0

4.0

5.0

1. Add the Industrial temp. & Lead Free Package

1. Add the 300MHz speed bin

Final

Nov. 10. 2004

Mar. 29. 2006

Jul. 26 2006

1. Change Vss/SA to NC/SA in Pin Configuration

The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the

specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions on the parameters of this device. If you have any ques-

tions, please contact the SAMSUNG branch office near your office, call or contact Headquarters.

Rev. 5.0 July 2006

- 2 -

K7I163682B

K7I161882B

512Kx36 & 1Mx18 DDRII CIO b2 SRAM

512Kx36-bit, 1Mx18-bit DDRII CIO b2 SRAM

FEATURES

• 1.8V+0.1V/-0.1V Power Supply.

Part

Cycle Access

Time Time

Organization

Unit

• DLL circuitry for wide output data valid window and future fre-

quency scaling.

Number

K7I163682B-E(F)C(I)30 3.3

K7I163682B-E(F)C(I)25 4.0

K7I163682B-E(F)C(I)20 5.0

K7I163682B-E(F)C(I)16 6.0

K7I161882B-E(F)C(I)30 3.3

K7I161882B-E(F)C(I)25 4.0

K7I161882B-E(F)C(I)20 5.0

K7I161882B-E(F)C(I)16 6.0

0.45

0.50

0.45

0.50

ns

• I/O Supply Voltage 1.5V+0.1V/-0.1V for 1.5V I/O,

1.8V+0.1V/-0.1V for 1.8V I/O.

X36

• Pipelined, double-data rate operation.

• Common data input/output bus.

• HSTL I/O

• Full data coherency, providing most current data.

• Synchronous pipeline read with self timed late write.

• Registered address, control and data input/output.

• DDR(Double Data Rate) Interface on read and write ports.

• Fixed 2-bit burst for both read and write operation.

• Clock-stop supports to reduce current.

• Two input clocks(K and K) for accurate DDR timing at clock

rising edges only.

X18

* -E(F)C(I)

E(F) [Package type] : E-Pb Free, F-Pb

C(I) [Operating Temperature] : C-Commercial, I-Industrial

• Two input clocks for output data(C and C) to minimize

clock-skew and flight-time mismatches.

• Two echo clocks (CQ and CQ) to enhance output data

traceability.

• Single address bus.

• Byte write (x18, x36) function.

• Simple depth expansion with no data contention.

• Programmable output impedance.

• JTAG 1149.1 compatible test access port.

• 165FBGA(11x15 ball array) with body size of 13mmx15mm.

& Lead Free

• Operating in commercial and industrial temperature range.

FUNCTIONAL BLOCK DIAGRAM

36 (or 18)

DATA

REG

36 (or 18)

WRITE DRIVER

18

ADD REG

&

18 (or 19)

4(or 2)

(or 19)

ADDRESS

A0

BURST

LOGIC

72

36

512Kx36

(1Mx18)

MEMORY

ARRAY

36 (or 18)

DQ

(or 36)

(or 18)

LD

R/W

BWX

CTRL

LOGIC

CQ, CQ

(Echo Clock out)

K

CLK

GEN

C

SELECT OUTPUT CONTROL

Notes: 1. Numbers in ( ) are for x18 device.

DDRII SRAM and Double Data Rate comprise a new family of products developed by Cypress, Hitachi, IDT, Micron, NEC and Samsung technology.

Rev. 5.0 July 2006

- 3 -

K7I163682B

K7I161882B

512Kx36 & 1Mx18 DDRII CIO b2 SRAM

PIN CONFIGURATIONS(TOP VIEW) K7I163682B(512Kx36)

1

2

NC/SA*

DQ27

NC

DQ29

NC

DQ30

DQ31

VREF

NC

3

4

5

6

K

7

8

LD

SA

VSS

9

SA

10

NC/SA*

NC

DQ17

NC

DQ15

NC

VREF

DQ13

DQ12

NC

DQ11

NC

11

CQ

A

B

C

D

E

F

G

H

J

K

L

M

N

P

R

CQ

NC

Doff

NC

TDO

NC

R/W

SA

VSS

BW2

BW3

SA

BW1

BW0

SA

DQ18

DQ28

DQ19

DQ20

DQ21

DQ22

VDDQ

DQ32

DQ23

DQ24

DQ34

DQ25

DQ26

SA

NC

VDDQ

NC

SA

DQ8

DQ7

DQ16

DQ6

DQ5

DQ14

ZQ

DQ4

DQ3

DQ2

DQ1

DQ10

DQ0

TDI

SA0

VSS

SA

C

VSS

VDD

VSS

SA

VSS

VDD

VSS

SA

VSS

VDDQ

VSS

VDDQ

VSS

NC

DQ33

NC

DQ35

NC

VSS

SA

VSS

SA

DQ9

TMS

TCK

C

Notes : 1. * Checked No Connect(NC) pins are reserved for higher density address, i.e. 3A for 32Mb, 10A for 72Mb, 2A for 144Mb .

2. BW⁰controls write to DQ0:DQ8, BW1 controls write to DQ9:DQ17, BW2 controls write to DQ18:DQ26 and BW3 controls write to DQ27:DQ35.

PIN NAME

SYMBOL

PIN NUMBERS

DESCRIPTION

Input Clock

NOTE

K, K

C, C

CQ, CQ

Doff

SA0

SA

6B, 6A

6P, 6R

11A, 1A

1H

Input Clock for Output Data

Output Echo Clock

DLL Disable when low

Burst Count Address Inputs

Address Inputs

1

6C

9A,4B,8B,5C,7C,5N-7N,4P,5P,7P,8P,3R-5R,7R-9R

2B,3B,11B,3C,10C,11C,2D,3D,11D,3E,10E,11E,2F,3F

11F,2G,3G,11G,3J,10J,11J,3K,10K,11K,2L,3L,11L

3M,10M,11M,2N,3N,11N,3P,10P,11P

DQ0-35

Data Inputs Outputs

Read, Write Control Pin, Read active

when high

R/W

LD

4A

8A

Synchronous Load Pin, bus Cycle

sequence is to be defined when low

BW0, BW1,BW2, BW3

7B,7A,5A,5B

2H,10H

11H

Block Write Control Pin,active when low

Input Reference Voltage

Output Driver Impedance Control Input

Power Supply ( 1.8 V )

VREF

ZQ

VDD

2

5F,7F,5G,7G,5H,7H,5J,7J,5K,7K

4E,8E,4F,8F,4G,8G,3H,4H,8H,9H,4J,8J,4K,8K,4L,8L

VDDQ

Output Power Supply ( 1.5V or 1.8V )

4C,8C,4D-8D,5E-7E,6F,6G,6H,6J,6K,5L-7L,

4M-8M,4N,8N

VSS

Ground

TMS

TDI

TCK

TDO

10R

11R

2R

JTAG Test Mode Select

JTAG Test Data Input

JTAG Test Clock

1R

JTAG Test Data Output

2A,3A,10A,1B,9B,10B,1C,2C,9C,1D,9D,10D,1E,2E,9E,

1F,9F,10F,1G,9G,10G,1J,2J,9J,1K,2K,9K

NC

No Connect

3

1L,9L,10L,1M,2M,9M,1N,9N,10N,1P,2P,9P

Notes: 1. C, C, K or K cannot be set to VREF voltage.

2. When ZQ pin is directly connected to V^DDoutput impedance is set to minimum value and it cannot be connected to ground or left unconnected

3. Not connected to chip pad internally.

.

Rev. 5.0 July 2006

- 4 -

K7I163682B

K7I161882B

512Kx36 & 1Mx18 DDRII CIO b2 SRAM

PIN CONFIGURATIONS(TOP VIEW) K7I161882B(1Mx18)

1

2

NC/SA*

DQ9

NC

3

4

5

6

7

NC

BW0

SA

8

LD

SA

VSS

9

SA

10

NC/SA*

NC

DQ7

NC

VREF

DQ4

NC

DQ1

NC

11

CQ

DQ8

NC

A

B

C

D

E

F

CQ

NC

Doff

NC

TDO

SA

NC

R/W

SA

VSS

BW1

NC

SA

K

NC

VDDQ

NC

SA

SA0

VSS

SA

C

NC

DQ12

NC

VREF

NC

DQ15

NC

DQ10

DQ11

NC

DQ13

VDDQ

NC

DQ14

NC

VSS

VDD

VSS

SA

VSS

VDD

VSS

SA

VSS

NC

VDDQ

VSS

VDDQ

VSS

DQ6

DQ5

NC

ZQ

NC

DQ3

DQ2

NC

DQ0

TDI

G

H

J

K

L

M

N

P

R

DQ16

DQ17

SA

VSS

SA

VSS

SA

NC

TMS

TCK

C

Notes: 1. * Checked No Connect(NC) pins are reserved for higher density address, i.e. 2A for 72Mb.

2. BW⁰controls write to DQ0:DQ8 and BW1 controls write to DQ9:DQ17.

PIN NAME

SYMBOL

K, K

PIN NUMBERS

DESCRIPTION

Input Clock

NOTE

6B, 6A

C, C

CQ, CQ

Doff

SA0

SA

6P, 6R

11A, 1A

1H

6C

Input Clock for Output Data

Output Echo Clock

DLL Disable when low

Burst Count Address Inputs

Address Inputs

1

3A,9A,4B,8B,5C,7C,5N-7N,4P,5P,7P,8P,3R-5R,7R-9R

2B,11B,10C,3D,3E,11E,2F,11F,3G,10J,3K,11K,2L,11L

10M,3N,3P,11P

DQ0-17

Data Inputs Outputs

Read, Write Control Pin, Read active

when high

R/W

4A

8A

Synchronous Load Pin, bus Cycle

sequence is to be defined when low

LD

BW0, BW1

VREF

7B, 5A

2H,10H

11H

Block Write Control Pin,active when low

Input Reference Voltage

Output Driver Impedance Control Input

Power Supply ( 1.8 V )

ZQ

VDD

2

5F,7F,5G,7G,5H,7H,5J,7J,5K,7K

VDDQ

VSS

4E,8E,4F,8F,4G,8G,3H,4H,8H,9H,4J,8J,4K,8K,4L,8L

Output Power Supply ( 1.5V or 1.8V )

Ground

4C,8C,4D-8D,5E-7E,6F,6G,6H,6J,6K,5L-7L,4M-8M,4N,8N

TMS

TDI

TCK

TDO

10R

11R

2R

JTAG Test Mode Select

JTAG Test Data Input

JTAG Test Clock

1R

JTAG Test Data Output

2A,7A,10A,1B,3B,5B,9B,10B,1C,2C,3C,9C,11C,1D,2D,9D,10D,

11D,1E,2E,9E,10E,1F,3F,9F,10F,1G,2G,9G,10G,11G

1J,2J,3J,9J,11J,1K,2K,9K,10K,1L,3L,9L,10L

NC

No Connect

3

1M,2M,3M,9M,11M,1N,2N,9N,10N,11N,1P,2P,9P,10P

Notes: 1. C, C, K or K cannot be set to VREF voltage.

2. When ZQ pin is directly connected to V^DDoutput impedance is set to minimum value and it cannot be connected to ground or left unconnected

3. Not connected to chip pad internally.

.

Rev. 5.0 July 2006

- 5 -

K7I163682B

K7I161882B

512Kx36 & 1Mx18 DDRII CIO b2 SRAM

GENERAL DESCRIPTION

The K7I163682B and K7I1161882B are 18,874,368-bits DDR Common I/O

Synchronous Pipelined Burst SRAMs.

They are organized as 524,288 words by 36bits for K7I163682B and 1,048,576 words by 18 bits for K7I161882B for K7I160882B.

Address, data inputs, and all control signals are synchronized to the input clock ( K or K ).

Normally data outputs are synchronized to output clocks ( C and C ), but when C and C are tied high,

the data outputs are synchronized to the input clocks ( K and K ).

Read data are referenced to echo clock ( CQ or CQ ) outputs.

Read address and write address are registered on rising edges of the input K clocks.

Common address bus is used to access address both for read and write operations.

The internal burst counter is fixed to 2-bit sequential for both read and write operations.

Synchronous pipeline read and late write enable high speed operations.

Simple depth expansion is accomplished by using LD for port selection.

Byte write operation is supported with BW0 and BW1 ( BW2 and BW3) pins for x18 ( x36 ) device.

Nibble write operation is supported with NW0 and NW1 pins for x8 device.

IEEE 1149.1 serial boundary scan (JTAG) simplifies monitoring package pads attachment status with system.

The K7I163682B and K7I161882B are implemented with SAMSUNG's high performance 6T CMOS technology

and is available in 165pin FBGA packages. Multiple power and ground pins minimize ground bounce.

Read Operations

Read cycles are initiated by initiating R/W as high at the rising edge of the positive input clock K.

Address is presented and stored in the read address register synchronized with K clock.

For 2-bit burst DDR operation, it will access two 36-bit, 18-bit or 8-bit data words with each read command.

The first pipelined data is transferred out of the device triggered by C clock following next K clock rising edge.

Next burst data is triggered by the rising edge of following C clock rising edge.

Continuous read operations are initiated with K clock rising edge.

And pipelined data are transferred out of device on every rising edge of both C and C clocks.

In case C and C tied to high, output data are triggered by K and K instead of C and C.

When the LD is disabled after a read operation, the K7I163682B and K7I161882B will first complete

burst read operation before entering into deselect mode at the next K clock rising edge.

Then output drivers disabled automatically to high impedance state.

Echo clock operation

To assure the output traceability, the SRAM provides the output Echo clock, pair of compliment clock CQ and CQ,

which are synchronized with internal data output.

Echo clocks run free during normal operation.

The Echo clock is triggered by internal output clock signal, and transferred to external through same structures

as output driver.

Power-Up/Power-Down Supply Voltage Sequencing

The following power-up supply voltage application is recommended: VSS, VDD, VDDQ, VREF, then VIN. VDD and VDDQ can be applied

simultaneously, as long as VDDQ does not exceed VDD by more than 0.5V during power-up. The following power-down supply voltage

removal sequence is recommended: VIN, VREF, VDDQ, VDD, VSS. VDD and VDDQ can be removed simultaneously, as long as VDDQ

does not exceed VDD by more than 0.5V during power-down.

Rev. 5.0 July 2006

- 6 -

K7I163682B

K7I161882B

512Kx36 & 1Mx18 DDRII CIO b2 SRAM

Write Operations

Write cycles are initiated by activating R/W as low at the rising edge of the positive input clock K.

Address is presented and stored in the write address register synchronized with next K clock.

For 2-bit burst DDR operation, it will write two 36-bit, 18-bit or 8-bit data words with each write command.

The first “late writed” data is transferred and registered in to the device synchronous with next K clock rising edge.

Next burst data is transferred and registered synchronous with following K clock rising edge.

Continuous write operations are initiated with K rising edge.

And “late writed” data is presented to the device on every rising edge of both K and K clocks.

When the LD is disabled, the K7I163682B and K7I161882B will enter into deselect mode.

The device disregards input data presented on the same cycle W disabled.

The K7I163682B and K7I161882B support byte write operations.

With activating BW0 or BW1 (BW2 or BW3) in write cycle, only one byte of input data is presented.

In K7I161882B, BW0 controls write operation to D0:D8, BW1 controls write operation to D9:D17.

And in K7I163682B BW2 controls write operation to D18:D26, BW3 controls write operation to D27:D35.

Programmable Impedance Output Buffer Operation

The designer can program the SRAM's output buffer impedance by terminating the ZQ pin to VSS through a precision resistor(RQ).

The value of RQ (within 15%) is five times the output impedance desired.

For example, 250Ω resistor will give an output impedance of 50Ω.

Impedance updates occur early in cycles that do not activate the outputs, such as deselect cycles.

In all cases impedance updates are transparent to the user and do not produce access time "push-outs" or other anomalous behav-

ior in the SRAM.

There are no power up requirements for the SRAM. However, to guarantee optimum output driver impedance after power up, the

SRAM needs 1024 non-read cycles.

Clock Consideration

K7I163682B and K7I161882B utilize internal DLL(Delay-Locked Loops) for maximum output data valid window.

It can be placed into a stopped-clock state to minimize power with a modest restart time of 1024 clock cycles.

Circuitry automatically resets the DLL when absence of input clock is detected.

Single Clock Mode

K7I163682B and K7I161882B can be operated with the single clock pair K and K,

instead of C or C for output clocks.

To operate these devices in single clock mode, C and C must be tied high during power up and must be maintained high

during operation.

After power up, this device can′t change to or from single clock mode.

System flight time and clock skew could not be compensated in this mode.

Depth Expansion

Each port can be selected and deselected independently with R/W be shared among all SRAMs and provide a new LD signal

for each bank.

Before chip deselected, all read and write pending operations are completed.

Rev. 5.0 July 2006

- 7 -

K7I163682B

K7I161882B

512Kx36 & 1Mx18 DDRII CIO b2 SRAM

LINEAR BURST SEQUENCE TABLE

Case 1

SA0

Case 2

SA0

BURST SEQUENCE

First Address

Second Address

0

1

0

STATE DIAGRAM

POWER-UP

LOAD

NOP

LOAD

LOAD NEW ADDRESS

LOAD

READ

LOAD

WRITE

LOAD

DDR READ

DDR WRITE

Notes: 1. Internal burst counter is fixed as 2-bit linear, i.e. when first address is A0+0, next internal burst address is A0+1.

2. "LOAD" refers to read new address active status with LD=Low, "LOAD" refers to read new address inactive status with LD=High.

3. "READ" refers to read active read status with R/W=High, "WRITE" refers to write active status with R/W=Low

Rev. 5.0 July 2006

- 8 -

K7I163682B

K7I161882B

512Kx36 & 1Mx18 DDRII CIO b2 SRAM

TRUTH TABLES

SYNCHRONOUS TRUTH TABLE

Q

K

LD

R/W

OPERATION

Q(A0)

Q(A1)

Stopped

X

H

L

X

H

L

Previous state

High-Z

Previous state

High-Z

Clock Stop

No Operation

Read

↑

QOUT at C(t+1)

Din at K(t+1)

QOUT at C(t+2)

Din at K(t+1)

L

Write

Notes: 1. X means "Don′t Care".

2. The rising edge of clock is symbolized by ( ↑ ).

3. Before enter into clock stop status, all pending read and write operations will be completed.

WRITE TRUTH TABLE(x18)

K

↑

BW0

L

BW1

L

OPERATION

↑

WRITE ALL BYTEs ( K↑ )

WRITE BYTE 0 ( K↑ )

WRITE BYTE 1 ( K↑ )

WRITE NOTHING ( K↑ )

L

↑

L

H

L

H

L

H

L

H

Notes: 1. X means "Don′t Care".

2. All inputs in this table must meet setup and hold time around the rising edge of input clock K or K ( ↑ ).

3. Assumes a WRITE cycle was initiated.

4. This table illustrates operation for x18 devices.

WRITE TRUTH TABLE(x36)

K

↑

BW0

L

BW1

L

BW2

L

BW3

L

OPERATION

↑

WRITE ALL BYTEs ( K↑ )

WRITE BYTE 0 ( K↑ )

L

↑

L

H

L

H

L

H

L

WRITE BYTE 0 ( K↑ )

H

WRITE BYTE 1 ( K↑ )

L

WRITE BYTE 1 ( K↑ )

H

WRITE BYTE 2 and BYTE 3 ( K↑ )

WRITE NOTHING ( K↑ )

L

H

Notes: 1. X means "Don′t Care".

2. All inputs in this table must meet setup and hold time around the rising edge of input clock K or K ( ↑ ).

3. Assumes a WRITE cycle was initiated.

Rev. 5.0 July 2006

- 9 -

K7I163682B

K7I161882B

ABSOLUTE MAXIMUM RATINGS*

512Kx36 & 1Mx18 DDRII CIO b2 SRAM

PARAMETER

Voltage on VDD Supply Relative to VSS

Voltage on VDDQ Supply Relative to VSS

Voltage on Input Pin Relative to VSS

Storage Temperature

SYMBOL

VDD

RATING

-0.5 to 2.9

-0.5 to VDD

-0.5 to VDD+0.3

-65 to 150

0 to 70

UNIT

V

VDDQ

VIN

V

TSTG

TOPR

TBIAS

°C

Commercial

Industrial

Operating Temperature

-40 to 85

Storage Temperature Range Under Bias

-10 to 85

*Note: 1. Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating

only and functional operation of the device at these or any other conditions above those indicated in the operating sections of this specification

is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.

2. V^DDQmust not exceed VDD during normal operation.

DC ELECTRICAL CHARACTERISTICS(VDD=1.8V ±0.1V, TA=0°C to +70°C)

PARAMETER

Input Leakage Current

Output Leakage Current

SYMBOL

TEST CONDITIONS

VDD=Max ; VIN=VSS to VDDQ

Output Disabled,

MIN

MAX

+2

UNIT NOTE

µA

IIL

-2

IOL

-2

+2

-30

-25

-20

-16

-30

-25

-20

-16

-30

-25

-20

-16

-

600

-

550

VDD=Max , IOUT=0mA

Cycle Time ≥ tKHKH Min

Operating Current

(x36) : DDR

ICC

mA

1,5

1,6

-

500

-

450

-

500

-

450

VDD=Max , IOUT=0mA

Cycle Time ≥ tKHKH Min

Operating Current

(x18) : DDR

-

400

-

350

-

230

Device deselected,

IOUT=0mA, f=Max,

All Inputs≤0.2V or ≥ VDD-0.2V

-

210

Standby Current(NOP): DDR

ISB1

-

190

-

170

Output High Voltage

Output Low Voltage

Output High Voltage

Output Low Voltage

Input Low Voltage

Input High Voltage

VOH1

VOL1

VOH2

VOL2

VIL

VDDQ/2-0.12

VDDQ-0.2

VSS

VDDQ/2+0.12

VDDQ

0.2

V

2,7

3,7

4

IOH=-1.0mA

IOL=1.0mA

4

-0.3

VREF-0.1

VDDQ+0.3

8,9

8,10

VIH

VREF+0.1

Notes: 1. Minimum cycle. IOUT=0mA.

2. |IOH|=(VDDQ/2)/(RQ/5)±15% for 175Ω ≤ RQ ≤ 350Ω.

3. |IOL|=(VDDQ/2)/(RQ/5)±15% for 175Ω ≤ RQ ≤ 350Ω.

4. Minimum Impedance Mode when ZQ pin is connected to VDDQ.

5. Operating current is calculated with 50% read cycles and 50% write cycles.

6. Standby Current is only after all pending read and write burst operations are completed.

7. Programmable Impedance Mode.

8. These are DC test criteria. DC design criteria is V^REF±50mV. The AC VIH/VIL levels are defined separately for measuring

timing parameters.

9. V^IL(Min)DC=-0.3V, VIL (Min)AC=-1.5V(pulse width ≤ 3ns).

10. V^IH(Max)DC=VDDQ+0.3, VIH (Max)AC=VDDQ+0.85V(pulse width ≤ 3ns).

Rev. 5.0 July 2006

- 10 -

K7I163682B

K7I161882B

512Kx36 & 1Mx18 DDRII CIO b2 SRAM

AC ELECTRICAL CHARACTERISTICS (VDD=1.8V ±0.1V, TA=0°C to +70°C)

PARAMETER

Input High Voltage

Input Low Voltage

SYMBOL

VIH (AC)

VIL (AC)

MIN

MAX

-

UNIT

V

NOTES

1,2

VREF + 0.2

-

VREF - 0.2

V

1,2

Notes: 1. This condition is for AC function test only, not for AC parameter test.

2. To maintain a valid level, the transition edge of the input must :

a) Sustain a constant slew rate from the current AC level through the target AC level, V^IL(AC)or VIH(AC)

b) Reach at least the target AC level

c) After the AC target level is reached, continue to maintain at least the target DC level, V^IL(DC)or VIH(DC)

Overershoot Timing

Undershoot Timing

20% tKHKH(MIN)

VIH

VDDQ+0.5V

VDDQ+0.25V

VDDQ

VSS

VSS-0.25V

VSS-0.5V

20% tKHKH(MIN)

VIL

Note: For power-up, VIH ≤ VDDQ+0.3V and VDD ≤ 1.7V and VDDQ ≤ 1.4V t ≤ 200ms

OPERATING CONDITIONS (0°C ≤ TA ≤ 70°C)

PARAMETER

SYMBOL

VDD

MIN

1.7

1.4

0.68

0

MAX

1.9

0.95

0

UNIT

V

Supply Voltage

VDDQ

VREF

Reference Voltage

Ground

VSS

AC TEST CONDITIONS

Parameter

Core Power Supply Voltage

Output Power Supply Voltage

Input High/Low Level

Symbol

VDD

Value

1.7~1.9

1.4~1.9

1.25/0.25

0.75

Unit

V

AC TEST OUTPUT LOAD

VDDQ

VIH/VIL

VREF

V

0.75V

VREF

VDDQ/2

V

Input Reference Level

V

50Ω

SRAM

Zo=50Ω

Input Rise/Fall Time

TR/TF

0.3/0.3

VDDQ/2

ns

V

Output Timing Reference Level

250Ω

ZQ

Note: Parameters are tested with RQ=250Ω

Rev. 5.0 July 2006

- 11 -

K7I163682B

K7I161882B

512Kx36 & 1Mx18 DDRII CIO b2 SRAM

AC TIMING CHARACTERISTICS(VDD=1.8V±0.1V, TA=0°C to +70°C)

-30

-25

-20

-16

PARAMETER

SYMBOL

UNIT NOTE

MIN

MAX

MIN

MAX

MIN

MAX

MIN

MAX

Clock

Clock Cycle Time (K, K, C, C)

Clock Phase Jitter (K, K, C, C)

Clock High Time (K, K, C, C)

Clock Low Time (K, K, C, C)

Clock to Clock (K↑ → K↑, C↑ → C↑)

Clock to data clock (K↑ → C↑, K↑→ C↑)

DLL Lock Time (K, C)

tKHKH

tKC var

tKHKL

3.30

8.40

0.20

4.00

8.40

0.20

5.00

8.40

0.20

6.00

8.40

0.20

ns

5

6

1.32

1.49

0.00

1024

30

1.60

1.80

0.00

1024

30

2.00

2.20

0.00

1024

30

2.40

2.70

0.00

1024

30

tKLKH

ns

tKHKH

tKHCH

tKC lock

tKC reset

ns

1.45

1.80

2.30

2.80

ns

cycle

ns

K Static to DLL reset

Output Times

C, C High to Output Valid

C, C High to Output Hold

C, C High to Echo Clock Valid

C, C High to Echo Clock Hold

CQ, CQ High to Output Valid

CQ, CQ High to Output Hold

C, High to Output High-Z

C, High to Output Low-Z

Setup Times

tCHQV

tCHQX

0.45

0.27

0.45

0.30

0.45

0.35

0.45

0.50

0.40

0.50

ns

3

-0.45

-0.27

-0.45

-0.30

-0.45

-0.35

-0.45

-0.50

-0.40

-0.50

tCHCQV

tCHCQX

tCQHQV

tCQHQX

tCHQZ

7

3

tCHQX1

Address valid to K rising edge

Control inputs valid to K rising edge

Data-in valid to K, K rising edge

Hold Times

tAVKH

tIVKH

0.40

0.30

0.50

0.35

0.60

0.40

0.70

0.50

ns

2

tDVKH

K rising edge to address hold

K rising edge to control inputs hold

K, K rising edge to data-in hold

tKHAX

tKHIX

0.40

0.30

0.50

0.35

0.60

0.40

0.70

0.50

ns

tKHDX

Notes: 1. All address inputs must meet the specified setup and hold times for all latching clock edges.

2. Control signal are R and W.

In case of BW⁰,BW1 (BW2, BW3, also for x36) signal follow the data setup/hold times.

3. If C,C are tied high, K,K become the references for C,C timing parameters.

4. To avoid bus contention, at a given voltage and temperature tCHQX¹is bigger than tCHQZ.

The specs as shown do not imply bus contention because tCHQX¹is a MIN parameter that is worst case at totally different test conditions

(0°C, 1.9V) than tCHQZ, which is a MAX parameter(worst case at 70°C, 1.7V)

It is not possible for two SRAMs on the same board to be at such different voltage and temperature.

5. Clock phase jitter is the variance from clock rising edge to the next expected clock rising edge.

6. Vdd slew rate must be less than 0.1V DC per 50 ns for DLL lock retention. DLL lock time begins once Vdd and input clock are stable.

Rev. 5.0 July 2006

- 12 -

K7I163682B

K7I161882B

512Kx36 & 1Mx18 DDRII CIO b2 SRAM

PIN CAPACITANCE

PRMETER

Address Control Input Capacitance

Input and Output Capacitance

Clock Capacitance

SYMBOL

CIN

TESTCONDITION

TYP

MAX

UNIT

pF

NOTE

VIN=0V

VOUT=0V

-

4

6

5

7

6

COUT

pF

CCLK

pF

Note: 1. Parameters are tested with RQ=250Ω and VDDQ=1.5V.

2. Periodically sampled and not 100% tested.

THERMAL RESISTANCE

PRMETER

Junction to Ambient

Junction to Case

SYMBOL

TYP

17.1

3.3

UNIT

NOTE

θJA

°C/W

θJC

Note: Junction temperature is a function of on-chip power dissipation, package thermal impedance, mounting site temperature and mounting site

thermal impedance. T^J=TA + PD x θJA

APPLICATION INRORMATION

R=250Ω

ZQ

SRAM#1

SRAM#4

CQ

Q

CQ

Q

Vt

D

SA

R W BW0 BW1 C C K K

RW BW0 BW1 C C K K

R

Data In

Data Out

Address

R

Vt

R

W

BW

MEMORY

CONTROLLER

Return CLK

Vt

Source CLK

Return CLK

Source CLK

R=50Ω Vt=VREF

SRAM1 Input CQ

SRAM4 Input CQ

Rev. 5.0 July 2006

- 13 -

K7I163682B

K7I161882B

512Kx36 & 1Mx18 DDRII CIO b2 SRAM

TIMING WAVE FORMS OF READ, WRITE AND NOP

NOP

READ

NOP

WRITE

READ

NOP

(burst of 2) (burst of 2) (burst of 2)

(burst of 2) (burst of 2) (burst of 2) (burst of 2)

(Note3)

9

5

1

2

4

7

6

8

10

12

11

3

K

t

KHKL

t

KHKH

tKHKH

tKLKH

tIVKH

tKHIX

LD

R/W

SA

A2

A5

A6

A0

A1

A3

A4

tKHDX

tDVKH

DQ

Q01

Q02

Q11

Q12

Q21

Q22

D

31

D32

D41

D42

Q51

Q52

Q61

Q62

tCHQV

tCHQX

tCHQZ

tCHQV

t

t^KKH^HK^KL^H

tKLKH

t

KHCH

tCHQX1

C

tCHCQX

t

CHCQX

tKHKH

tCHCQV

CQ

tCHCQV

DON′T CARE

UNDEFINED

NOTE

1. Q⁰¹refers to output from address A. Q02 refers to output from the next internal burst address following A, etc.

2. Outputs are disabled(High-Z) one clock cycle after a NOP.

3. The second NOP cycle is not necessary for correct device operation; however, at high clock frequencies, it may be required to prevent

bus contention.

Rev. 5.0 July 2006

- 14 -

K7I163682B

K7I161882B

512Kx36 & 1Mx18 DDRII CIO b2 SRAM

IEEE 1149.1 TEST ACCESS PORT AND BOUNDARY SCAN-JTAG

This part contains an IEEE standard 1149.1 Compatible Test Access Port(TAP). The package pads are monitored by the Serial Scan

circuitry when in test mode. This is to support connectivity testing during manufacturing and system diagnostics. Internal data is not

driven out of the SRAM under JTAG control. In conformance with IEEE 1149.1, the SRAM contains a TAP controller, Instruction Reg-

ister, Bypass Register and ID register. The TAP controller has a standard 16-state machine that resets internally upon power-up,

therefore, TRST signal is not required. It is possible to use this device without utilizing the TAP. To disable the TAP controller without

interfacing with normal operation of the SRAM, TCK must be tied to VSS to preclude mid level input. TMS and TDI are designed so an

undriven input will produce a response identical to the application of a logic 1, and may be left unconnected. But they may also be

tied to VDD through a resistor. TDO should be left unconnected.

JTAG Block Diagram

JTAG Instruction Coding

IR2 IR1 IR0 Instruction

TDO Output

Notes

0

1

0

1

0

1

0

1

0

1

0

1

EXTEST

IDCODE

SAMPLE-Z

Boundary Scan Register

Identification Register

Boundary Scan Register

1

3

2

6

5

6

4

0

RESERVED Do Not Use

1

SAMPLE

Boundary Scan Register

1

RESERVED Do Not Use

SRAM

CORE

1

BYPASS

Bypass Register

NOTE :

1. Places DQs in Hi-Z in order to sample all input data regardless of other

SRAM inputs. This instruction is not IEEE 1149.1 compliant.

2. Places DQs in Hi-Z in order to sample all input data regardless of other

SRAM inputs.

TDI

BYPASS Reg.

Identification Reg.

Instruction Reg.

TDO

3. TDI is sampled as an input to the first ID register to allow for the serial shift

of the external TDI data.

4. Bypass register is initiated to V^SSwhen BYPASS instruction is invoked. The

Bypass Register also holds serially loaded TDI when exiting the Shift DR

states.

5. SAMPLE instruction dose not places DQs in Hi-Z.

6. This instruction is reserved for future use.

Control Signals

TAP Controller

TMS

TCK

TAP Controller State Diagram

1

0

Test Logic Reset

0

1

0

1

Run Test Idle

Select DR

0

Capture DR

0

Shift DR

1

Exit1 DR

0

Select IR

0

1

Capture IR

0

Shift IR

1

Exit1 IR

0

Pause DR

1

Pause IR

1

Exit2 IR

1

Exit2 DR

1

0

Update DR

0

Update IR

1

Rev. 5.0 July 2006

- 15 -

K7I163682B

K7I161882B

512Kx36 & 1Mx18 DDRII CIO b2 SRAM

SCAN REGISTER DEFINITION

Part

Instruction Register

Bypass Register

ID Register

32 bits

Boundary Scan

107 bits

512Kx36

1Mx18

3 bits

1 bit

107 bits

ID REGISTER DEFINITION

Revision Number

Part Configuration

(28:12)

00def0wx0t0q0b0s0

Samsung JEDEC Code

(11: 1)

Part

Start Bit(0)

(31:29)

000

512Kx36

1Mx18

00001001110

1

000

00def0wx0t0q0b0s0

Note : Part Configuration

/def=001 for 18Mb, /wx=11 for x36, 10 for x18

/t=1 for DLL Ver., 0 for non-DLL Ver. /q=1 for QDR, 0 for DDR /b=1 for 4Bit Burst, 0 for 2Bit Burst /s=1 for Separate I/O, 0 for Common I/O

BOUNDARY SCAN EXIT ORDER

ORDER

PIN ID

ORDER

PIN ID

10D

9E

10C

11D

9C

ORDER

73

PIN ID

2C

3E

2D

2E

1E

2F

3F

1G

1F

3G

2G

1J

2J

3K

3J

2K

1K

2L

1

2

6R

6P

37

38

39

40

41

42

43

44

45

46

47

48

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

64

65

66

67

68

69

70

71

72

74

75

76

77

78

79

80

81

82

83

84

85

86

87

88

89

90

91

92

93

94

95

96

97

3

4

6N

7P

5

6

7N

7R

9D

7

8

8R

8P

11B

11C

9B

10B

11A

Internal

9A

8B

7C

6C

8A

7A

7B

6B

6A

5B

5A

4A

5C

4B

3A

1H

1A

2B

3B

1C

1B

9

9R

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

11P

10P

10N

9P

10M

11N

9M

9N

11L

11M

9L

10L

11K

10K

9J

3L

1M

1L

3N

3M

1N

2M

3P

2N

2P

1P

3R

4R

4P

5P

5N

5R

9K

98

99

10J

11J

11H

10G

9G

11F

11G

9F

100

101

102

103

104

105

106

107

10F

11E

10E

3D

3C

1D

Note: 1. NC pins are read as "X" ( i.e. don′t care.)

Rev. 5.0 July 2006

- 16 -

K7I163682B

K7I161882B

512Kx36 & 1Mx18 DDRII CIO b2 SRAM

JTAG DC OPERATING CONDITIONS

Parameter

Symbol

Min

1.7

Typ

Max

1.9

Unit

V

Note

Power Supply Voltage

VDD

VIH

1.8

Input High Level

1.3

-

VDD+0.3

0.5

V

Input Low Level

VIL

-0.3

1.4

V

Output High Voltage(IOH=-2mA)

Output Low Voltage(IOL=2mA)

VOH

VOL

VDD

V

VSS

0.4

V

Note: 1. The input level of SRAM pin is to follow the SRAM DC specification.

JTAG AC TEST CONDITIONS

Parameter

Symbol

VIH/VIL

TR/TF

Min

1.8/0.0

1.0/1.0

0.9

Unit

V

Note

Input High/Low Level

Input Rise/Fall Time

ns

V

Input and Output Timing Reference Level

Note: 1. See SRAM AC test output load on page 11.

1

JTAG AC Characteristics

Parameter

Symbol

Min

50

20

5

Max

Unit

Note

TCK Cycle Time

tCHCH

tCHCL

tCLCH

tMVCH

tCHMX

tDVCH

tCHDX

tSVCH

tCHSX

tCLQV

-

ns

TCK High Pulse Width

TCK Low Pulse Width

TMS Input Setup Time

TMS Input Hold Time

TDI Input Setup Time

TDI Input Hold Time

-

5

-

5

-

5

-

SRAM Input Setup Time

SRAM Input Hold Time

Clock Low to Output Valid

5

-

5

-

0

10

JTAG TIMING DIAGRAM

TCK

tCHCH

tCLCH

tCHCL

tMVCH

tCHMX

TMS

TDI

tDVCH

tSVCH

tCHDX

tCHSX

PI

(SRAM)

tCLQV

TDO

Rev. 5.0 July 2006

- 17 -

K7I163682B

K7I161882B

512Kx36 & 1Mx18 DDRII CIO b2 SRAM

165 FBGA PACKAGE DIMENSIONS

13mm x 15mm Body, 1.0mm Bump Pitch, 11x15 Ball Array

B

Top View

A

C

Side View

D

A

G

E

B

F

Bottom View

H ∅

E

Symbol

Value

13 ± 0.1

Units

Note

Symbol

Value

1.0

Units

mm

Note

A

B

C

D

mm

E

F

15 ± 0.1

1.3 ± 0.1

0.35 ± 0.05

14.0

G

H

10.0

0.5 ± 0.05

Rev. 5.0 July 2006

- 18 -


型号：	K7I163682B-EC200
厂家：	SAMSUNG
描述：	DDR SRAM, 512KX36, 0.45ns, CMOS, PBGA165, 13 X 15 MM, 1 MM PITCH, ROHS COMPLIANT, FBGA-165 双倍数据速率静态存储器
文件：	总18页 (文件大小：410K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

K7I163682B-EC200 [SAMSUNG]

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