K7I321884M-FC25 [SAMSUNG]
DDR SRAM, 2MX18, 0.45ns, CMOS, PBGA165, 15 X 17 MM, 1 MM PITCH, FBGA-165;型号: | K7I321884M-FC25 |
厂家: | SAMSUNG |
描述: | DDR SRAM, 2MX18, 0.45ns, CMOS, PBGA165, 15 X 17 MM, 1 MM PITCH, FBGA-165 时钟 双倍数据速率 静态存储器 内存集成电路 |
文件: | 总18页 (文件大小:181K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
K7I323684M
K7I321884M
K7I320884M
Preliminary
1Mx36 & 2Mx18 & 4Mx8 DDRII CIO b4 SRAM
Document Title
1Mx36-bit, 2Mx18-bit, 4Mx8-bit DDRII CIO b4 SRAM
Revision History
Rev. No.
History
Draft Date
Remark
0.0
1. Initial document.
Advance
Preliminary
October, 22 2001
0.1
1. Pin name change from DLL to Doff.
December, 14 2001
2. Vddq range change from 1.5V to 1.5V~1.8V.
3. Update JTAG test conditions.
4. Reserved pin for high density name change from NC to Vss/SA
5. Delete AC test condition about Clock Input timing Reference Level
6. Delete clock description on page 2 and add HSTL I/O comment
0.2
0.3
0.4
1. Update current characteristics in DC electrical characteristics
2. Change AC timing characteristics
Preliminary
Preliminary
Preliminary
July, 29. 2002
Sep. 6. 2002
Oct. 7. 2002
3. Update JTAG instruction coding and diagrams
1. Add AC electrical characteristics.
2. Change AC timing characteristics.
3. Change DC electrical characteristics(ISB1)
1. Change the data Setup/Hold time.
2. Change the Access Time.(tCHQV, tCHQX, etc.)
3. Change the Clock Cycle Time.(MAX value of tKHKH)
4. Change the JTAG instruction coding.
0.5
1. Change the Boundary scan exit order.
Preliminary
Dec. 16, 2002
2. Change the AC timing characteristics(-25, -20)
3. Correct the Overshoot and Undershoot timing diagrams.
The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the
specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions on the parameters of this device. If you have any ques-
tions, please contact the SAMSUNG branch office near your office, call or contact Headquarters.
Dec. 2002
Rev 0.5
- 1 -
K7I323684M
K7I321884M
K7I320884M
Preliminary
1Mx36 & 2Mx18 & 4Mx8 DDRII CIO b4 SRAM
1Mx36-bit, 2Mx18-bit, 4Mx8-bit DDRII CIO b4 SRAM
FEATURES
• 1.8V+0.1V/-0.1V Power Supply.
Part
Cycle Access
Organization
Unit
• DLL circuitry for wide output data valid window and future
Number
Time
Time
freguency scaling.
• I/O Supply Voltage 1.5V+0.1V/-0.1V for 1.5V I/O,
1.8V+0.1V/-0.1V for 1.8V I/O.
• Pipelined, double-data rate operation.
• Common data input/output bus .
K7I323684M-FC25
K7I323684M-FC20
K7I323684M-FC16
K7I323684M-FC13
K7I321884M-FC25
K7I321884M-FC20
K7I321884M-FC16
K7I321884M-FC13
K7I320884M-FC25
K7I320884M-FC20
K7I320884M-FC16
K7I320884M-FC13
4.0
5.0
6.0
7.5
4.0
5.0
6.0
7.5
4.0
5.0
6.0
7.5
0.45
0.45
0.50
0.50
0.45
0.45
0.50
0.50
0.45
0.45
0.50
0.50
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
X36
X18
• HSTL I/O
• Full data coherency, providing most current data.
• Synchronous pipeline read with self timed late write.
• Registered address, control and data input/output.
• DDR(Double Data Rate) Interface on read and write ports.
• Fixed 4-bit burst for both read and write operation.
• Clock-stop supports to reduce current.
• Two input clocks(K and K) for accurate DDR timing at clock
rising edges only.
• Two input clocks for output data(C and C) to minimize
clock-skew and flight-time mismatches.
• Two echo clocks (CQ and CQ) to enhance output data
traceability.
X8
• Single address bus.
• Byte write (x18, x36) and nybble(x8) write function.
• Simple depth expansion with no data contention.
• Programmable output impedance.
• JTAG 1149.1 compatible test access port.
• 165FBGA(11x15 ball aray FBGA) with body size of 15x17mm
FUNCTIONAL BLOCK DIAGRAM
36 (or 18)
DATA
REG
36 (or 18)
WRITE DRIVER
18
(or 19)
ADD REG
&
BURST
18 (or 19)
ADDRESS
A0,A1
LOGIC
72
(or 36)
72
(or 36)
1Mx36
(2Mx18)
MEMORY
ARRAY
36 (or 18)
DQ
LD
CTRL
LOGIC
R/W
BWX
4(or 2)
CQ, CQ
(Echo Clock out)
K
K
CLK
GEN
C
C
SELECT OUTPUT CONTROL
Notes: 1. Numbers in ( ) are for x18 device, x8 device also the same with appropriate adjustments of depth and width.
DDRII SRAM and Double Data Rate comprise a new family of products developed by Cypress, Hitachi, IDT, Micron, NEC and Samsung te chnology.
Dec. 2002
Rev 0.5
- 2 -
K7I323684M
K7I321884M
K7I320884M
Preliminary
1Mx36 & 2Mx18 & 4Mx8 DDRII CIO b4 SRAM
PIN CONFIGURATIONS(TOP VIEW) K7I323684M(1Mx36)
1
2
VSS/SA*
DQ27
NC
3
4
5
6
7
8
9
SA
10
VSS/SA*
NC
11
CQ
A
B
C
D
E
F
CQ
NC
NC
NC
NC
NC
NC
Doff
NC
NC
NC
NC
NC
NC
TDO
SA
R/W
SA
BW2
BW3
SA
K
BW1
BW0
SA1
VSS
VSS
VDD
VDD
VDD
VDD
VDD
VSS
VSS
SA
LD
DQ18
DQ28
DQ19
DQ20
DQ21
DQ22
VDDQ
DQ32
DQ23
DQ24
DQ34
DQ25
DQ26
SA
K
SA
NC
NC
NC
NC
NC
NC
VDDQ
NC
NC
NC
NC
NC
NC
SA
DQ8
DQ7
DQ16
DQ6
DQ5
DQ14
ZQ
VSS
SA0
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
SA
VSS
DQ17
NC
DQ29
NC
VSS
VSS
VSS
VDD
VDD
VDD
VDD
VDD
VSS
VSS
SA
VSS
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VSS
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VSS
DQ15
NC
DQ30
DQ31
VREF
NC
G
H
J
NC
VREF
DQ13
DQ12
NC
DQ4
DQ3
DQ2
DQ1
DQ10
DQ0
TDI
K
L
NC
DQ33
NC
M
N
P
R
DQ11
NC
DQ35
NC
VSS
VSS
SA
SA
C
SA
SA
DQ9
TMS
TCK
SA
SA
C
SA
SA
Notes : 1. * Checked No Connect(NC) pins are reserved for higher density address, i.e. 10A for 64Mb, 2A for 128Mb .
2. BW0 controls write to DQ0:DQ8, BW1 controls write to DQ9:DQ17, BW2 controls write to DQ18:DQ26 and BW3 controls write to DQ27:DQ35.
PIN NAME
SYMBOL
PIN NUMBERS
DESCRIPTION
Input Clock
NOTE
K, K
C, C
6B, 6A
6P, 6R
Input Clock for Output Data
Output Echo Clock
DLL Disable when low
Burst Count Address Inputs
Address Inputs
1
CQ, CQ
Doff
11A, 1A
1H
SA0,SA1
SA
6C,7C
3A,9A,4B,8B,5C,5N-7N,4P,5P,7P,8P,3R-5R,7R-9R
2B,3B,11B,3C,10C,11C,2D,3D,11D,3E,10E,11E,2F,3F
11F,2G,3G,11G,3J,10J,11J,3K,10K,11K,2L,3L,11L
3M,10M,11M,2N,3N,11N,3P,10P,11P
DQ0-35
Data Inputs Outputs
Read, Write Control Pin, Read active
when high
R/W
LD
4A
8A
Synchronous Load Pin, bus Cycle
sequence is to be defined when low
BW0, BW1,BW2, BW3
7B,7A,5A,5B
Block Write Control Pin,active when low
Input Reference Voltage
VREF
ZQ
2H,10H
11H
Output Driver Impedance Control Input
Power Supply ( 1.8 V )
2
VDD
5F,7F,5G,7G,5H,7H,5J,7J,5K,7K
4E,8E,4F,8F,4G,8G,3H,4H,8H,9H,4J,8J,4K,8K,4L,8L
VDDQ
Output Power Supply ( 1.5V or 1.8V )
2A,10A,4C,8C,4D-8D,5E-7E,6F,6G,6H,6J,6K,5L-7L,
4M-8M,4N,8N
VSS
Ground
TMS
TDI
10R
11R
2R
JTAG Test Mode Select
JTAG Test Data Input
JTAG Test Clock
TCK
TDO
1R
JTAG Test Data Output
1B,9B,10B,1C,2C,9C,1D,9D,10D,1E,2E,9E,
1F,9F,10F,1G,9G,10G,1J,2J,9J,1K,2K,9K
1L,9L,10L,1M,2M,9M,1N,9N,10N,1P,2P,9P
NC
No Connect
3
Notes: 1. C, C, K or K cannot be set to VREF voltage.
2. When ZQ pin is directly connected to VDD output impedance is set to minimum value and it cannot be connected to ground or left unconnected.
3. Not connected to chip pad internally.
Dec. 2002
Rev 0.5
- 3 -
K7I323684M
K7I321884M
K7I320884M
Preliminary
1Mx36 & 2Mx18 & 4Mx8 DDRII CIO b4 SRAM
PIN CONFIGURATIONS(TOP VIEW) K7I321884M(2Mx18)
1
CQ
NC
NC
NC
NC
NC
NC
Doff
NC
NC
NC
NC
NC
NC
TDO
2
VSS/SA*
DQ9
NC
3
4
5
6
7
8
9
SA
NC
NC
NC
NC
NC
NC
VDDQ
NC
NC
NC
NC
NC
NC
SA
10
SA
11
CQ
DQ8
NC
A
B
C
D
E
F
SA
R/W
SA
BW1
NC
SA
K
NC
LD
NC
K
BW0
SA1
VSS
VSS
VDD
VDD
VDD
VDD
VDD
VSS
VSS
SA
SA
NC
NC
VSS
VSS
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VSS
VSS
SA
SA0
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
SA
C
VSS
DQ7
NC
NC
DQ10
DQ11
NC
VSS
VSS
VDD
VDD
VDD
VDD
VDD
VSS
VSS
SA
VSS
NC
NC
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VSS
NC
DQ6
DQ5
NC
DQ12
NC
NC
G
H
J
DQ13
VDDQ
NC
NC
VREF
NC
VREF
DQ4
NC
ZQ
NC
K
L
NC
DQ14
NC
DQ3
DQ2
NC
DQ15
NC
NC
M
N
P
R
NC
DQ1
NC
NC
DQ16
DQ17
SA
VSS
NC
NC
SA
SA
SA
NC
DQ0
TDI
TCK
SA
SA
C
SA
SA
TMS
Notes: 1. * Checked No Connect(NC) pins are reserved for higher density address, i.e. 2A for 64Mb.
2. BW0 controls write to DQ0:DQ8 and BW1 controls write to DQ9:DQ17.
PIN NAME
SYMBOL
K, K
PIN NUMBERS
DESCRIPTION
NOTE
6B, 6A
Input Clock
C, C
6P, 6R
Input Clock for Output Data
Output Echo Clock
1
CQ, CQ
Doff
11A, 1A
1H
DLL Disable when low
Burst Count Address Inputs
Address Inputs
SA0,SA1
SA
6C,7C
3A,9A,10A,4B,8B,5C,5N-7N,4P,5P,7P,8P,3R-5R,7R-9R
2B,11B,10C,3D,3E,11E,2F,11F,3G,10J,3K,11K,2L,11L
10M,3N,3P,11P
DQ0-17
R/W
Data Inputs Outputs
Read, Write Control Pin, Read active
when high
4A
8A
Synchronous Load Pin, bus Cycle
sequence is to be defined when low
LD
BW0, BW1
VREF
7B, 5A
Block Write Control Pin,active when low
Input Reference Voltage
2H,10H
11H
ZQ
Output Driver Impedance Control Input
Power Supply ( 1.8 V )
2
VDD
5F,7F,5G,7G,5H,7H,5J,7J,5K,7K
VDDQ
4E,8E,4F,8F,4G,8G,3H,4H,8H,9H,4J,8J,4K,8K,4L,8L
Output Power Supply ( 1.5V or 1.8V )
VSS
TMS
TDI
2A,4C,8C,4D-8D,5E-7E,6F,6G,6H,6J,6K,5L-7L,4M-8M,4N,8N
Ground
10R
11R
2R
JTAG Test Mode Select
JTAG Test Data Input
JTAG Test Clock
TCK
TDO
1R
JTAG Test Data Output
7A,1B,3B,5B,9B,10B,1C,2C,3C,9C,11C,1D,2D,9D,10D,11D
1E,2E,9E,10E,1F,3F,9F,10F,1G,2G,9G,10G,11G
1J,2J,3J,9J,11J,1K,2K,9K,10K,1L,3L,9L,10L
NC
No Connect
3
1M,2M,3M,9M,11M,1N,2N,9N,10N,11N,1P,2P,9P,10P
Notes: 1. C, C, K or K cannot be set to VREF voltage.
2. When ZQ pin is directly connected to VDD output impedance is set to minimum value and it cannot be connected to ground or left unconnected.
3. Not connected to chip pad internally.
Dec. 2002
Rev 0.5
- 4 -
K7I323684M
K7I321884M
K7I320884M
Preliminary
1Mx36 & 2Mx18 & 4Mx8 DDRII CIO b4 SRAM
PIN CONFIGURATIONS(TOP VIEW) K7I320884M(4Mx8)
1
CQ
NC
NC
NC
NC
NC
NC
Doff
NC
NC
NC
NC
NC
NC
TDO
2
VSS/SA*
NC
3
4
5
6
7
8
9
SA
NC
NC
NC
NC
NC
NC
VDDQ
NC
NC
NC
NC
NC
NC
SA
10
SA
11
CQ
DQ3
NC
A
B
C
D
E
F
SA
R/W
SA
NW1
NC
SA
K
NC
NW 0
SA
LD
NC
NC
NC
DQ4
NC
DQ5
VDDQ
NC
NC
NC
NC
NC
DQ7
SA
K
SA
NC
NC
VSS
VSS
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VSS
VSS
SA
NC
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
SA
C
VSS
NC
NC
VSS
VSS
VDD
VDD
VDD
VDD
VDD
VSS
VSS
SA
VSS
VSS
VDD
VDD
VDD
VDD
VDD
VSS
VSS
SA
VSS
NC
NC
NC
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VSS
NC
DQ2
NC
NC
NC
G
H
J
NC
NC
NC
VREF
NC
VREF
DQ1
NC
ZQ
NC
K
L
NC
NC
DQ6
NC
NC
DQ0
NC
M
N
P
R
NC
NC
VSS
NC
NC
NC
SA
SA
SA
NC
NC
TCK
SA
SA
C
SA
SA
TMS
TDI
Notes: 1. * Checked No Connect(NC) pin is reserved for higher density address, i.e. 2A for 72Mb.
2. NW 0 controls write to DQ0:DQ3 and NW1 controls write to DQ4:DQ7.
PIN NAME
SYMBOL
K, K
PIN NUMBERS
DESCRIPTION
NOTE
6B, 6A
Input Clock
C, C
6P, 6R
Input Clock for Output Data
Output Echo Clock
1
CQ, CQ
Doff
11A, 1A
1H
DLL Disable when low
Address Inputs
SA
3A,9A,10A,4B,8B,5C,7C,5N-7N,4P,5P,7P,8P,3R-5R,7R-9R
10J,11B,3E,11E,3G,2L,11L,3P
DQ0-7
Data Inputs Outputs
Read, Write Control Pin, Read active
when high
R/W
LD
4A
8A
Synchronous Load Pin, bus Cycle
sequence is to be defined when low
NW0, NW1
VREF
ZQ
7B, 5A
Nybble Write Control Pin,active when low
Input Reference Voltage
Output Driver Impedance Control Input
Power Supply ( 1.8 V )
2H,10H
11H
2
VDD
5F,7F,5G,7G,5H,7H,5J,7J,5K,7K
VDDQ
VSS
4E,8E,4F,8F,4G,8G,3H,4H,8H,9H,4J,8J,4K,8K,4L,8L
Output Power Supply ( 1.5V or 1.8V )
Ground
2A,4C,8C,4D-8D,5E-7E,6F,6G,6H,6J,6K,5L-7L,4M-8M,4N,8N
TMS
TDI
10R
11R
2R
JTAG Test Mode Select
JTAG Test Data Input
TCK
TDO
JTAG Test Clock
1R
JTAG Test Data Output
7A,1B,2B,3B,5B,9B,10B,1C,2C,3C,7C,9C,10C,11C
1D,2D,3D,9D,10D,11D,1E,2E,9E,10E,1F,2F,3F,9F,10F,11F
1G,2G,9G,10G,11G,1J,2J,3J,9J,11J,1K,2K,3K,9K,10K,11K
1L,3L,9L,10L,1M,2M,3M,9M,10M,11M,1N,2N,3N,9N,10N
11N,1P,2P,9P,10P,11P
NC
No Connect
3
Notes: 1. C, C, K or K cannot be set to VREF voltage.
2. When ZQ pin is directly connected to VDD output impedance is set to minimum value and itcannot be connected to ground or left unconnected.
3. Not connected to chip pad internally.
4. The X8 product does not permit random start address on the least significant address bit.
Dec. 2002
Rev 0.5
- 5 -
K7I323684M
K7I321884M
K7I320884M
Preliminary
1Mx36 & 2Mx18 & 4Mx8 DDRII CIO b4 SRAM
GENERAL DESCRIPTION
The K7I323684M,K7I321884M and K7I320884M are 37,748,736-bits DDR Common I/O
Synchronous Pipelined Burst SRAMs.
They are organized as 1,048,576 words by 36bits for K7I323684M, 2,097,152 words by 18 bits for K7I321884M and
4,194,304 words by 8bits for K7I320884M.
Address, data inputs, and all control signals are synchronized to the input clock ( K or K ).
Normally data outputs are synchronized to output clocks ( C and C ), but when C and C are tied high,
the data outputs are synchronized to the input clocks ( K and K ).
Read data are referenced to echo clock ( CQ or CQ ) outputs.
Read address and write address are registered on rising edges of the input K clocks.
Common address bus is used to access address both for read and write operations.
The internal burst counter is fiexd to 4-bit sequential for both read and write operations.
Synchronous pipeline read and late write enable high speed operations.
Simple depth expansion is accomplished by using LD for port selection.
Byte write operation is supported with BW0 and BW1 ( BW2 and BW3) pins for x18 ( x36 ) device.
Nybble write operation is supported with NW 0 and NW1 pins for x8 device.
IEEE 1149.1 serial boundary scan (JTAG) simplifies monitoriing package pads attachment status with system.
The K7I323684M,K7I321884M and K7I320884M are implemented with SAMSUNG's high performance 6T CMOS technology
and is available in 165pin FBGA packages. Multiple power and ground pins minimize ground bounce.
Read Operations
Read cycles are initiated by initiating R/W as high at the rising edge of the positive input clock K.
Address is presented and stored in the read address register synchronized with K clock.
For 4-bit burst DDR operation, it will access four 36-bit, 18-bit or 8-bit data words with each read command.
The first pipelined data is transfered out of the device triggered by C clock following next K clock rising edge.
Next burst data is triggered by the rising edge of following C clock rising edge.
Continuous read operations are initated with K clock rising edge.
And pipelined data are transferred out of device on every rising edge of both C and C clocks.
In case C and C tied to high, output data are triggered by K and K insted of C and C.
When the LD is disabled after a read operation, the K7I323684M,K7I321884M and K7I320884M will first complete
burst read operation before entering into deselect mode at the next K clock rising edge.
Then output drivers disabled automatically to high impedance state.
Echo clock operation
To assure the output tracibility, the SRAM provides the output Echo clock, pair of compliment clock CQ and CQ,
which are synchronized with internal data output.
Echo clocks run free during normal operation.
The Echo clock is triggered by internal output clock signal, and transfered to external through same structures
as output driver.
Dec. 2002
Rev 0.5
- 6 -
K7I323684M
K7I321884M
K7I320884M
Preliminary
1Mx36 & 2Mx18 & 4Mx8 DDRII CIO b4 SRAM
Write Operations
Write cycles are initiated by activating R/W as low at the rising edge of the positive input clock K.
Address is presented and stored in the write address register synchronized with next K clock.
For 4-bit burst DDR operation, it will write two 36-bit, 18-bit or 8-bit data words with each write command.
The first "late writed" data is transfered and registered in to the device synchronous with next K clock rising edge.
Next burst data is transfered and registered synchronous with following K clock rising edge.
Continuous write operations are initated with K rising edge.
And "late writed" data is presented to the device on every rising edge of both K and K clocks.
When the LD is disabled, the K7I323684M,K7I321884M and K7I320884M will enter into deselect mode.
The device disregards input data presented on the same cycle W disabled.
The K7I323684M and K7I321884M support byte write operations.
With activating BW0 or BW1 ( BW2 or BW3 ) in write cycle, only one byte of input data is presented.
In K7I321884M, BW0 controls write operation to D0:D8, BW1 controls write operation to D9:D17.
And in K7I323684M BW2 controls write operation to D18:D26, BW3 controls write operation to D27:D35.
The the K7I320884M support nybble write operations.
In K7I320884M, NW0 controls write operation to D0:D3, NW 1 controls write operation to D4:D7.
Programmable Impedance Output Buffer Operation
The designer can program the SRAM's output buffer impedance by terminating the ZQ pin to VSS through a precision resistor(RQ).
The value of RQ (within 15%) is five times the output impedance desired.
For example, 250W resistor will give an output impedance of 50W.
Impedance updates occur early in cycles that do not activate the outputs, such as deselect cycles.
In all cases impedance updates are transparent to the user and do not produce access time "push-outs" or other anomalous behav-
ior in the SRAM.
There are no power up requirements for the SRAM. However, to guarantee optimum output driver impedance after power up, the
SRAM needs 1024 non-read cycles.
Clock Consideration
K7I323684M, K7I321884M and K7I320884M utilize internal DLL(Delay-Locked Loops) for maximum output data valid window.
It can be placed into a stopped-clock state to minimize power with a modest restart time of 1024 clock cycles.
Circuitry automatically resets the DLL when absence of input clock is detected.
Single Clock Mode
K7I323684M, K7I321884M and K7I320884M can be operated with the single clock pair K and K,
insted of C or C for output clocks.
To operate these devices in single clock mode, C and C must be tied high during power up and must be maintained high
during operation.
After power up, this device can ¢t change to or from single clock mode.
System flight time and clock skew could not be compensated in this mode.
Depth Expansion
Each port can be selected and deselected independently with R/W be shared among all SRAMs and provide a new LD signal
for each bank.
Before chip deselected, all read and write pending operations are completed.
Dec. 2002
Rev 0.5
- 7 -
K7I323684M
K7I321884M
K7I320884M
Preliminary
1Mx36 & 2Mx18 & 4Mx8 DDRII CIO b4 SRAM
LINEAR BURST SEQUENCE TABLE
Case 1
Case 2
Case 3
Case 4
BURST SEQUENCE
SA1
SA0
SA1
SA0
SA1
SA0
SA1
SA0
First Address
0
0
1
1
0
1
0
1
0
1
1
0
1
0
1
0
1
1
0
0
0
1
0
1
1
0
0
1
1
0
1
0
Fourth Address
STATE DIAGRAM
POWER-UP
LOAD
NOP
LOAD
LOAD NEW ADDRESS
Dcount = 0
LOAD
Dcount = 2
LOAD
READ
WRITE
Dcount = 2
LOAD
LOAD
DDR READ
Dcount=Dcount+1
DDR WRITE
Dcount=Dcount+1
READ
Dcount = 1
WRITE
Dcount = 1
ALWAYS
ALWAYS
INCREMENT
READ ADDRESS
INCREMENT
WRITE ADDRESS
Notes: 1. Internal burst counter is fixed as 4-bit linear, i.e. when first address is A0+0, next internal burst address is A0+1.
2. "LOAD" refers to read new address active status with LD=Low, "LOAD" refers to read new address inactive status with LD=High.
3. "READ" refers to read active read status with R/W=High, "WRITE" refers to write active status with R/W=Low
Dec. 2002
Rev 0.5
- 8 -
K7I323684M
K7I321884M
K7I320884M
Preliminary
1Mx36 & 2Mx18 & 4Mx8 DDRII CIO b4 SRAM
TRUTH TABLES
SYNCHRONOUS TRUTH TABLE
Q
K
LD
R/W
OPERATION
Q(A0)
Q(A1)
Q(A2)
Q(A3)
Previous
state
Previous
state
Previous
state
Previous
state
Stopped
X
H
L
X
X
H
L
Clock Stop
No Operation
Read
•
•
•
High-Z
High-Z
High-Z
High-Z
QOUT at
C(t+1)
QOUT at
C(t+2)
QOUT at
C(t+2)
QOUT at
C(t+3)
L
Din at K(t+1) Din at K(t+1) Din at K(t+2) Din at K(t+2)
Write
Notes: 1. X means "Don¢t Care".
2. The rising edge of clock is symbolized by ( • ).
WRITE TRUTH TABLE(x18)
K
K
BW0
L
BW1
L
OPERATION
•
WRITE ALL BYTEs ( K• )
WRITE ALL BYTEs ( K• )
WRITE BYTE 0 ( K• )
WRITE BYTE 0 ( K• )
WRITE BYTE 1 ( K• )
WRITE BYTE 1 ( K• )
WRITE NOTHING ( K• )
WRITE NOTHING ( K• )
•
L
L
•
•
•
L
H
•
L
H
H
L
•
H
L
H
H
•
H
H
Notes: 1. X means "Don¢t Care".
2. All inputs in this table must meet setup and hold time around the rising edge of input clock K or K ( • ).
3. Assumes a WRITE cycle was initiated.
4. This table illustates operation for x18 devices. x8 device operation is similar except that NW0 controls D0:D3 and NW 0 controls D4:D7.
WRITE TRUTH TABLE(x36)
K
K
BW0
L
BW 1
L
BW2
L
BW 3
L
OPERATION
WRITE ALL BYTEs ( K • )
WRITE ALL BYTEs ( K• )
WRITE BYTE 0 ( K• )
•
•
L
L
L
L
•
•
•
•
L
H
H
H
H
H
L
H
•
L
H
H
WRITE BYTE 0 ( K• )
H
H
H
H
H
H
L
H
WRITE BYTE 1 ( K• )
•
L
H
WRITE BYTE 1 ( K• )
H
L
WRITE BYTE 2 and BYTE 3 ( K• )
WRITE BYTE 2 and BYTE 3 ( K• )
WRITE NOTHING ( K• )
WRITE NOTHING ( K• )
•
H
L
L
H
H
H
H
•
H
H
Notes: 1. X means "Don¢t Care".
2. All inputs in this table must meet setup and hold time around the rising edge of input clock K or K ( • ).
3. Assumes a WRITE cycle was initiated.
Dec. 2002
Rev 0.5
- 9 -
K7I323684M
K7I321884M
K7I320884M
Preliminary
1Mx36 & 2Mx18 & 4Mx8 DDRII CIO b4 SRAM
ABSOLUTE MAXIMUM RATINGS*
PARAMETER
Voltage on VDD Supply Relative to VSS
Voltage on VDDQ Supply Relative to VSS
Voltage on Input Pin Relative to VSS
Power Dissipation
SYMBOL
VDD
RATING
-0.5 to 2.9
-0.5 to VDD
-0.5 to VDD+0.3
TBD
UNIT
V
VDDQ
VIN
V
V
PD
W
Storage Temperature
TSTG
TOPR
TBIAS
-65 to 150
0 to 70
°C
°C
°C
Operating Temperature
Storage Temperature Range Under Bias
-10 to 85
*Note: 1. Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating
only and functional operation of the device at these or any other conditions above those indicated in the operating sections of this specification
is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
2. VDDQ must not exceed VDD during normal operation.
DC ELECTRICAL CHARACTERISTICS(VDD=1.8V ±0.1V, TA=0°C to +70°C)
PARAMETER
Input Leakage Current
Output Leakage Current
SYMBOL
TEST CONDITIONS
VDD=Max ; VIN=VSS to VDDQ
Output Disabled,
MIN
MAX
+2
UNIT NOTES
IIL
-2
-2
-
mA
mA
IOL
+2
-25
-20
-16
-13
-25
-20
-16
-13
-25
-20
-16
-13
-25
-20
-16
-13
620
520
440
360
560
470
410
350
540
450
390
350
200
180
160
140
-
VDD=Max , IOUT=0mA
Operating Current (x36): DDR
Operating Current (x18): DDR
Operating Current (x8): DDR
Standby Current(NOP): DDR
ICC
ICC
ICC
ISB1
mA
mA
mA
mA
1,5
1,5
1,5
1,6
Cycle Time ³ tKHKH Min
-
-
-
-
-
-
-
-
VDD=Max , IOUT=0mA
Cycle Time ³ tKHKH Min
VDD=Max , IOUT=0mA
Cycle Time ³ tKHKH Min
-
-
-
-
Device deselected, IOUT=0mA,
f=Max,
All Inputs£0.2V or ³ VDD-0.2V
Output High Voltage
Output Low Voltage
Output High Voltage
Output Low Voltage
Input Low Voltage
Input High Voltage
VOH1
VOL1
VOH2
VOL2
VIL
VDDQ/2-0.12 VDDQ/2+0.12
VDDQ/2-0.12 VDDQ/2+0.12
V
V
V
V
V
V
2,7
3,7
4
IOH=-1.0mA
IOL=1.0mA
VDDQ -0.2
VSS
VDDQ
0.2
4
-0.3
VREF-0.1
VDDQ+0.3
8,9
8,10
VIH
VREF+0.1
Notes: 1. Minimum cycle. IOUT=0mA.
2. |IOH|=(VDDQ/2)/(RQ/5) for 175W £ RQ £ 350W.
3. |IOL|=(VDDQ/2)/(RQ/5) for 175W £ RQ £ 350W.
4. Minimum Impedance Mode when ZQ pin is connected to VDD.
5. Operating current is calculated with 50% read cycles and 50% write cycles.
6. Standby Current is only after all pending read and write burst opeactions are completed.
7. Programmable Impedance Mode.
8. These are DC test criteria. DC design criteria is VREF±50mV. The AC VIH/VIL levels are defined separately for measuring
timing parameters.
9. VIL (Min)DC=-0.3V, VIL (Min)AC=-1.5V(pulse width £ 3ns).
10. VIH (Max)DC=VDDQ +0.3, VIH (Max)AC=VDDQ +0.85V(pulse width £ 3ns).
Dec. 2002
Rev 0.5
- 10 -
K7I323684M
K7I321884M
K7I320884M
Preliminary
1Mx36 & 2Mx18 & 4Mx8 DDRII CIO b4 SRAM
AC ELECTRICAL CHARACTERISTICS (VDD=1.8V ±0.1V, TA=0°C to +70°C)
PARAMETER
Input High Voltage
Input Low Voltage
MAX
UNIT
NOTES
1,2
SYMBOL
VIH (AC)
VIL (AC)
MIN
VREF + 0.2
-
-
V
V
VREF - 0.2
1,2
Notes: 1. This condition is for AC function test only, not for AC parameter test.
2. To maintain a valid level, the transitioning edge of the input must :
a) Sustain a constant slew rate from the current AC level through the target AC level, VIL(AC) or VIH(AC)
b) Reach at least the target AC level
c) After the AC target level is reached, continue to maintain at least the target DC level, VIL(DC) or VIH(DC)
Overershoot Timing
Undershoot Timing
20% tKHKH(MIN)
VIH
VDDQ+0.5V
VDDQ+0.25V
VSS
VDDQ
VSS-0.25V
VSS-0.5V
20% tKHKH(MIN)
VIL
Note: For power-up, VIH £ VDDQ+0.3V and VDD £ 1.7V and VDDQ £ 1.4V t £ 200ms
OPERATING CONDITIONS (0°C £ TA £ 70°C)
PARAMETER
SYMBOL
MIN
1.7
1.4
0.68
0
MAX
1.9
1.9
0.95
0
UNIT
VDD
V
V
V
V
Supply Voltage
VDDQ
VREF
VSS
Reference Voltage
Ground
AC TEST CONDITIONS
Parameter
Symbol
VDD
Value
1.7~1.9
1.4~1.9
1.25/0.25
0.75
Unit
V
AC TEST OUTPUT LOAD
Core Power Supply Voltage
Output Power Supply Voltage
Input High/Low Level
VDDQ
VIH/VIL
VREF
V
0.75V
VREF
VDDQ/2
V
Input Reference Level
V
50W
SRAM
Zo=50W
Input Rise/Fall Time
TR/TF
0.3/0.3
VDDQ/2
ns
V
Output Timing Reference Level
250W
ZQ
Note: Parameters are tested with RQ=250W
Dec. 2002
Rev 0.5
- 11 -
K7I323684M
K7I321884M
K7I320884M
Preliminary
1Mx36 & 2Mx18 & 4Mx8 DDRII CIO b4 SRAM
AC TIMING CHARACTERISTICS(VDD=1.8V±0.1V, TA=0°C to +70°C)
-25
-20
-16
MAX
-13
MAX
PARAMETER
SYMBOL
UNITS NOTES
MIN
MAX
MIN
MAX
MIN
MIN
Clock
Clock Cycle Time (K, K, C, C)
Clock Phase Jitter (K, K, C, C)
Clock High Time (K, K, C, C)
Clock Low Time (K, K, C, C)
Clock to Clock (K• ® K• , C• ® C• )
Clock to data clock (K• ® C• , K• ® C• )
DLL Lock Time (K, C)
tKHKH
tKC var
tKHKL
4.00
5.25
0.20
5.00
6.30
0.20
6.00
7.88
0.20
7.50
8.40
0.20
ns
ns
ns
5
6
1.60
1.60
1.80
0.00
1024
30
2.00
2.00
2.20
0.00
1024
30
2.40
2.40
2.70
0.00
1024
30
3.00
3.00
3.38
0.00
1024
30
tKLKH
ns
tKHKH
2.20
1.80
2.75
2.30
3.30
2.80
4.13
3.55
ns
tKHCH
tKC lock
tKC reset
ns
cycle
ns
K Static to DLL reset
Output Times
C, C High to Output Valid
C, C High to Output Hold
tCHQV
tCHQX
0.45
0.45
0.30
0.45
0.45
0.45
0.35
0.45
0.50
0.50
0.40
0.50
0.50
0.50
0.40
0.50
ns
ns
ns
ns
ns
ns
ns
ns
3
3
-0.45
-0.45
-0.30
-0.45
-0.45
-0.45
-0.35
-0.45
-0.50
-0.50
-0.40
-0.50
-0.50
-0.50
-0.40
-0.50
C, C High to Echo Clock Valid
C, C High to Echo Clock Hold
CQ, CQ High to Output Valid
CQ, CQ High to Output Hold
C, High to Output High-Z
tCHCQV
tCHCQX
tCQHQV
tCQHQX
tCHQZ
7
7
3
3
C, High to Output Low-Z
tCHQX1
Setup Times
Address valid to K rising edge
Control inputs valid to K rising edge
Data-in valid to K, K rising edge
Hold Times
tAVKH
tIVKH
0.50
0.50
0.35
0.60
0.60
0.40
0.70
0.70
0.50
0.70
0.70
0.50
ns
ns
ns
2
tDVKH
K rising edge to address hold
K rising edge to control inputs hold
K, K rising edge to data-in hold
tKHAX
tKHIX
0.50
0.50
0.35
0.60
0.60
0.40
0.70
0.70
0.50
0.70
0.70
0.50
ns
ns
ns
tKHDX
Notes: 1. All address inputs must meet the specified setup and hold times for all latching clock edges.
2. Control singles are R, W,BW0,BW1 and (NW0, NW1, for x8) and (BW2, BW3, also for x36)
3. If C,C are tied high, K,K become the references for C,C timing parameters.
4. To avoid bus contention, at a given voltage and temperature tCHQX1 is bigger than tCHQZ.
The specs as shown do not imply bus contention beacuse tCHQX1 is a MIN parameter that is worst case at totally different test conditions
(0°C, 1.9V) than tCHQZ, which is a MAX parameter(worst case at 70°C, 1.7V)
It is not possible for two SRAMs on the same board to be at such different voltage and temperature.
5. Clock phase jitter is the variance from clock rising edge to the next expected clock rising edge.
6. Vdd slew rate must be less than 0.1V DC per 50 ns for DLL lock retention. DLL lock time begins once Vdd and input clock are stable.
7. Echo clock is very tightly controlled to data valid/data hold. By design, there is a ± 0.1ns variation from echo clock to data.
The data sheet parameters reflect tester guardbands and test setup variations.
Dec. 2002
Rev 0.5
- 12 -
K7I323684M
K7I321884M
K7I320884M
Preliminary
1Mx36 & 2Mx18 & 4Mx8 DDRII CIO b4 SRAM
PIN CAPACITANCE
PRMETER
Address Control Input Capacitance
Input and Output Capacitance
Clock Capacitance
SYMBOL
CIN
TESTCONDITION
Typ
4
MAX
Unit
pF
NOTES
VIN=0V
VOUT=0V
-
5
7
6
COUT
6
pF
CCLK
5
pF
Note: 1. Parameters are tested with RQ=250Wand VDDQ=1.5V.
2. Periodically sampled and not 100% tested.
THERMAL RESISTANCE
PRMETER
Junction to Ambient
SYMBOL
TYP
TBD
TBD
TBD
Unit
NOTES
qJA
qJC
qJB
°C/W
°C/W
°C/W
Junction to Case
Junction to Pins
Note: Junction temperature is a function of on-chip power dissipation, package thermal impedance, mounting site temperature and mounting site
thermal impedance. TJ=TA + PD x qJA
APPLICATION INRORMATION
2Mx18
SRAM#1
SRAM#4
R=250W
R=250W
ZQ
DQ0-17
ZQ
DQ0-17
Vt
SA
SA
R/W LD0BW0 BW1C C K K
R/WLD3BW0BW1 C C K K
R
DQ
Vt
Address
R/W
R
LD0-3
BW0-7
MEMORY
CONTROLLER
Return CLK
Source CLK
Return CLK
Source CLK
R=50W Vt=VREF
Dec. 2002
Rev 0.5
- 13 -
K7I323684M
K7I321884M
K7I320884M
Preliminary
1Mx36 & 2Mx18 & 4Mx8 DDRII CIO b4 SRAM
TIMING WAVE FORMS OF READ, WRITE AND NOP
NOP
READ
(burst of 4)
READ
(burst of 4)
NOP
NOP
(Note3)
WRITE
(burst of 4)
READ
(burst of 4)
9
1
2
5
4
6
7
8
10
11
12
3
K
K
tKHKL
tKHKH
tKH KH
tKLKH
tIVKH
tKHIX
LD
R/W
A2
A0
A1
A3
SA
tKHDX
tDVKH
tAVKH
tKHAX
DQ
Q01
Q02
Q03
Q04
Q11
Q12
Q13
Q14
D21
D22
D23
D24
Q31
Q32
Q33
tCHQX
tCQHQX
tCHQZ
tCHQV
tCHQX1
tCQHQV
tKHCH
C
C
tKHKH
tKHKL
tCQHQZ
tKLKH
tKHKH
tCHCQH
CQ
CQ
DON¢T CARE
UNDEFINED
NOTE
1. Q01 refers to output from address A. Q02 refers to output from the next internal burst address following A, etc.
2. Outputs are disabled(High-Z) one clock cycle after a NOP .
3. The second NOP cycle is not necessary for correct device operation; however, at high clock frequencies, it may be required toprevent
bus contention.
Dec. 2002
Rev 0.5
- 14 -
K7I323684M
K7I321884M
K7I320884M
Preliminary
1Mx36 & 2Mx18 & 4Mx8 DDRII CIO b4 SRAM
IEEE 1149.1 TEST ACCESS PORT AND BOUNDARY SCAN-JTAG
This part contains an IEEE standard 1149.1 Compatible Test Access Port(TAP). The package pads are monitored by the Serial Scan
circuitry when in test mode. This is to support connectivity testing during manufacturing and system diagnostics. Internal data is not
driven out of the SRAM under JTAG control. In conformance with IEEE 1149.1, the SRAM contains a TAP controller, Instruction Reg-
ister, Bypass Register and ID register. The TAP controller has a standard 16-state machine that resets internally upon power-up,
therefore, TRST signal is not required. It is possible to use this device without utilizing the TAP. To disable the TAP controller without
interfacing with normal operation of the SRAM, TCK must be tied to VSS to preclude mid level input. TMS and TDI are designed so an
undriven input will produce a response identical to the application of a logic 1, and may be left unconnected. But they may also be
tied to VDD through a resistor. TDO should be left unconnected.
JTAG Block Diagram
JTAG Instruction Coding
IR2 IR1 IR0 Instruction
TDO Output
Notes
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
EXTEST
Boundary Scan Register
Identification Register
Boundary Scan Register
1
3
2
6
5
6
6
4
IDCODE
SAMPLE-Z
RESERVED Do Not Use
SAMPLE
Boundary Scan Register
RESERVED Do Not Use
RESERVED Do Not Use
SRAM
CORE
BYPASS
Bypass Register
NOTE :
1. Places DQs in Hi-Z in order to sample all input data regardless of other
SRAM inputs. This instruction is not IEEE 1149.1 compliant.
TDI
BYPASS Reg.
TDO
2. Places DQs in Hi-Z in order to sample all input data regardless of other
SRAM inputs.
Identification Reg.
Instruction Reg.
3. TDI is sampled as an input to the first ID register to allow for the serial shift
of the external TDI data.
4. Bypass register is initiated to VSS when BYPASS instruction is invoked. The
Bypass Register also holds serially loaded TDI when exiting the Shift DR
states.
Control Signals
TAP Controller
TMS
TCK
5. SAMPLE instruction dose not places DQs in Hi-Z.
6. This instruction is reserved for future use.
TAP Controller State Diagram
1
0
Test Logic Reset
0
1
1
0
1
Run Test Idle
Select DR
0
Select IR
0
1
1
1
1
Capture DR
0
Capture IR
0
0
Shift DR
1
Shift IR
1
Exit1 DR
0
Exit1 IR
0
0
0
0
0
Pause DR
1
Pause IR
1
Exit2 DR
1
Exit2 IR
1
1
0
Update DR
0
Update IR
1
Dec. 2002
Rev 0.5
- 15 -
K7I323684M
K7I321884M
K7I320884M
Preliminary
1Mx36 & 2Mx18 & 4Mx8 DDRII CIO b4 SRAM
SCAN REGISTER DEFINITION
Part
1Mx36
2Mx18
4Mx8
Instruction Register
Bypass Register
ID Register
32 bits
Boundary Scan
109 bits
3 bits
3 bits
3 bits
1 bit
1 bit
1 bit
32 bits
109 bits
32 bits
109 bits
ID REGISTER DEFINITION
Revision Number
Part Configuration
(28:12)
Samsung JEDEC Code
(11: 1)
Part
Start Bit(0)
(31:29)
1Mx36
2Mx18
000
00def0wx0t0q0b0s0
00def0wx0t0q0b0s0
00def0wx0t0q0b0s0
00001001110
00001001110
00001001110
1
1
1
000
4Mx8
000
Note : Part Configuration
/def=010 for 32Mb, /wx=11 for x36, 10 for x18, 01 for x8
/t=1 for DLL Ver., 0 for non-DLL Ver. /q=1 for DDR, 0 for DDR /b=1 for 4Bit Burst, 0 for 2Bit Burst /s=1 for Separate I/O, 0 for Common I/O
BOUNDARY SCAN EXIT ORDER
ORDER
PIN ID
ORDER
PIN ID
ORDER
73
PIN ID
2C
3E
2D
2E
1E
2F
1
6R
6P
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
10D
9E
74
2
75
3
6N
10C
11D
9C
9D
11B
11C
9B
76
4
7P
77
5
7N
78
6
7R
79
3F
7
8R
80
1G
1F
8
8P
81
9
9R
82
3G
2G
1H
1J
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
11P
10P
10N
9P
10B
11A
10A
9A
83
84
85
86
2J
10M
11N
9M
8B
87
3K
3J
7C
6C
8A
88
89
2K
1K
2L
9N
90
11L
11M
9L
7A
91
7B
92
3L
6B
93
1M
1L
10L
11K
10K
9J
6A
94
5B
95
3N
3M
1N
2M
3P
2N
2P
1P
3R
4R
4P
5P
5N
5R
Internal
5A
96
4A
97
9K
5C
4B
98
10J
11J
11H
10G
9G
99
3A
100
101
102
103
104
105
106
107
108
109
2A
1A
2B
11F
11G
9F
3B
1C
1B
10F
11E
10E
3D
3C
1D
Note: 1. NC pins are read as "X" ( i.e. don¢t care.)
Dec. 2002
Rev 0.5
- 16 -
K7I323684M
K7I321884M
K7I320884M
Preliminary
1Mx36 & 2Mx18 & 4Mx8 DDRII CIO b4 SRAM
JTAG DC OPERATING CONDITIONS
Parameter
Power Supply Voltage
Symbol
Min
TBD
TBD
TBD
TBD
TBD
Typ
Max
TBD
TBD
TBD
TBD
TBD
Unit
V
Note
VDD
VIH
VIL
TBD
Input High Level
-
-
-
-
V
Input Low Level
V
Output High Voltage(IOH=-2mA)
Output Low Voltage(IOL=2mA)
VOH
VOL
V
V
Note: 1. The input level of SRAM pin is to follow the SRAM DC specification.
JTAG AC TEST CONDITIONS
Parameter
Input High/Low Level
Symbol
VIH/VIL
TR/TF
Min
Unit
V
Note
TBD
TBD
TBD
Input Rise/Fall Time
ns
V
Input and Output Timing Reference Level
Note: 1. See SRAM AC test output load on page 11.
1
JTAG AC Characteristics
Parameter
TCK Cycle Time
Symbol
Min
Max
Unit
Note
tCHCH
tCHCL
tCLCH
tMVCH
tCHMX
tDVCH
tCHDX
tSVCH
tCHSX
tCLQV
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
TCK High Pulse Width
TCK Low Pulse Width
TMS Input Setup Time
TMS Input Hold Time
TDI Input Setup Time
TDI Input Hold Time
-
-
-
-
-
-
SRAM Input Setup Time
SRAM Input Hold Time
Clock Low to Output Valid
-
-
TBD
JTAG TIMING DIAGRAM
TCK
tCHCH
tCHCL
tCLCH
tMVCH
tCHMX
TMS
TDI
tDVCH
tSVCH
tCHDX
tCHSX
PI
(SRAM)
tCLQV
TDO
Dec. 2002
Rev 0.5
- 17 -
K7I323684M
K7I321884M
K7I320884M
Preliminary
1Mx36 & 2Mx18 & 4Mx8 DDRII CIO b4 SRAM
165 FBGA PACKAGE DIMENSIONS
15mm x 17mm Body, 1.0mm Bump Pitch, 11x15 Ball Array
B
Top View
A
C
Side View
D
A
G
E
B
F
Bottom View
H Æ
E
Symbol
Value
15 ± 0.1
17 ± 0.1
1.3 ± 0.1
0.35 ± 0.05
Units
Note
Symbol
Value
1.0
Units
mm
Note
A
B
C
D
mm
mm
mm
mm
E
F
14.0
mm
G
H
10.0
mm
0.45 ± 0.05
mm
Dec. 2002
Rev 0.5
- 18 -
相关型号:
K7I323682C-EC250
DDR SRAM, 1MX36, 0.45ns, CMOS, PBGA165, 15 X 17 MM, 1 MM PITCH, ROHS COMPLIANT, FBGA-165
SAMSUNG
K7I323682C-EC300
DDR SRAM, 1MX36, 0.45ns, CMOS, PBGA165, 15 X 17 MM, 1 MM PITCH, ROHS COMPLIANT, FBGA-165
SAMSUNG
K7I323682C-EC330
DDR SRAM, 1MX36, 0.45ns, CMOS, PBGA165, 15 X 17 MM, 1 MM PITCH, ROHS COMPLIANT, FBGA-165
SAMSUNG
K7I323682C-EI250
DDR SRAM, 1MX36, 0.45ns, CMOS, PBGA165, 15 X 17 MM, 1 MM PITCH, ROHS COMPLIANT, FBGA-165
SAMSUNG
K7I323682C-EI300
DDR SRAM, 1MX36, 0.45ns, CMOS, PBGA165, 15 X 17 MM, 1 MM PITCH, ROHS COMPLIANT, FBGA-165
SAMSUNG
K7I323682C-EI330
DDR SRAM, 1MX36, 0.45ns, CMOS, PBGA165, 15 X 17 MM, 1 MM PITCH, ROHS COMPLIANT, FBGA-165
SAMSUNG
©2020 ICPDF网 联系我们和版权申明