K7K3218T2C-FI33T [SAMSUNG]
Standard SRAM, 2MX18, 0.45ns, CMOS, PBGA165;型号: | K7K3218T2C-FI33T |
厂家: | SAMSUNG |
描述: | Standard SRAM, 2MX18, 0.45ns, CMOS, PBGA165 静态存储器 |
文件: | 总19页 (文件大小:401K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
K7K3236T2C
K7K3218T2C
1Mx36 & 2Mx18 DDRII+ CIO b2 SRAM
36Mb DDRII+ SRAM Specification
165 FBGA with Pb & Pb-Free
(RoHS compliant)
INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS,
AND IS SUBJECT TO CHANGE WITHOUT NOTICE.
NOTHING IN THIS DOCUMENT SHALL BE CONSTRUED AS GRANTING ANY LICENSE,
EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE,
TO ANY INTELLECTUAL PROPERTY RIGHTS IN SAMSUNG PRODUCTS OR TECHNOLOGY.
ALL INFORMATION IN THIS DOCUMENT IS PROVIDED
ON AS "AS IS" BASIS WITHOUT GUARANTEE OR WARRANTY OF ANY KIND.
1. For updates or additional information about Samsung products, contact your nearest Samsung office.
2. Samsung products are not intended for use in life support, critical care, medical, safety equipment, or simi-
lar applications where Product failure couldresult in loss of life or personal or physical harm, or any military
or defense application, or any governmental procurement to which special terms or provisions may apply.
* Samsung Electronics reserves the right to change products or specification without notice.
Rev. 1.3 August 2008
- 1 -
K7K3236T2C
K7K3218T2C
1Mx36 & 2Mx18 DDRII+ CIO b2 SRAM
Document Title
1Mx36-bit, 2Mx18-bit DDRTM II+ CIO b2 SRAM
Revision History
Rev. No.
History
Draft Date
Remark
0.0
1. Initial document.
Advance
Nov. 25, 2005
Dec. 12, 2005
Mar. 03, 2006
Mar. 03. 2006
Apr. 25. 2006
0.1
1. Modify the READ/WRITE timing diagram
1. Add comment Pb Free and Industrial
1. Change Max of clock cycle time
Preliminary
Preliminary
Preliminary
Preliminary
0.2
0.3
0.4
1. Change DC Characteristics, Pin Capacitance and Thermal Resis-
tance
0.5
0.6
1.0
1.1
1. Correct errors
Preliminary
Preliminary
Final
May. 03. 2006
Jun. 05, 2006
Aug. 23, 2006
Jan. 30, 2007
1. Change Samsung JEDEC Code in ID REGISTER DEFINITION
1. Correct typo
1. Change ICC measure condition
2. Change programmable impedence output buffer operation
3. Add AC Timing Characteristics
Final
1.2
1.3
1. Add AC/DC Parameter of 450MHz
1. Delete AC/DC Parameter of 450MHz
Final
Final
Mar. 16, 2007
Aug. 27, 2008
Rev. 1.3 August 2008
- 2 -
K7K3236T2C
K7K3218T2C
1Mx36 & 2Mx18 DDRII+ CIO b2 SRAM
1Mx36-bit, 2Mx18-bit DDRII CIO b2 SRAM
FEATURES
• 1.8V+0.1V/-0.1V Power Supply.
Organiza-
Part
Cycle Access
Time Time
Unit
• DLL circuitry for wide output data valid window and future
freguency scaling.
tion
Number
X36
K7K3236T2C-F(E)C(I)40
K7K3236T2C-F(E)C(I)33
K7K3218T2C-F(E)C(I)40
K7K3218T2C-F(E)C(I)33
2.5
3.0
2.5
3.0
0.45
0.45
0.45
0.45
ns
ns
ns
ns
• I/O Supply Voltage 1.5V+0.1V/-0.1V
• Pipelined, double-data rate operation.
• Common data input/output bus .
X18
• HSTL I/O
• Full data coherency, providing most current data.
• Synchronous pipeline read with self timed late write.
• Read latency : 2 clock cycles
* -F(E)C(I)
F(E) [Package type] : E-Pb Free, F-Pb
• Registered address, control and data input/output.
• DDR(Double Data Rate) Interface on read and write ports.
• Fixed 2-bit burst for both read and write operation.
• Clock-stop supports to reduce current.
• Two input clocks(K and K) for accurate DDR timing at clock
rising edges only.
C(I) [Operating Temperature] : C-Commercial, I-Industrial
• Two echo clocks (CQ and CQ) to enhance output data
traceability.
• Data Valid pin(QVLD) supported
• Single address bus.
• Byte write (x18, x36) function.
• Simple depth expansion with no data contention.
• Programmable output impedance(ZQ).
• JTAG 1149.1 compatible test access port.
• 165FBGA(11x15 ball aray FBGA) with body size of 15x17mm
FUNCTIONAL BLOCK DIAGRAM
36 (or 18)
DATA
REG
36 (or 18)
WRITE DRIVER
19
19 (or 20)
4(or 2)
(or 20)
ADD
REG
ADDRESS
LD
R/W
BWX
72
(or 36)
36 (or 18)
DQ
36
1Mx36
(2Mx18)
MEMORY
ARRAY
(or 18)
CTRL
QVLD
LOGIC
CQ, CQ
(Echo Clock out)
K
K
CLK
GEN
SELECT OUTPUT CONTROL
Doff
Notes: 1. Numbers in ( ) are for x18 device
DDR SRAM and Double Data Rate comprise a new family of products developed by Cypress, Renesas, IDT, RNEeCvan.d1S.a3msuAngutegchunoslotgy2. 008
- 3 -
K7K3236T2C
K7K3218T2C
1Mx36 & 2Mx18 DDRII+ CIO b2 SRAM
PIN CONFIGURATIONS(TOP VIEW) K7K3236T2C(1Mx36)
1
2
NC/SA*
DQ27
NC
DQ29
NC
DQ30
DQ31
VREF
NC
NC
DQ33
NC
DQ35
NC
TCK
3
4
5
6
K
K
7
8
LD
SA
VSS
9
SA
10
NC/SA*
NC
DQ17
NC
11
CQ
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
CQ
NC
NC
NC
NC
NC
NC
Doff
NC
NC
NC
NC
NC
NC
TDO
SA
R/W
SA
VSS
BW2
BW3
SA
BW1
BW0
SA
DQ18
DQ28
DQ19
DQ20
DQ21
DQ22
VDDQ
DQ32
DQ23
DQ24
DQ34
DQ25
DQ26
SA
NC
NC
NC
NC
NC
NC
VDDQ
NC
NC
NC
NC
NC
NC
SA
DQ8
DQ7
DQ16
DQ6
DQ5
DQ14
ZQ
NC
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
SA
VSS
VSS
VSS
VDD
VDD
VDD
VDD
VDD
VSS
VSS
SA
VSS
VSS
VDD
VDD
VDD
VDD
VDD
VSS
VSS
SA
VSS
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VSS
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VSS
DQ15
NC
NC
VREF
DQ13
DQ12
NC
DQ11
NC
DQ4
DQ3
DQ2
DQ1
DQ10
DQ0
TDI
VSS
VSS
SA
SA
SA
SA
QVLD
NC
SA
SA
DQ9
TMS
SA
SA
Notes : 1. * Checked No Connect(NC) pins are reserved for higher density address, i.e. 10A for 72Mb, 2A for 144Mb .
2. BW0 controls write to DQ0:DQ8, BW1 controls write to DQ9:DQ17, BW2 controls write to DQ18:DQ26 and BW3 controls write to DQ27:DQ35.
PIN NAME
SYMBOL
PIN NUMBERS
DESCRIPTION
Input Clock
Q Valid output
Output Echo Clock
DLL Disable
NOTE
K, K
QVLD
CQ, CQ
Doff
6B, 6A
6P
11A, 1A
1H
SA
3A,9A,4B,8B,5C,7C,5N-7N,4P,5P,7P,8P,3R-5R,7R-9R
Address Inputs
2B,3B,11B,3C,10C,11C,2D,3D,11D,3E,10E,11E,2F,3F
11F,2G,3G,11G,3J,10J,11J,3K,10K,11K,2L,3L,11L
3M,10M,11M,2N,3N,11N,3P,10P,11P
DQ0-35
Data Inputs Outputs
Read, Write Control Pin, Read active
when high
R/W
LD
4A
8A
Synchronous Load Pin, bus Cycle
sequence is to be defined when low
BW0, BW1,BW2, BW3
7B,7A,5A,5B
2H,10H
11H
Block Write Control Pin,active when low
Input Reference Voltage
Output Driver Impedance Control Input
Power Supply ( 1.8 V )
VREF
ZQ
VDD
1
5F,7F,5G,7G,5H,7H,5J,7J,5K,7K
4E,8E,4F,8F,4G,8G,3H,4H,8H,9H,4J,8J,4K,8K,4L,8L
VDDQ
Output Power Supply ( 1.5V )
4C,8C,4D-8D,5E-7E,6F,6G,6H,6J,6K,5L-7L,
4M-8M,4N,8N
VSS
Ground
TMS
TDI
TCK
TDO
10R
11R
2R
JTAG Test Mode Select
JTAG Test Data Input
JTAG Test Clock
1R
JTAG Test Data Output
2A,10A,1B,9B,10B,1C,2C,6C,9C,1D,9D,10D,1E,2E,9E,
1F,9F,10F,1G,9G,10G,1J,2J,9J,1K,2K,9K
NC
No Connect
2
1L,9L,10L,1M,2M,9M,1N,9N,10N,1P,2P,9P,6R
Notes:
1. When ZQ pin is directly connected to VDD output impedance is set to minimum value and it cannot be connected to ground or left unconnected
.
2. Not connected to chip pad internally.
3. K, K can not be set to VREF voltage.
Rev. 1.3 August 2008
- 4 -
K7K3236T2C
K7K3218T2C
1Mx36 & 2Mx18 DDRII+ CIO b2 SRAM
PIN CONFIGURATIONS(TOP VIEW) K7K3218T2C(2Mx18)
1
2
NC/SA*
DQ9
NC
3
4
5
6
K
7
NC
BW0
SA
8
LD
SA
VSS
9
SA
10
SA
NC
DQ7
NC
NC
NC
NC
VREF
DQ4
NC
NC
DQ1
NC
NC
TMS
11
CQ
DQ8
NC
A
B
C
D
E
F
CQ
NC
NC
NC
NC
NC
NC
Doff
NC
NC
NC
NC
NC
NC
TDO
SA
NC
NC
R/W
SA
VSS
BW1
NC
SA
K
NC
NC
NC
NC
NC
NC
VDDQ
NC
NC
NC
NC
NC
NC
SA
NC
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
SA
NC
NC
DQ12
NC
VREF
NC
NC
DQ15
NC
NC
NC
DQ10
DQ11
NC
DQ13
VDDQ
NC
DQ14
NC
NC
VSS
VSS
VSS
VDD
VDD
VDD
VDD
VDD
VSS
VSS
SA
VSS
VSS
VDD
VDD
VDD
VDD
VDD
VSS
VSS
SA
VSS
NC
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VSS
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VSS
DQ6
DQ5
NC
ZQ
NC
DQ3
DQ2
NC
NC
DQ0
TDI
G
H
J
K
L
M
N
P
R
DQ16
DQ17
SA
VSS
SA
SA
VSS
SA
SA
SA
SA
QVLD
NC
SA
SA
TCK
Notes: 1. * Checked No Connect(NC) pins are reserved for higher density address, i.e. 2A for 72Mb.
2. BW0 controls write to DQ0:DQ8 and BW1 controls write to DQ9:DQ17.
PIN NAME
SYMBOL
K, K
PIN NUMBERS
DESCRIPTION
Input Clock
NOTE
6B, 6A
QVLD
CQ, CQ
Doff
6P
11A, 1A
1H
Q Valid output
Output Echo Clock
DLL Disable
SA
3A,9A,10A,4B,8B,5C,7C,5N-7N,4P,5P,7P,8P,3R-5R,7R-9R
Address Inputs
2B,11B,10C,3D,3E,11E,2F,11F,3G,10J,3K,11K,2L,11L
10M,3N,3P,11P
DQ0-17
Data Inputs Outputs
Read, Write Control Pin, Read active
when high
R/W
4A
8A
Synchronous Load Pin, bus Cycle
sequence is to be defined when low
LD
BW0, BW1
VREF
7B, 5A
2H,10H
11H
Block Write Control Pin,active when low
Input Reference Voltage
Output Driver Impedance Control Input
Power Supply ( 1.8 V )
ZQ
VDD
1
5F,7F,5G,7G,5H,7H,5J,7J,5K,7K
VDDQ
VSS
4E,8E,4F,8F,4G,8G,3H,4H,8H,9H,4J,8J,4K,8K,4L,8L
Output Power Supply ( 1.5V )
Ground
4C,8C,4D-8D,5E-7E,6F,6G,6H,6J,6K,5L-7L,4M-8M,4N,8N
TMS
TDI
TCK
TDO
10R
11R
2R
JTAG Test Mode Select
JTAG Test Data Input
JTAG Test Clock
1R
JTAG Test Data Output
2A,7A,1B,3B,5B,9B,10B,1C,2C,3C,6C,9C,11C,1D,2D,9D,10D
11D,1E,2E,9E,10E,1F,3F,9F,10F,1G,2G,9G,10G,11G
1J,2J,3J,9J,11J,1K,2K,9K,10K,1L,3L,9L,10L
NC
No Connect
2
1M,2M,3M,9M,11M,1N,2N,9N,10N,11N,1P,2P,9P,10P,6R
Notes:
1. When ZQ pin is directly connected to VDD output impedance is set to minimum value and it cannot be connected to ground or left unconnected
.
2. Not connected to chip pad internally.
3. K, K can not be set to VREF voltage.
Rev. 1.3 August 2008
- 5 -
K7K3236T2C
K7K3218T2C
1Mx36 & 2Mx18 DDRII+ CIO b2 SRAM
GENERAL DESCRIPTION
The K7K3236T2C and K7K3218T2C are 37,748,736-bits DDR Common I/O Synchronous Pipelined Burst SRAMs. They are orga-
nized as 1,048,576 words by 36bits for K7K3236T2C and 2,097,152 words by 18 bits for K7K3218T2C .
Address, data inputs, and all control signals are synchronized to the input clock ( K or K ). Read data are referenced to echo clock (
CQ or CQ ) outputs. Read address and write address are registered on rising edges of the input K clocks. Common address bus is
used to access address both for read and write operations. The internal burst counter is fixed to 2-bit sequential for both read and
write operations. Synchronous pipeline read and late write enable high speed operations. Simple depth expansion is accomplished
by using LD for port selection. Byte write operation is supported with BW0 and BW1 ( BW2 and BW3) pins for x18 ( x36 ) device.
IEEE 1149.1 serial boundary scan (JTAG) simplifies monitoriing package pads attachment status with system.
The K7K3236T2C and K7K3218T2C are implemented with SAMSUNG's high performance 6T CMOS technology and is available in
165pin FBGA packages. Multiple power and ground pins minimize ground bounce.
Read Operations
Read cycles are initiated by initiating R/W as high at the rising edge of the positive input clock K. Address is presented and stored in
the read address register synchronized with K clock. For 2-bit burst DDR operation, it will access two 36-bit or 18-bit data words with
each read command.
The first pipelined data is transfered out of the device triggered by K clock rising edge. Next burst data is triggered by the rising edge
of following K clock rising edge. Continuous read operations are initated with K clock rising edge. And pipelined data are transferred
out of device on every rising edge of both K and K clocks. Initial read data latency is 2 clock cycles when DLL is on.
When the LD is disabled after a read operation, the K7K3236T2C and K7K3218T2C will first complete burst read operation before
entering into deselect mode at the next K clock rising edge. Then output drivers disabled automatically to high impedance state.
Write Operations
Write cycles are initiated by activating R/W as low at the rising edge of the positive input clock K. Address is presented and stored in
the write address register synchronized with next K clock. For 2-bit burst DDR operation, it will write two 36-bit or 18-bit data words
with each write command.
The first "late writed" data is transfered and registered in to the device synchronous with next K clock rising edge. Next burst data is
transfered and registered synchronous with following K clock rising edge. Continuous write operations are initated with K rising edge.
And "late writed" data is presented to the device on every rising edge of both K and K clocks. When the LD is disabled, the
K7K3236T2C and K7K3218T2C will enter into deselect mode.
The device disregards input data presented on the same cycle R/W disabled. The K7K3236T2C and K7K3218T2C support byte write
operations. With activating BW0 or BW1 ( BW2 or BW3 ) in write cycle, only one byte of input data is presented. In K7K3218T2C, BW0
controls write operation to D0:D8, BW1 controls write operation to D9:D17. And in K7K3236T2C, BW2 controls write operation to
D18:D26, BW3 controls write operation to D27:D35.
Rev. 1.3 August 2008
- 6 -
K7K3236T2C
K7K3218T2C
1Mx36 & 2Mx18 DDRII+ CIO b2 SRAM
Depth Expansion
Each port can be selected and deselected independently with R/W be shared among all SRAMs and provide a new LD signal for
each bank. Before chip deselected, all read and write pending operations are completed.
Programmable Impedance Output Buffer Operation
The designer can program the SRAM's output buffer impedance by terminating the ZQ pin to VSS through a precision resistor(RQ).
The allowable range of RQ is between 175Ωand 350Ω. The value of RQ (within 15%) is five times the output impedance desired. For
example, 250Ω resistor will give an output impedance of 50Ω.
Impedance updates occur early in cycles that do not activate the outputs, such as deselect cycles. In all cases impedance updates
are transparent to the user and do not produce access time "push-outs" or other anomalous behavior in the SRAM. To guarantee
optimum output driver impedance after power up, the SRAM needs 1024 non-read cycles.
Output Valid Pin (QVLD)
The Q Valid indicates valid output data. QVLD is activated half cycle before the read data for the receiver to be ready for capturing
the data. QVLD is edge aligned with CQ and CQ.
Echo clock operation
To assure the output tracibility, the SRAM provides the output Echo clock, pair of compliment clock CQ and CQ, which are synchro-
nized with internal data output. Echo clocks run free during normal operation.
The Echo clock is triggered by internal output clock signal, and transfered to external through same structures as output driver.
Power-Up/Power-Down Supply Voltage Sequencing
The following power-up supply voltage application is recommended: VSS, VDD, VDDQ, VREF, then VIN. VDD and VDDQ can be applied
simultaneously, as long as VDDQ does not exceed VDD by more than 0.5V during power-up. The following power-down supply voltage
removal sequence is recommended: VIN, VREF, VDDQ, VDD, VSS. VDD and VDDQ can be removed simultaneously, as long as VDDQ
does not exceed VDD by more than 0.5V during power-down.
Rev. 1.3 August 2008
- 7 -
K7K3236T2C
K7K3218T2C
1Mx36 & 2Mx18 DDRII+ CIO b2 SRAM
Detail Specification of Power-Up Sequence in DDRII+ SRAM
DDRII+ SRAMs must be powered up and initialized in a predefined manner to prevent undefined operations.
• Power-Up Sequence
1. Apply power and keep Doff at low state (All other inputs may be undefined)
- Apply VDD before VDDQ
- Apply VDDQ before VREF or the same time with VREF
2. Just after the stable power and clock(K,K), take Doff to be high.
3. The additional 2048 cycles of clock input is required to lock the DLL after enabling DLL
* Notes: If you want to tie up the Doff pin to High with unstable clock, then you must stop the clock for a few seconds
(Min. 30ns) to reset the DLL after it become a stable clock status.
• DLL Constraints
1. DLL uses K clock as its synchronizing input, the input should have low phase jitter which is specified as TK var.
2. The lower end of the frequency at which the DLL can operate is 120MHz.
3. If the incoming clock is unstable and the DLL is enabled, then the DLL may lock onto a wrong frequency
and this may cause the failure in the initial stage.
Power up & Initialization Sequence (Doff pin controlled)
K,K
2048 cycle
Unstable
Any
Power-Up
DLL Locking Range
Inputs Clock
Status
VDD
CLKstage
Command
must be stable
VDDQ
VREF
Doff
Power up & Initialization Sequence (Doff pin Fixed high, Clock controlled)
K,K
Min 30ns
2048 cycle
Unstable
Any
Stop Clock
Power-Up
DLL Locking Range
Inputs Clock
Status
VDD
CLKstage
Command
must be stable
VDDQ
VREF
* Notes: When the operating frequency is changed, DLL reset should be required again.
After DLL reset again, the minimum 2048 cycles of clock input is needed to lock the DLL.
Rev. 1.3 August 2008
- 8 -
K7K3236T2C
K7K3218T2C
1Mx36 & 2Mx18 DDRII+ CIO b2 SRAM
TRUTH TABLES
SYNCHRONOUS TRUTH TABLE
DQ
K
LD
R/W
OPERATION
DQ(A1)
DQ(A2)
Previous state
High-Z
Stopped
X
H
L
X
X
H
L
Previous state
High-Z
Clock Stop
No Operation
Read
↑
↑
↑
QOUT at K(t+2)
Din at K(t+1)
QOUT at K(t+2)
Din at K(t+1)
L
Write
Notes: 1. X means "Don′t Care".
2. The rising edge of clock is symbolized by ( ↑ ).
3. Before enter into clock stop status, all pending read and write operations will be completed.
WRITE TRUTH TABLE(x18)
K
K
↑
↑
↑
↑
BW0
L
BW1
L
OPERATION
↑
WRITE ALL BYTEs ( K↑ )
WRITE ALL BYTEs ( K↑ )
WRITE BYTE 0 ( K↑ )
WRITE BYTE 0 ( K↑ )
WRITE BYTE 1 ( K↑ )
WRITE BYTE 1 ( K↑ )
WRITE NOTHING ( K↑ )
WRITE NOTHING ( K↑ )
L
L
↑
↑
↑
L
H
L
H
H
L
H
L
H
H
H
H
Notes: 1. X means "Don′t Care".
2. All inputs in this table must meet setup and hold time around the rising edge of input clock K or K ( ↑ ).
3. Assumes a WRITE cycle was initiated.
4. This table illustates operation for x18 devices.
WRITE TRUTH TABLE(x36)
K
K
↑
↑
↑
↑
↑
BW0
L
BW1
L
BW2
L
BW3
L
OPERATION
↑
WRITE ALL BYTEs ( K↑ )
WRITE ALL BYTEs ( K↑ )
WRITE BYTE 0 ( K↑ )
L
L
L
L
↑
↑
↑
↑
L
H
H
L
H
H
H
H
L
H
H
H
H
L
L
WRITE BYTE 0 ( K↑ )
H
H
H
H
H
H
WRITE BYTE 1 ( K↑ )
L
WRITE BYTE 1 ( K↑ )
H
H
H
H
WRITE BYTE 2 and BYTE 3 ( K↑ )
WRITE BYTE 2 and BYTE 3 ( K↑ )
WRITE NOTHING ( K↑ )
WRITE NOTHING ( K↑ )
L
L
H
H
H
H
Notes: 1. X means "Don′t Care".
2. All inputs in this table must meet setup and hold time around the rising edge of input clock K or K ( ↑ ).
3. Assumes a WRITE cycle was initiated.
Rev. 1.3 August 2008
- 9 -
K7K3236T2C
K7K3218T2C
1Mx36 & 2Mx18 DDRII+ CIO b2 SRAM
ABSOLUTE MAXIMUM RATINGS
PARAMETER
Voltage on VDD Supply Relative to VSS
Voltage on VDDQ Supply Relative to VSS
Voltage on Input Pin Relative to VSS
Storage Temperature
SYMBOL
VDD
RATING
-0.5 to 2.9
UNIT
V
VDDQ
VIN
-0.5 to VDD
V
-0.5 to VDD+0.3
-65 to 150
V
TSTG
TOPR
TBIAS
°C
°C
°C
Operating Temperature
Commercial / Industrial
0 to 70 / -40 to 85
-10 to 85
Storage Temperature Range Under Bias
Note: 1. Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating
only and functional operation of the device at these or any other conditions above those indicated in the operating sections of this specification
is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
OPERATING CONDITIONS (0°C ≤ TA ≤ 70°C)
PARAMETER
SYMBOL
VDD
MIN
1.7
1.4
TYP
1.8
MAX
1.9
UNIT
V
Supply Voltage
VDDQ
1.5
1.6
V
VREF
0.7
0.75
0.8
V
Reference Voltage
Input Low Voltage(DC) 2,3)
Input High Voltage(DC) 2,4)
Input Low Voltage(AC) 6,7)
Input High Voltage(AC) 6,7)
VIL(DC)
VIH(DC)
VIL(AC)
VIH(AC)
-0.3
-
-
-
-
VREF - 0.1
VDDQ + 0.3
VREF - 0.2
-
V
VREF + 0.1
-
V
V
VREF + 0.2
V
Note: 1. VDDQ must not exceed VDD during normal operation.
2. These are DC test criteria. DC design criteria is VREF±50mV. The AC VIH/VIL levels are defined separately for measuring
timing parameters.
3. VIL (Min)DC=-0.3V, VIL (Min)AC=-1.5V(pulse width ≤ 3ns).
4. VIH (Max)DC=VDDQ+0.3V, VIH (Max)AC=VDDQ+0.85V(pulse width ≤ 3ns).
5. Overshoot : VIH (AC) ≤ VDDQ+0.5V for t ≤ 50% tKHKH(MIN).
Undershoot : VIL (AC) ≤ VSS-0.5V for t ≤ 50% tKHKH(MIN).
6. This condition is for AC function test only, not for AC parameter test.
7. To maintain a valid level, the transitioning edge of the input must :
a) Sustain a constant slew rate from the current AC level through the target AC level, VIL(AC) or VIH(AC)
b) Reach at least the target AC level
c) After the AC target level is reached, continue to maintain at least the target DC level, VIL(DC) or VIH(DC)
Rev. 1.3 August 2008
- 10 -
K7K3236T2C
K7K3218T2C
1Mx36 & 2Mx18 DDRII+ CIO b2 SRAM
DC ELECTRICAL CHARACTERISTICS (VDD=1.8V ±0.1V, TA=0°C to +70°C)
PARAMETER
Input Leakage Current
Output Leakage Current
SYMBOL
TEST CONDITIONS
VDD=Max ; VIN=VSS to VDDQ
Output Disabled,
MIN
MAX
+2
UNIT NOTES
IIL
-2
-2
-
µA
µA
IOL
+2
-40
-33
-40
-33
-40
-33
900
800
900
700
350
300
VDD=Max , IOUT=0mA
Operating Current (x36): DDR
Operating Current (x18): DDR
Standby Current(NOP): DDR
ICC
ICC
mA
mA
1,4
1,4
1,5
Cycle Time ≥ tKHKH Min
-
-
VDD=Max , IOUT=0mA
Cycle Time ≥ tKHKH Min
-
-
Device deselected, IOUT=0mA, f=Max,
All Inputs≤0.2V or ≥ VDD-0.2V
ISB1
mA
-
Output High Voltage
Output Low Voltage
Output High Voltage
Output Low Voltage
VOH1
VOL1
VOH2
VOL2
VDDQ/2-0.12 VDDQ/2+0.12
VDDQ/2-0.12 VDDQ/2+0.12
V
V
V
V
2,6
2,6
3
IOH=-1.0mA
IOL=1.0mA
VDDQ-0.2
VSS
VDDQ
0.2
3
Notes: 1. Minimum cycle. IOUT=0mA.
2. |IOH|=(VDDQ/2)/(RQ/5)±15% for 175Ω ≤ RQ ≤ 350Ω. |IOL|=(VDDQ/2)/(RQ/5)±15% for 175Ω ≤ RQ ≤ 350Ω.
3. Minimum Impedance Mode when ZQ pin is connected to VDD.
4. Operating current is calculated with 100% read cycles or 100% write cycles.
5. Standby Current is only after all pending read and write burst opeactions are completed.
6. Programmable Impedance Mode.
Rev. 1.3 August 2008
- 11 -
K7K3236T2C
K7K3218T2C
1Mx36 & 2Mx18 DDRII+ CIO b2 SRAM
AC TIMING CHARACTERISTICS (VDD=1.8V±0.1V, TA=0°C to +70°C)
-40
-33
PARAMETER
SYMBOL
UNIT
NOTE
MIN
MAX
MIN
MAX
Clock
Clock Cycle Time (K, K)
Clock Phase Jitter (K, K)
Clock High Time (K, K)
tKHKH
tK var
2.5
8.4
3.0
8.4
ns
ns
0.20
0.20
4
tKHKL
tKLKH
tKHKH
tK lock
tK reset
0.4
0.4
0.4
0.4
ns
Clock Low Time (K, K)
Clock to Clock (K↑ → K↑)
ns
1.06
2048
30
1.3
ns
DLL Lock Time (K)
2048
30
cycle
ns
5
K Static to DLL reset
Output Times
K, K High to Output Valid
K, K High to Output Hold
K, K High to Echo Clock Valid
K, K High to Echo Clock Hold
CQ, CQ High to Output Valid
CQ, CQ High to Output Hold
CQ High to CQ High
tKHQV
tKHQX
0.45
0.45
0.2
0.45
0.45
0.2
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
-0.45
-0.45
-0.45
-0.45
tKHCQV
tKHCQX
tCQHQV
tCQHQX
tCQHCQH
tKHZ
-0.2
-0.2
1.1
0.86
6
2
K, K High to Output High-Z
K, K High to Output Low-Z
CQ, CQ High to QVLD Valid
Setup Times
0.45
0.2
0.45
0.2
tKLZ
-0.45
-0.2
-0.45
-0.2
tQVLD
Address valid to K rising edge
Control inputs valid to K rising edge
Data-in valid to K, K rising edge
Hold Times
tAVKH
tIVKH
tDVKH
0.40
0.40
0.28
0.40
0.40
0.28
ns
ns
ns
K rising edge to address hold
K rising edge to control inputs hold
K, K rising edge to data-in hold
tKHAX
tKHIX
0.40
0.40
0.28
0.40
0.40
0.28
ns
ns
ns
tKHDX
Notes: 1. All address inputs must meet the specified setup and hold times for all latching clock edges.
2. Control signals are R/ W and LD.
However BWx does not apply to this parameters. BWx signals obey the data setup and hold times.
3. To avoid bus contention, at a given voltage and temperature tKLZ is bigger than tKHZ.
The specs as shown do not imply bus contention because tKLZ is a MIN parameter that is worst case at totally different test conditions
(0°C, 1.9V) than tKHZ, which is a MAX parameter(worst case at 70°C, 1.7V)
It is not possible for two SRAMs on the same board to be at such different voltage and temperature.
4. Clock phase jitter is the variance from clock rising edge to the next expected clock rising edge.
5. Vdd slew rate must be less than 0.1V DC per 50 ns for DLL lock retention. DLL lock time begins once Vdd and input clock are stable.
6. This parameter is extrapolated from the input timing parameters (tKHKH - 200ps where 200ps is the internal jitter.) This parameter is only
guaranteed by design and not tested in production.
Rev. 1.3 August 2008
- 12 -
K7K3236T2C
K7K3218T2C
1Mx36 & 2Mx18 DDRII+ CIO b2 SRAM
THERMAL RESISTANCE
PRMETER
Junction to Ambient
Junction to Case
SYMBOL
θJA
TYP
20.8
2.3
Unit
°C/W
°C/W
°C/W
NOTES
θJC
Junction to Pins
θJB
4.3
Note: Junction temperature is a function of on-chip power dissipation, package thermal impedance, mounting site temperature and mounting site
thermal impedance. TJ=TA + PD x θJA
PIN CAPACITANCE
PRMETER
Address Control Input Capacitance
Input and Output Capacitance
Clock Capacitance
SYMBOL
CIN
TESTCONDITION
TYP
3.5
4
MAX
Unit
pF
NOTES
VIN=0V
VOUT=0V
-
4
5
4
COUT
pF
CCLK
3
pF
Note: 1. Parameters are tested with RQ=250Ω and VDDQ=1.5V.
2. Periodically sampled and not
AC TEST CONDITIONS
AC TEST OUTPUT LOAD
Parameter
Symbol
VDD
Value
1.7~1.9
1.4~1.6
1.25/0.25
0.75
Unit
V
Core Power Supply Voltage
Output Power Supply Voltage
Input High/Low Level
0.75V
VREF
VDDQ/2
VDDQ
VIH/VIL
VREF
V
50Ω
V
SRAM
Zo=50Ω
Input Reference Level
V
250Ω
Input Rise/Fall Time
TR/TF
0.3/0.3
VDDQ/2
ns
V
ZQ
Output Timing Reference Level
Note: Parameters are tested with RQ=250Ω
Rev. 1.3 August 2008
- 13 -
K7K3236T2C
K7K3218T2C
1Mx36 & 2Mx18 DDRII+ CIO b2 SRAM
APPLICATION INRORMATION
R=250Ω
R=250Ω
ZQ
CQ
CQ
DQ
K K
ZQ
CQ
CQ
DQ
SRAM#1
SRAM#4
Vt
SA
SA
R
R/W LD0 BW0 BW1
R/WLD3BW0BW1
K K
R
DQ
Vt
Address
R/W
LD
BW
MEMORY
CONTROLLER
Return CLK
Source CLK
Return CLK
Source CLK
R=50Ω Vt=VREF
SRAM1 Input CQ
SRAM1 Input CQ
SRAM4 Input CQ
SRAM4 Input CQ
Rev. 1.3 August 2008
- 14 -
K7K3236T2C
K7K3218T2C
1Mx36 & 2Mx18 DDRII+ CIO b2 SRAM
TIMING WAVE FORMS OF READ, WRITE AND NOP
WRITE
READ
READ
NOP
NOP
READ
NOP
WRITE
NOP
NOP
NOP
WRITE
(Note3)
9
5
1
2
4
7
6
8
10
12
11
3
K
K
t
KHKL
t
KHKH
t
KHKH
tKLKH
tIVKH
tKHIX
LD
R/W
SA
A4
A5
A6
A1
A2
A3
tQVLD
QVLD
t
KHQV
Q1-1 Q1-2
KHCQV
tKHQX
D2-1 D2-2
Q3-1 Q3-2 Q4-1 Q4-2
CQHQV
D5-1 D5-2
DQ
CQ
t
t
CQ
DON′T CARE
UNDEFINED
NOTE
1. Q1-1 refers to output from address A1. Q1-2 refers to output from the next internal burst address following A, etc.
2. Outputs are disabled(High-Z) two clock cycle after a NOP .
3. Two NOP cycle is the mandatory and 3rd NOP cycle is not necessary for correct DDRII+ READ/WRITE operation.
However at high clock frequencies, considering the delay of real system board condition, it may be required to prevent bus contention.
Rev. 1.3 August 2008
- 15 -
K7K3236T2C
K7K3218T2C
1Mx36 & 2Mx18 DDRII+ CIO b2 SRAM
IEEE 1149.1 TEST ACCESS PORT AND BOUNDARY SCAN-JTAG
This part contains an IEEE standard 1149.1 Compatible Test Access Port(TAP). The package pads are monitored by the Serial Scan
circuitry when in test mode. This is to support connectivity testing during manufacturing and system diagnostics. Internal data is not
driven out of the SRAM under JTAG control. In conformance with IEEE 1149.1, the SRAM contains a TAP controller, Instruction Reg-
ister, Bypass Register and ID register. The TAP controller has a standard 16-state machine that resets internally upon power-up,
therefore, TRST signal is not required. It is possible to use this device without utilizing the TAP. To disable the TAP controller without
interfacing with normal operation of the SRAM, TCK must be tied to VSS to preclude mid level input. TMS and TDI are designed so an
undriven input will produce a response identical to the application of a logic 1, and may be left unconnected. But they may also be
tied to VDD through a resistor. TDO should be left unconnected.
JTAG Block Diagram
JTAG Instruction Coding
IR2 IR1 IR0 Instruction
TDO Output
Notes
0
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
EXTEST
IDCODE
SAMPLE-Z
Boundary Scan Register
Identification Register
Boundary Scan Register
1
3
2
6
5
6
6
4
0
0
0
RESERVED Do Not Use
1
SAMPLE
Boundary Scan Register
1
RESERVED Do Not Use
RESERVED Do Not Use
SRAM
CORE
1
1
BYPASS
Bypass Register
NOTE :
1. Places DQs in Hi-Z in order to sample all input data regardless of other
SRAM inputs. This instruction is not IEEE 1149.1 compliant.
2. Places DQs in Hi-Z in order to sample all input data regardless of other
SRAM inputs.
TDI
BYPASS Reg.
Identification Reg.
Instruction Reg.
TDO
3. TDI is sampled as an input to the first ID register to allow for the serial shift
of the external TDI data.
4. Bypass register is initiated to VSS when BYPASS instruction is invoked. The
Bypass Register also holds serially loaded TDI when exiting the Shift DR
states.
5. SAMPLE instruction dose not places DQs in Hi-Z.
6. This instruction is reserved for future use.
Control Signals
TAP Controller
TMS
TCK
TAP Controller State Diagram
1
0
Test Logic Reset
0
1
1
0
1
Run Test Idle
Select DR
0
Capture DR
0
Shift DR
1
Exit1 DR
0
Select IR
0
1
1
1
1
Capture IR
0
0
Shift IR
1
Exit1 IR
0
0
0
0
0
Pause DR
1
Pause IR
1
Exit2 IR
1
Exit2 DR
1
1
0
Update DR
0
Update IR
1
Rev. 1.3 August 2008
- 16 -
K7K3236T2C
K7K3218T2C
1Mx36 & 2Mx18 DDRII+ CIO b2 SRAM
SCAN REGISTER DEFINITION
Part
Instruction Register
Bypass Register
ID Register
32 bits
32 bits
Boundary Scan
109 bits
1Mx36
2Mx18
3 bits
3 bits
1 bit
1 bit
109 bits
ID REGISTER DEFINITION
Revision Number
Part Configuration
(28:12)
00def0wx0t0q0b0s0
Samsung JEDEC Code
(11: 1)
Part
Start Bit(0)
(31:29)
000
1Mx36
2Mx18
00011001110
00011001110
1
1
000
00def0wx0t0q0b0s0
Note : Part Configuration
/def=010 for 36Mb, /wx=11 for x36, 10 for x18
/t=1 for DLL Ver., 0 for non-DLL Ver. /q=1 for QDR, 0 for DDR /b=1 for 4Bit Burst, 0 for 2Bit Burst /s=1 for Separate I/O, 0 for Common I/O
BOUNDARY SCAN EXIT ORDER
ORDER
PIN ID
ORDER
PIN ID
10D
9E
ORDER
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
PIN ID
2C
3E
2D
2E
1E
2F
3F
1G
1F
3G
2G
1H
1J
2J
3K
3J
2K
1K
2L
3L
1M
1L
3N
3M
1N
2M
3P
2N
2P
1P
3R
4R
4P
5P
5N
5R
Internal
1
2
6R
6P
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
3
4
6N
7P
10C
11D
9C
9D
11B
11C
9B
10B
11A
10A
9A
5
6
7N
7R
7
8
8R
8P
9
9R
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
11P
10P
10N
9P
10M
11N
9M
9N
11L
11M
9L
10L
11K
10K
9J
8B
7C
6C
8A
7A
7B
6B
6A
5B
5A
4A
5C
4B
3A
2A
1A
2B
3B
1C
1B
97
98
99
9K
10J
11J
11H
10G
9G
11F
11G
9F
100
101
102
103
104
105
106
107
108
109
10F
11E
10E
3D
3C
1D
Note: 1. NC pins are read as "X" ( i.e. don′t care.)
Rev. 1.3 August 2008
- 17 -
K7K3236T2C
K7K3218T2C
1Mx36 & 2Mx18 DDRII+ CIO b2 SRAM
JTAG DC OPERATING CONDITIONS
Parameter
Symbol
Min
1.7
Typ
Max
1.9
Unit
V
Note
Power Supply Voltage
VDD
VIH
1.8
Input High Level
1.3
-
-
-
-
VDD+0.3
0.5
V
Input Low Level
VIL
-0.3
1.4
V
Output High Voltage(IOH=-2mA)
Output Low Voltage(IOL=2mA)
VOH
VOL
VDD
V
VSS
0.4
V
Note: 1. The input level of SRAM pin is to follow the SRAM DC specification.
JTAG AC TEST CONDITIONS
Parameter
Symbol
VIH/VIL
TR/TF
Min
1.8/0.0
1.0/1.0
0.9
Unit
V
Note
Input High/Low Level
Input Rise/Fall Time
ns
V
Input and Output Timing Reference Level
Note: 1. See SRAM AC test output load on page 11.
1
JTAG AC Characteristics
Parameter
Symbol
Min
50
20
20
5
Max
Unit
Note
TCK Cycle Time
tCHCH
tCHCL
tCLCH
tMVCH
tCHMX
tDVCH
tCHDX
tSVCH
tCHSX
tCLQV
-
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
TCK High Pulse Width
TCK Low Pulse Width
TMS Input Setup Time
TMS Input Hold Time
TDI Input Setup Time
TDI Input Hold Time
-
-
5
-
5
-
5
-
SRAM Input Setup Time
SRAM Input Hold Time
Clock Low to Output Valid
5
-
5
-
0
10
JTAG TIMING DIAGRAM
TCK
tCHCH
tCLCH
tCHCL
tMVCH
tCHMX
TMS
TDI
tDVCH
tSVCH
tCHDX
tCHSX
PI
(SRAM)
tCLQV
TDO
Rev. 1.3 August 2008
- 18 -
K7K3236T2C
K7K3218T2C
1Mx36 & 2Mx18 DDRII+ CIO b2 SRAM
165 FBGA PACKAGE DIMENSIONS
15mm x 17mm Body, 1.0mm Bump Pitch, 11x15 Ball Array
B
Top View
A
C
Side View
D
A
G
E
B
F
Bottom View
H ∅
E
Symbol
Value
15 ± 0.1
Units
Note
Symbol
Value
1.0
Units
mm
mm
mm
mm
Note
A
B
C
D
mm
mm
mm
mm
E
F
17 ± 0.1
14.0
1.3 ± 0.1
0.35 ± 0.05
G
H
10.0
0.5 ± 0.05
Rev. 1.3 August 2008
- 19 -
相关型号:
K7K3236T2C-EC330
DDR SRAM, 1MX36, 0.45ns, CMOS, PBGA165, 15 X 17 MM, 1 MM PITCH, ROHS COMPLIANT, FBGA-165
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K7K3236T2C-EI330
DDR SRAM, 1MX36, 0.45ns, CMOS, PBGA165, 15 X 17 MM, 1 MM PITCH, ROHS COMPLIANT, FBGA-165
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