K7M163625A-QI600_技术文档

K7M163625A

K7M163225A

K7M161825A

512Kx36/32 & 1Mx18 Flow-Through NtRAM^TM

Document Title

512Kx36/32 & 1Mx18-Bit Flow Through NtRAM^TM

Revision History

Rev. No.

History

Draft Date

Remark

0.0

0.1

0.2

1. Initial document.

1. Add JTAG Scan Order

Feb. 23. 2001

May. 10. 2001

Aug. 03. 2001

Preliminary

1. Remove bin -90

2. Updated DC characteristics(ICC,ISB,ISB1,ISB2)

1. Add x32 org and industrial temperature .

2. Add 165FBGA package

0.3

Aug. 30. 2001

Preliminary

1.0

2.0

2.1

1. Final spec release

May. 10. 2002

Oct. 26, 2002

April. 04. 2003

Final

1. Add the speed bin (-60)

1. Delete 119BGA package.

2. Correct the Ball Size of 165 FBGA.

The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the

specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions on the parameters of this device. If you have any ques-

tions, please contact the SAMSUNG branch office near your office, call or contact Headquarters.

- 1 -

April 2003

Rev 2.1

K7M163625A

K7M163225A

K7M161825A

512Kx36/32 & 1Mx18 Flow-Through NtRAM^TM

16Mb NtRAM(Flow Through / Pipelined) , Double Late Write RAM x72 Ordering Information

Speed

Org.

Part Number

Mode

VDD

FT ; Access Time(ns)

PKG

Temp

Pipelined ; Cycle Time(MHz)

K7M161825A-Q(F)C(I)60/65/75/85

K7N161801A-Q(F)C(I)25/22/20/16/13

K7N161845A-Q(F)C(I)25/22/20/16/13

K7M163225A-QC(I)60/65/75/85

FlowThrough 3.3

6.0/6.5/7.5/8.5ns

250/225/200/167/133MHz

6.0/6.5/7.5/8.5ns

1Mx18

Pipelined

3.3

2.5

FlowThrough 3.3

C

Q : 100TQFP

F : 165FBGA

512Kx32

512Kx36

K7N163201A-QC(I)25/22/20/16/13

K7N163245A-QC(I)25/22/20/16/13

K7M163625A-Q(F)C(I)60/65/75/85

K7N163601A-Q(F)C(I)25/22/20/16/13

K7N163645A-Q(F)C(I)25/22/20/16/13

Pipelined

3.3

2.5

250/225/200/167/133MHz

6.0/6.5/7.5/8.5ns

(Commercial

Temperature

Range)

FlowThrough 3.3

I

Pipelined

3.3

2.5

250/225/200/167/133MHz

(Industrial

Temperature

Range)

Pipelined

(Normal

K7N167245A-HC25/22/20/16/13

K7Z167285A-HC30/27/25

2.5

1.8

250/225/200/167/133MHz

300/275/250MHz

H : 209BGA

256Kx72

Pipelined

(Sigma Type)

NOTE : 119BGA is only supported with K7N161801A - HC13, K7N163645A - HC16, K7N161845A - HC13 and K7N163645 - HC16.

- 2 -

April 2003

Rev 2.1

K7M163625A

K7M163225A

K7M161825A

512Kx36/32 & 1Mx18 Flow-Through NtRAM^TM

512Kx36/32 & 1Mx18-Bit Flow Through NtRAM^TM

FEATURES

GENERAL DESCRIPTION

• 3.3V+0.165V/-0.165V Power Supply.

• I/O Supply Voltage 3.3V+0.165V/-0.165V for 3.3V I/O

or 2.5V+0.4V/-0.125V for 2.5V I/O

The K7M163625A, K7M163225A and K7M161825A are

18,874,368-bits Synchronous Static SRAMs.

The NtRAM^TM, or No Turnaround Random Access Memory uti-

lizes all bandwidth in any combination of operating cycles.

Address, data inputs, and all control signals except output

enable and linear burst order are synchronized to input clock.

Burst order control must be tied "High or Low".

• Byte Writable Function.

• Enable clock and suspend operation.

• Single READ/WRITE control pin.

• Self-Timed Write Cycle.

• Three Chip Enable for simple depth expansion with no data

contention .

Asynchronous inputs include the sleep mode enable(ZZ).

Output Enable controls the outputs at any given time.

Write cycles are internally self-timed and initiated by the rising

edge of the clock input. This feature eliminates complex off-chip

write pulse generation

• A interleaved burst or a linear burst mode.

• Asynchronous output enable control.

• Power Down mode.

• TTL-Level Three-State Outputs.

• 100-TQFP-1420A

• 165FBGA(11x15 ball aray) with body size of 13mmx15mm.

• Operating in commeical and industrial temperature range.

and provides increased timing flexibility for incoming signals.

For read cycles, Flow-Through SRAM allows output data to

simply flow freely from the memory array.

The K7M163625A, K7M163225A and K7M161825A are imple-

mented with SAMSUNG¢s high performance CMOS technology

and is available in 100pin TQFP and 165FBGA packages. Mul-

tiple power and ground pins minimize ground bounce.

FAST ACCESS TIMES

Parameter

Cycle Time

Clock Access Time

Sym. -60 -65 -75 -85 Unit

tCYC 7.5 7.5 8.5 10 ns

tCD 6.0 6.5 7.5 8.5 ns

3.5 3.5 3.5 4.0 ns

Output Enable Access Time tOE

LOGIC BLOCK DIAGRAM

LBO

BURST

ADDRESS

COUNTER

A¢0~A¢1

A [0:18]or

A [0:19]

A0~A1

512Kx36/32 , 1Mx18

MEMORY

ADDRESS

REGISTER

A2~A18 or A2~A19

ARRAY

WRITE

ADDRESS

REGISTER

CLK

CKE

K

DATA-IN

REGISTER

K

CS1

CS2

ADV

WE

CONTROL

LOGIC

BWx

(x=a,b,c,d or a,b)

BUFFER

OE

ZZ

36/32 or 18

DQa0 ~ DQd7 or DQa0 ~ DQb8

DQPa ~ DQPd

NtRAM^TMand No Turnaround Random Access Memory are trademarks of Samsung.

- 3 -

April 2003

Rev 2.1

K7M163625A

K7M163225A

K7M161825A

512Kx36/32 & 1Mx18 Flow-Through NtRAM^TM

PIN CONFIGURATION(TOP VIEW)

NC/DQPc

1

DQPb/NC

DQb7

DQb6

VDDQ

VSSQ

DQb5

DQb4

DQb3

DQb2

VSSQ

VDDQ

DQb1

DQb0

VSS

VDD

80

79

78

77

76

75

74

73

72

71

70

69

68

67

66

65

64

63

62

61

60

59

58

57

56

55

54

53

52

51

DQc0

DQc1

VDDQ

VSSQ

2

3

4

5

DQc2

DQc3

DQc4

DQc5

VSSQ

VDDQ

DQc6

DQc7

Vss

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

100 Pin TQFP

VDD

VSS

(20mm x 14mm)

ZZ

DQa7

DQa6

VDDQ

VSSQ

DQa5

DQa4

DQa3

DQa2

VSSQ

VDDQ

DQa1

DQa0

DQPa/NC

DQd0

DQd1

VDDQ

VSSQ

DQd2

DQd3

DQd4

DQd5

VSSQ

K7M163625A(512Kx36)

K7M163225A(512Kx32)

VDDQ

DQd6

DQd7

NC/DQPd

PIN NAME

SYMBOL

PIN NAME

TQFP PIN NO.

SYMBOL

PIN NAME

TQFP PIN NO.

A0 - A18

Address Inputs

32,33,34,35,36,37,44 VDD

45,46,47,48,49,50,81 VSS

82,83,84,99,100

Power Supply(+3.3V) 15,16,41,65,91

Ground

14,17,40,66,67,90

38,39,42,43

ADV

WE

Address Advance/Load

Read/Write Control Input 88

85

No Connect

N.C.

CLK

CKE

CS1

CS2

Clock

89

Data Inputs/Outputs

52,53,56,57,58,59,62,63

68,69,72,73,74,75,78,79

2,3,6,7,8,9,12,13

18,19,22,23,24,25,28,29

51,80,1,30

DQa0~a7

DQb0~b7

DQc0~c7

DQd0~d7

DQPa~Pd

or NC

Clock Enable

Chip Select

87

98

97

92

BWx(x=a,b,c,d) Byte Write Inputs

93,94,95,96

OE

ZZ

LBO

Output Enable

86

64

31

Power Sleep Mode

Burst Mode Control

Output Power Supply 4,11,20,27,54,61,70,77

(2.5V or 3.3V)

VDDQ

VSSQ

Output Ground

5,10,21,26,55,60,71,76

Notes : 1. A0 and A1 are the two least significant bits(LSB) of the address field and set the internal burst counter if burst is desired.

- 4 -

April 2003

Rev 2.1

K7M163625A

K7M163225A

K7M161825A

512Kx36/32 & 1Mx18 Flow-Through NtRAM^TM

PIN CONFIGURATION(TOP VIEW)

80

79

78

77

76

75

74

73

72

71

70

69

68

67

66

65

64

63

62

61

60

59

58

57

56

55

54

53

52

51

A10

N.C.

VDDQ

VSSQ

N.C.

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

N.C.

VDDQ

VSSQ

N.C.

DQa0

DQa1

DQa2

VSSQ

VDDQ

DQa3

DQa4

VSS

N.C.

DQb8

DQb7

VSSQ

VDDQ

DQb6

DQb5

VSS

VDD

VSS

DQb4

DQb3

VDDQ

VSSQ

DQb2

DQb1

DQb0

N.C.

VSSQ

VDDQ

N.C.

100 Pin TQFP

(20mm x 14mm)

VSS

VDD

ZZ

DQa5

DQa6

VDDQ

VSSQ

DQa7

DQa8

N.C.

VSSQ

VDDQ

N.C.

K7M161825A(1Mx18)

PIN NAME

SYMBOL

PIN NAME

Address Inputs

TQFP PIN NO.

SYMBOL

PIN NAME

TQFP PIN NO.

A0 - A19

32,33,34,35,36,37,44 VDD

45,46,47,48,49,50,80 VSS

81,82,83,84,99,100

Power Supply(+3.3V) 15,16,41,65,91

Ground

14,17,40,66,67,90

ADV

WE

Address Advance/Load

Read/Write Control Input 88

Clock

85

No Connect

1,2,3,6,7,25,28,29,30,

38,39,42,43,51,52,53,

56,57,75,78,79,95,96

N.C.

CLK

CKE

CS1

CS2

89

Clock Enable

Chip Select

87

98

97

Data Inputs/Outputs

58,59,62,63,68,69,72,73,74

8,9,12,13,18,19,22,23,24

DQa0~a8

DQb0~b8

92

BWx(x=a,b) Byte Write Inputs

93,94

86

OE

ZZ

Output Enable

Output Power Supply 4,11,20,27,54,61,70,77

(2.5V or 3.3V)

VDDQ

VSSQ

Power Sleep Mode

Burst Mode Control

64

31

LBO

Output Ground

5,10,21,26,55,60,71,76

Notes : 1. A0 and A1 are the two least significant bits(LSB) of the address field and set the internal burst counter if burst is desired.

- 5 -

April 2003

Rev 2.1

K7M163625A

K7M163225A

K7M161825A

512Kx36/32 & 1Mx18 Flow-Through NtRAM^TM

165-PIN FBGA PACKAGE CONFIGURATIONS(TOP VIEW)

K7M163625A(512Kx36)

1

2

3

4

5

6

7

8

9

10

A

11

NC

CS2

A

B

C

D

E

F

NC

A

CS 1

BWc

BWd

VSS

VDD

VSS

A

BWb

BWa

VSS

NC

CKE

WE

ADV

OE

A

NC

A

CS2

CLK

VSS

NC

A

NC

DQPc

DQc

NC

VDDQ

NC

VSS

NC

VSS

VDD

VSS

A

VDDQ

NC

DQPb

DQb

ZZ

DQc

VDD

DQd

NC

DQb

NC

G

H

J

DQd

DQPd

NC

VDDQ

A

VDDQ

A

DQa

NC

DQa

DQPa

NC

K

L

M

N

P

R

NC

TDI

TMS

A1*

TDO

TCK

A

LBO

NC

A

A0*

A

Note : * A0 and A1 are the two least significant bits(LSB) of the address field and set the internal burst counter if burst is desired.

PIN NAME

SYMBOL

PIN NAME

SYMBOL

PIN NAME

A

Address Inputs

VDD

VSS

Power Supply

Ground

A0,A1

ADV

WE

Burst Address Inputs

Address Advance/Load

Read/Write Control Input

Clock

Clock Enable

Chip Select

N.C.

No Connect

CLK

CKE

CS1

DQa

DQb

DQc

DQd

Data Inputs/Outputs

CS2

Chip Select

DQPa~Pd

BWx

(x=a,b,c,d)

Byte Write Inputs

VDDQ

Output Power Supply

OE

ZZ

LBO

Output Enable

Power Sleep Mode

Burst Mode Control

TCK

TMS

TDI

JTAG Test Clock

JTAG Test Mode Select

JTAG Test Data Input

JTAG Test Data Output

TDO

- 6 -

April 2003

Rev 2.1

K7M163625A

K7M163225A

K7M161825A

512Kx36/32 & 1Mx18 Flow-Through NtRAM^TM

165-PIN FBGA PACKAGE CONFIGURATIONS(TOP VIEW)

K7M161825A(1Mx18)

1

NC

2

A

3

4

5

6

7

8

9

10

A

11

A

CS2

A

B

C

D

E

F

CS 1

BWb

NC

CKE

WE

ADV

OE

A

NC

A

CS2

BWa

VSS

NC

CLK

VSS

NC

A

NC

DQb

VDD

NC

VDDQ

NC

VSS

VDD

VSS

A

VSS

NC

VSS

VDD

VSS

A

VDDQ

NC

DQa

NC

A

DQPa

DQa

ZZ

NC

G

H

J

NC

DQb

DQPb

NC

VDDQ

A

VDDQ

A

NC

K

L

NC

M

N

P

R

NC

TDI

TMS

A1*

TDO

TCK

NC

LBO

A

A0*

A

Note : * A0 and A1 are the two least significant bits(LSB) of the address field and set the internal burst counter if burst is desired.

PIN NAME

SYMBOL

PIN NAME

SYMBOL

PIN NAME

A

Address Inputs

VDD

VSS

Power Supply

Ground

A0,A1

ADV

WE

CLK

CKE

CS1

Burst Address Inputs

Address Advance/Load

Read/Write Control Input

Clock

No Connect

N.C.

Clock Enable

Data Inputs/Outputs

DQa

DQb

DQPa, Pb

Chip Select

CS2

Chip Select

BWx

(x=a,b)

Byte Write Inputs

Output Power Supply

VDDQ

OE

ZZ

LBO

Output Enable

Power Sleep Mode

Burst Mode Control

TCK

TMS

TDI

JTAG Test Clock

JTAG Test Mode Select

JTAG Test Data Input

JTAG Test Data Output

TDO

- 7 -

April 2003

Rev 2.1

K7M163625A

K7M163225A

K7M161825A

512Kx36/32 & 1Mx18 Flow-Through NtRAM^TM

FUNCTION DESCRIPTION

The K7M163625A, K7M163225A and K7M161825A are NtRAM^TMdesigned to sustain 100% bus bandwidth by eliminating turn-

around cycle when there is transition from Read to Write, or vice versa.

All inputs (with the exception of OE, LBO and ZZ) are synchronized to rising clock edges.

All read, write and deselect cycles are initiated by the ADV input. Subsequent burst addresses can be internally generated by the

burst advance pin (ADV). ADV should be driven to Low once the device has been deselected in order to load a new address for next

operation.

Clock Enable(CKE) pin allows the operation of the chip to be suspended as long as necessary. When CKE is high, all synchronous

inputs are ignored and the internal device registers will hold their previous values.

NtRAM^TMlatches external address and initiates a cycle, when CKE, ADV are driven to low and all three chip enables(CS1, CS 2, CS 2)

are active .

Output Enable(OE) can be used to disable the output at any given time.

Read operation is initiated when at the rising edge of the clock, the address presented to the address inputs are latched in the

address register, CKE is driven low, all three chip enables(CS 1, CS2, CS2) are active, the write enable input signals WE are driven

high, and ADV driven low. Data appears at the outputs within the same clock cycle as the address for the data. Also during read

operation OE must be driven low for the device to drive out the requested data.

Write operation occurs when WE is driven low at the rising edge of the clock. BW[d:a] can be used for byte write operation. The Flow

Through NtRAM^TMuses a late write cycle to utilize 100% of the bandwidth.

At the first rising edge of the clock, WE and address are registered, and the data associated with that address is required one cycle

later.

Subsequent addresses are generated by ADV High for the burst access as shown below. The starting point of the burst seguence is

provided by the external address. The burst address counter wraps around to its initial state upon completion.

The burst sequence is determined by the state of the LBO pin. When this pin is low, linear burst sequence is selected.

And when this pin is high, Interleaved burst sequence is selected.

During normal operation, ZZ must be driven low. When ZZ is driven high, the SRAM will enter a Power Sleep Mode after 2 cycles. At

this time, internal state of the SRAM is preserved. When ZZ returns to low, the SRAM normally operates after 2 cycles of wake up

time.

BURST SEQUENCE TABLE

(Interleaved Burst, LBO=High)

Case 4

Case 1

Case 2

Case 3

LBO PIN

HIGH

First Address

A1

A0

A1

A0

A1

A0

A1

A0

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

Fourth Address

BQ TABLE

(Linear Burst, LBO=Low)

Case 4

Case 1

Case 2

Case 3

LBO PIN

LOW

First Address

A1

A0

A1

A0

A1

A0

A1

A0

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

Fourth Address

Note : 1. LBO pin must be tied to High or Low, and Floating State must not be allowed.

- 8 -

April 2003

Rev 2.1

K7M163625A

K7M163225A

K7M161825A

512Kx36/32 & 1Mx18 Flow-Through NtRAM^TM

STATE DIAGRAM FOR NtRAM^TM

WRITE

READ

BEGIN

READ

BEGIN

WRITE

READ

DESELECT

BURST

READ

BURST

WRITE

BURST

COMMAND

ACTION

DS

DESELECT

READ

WRITE

BEGIN READ

BEGIN WRITE

BEGIN READ

BURST

BEGIN WRITE

CONTINUE DESELECT

Notes : 1. An IGNORE CLOCK EDGE cycle is not shown is the above diagram. This is because CKE HIGH only blocks the clock(CLK) input and does

not change the state of the device.

2. States change on the rising edge of the clock(CLK)

- 9 -

April 2003

Rev 2.1

K7M163625A

K7M163225A

K7M161825A

512Kx36/32 & 1Mx18 Flow-Through NtRAM^TM

TRUTH TABLES

SYNCHRONOUS TRUTH TABLE

CS1

H

X

L

CS2

X

CS 2 ADV WE BWx

OE

X

L

CKE CLK

ADDRESS ACCESSED

N/A

OPERATION

Not Selected

X

H

X

L

X

H

X

H

X

L

X

L

H

•

L

N/A

Not Selected

X

L

N/A

Not Selected

X

H

L

N/A

Not Selected Continue

Begin Burst Read Cycle

Continue Burst Read Cycle

NOP/Dummy Read

Dummy Read

H

X

External Address

Next Address

External Address

Next Address

External Address

Next Address

N/A

X

L

X

L

H

L

H

X

H

X

L

X

L

H

L

H

X

Begin Burst Write Cycle

Continue Burst Write Cycle

NOP/Write Abort

X

L

X

L

H

L

X

L

H

X

H

X

H

X

Next Address

Current Address

Write Abort

X

Ignore Clock

Notes : 1. X means "Don¢t Care".

2. The rising edge of clock is symbolized by (• ).

3. A continue deselect cycle can only be enterd if a deselect cycle is executed first.

4. WRITE = L means Write operation in WRITE TRUTH TABLE.

WRITE = H means Read operation in WRITE TRUTH TABLE.

5. Operation finally depends on status of asynchronous input pins(ZZ and OE).

WRITE TRUTH TABLE( x36 / x32)

WE

H

L

BWa

X

BWb

BW c

X

BW d

OPERATION

READ

X

H

L

X

H

L

H

WRITE BYTE a

WRITE BYTE b

WRITE BYTE c

WRITE BYTE d

WRITE ALL BYTEs

WRITE ABORT/NOP

L

H

L

H

L

H

L

H

Notes : 1. X means "Don¢t Care".

2. All inputs in this table must meet setup and hold time around the rising edge of CLK(• ).

WRITE TRUTH TABLE(x18)

WE

H

L

BWa

BWb

OPERATION

X

L

X

H

L

READ

WRITE BYTE a

WRITE BYTE b

WRITE ALL BYTEs

WRITE ABORT/NOP

L

H

L

H

Notes : 1. X means "Don¢t Care".

2. All inputs in this table must meet setup and hold time around the rising edge of CLK(• ).

- 10 -

April 2003

Rev 2.1

K7M163625A

K7M163225A

K7M161825A

512Kx36/32 & 1Mx18 Flow-Through NtRAM^TM

ASYNCHRONOUS TRUTH TABLE

Notes

Operation

ZZ

H

L

OE

X

I/O STATUS

1. X means "Don¢t Care".

2. Sleep Mode means power Sleep Mode of which stand-by current does

not depend on cycle time.

3. Deselected means power Sleep Mode of which stand-by current

depends on cycle time.

Sleep Mode

High-Z

DQ

L

Read

L

H

X

High-Z

Write

L

Din, High-Z

High-Z

Deselected

L

X

ABSOLUTE MAXIMUM RATINGS*

PARAMETER

Voltage on VDD Supply Relative to VSS

Voltage on Any Other Pin Relative to VSS

Power Dissipation

SYMBOL

VDD

RATING

-0.3 to 4.6

-0.3 to VDD+0.3

1.6

UNIT

V

VIN

V

PD

W

Storage Temperature

TSTG

TOPR

TBIAS

-65 to 150

0 to 70

°C

Commercial

Industrial

Operating Temperature

-40 to 85

-10 to 85

Storage Temperature Range Under Bias

*Notes : Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only

and functional operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not

implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.

OPERATING CONDITIONS at 3.3V I/O(0°C £ TA £ 70°C)

PARAMETER

Supply Voltage

Ground

SYMBOL

VDD

MIN

3.135

0

Typ.

3.3

0

MAX

3.465

0

UNIT

V

VDDQ

VSS

* The above parameters are also guaranteed at industrial temperature range.

OPERATING CONDITIONS at 2.5V I/O(0°C £ TA £ 70°C)

PARAMETER

Supply Voltage

Ground

SYMBOL

VDD

MIN

3.135

2.375

0

Typ.

3.3

2.5

0

MAX

3.465

2.9

UNIT

V

VDDQ

VSS

0

* The above parameters are also guaranteed at industrial temperature range.

CAPACITANCE*(TA=25°C, f=1MHz)

PARAMETER

SYMBOL

TEST CONDITION

VIN=0V

MIN

MAX

UNIT

Input Capacitance

CIN

-

5

7

pF

Output Capacitance

COUT

VOUT=0V

*Note : Sampled not 100% tested.

- 11 -

April 2003

Rev 2.1

K7M163625A

K7M163225A

K7M161825A

512Kx36/32 & 1Mx18 Flow-Through NtRAM^TM

DC ELECTRICAL CHARACTERISTICS(VDD=3.3V+0.165V/-0.165V, TA=0°C to +70°C)

PARAMETER

SYMBOL

TEST CONDITIONS

MIN

MAX

UNIT NOTES

Input Leakage Current(except ZZ)

Output Leakage Current

IIL

VDD=Max ; VIN=VSS to VDD

-2

-

+2

mA

IOL

Output Disabled,

+2

-60

-65

-75

-85

-60

-65

-75

-85

280

270

250

230

110

100

90

-

Device Selected, IOUT=0mA,

Operating Current

ICC

ISB

mA

1,2

ZZ£VIL , Cycle Time ³ tCYC Min

-

Device deselected, IOUT=0mA,

ZZ£VIL, f=Max,

-

All Inputs£0.2V or ³ VDD-0.2V

-

80

Standby Current

Device deselected, IOUT=0mA, ZZ£0.2V, f=0,

ISB1

ISB2

-

70

60

mA

All Inputs=fixed (VDD -0.2V or 0.2V)

Device deselected, IOUT=0mA, ZZ³ VDD-0.2V,

f=Max, All Inputs£VIL or ³ VIH

Output Low Voltage(3.3V I/O)

Output High Voltage(3.3V I/O)

Output Low Voltage(2.5V I/O)

Output High Voltage(2.5V I/O)

Input Low Voltage(3.3V I/O)

Input High Voltage(3.3V I/O)

Input Low Voltage(2.5V I/O)

Input High Voltage(2.5V I/O)

VOL

VOH

VOL

VOH

VIL

IOL=8.0mA

IOH=-4.0mA

IOL=1.0mA

IOH=-1.0mA

-

0.4

V

2.4

-

0.4

2.0

-0.3*

2.0

-0.3*

1.7

-

0.8

VDD+0.3**

0.7

3

VIH

VIL

VIH

VDD+0.3**

Notes : 1. The above parameters are also guaranteed at industrial temperature range.

2. Reference AC Operating Conditions and Characteristics for input and timing.

3. Data states are all zero.

4. In Case of I/O Pins, the Max. VIH=VDDQ +0.3V.

VIH

VSS

VSS-1.0V

20% tCYC (MIN)

TEST CONDITIONS

(VDD=3.3V+0.165V/-0.165V,VDDQ=3.3V+0.165/-0.165V or VDD=3.3V+0.165V/-0.165V,VDDQ=2.5V+0.4V/-0.125V, TA=0to70°C)

PARAMETER

VALUE

0 to 3.0V

0 to 2.5V

1.0V/ns

1.5V

Input Pulse Level(for 3.3V I/O)

Input Pulse Level(for 2.5V I/O)

Input Rise and Fall Time(Measured at 20% to 80% for 3.3V I/O)

Input Rise and Fall Time(Measured at 20% to 80% for 2.5V I/O)

Input and Output Timing Reference Levels for 3.3V I/O

Input and Output Timing Reference Levels for 2.5V I/O

Output Load

VDDQ/2

See Fig. 1

* The above parameters are also guaranteed at industrial temperature range.

- 12 -

April 2003

Rev 2.1

K7M163625A

K7M163225A

K7M161825A

512Kx36/32 & 1Mx18 Flow-Through NtRAM^TM

Output Load(A)

Output Load(B),

(for tLZC, tLZOE, tHZOE & tHZC)

+3.3V for 3.3V I/O

/+2.5V for 2.5V I/O

RL=50W

30pF*

Dout

VL=1.5V for 3.3V I/O

VDDQ/2 for 2.5V I/O

319W / 1667W

Dout

Zo=50W

353W / 1538W

5pF*

* Including Scope and Jig Capacitance

Fig. 1

AC TIMING CHARACTERISTICS(VDD=3.3V+0.165V/-0.165V, TA=0°C to +70°C)

-60

-65

-75

-85

PARAMETER

SYMBOL

UNIT

MAX

MIN

7.5

-

MAX

MIN

7.5

-

MAX

MIN

8.5

-

MAX

MIN

10

-

Cycle Time

tCYC

tCD

-

ns

Clock Access Time

6.0

6.5

7.5

8.5

Output Enable to Data Valid

Clock High to Output Low-Z

Output Hold from Clock High

Output Enable Low to Output Low-Z

Output Enable High to Output High-Z

Clock High to Output High-Z

Clock High Pulse Width

tOE

-

3.5

-

3.5

-

3.5

-

4.0

ns

tLZC

tOH

2.5

0

-

2.5

0

-

2.5

0

-

2.5

0

-

ns

-

ns

tLZOE

tHZOE

tHZC

tCH

-

ns

-

3.5

-

3.5

-

3.5

-

4.0

ns

-

3.8

-

3.8

-

4.0

-

5.0

ns

2.5

1.5

0.5

2

-

2.5

1.5

0.5

2

-

2.8

2.0

0.5

2

-

3.0

2.0

0.5

2

-

ns

Clock Low Pulse Width

tCL

ns

Address Setup to Clock High

CKE Setup to Clock High

tAS

ns

tCES

tDS

ns

Data Setup to Clock High

ns

Write Setup to Clock High (WE, BWX)

Address Advance Setup to Clock High

Chip Select Setup to Clock High

Address Hold from Clock High

CKE Hold from Clock High

tWS

ns

tADVS

tCSS

tAH

ns

tCEH

tDH

ns

Data Hold from Clock High

ns

Write Hold from Clock High (WE, BWX)

Address Advance Hold from Clock High

Chip Select Hold from Clock High

ZZ High to Power Down

tWH

tADVH

tCSH

tPDS

tPUS

ns

cycle

ZZ Low to Power Up

2

Notes : 1. The above parameters are also guaranteed at industrial temperature range.

2. All address inputs must meet the specified setup and hold times for all rising clock(CLK) edges when ADV is sampled low and CS is sampled

low. All other synchronous inputs must meet the specified setup and hold times whenever this device is chip selected.

3. Chip selects must be valid at each rising edge of CLK(when ADV is Low) to remain enabled.

4. A write cycle is defined by WE low having been registerd into the device at ADV Low, A Read cycle is defined by WE High with ADV Low,

Both cases must meet setup and hold times.

5. To avoid bus contention, At a given vlotage and temperature tLZC is more than tHZC.

The soecs as shown do not imply bus contention because tLZC is a Min. parameter that is worst case at totally different test conditions

(0°C,3.465V) than tHZC, which is a Max. parameter(worst case at 70°C,3.135V)

It is not possible for two SRAMs on the same board to be at such different voltage and temperatue.

- 13 -

April 2003

Rev 2.1

K7M163625A

K7M163225A

K7M161825A

512Kx36/32 & 1Mx18 Flow-Through NtRAM^TM

SLEEP MODE

SLEEP MODE is a low current, power-down mode in which the device is deselected and current is reduced to ISB2. The duration of

SLEEP MODE is dictated by the length of time the ZZ is in a High state.

After entering SLEEP MODE, all inputs except ZZ become disabled and all outputs go to High-Z

The ZZ pin is an asynchronous, active high input that causes the device to enter SLEEP MODE.

When the ZZ pin becomes a logic High, ISB2 is guaranteed after the time tZZI is met. Any operation pending when entering SLEEP

MODE is not guaranteed to successful complete. Therefore, SLEEP MODE (READ or WRITE) must not be initiated until valid pend-

ing operations are completed. similarly, when exiting SLEEP MODE during tPUS, only a DESELECT or READ cycle should be given

while the SRAM is transitioning out of SLEEP MODE.

SLEEP MODE ELECTRICAL CHARACTERISTICS

DESCRIPTION

Current during SLEEP MODE

CONDITIONS

SYMBOL

ISB2

MIN

MAX

UNITS

mA

ZZ ³ VIH

60

ZZ active to input ignored

tPDS

2

cycle

tPUS

ZZ inactive to input sampled

ZZ active to SLEEP current

tZZI

2

ZZ inactive to exit SLEEP current

tRZZI

0

SLEEP MODE WAVEFORM

K

tPDS

ZZ setup cycle

tPUS

ZZ recovery cycle

ZZ

tZZI

Isupply

ISB2

tRZZI

All inputs

(except ZZ)

Deselect or Read Only

Normal

operation

cycle

Outputs

(Q)

High-Z

DON¢T CARE

- 14 -

April 2003

Rev 2.1

K7M163625A

K7M163225A

K7M161825A

512Kx36/32 & 1Mx18 Flow-Through NtRAM^TM

IEEE 1149.1 TEST ACCESS PORT AND BOUNDARY SCAN-JTAG

This part contains an IEEE standard 1149.1 Compatible Test Access Port(TAP). The package pads are monitored by the Serial Scan

circuitry when in test mode. This is to support connectivity testing during manufacturing and system diagnostics. Internal data is not

driven out of the SRAM under JTAG control. In conformance with IEEE 1149.1, the SRAM contains a TAP controller, Instruction Reg-

ister, Bypass Register and ID register. The TAP controller has a standard 16-state machine that resets internally upon power-up,

therefore, TRST signal is not required. It is possible to use this device without utilizing the TAP. To disable the TAP controller without

interfacing with normal operation of the SRAM, TCK must be tied to VSS to preclude mid level input. TMS and TDI are designed so an

undriven input will produce a response identical to the application of a logic 1, and may be left unconnected. But they may also be

tied to VDD through a resistor. TDO should be left unconnected.

JTAG Block Diagram

JTAG Instruction Coding

IR2 IR1 IR0 Instruction

TDO Output

Notes

0

1

0

1

0

1

0

1

0

1

0

1

0

1

EXTEST

IDCODE

SAMPLE-Z

BYPASS

SAMPLE

Boundary Scan Register

Identification Register

Boundary Scan Register

Bypass Register

1

3

2

4

5

6

4

Boundary Scan Register

RESERVED Do Not Use

SRAM

CORE

BYPASS

Bypass Register

NOTE :

1. Places DQs in Hi-Z in order to sample all input data regardless of other

SRAM inputs. This instruction is not IEEE 1149.1 compliant.

TDI

BYPASS Reg.

TDO

2. Places DQs in Hi-Z in order to sample all input data regardless of other

SRAM inputs.

Identification Reg.

Instruction Reg.

3. TDI is sampled as an input to the first ID register to allow for the serial shift

of the external TDI data.

4. Bypass register is initiated to VSS when BYPASS instruction is invoked. The

Bypass Register also holds serially loaded TDI when exiting the Shift DR

states.

Control Signals

TAP Controller

TMS

TCK

5. SAMPLE instruction dose not places DQs in Hi-Z.

6. This instruction is reserved for future use.

TAP Controller State Diagram

1

0

Test Logic Reset

0

1

0

1

Run Test Idle

Select DR

0

Select IR

0

1

Capture DR

0

Capture IR

0

Shift DR

1

Shift IR

1

Exit1 DR

0

Exit1 IR

0

Pause DR

1

Pause IR

1

Exit2 DR

1

Exit2 IR

1

0

Update DR

0

Update IR

1

- 15 -

April 2003

Rev 2.1

K7M163625A

K7M163225A

K7M161825A

512Kx36/32 & 1Mx18 Flow-Through NtRAM^TM

SCAN REGISTER DEFINITION

Part

512Kx36

1Mx18

Instruction Register

Bypass Register

1 bits

ID Register

32 bits

Boundary Scan

75 bits

3 bits

1 bits

32 bits

75 bits

ID REGISTER DEFINITION

Revision Number

Part

Part Configuration Vendor Definition Samsung JEDEC Code

Start Bit(0)

(31:28)

(27:18)

(17:12)

XXXXXX

(11: 1)

512Kx36

1Mx18

0000

00111 00100

01000 00011

00001001110

1

165FBGA BOUNDARY SCAN EXIT ORDER(x36)

165FBGA BOUNDARY SCAN EXIT ORDER(x18)

1

1R

6N

LBO

NC

CLK

NC

6B

11B

1A

6A

5B

5A

4A

4B

3B

3A

2A

2B

1B

1C

1D

1E

1F

1G

2D

2E

2F

2G

1J

39

40

41

42

43

44

45

46

47

48

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

64

65

66

67

68

69

70

71

72

73

74

75

1

1R

6N

LBO

NC

A

CLK

NC

CS2

BWa

NC

BWb

NC

CS2

CS1

A

6B

11B

1A

6A

5B

5A

4A

4B

3B

3A

2A

2B

1B

1C

1D

1E

1F

1G

2D

2E

2F

2G

1J

39

40

41

42

43

44

45

46

47

48

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

64

65

66

67

68

69

70

71

72

73

74

75

2

3

11P

8P

NC

3

11P

8P

4

A

CS2

BWa

BWb

BWc

BWd

CS2

CS1

A

4

5

8R

A

5

8R

A

6

9R

A

6

9R

A

7

9P

A

7

9P

A

8

10P

10R

11R

11H

11N

11M

11L

11K

11J

10M

10L

10K

10J

11G

11F

11E

11D

10G

10F

10E

10D

11C

11A

10A

10B

9A

A

8

10P

10R

11R

11H

11N

11M

11L

11K

11J

10M

10L

10K

10J

11G

11F

11E

11D

11C

10F

10E

10D

10G

11A

10A

10B

9A

A

9

A

9

A

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

A

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

A

ZZ

DQa

DQb

NC

A

NC

DQa

NC

A

NC

DQb

NC

A

DQc

DQd

A

1K

1L

1K

1L

1M

2J

1M

1N

2K

2L

2K

2L

2M

1N

3P

3R

4R

4P

6P

6R

2M

2J

A

3P

3R

4R

4P

6P

6R

A

9B

A

9B

A

8A

ADV

OE

CKE

WE

A

8A

ADV

OE

CKE

WE

A

8B

A1

8B

A1

7A

A0

7A

A0

7B

NOTE, NC ; Don¢t Care

- 16 -

April 2003

Rev 2.1

K7M163625A

K7M163225A

K7M161825A

512Kx36/32 & 1Mx18 Flow-Through NtRAM^TM

JTAG DC OPERATING CONDITIONS

Parameter

Power Supply Voltage

Symbol

Min

3.135

2.0 / 1.7

-0.3

Typ

Max

3.465

Unit

V

Note

VDD

VIH

VIL

3.3

Input High Level ( 3.3V I/O / 2.5V I/O )

Input Low Level ( 3.3V I/O / 2.5V I/O )

Output High Voltage( 3.3V I/O / 2.5V I/O )

Output Low Voltage( 3.3V I/O / 2.5V I/O )

-

VDD+0.3

0.8 / 0.7

-

V

1

V

VOH

VOL

2.4 / 2.0

-

V

0.4 / 0.4

V

NOTE : The input level of SRAM pin is to follow the SRAM DC specification.

1. In Case of I/O Pins, the Max. VIH=VDDQ +0.3V.

JTAG AC TEST CONDITIONS

Parameter

Symbol

VIH/VIL

TR/TF

Min

Unit

V

Note

Input High/Low Level( 3.3V I/O , 2.5V I/O )

Input Rise/Fall Time( 3.3V I/O , 2.5V I/O )

Input and Output Timing Reference Level

3.0/0 , 2.5/0

1.0/1.0 , 1.0/1.0

VDDQ/2

ns

V

JTAG AC Characteristics

Parameter

TCK Cycle Time

Symbol

Min

50

20

5

Max

Unit

Note

tCHCH

tCHCL

tCLCH

tMVCH

tCHMX

tDVCH

tCHDX

tSVCH

tCHSX

tCLQV

-

ns

TCK High Pulse Width

TCK Low Pulse Width

TMS Input Setup Time

TMS Input Hold Time

TDI Input Setup Time

TDI Input Hold Time

5

SRAM Input Setup Time

SRAM Input Hold Time

Clock Low to Output Valid

5

0

10

JTAG TIMING DIAGRAM

TCK

tCHCH

tCHCL

tCLCH

tMVCH

tCHMX

tCHDX

TMS

TDI

tDVCH

tSVCH

tCHSX

PI

(SRAM)

tCLQV

TDO

- 17 -

April 2003

Rev 2.1

K7M163625A

K7M163225A

K7M161825A

512Kx36/32 & 1Mx18 Flow-Through NtRAM^TM

- 18 -

April 2003

Rev 2.1

K7M163625A

K7M163225A

K7M161825A

512Kx36/32 & 1Mx18 Flow-Through NtRAM^TM

- 19 -

April 2003

Rev 2.1

K7M163625A

K7M163225A

K7M161825A

512Kx36/32 & 1Mx18 Flow-Through NtRAM^TM

- 20 -

April 2003

Rev 2.1

K7M163625A

K7M163225A

K7M161825A

512Kx36/32 & 1Mx18 Flow-Through NtRAM^TM

- 21 -

April 2003

Rev 2.1

K7M163625A

K7M163225A

K7M161825A

512Kx36/32 & 1Mx18 Flow-Through NtRAM^TM

- 22 -

April 2003

Rev 2.1

K7M163625A

K7M163225A

K7M161825A

512Kx36/32 & 1Mx18 Flow-Through NtRAM^TM

PACKAGE DIMENSIONS

100-TQFP-1420A

Units ; millimeters/Inches

22.00 ±0.30

20.00 ±0.20

0~8°

0.127^{+ 0.10}

- 0.05

16.00 ± 0.30

14.00± 0.20

0.10 MAX

(0.83)

0.50 ±0.10

#1

0.65

(0.58)

0.30 ± 0.10

0.10 MAX

1.40 ± 0.10

1.60 MAX

0.05 MIN

0.50 ± 0.10

- 23 -

April 2003

Rev 2.1

K7M163625A

K7M163225A

K7M161825A

512Kx36/32 & 1Mx18 Flow-Through NtRAM^TM

119BGA PACKAGE DIMENSIONS

1.27

14.00±0.10

22.00±0.10

Indicator of

Ball(1A) Location

20.50±0.10

C0.70

C1.00

0.750±0.15

1.50REF

0.60±0.10

Notes

1. All Dimensions are in Millimeters.

2. Solder Ball to PCB Offset : 0.10 MAX.

3. PCB to Cavity Offset : 0.10 MAX.

12.50±0.10

NOTE : 119BGA is only supported with K7N161801A - HC13, K7N163645A - HC16, K7N161845A - HC13 and K7N163645 - HC16.

- 24 -

April 2003

Rev 2.1

K7M163625A

K7M163225A

K7M161825A

512Kx36/32 & 1Mx18 Flow-Through NtRAM^TM

165 FBGA PACKAGE DIMENSIONS

13mm x 15mm Body, 1.0mm Bump Pitch, 11x15 Ball Array

A

B

Top View

C

Side View

D

A

F

E

B

G

Bottom View

Æ H

E

Symbol

Value

15 ± 0.1

13 ± 0.1

1.3 ± 0.1

0.35 ± 0.05

Units

mm

Note

Symbol

Value

1.0

Units

mm

Note

A

B

C

D

E

F

14.0

10.0

mm

G

H

mm

0.5 ± 0.05

mm

- 25 -

April 2003

Rev 2.1


型号：	K7M163625A-QI600
厂家：	SAMSUNG
描述：	ZBT SRAM, 512KX36, 6ns, CMOS, PQFP100, 20 X 14 MM, TQFP-100 静态存储器内存集成电路
文件：	总25页 (文件大小：298K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

K7M163625A-QI600 [SAMSUNG]

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