K7M323625M-90 [SAMSUNG]
SRAM;
SAMSUNG 
K7M323625M
K7M321825M
Preliminary
1Mx36 & 2Mx18 Flow-Through NtRAMTM
1Mx36 & 2Mx18-Bit Flow Through NtRAMTM
FEATURES
GENERAL DESCRIPTION
• 3.3V+0.165V/-0.165V Power Supply.
• I/O Supply Voltage 3.3V+0.165V/-0.165V for 3.3V I/O
or 2.5V+0.4V/-0.125V for 2.5V I/O
• Byte Writable Function.
• Enable clock and suspend operation.
• Single READ/WRITE control pin.
• Self-Timed Write Cycle.
• Three Chip Enable for simple depth expansion with no data
contention .
• A interleaved burst or a linear burst mode.
• Asynchronous output enable control.
• Power Down mode.
The K7M323625M and K7M321825M are 37,748,736-bits Syn-
chronous Static SRAMs.
The NtRAMTM, or No Turnaround Random Access Memory uti-
lizes all bandwidth in any combination of operating cycles.
Address, data inputs, and all control signals except output
enable and linear burst order are synchronized to input clock.
Burst order control must be tied "High or Low".
Asynchronous inputs include the sleep mode enable(ZZ).
Output Enable controls the outputs at any given time.
Write cycles are internally self-timed and initiated by the rising
edge of the clock input. This feature eliminates complex off-chip
write pulse generation
• TTL-Level Three-State Outputs.
• 100-TQFP-1420A /119BGA(7x17 Ball Grid Array Package).
and provides increased timing flexibility for incoming signals.
For read cycles, Flow-Through SRAM allows output data to
simply flow freely from the memory array.
FAST ACCESS TIMES
The K7M323625M and K7M321825M are implemented with
SAMSUNG¢s high performance CMOS technology and is avail-
able in 100pin TQFP and 119BGA packages. Multiple power
and ground pins minimize ground bounce.
Parameter
Cycle Time
Symbol -65 -75 -85 -90 Unit
tCYC
tCD
7.5 8.5 10 10 ns
6.5 7.5 8.5 9.0 ns
3.5 3.5 4.0 4.0 ns
Clock Access Time
Output Enable Access Time
tOE
LOGIC BLOCK DIAGRAM
LBO
BURST
ADDRESS
COUNTER
A¢0~A¢1
A [0:19]or
A [0:20]
A0~A1
A2~A19 or A2~A20
1Mx36 , 2Mx18
MEMORY
ARRAY
ADDRESS
REGISTER
WRITE
ADDRESS
REGISTER
CLK
CKE
K
DATA-IN
REGISTER
K
CS1
CS2
CS2
ADV
WE
CONTROL
LOGIC
BWx
(x=a,b,c,d or a,b)
BUFFER
OE
ZZ
36 or 18
DQa0 ~ DQd7 orDQa0 ~ DQb8
DQPa ~ DQPd
TM
NtRAM and No Turnaround Random Access Memory are trademarks of Samsung.
- 1 -
May 2001
Rev 0.0
K7M323625M
K7M321825M
Preliminary
1Mx36 & 2Mx18 Flow-Through NtRAMTM
(TOP VIEW)
PIN CONFIGURATION
DQPc
DQc0
DQc1
VDDQ
VSSQ
DQc2
DQc3
DQc4
DQc5
VSSQ
VDDQ
DQc6
DQc7
Vss
DQPb
DQb7
DQb6
VDDQ
VSSQ
DQb5
DQb4
DQb3
DQb2
VSSQ
VDDQ
DQb1
DQb0
VSS
1
2
3
4
5
6
7
8
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
100 Pin TQFP
(20mm x 14mm)
VDD
VSS
VDD
ZZ
VDD
VSS
DQd0
DQd1
VDDQ
VSSQ
DQd2
DQd3
DQd4
DQd5
VSSQ
VDDQ
DQd6
DQd7
DQPd
DQa7
DQa6
VDDQ
VSSQ
DQa5
DQa4
DQa3
DQa2
VSSQ
VDDQ
DQa1
DQa0
DQPa
K7M323625M(1Mx36)
PIN NAME
SYMBOL
PIN NAME
Address Inputs
TQFP PIN NO.
SYMBOL
PIN NAME
TQFP PIN NO.
A0 - A18
32,33,34,35,36,37,43 VDD
4445,46,47,48,49,50, VSS
8182,83,84,99,100
Power Supply(+3.3V) 15,16,41,65,91
Ground
14,17,40,66,67,90
38,39,42,43
ADV
WE
Address Advance/Load
Read/Write Control Input 88
85
No Connect
N.C.
CLK
CKE
CS1
CS2
CS2
Clock
89
87
98
97
Data Inputs/Outputs
Data Inputs/Outputs
Data Inputs/Outputs
Data Inputs/Outputs
Data Inputs/Outputs
52,53,56,57,58,59,62,63
68,69,72,73,74,75,78,79
2,3,6,7,8,9,12,13
18,19,22,23,24,25,28,29
51,80,1,30
DQa0~a7
DQb0~b7
DQc0~c7
DQd0~d7
DQPa~Pd
Clock Enable
Chip Select
Chip Select
Chip Select
92
BWx(x=a,b,c,d) Byte Write Inputs
93,94,95,96
OE
ZZ
LBO
Output Enable
Power Sleep Mode
Burst Mode Control
86
64
31
Output Power Supply 4,11,20,27,54,61,70,77
(2.5V or 3.3V)
VDDQ
VSSQ
Output Ground
5,10,21,26,55,60,71,76
Notes : 1. A0 and A1 are the two least significant bits(LSB) of the address field and set the internal burst counter if burst is desired.
- 2 -
May 2001
Rev 0.0
K7M323625M
K7M321825M
Preliminary
1Mx36 & 2Mx18 Flow-Through NtRAMTM
(TOP VIEW)
PIN CONFIGURATION
N.C.
N.C.
N.C.
VDDQ
VSSQ
N.C.
1
2
3
4
5
6
7
8
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
A10
N.C.
N.C.
VDDQ
VSSQ
N.C.
DQa0
DQa1
DQa2
VSSQ
VDDQ
DQa3
DQa4
VSS
N.C.
DQb8
DQb7
VSSQ
VDDQ
DQb6
DQb5
VSS
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
100 Pin TQFP
VDD
VSS
VDD
ZZ
(20mm x 14mm)
VDD
VSS
DQb4
DQb3
VDDQ
VSSQ
DQb2
DQb1
DQb0
N.C.
VSSQ
VDDQ
N.C.
N.C.
N.C.
DQa5
DQa6
VDDQ
VSSQ
DQa7
DQa8
N.C.
N.C.
VSSQ
VDDQ
N.C.
N.C.
N.C.
K7M321825M(2Mx18)
PIN NAME
SYMBOL
PIN NAME
Address Inputs
TQFP PIN NO.
SYMBOL
PIN NAME
TQFP PIN NO.
A0 - A19
32,33,34,35,36,37,43 VDD
44,45,46,47,48,49,50, VSS
8081,82,83,84,99,100
Power Supply(+3.3V) 15,16,41,65,91
Ground
14,17,40,66,67,90
ADV
WE
Address Advance/Load
Read/Write Control Input 88
Clock
Clock Enable
Chip Select
Chip Select
Chip Select
85
No Connect
1,2,3,6,7,25,28,29,30,
38,39,42,43,51,52,53,
56,57,75,78,79,95,96
N.C.
CLK
CKE
CS1
CS2
CS2
89
87
98
97
Data Inputs/Outputs
Data Inputs/Outputs
58,59,62,63,68,69,72,73,74
8,9,12,13,18,19,22,23,24
DQa0~a8
DQb0~b8
92
BWx(x=a,b) Byte Write Inputs
93,94
86
64
OE
ZZ
Output Enable
Power Sleep Mode
Output Power Supply 4,11,20,27,54,61,70,77
(2.5V or 3.3V)
VDDQ
VSSQ
LBO
Burst Mode Control
31
Output Ground
5,10,21,26,55,60,71,76
Notes : 1. A0 and A1 are the two least significant bits(LSB) of the address field and set the internal burst counter if burst is desired.
- 3 -
May 2001
Rev 0.0
K7M323625M
K7M321825M
Preliminary
1Mx36 & 2Mx18 Flow-Through NtRAMTM
(TOP VIEW)
119BGA PACKAGE PIN CONFIGURATIONS
K7M323625M(1Mx36)
1
2
3
A
4
5
A
6
A
7
A
B
C
D
E
F
VDDQ
NC
A
A
VDDQ
NC
CS2
A
A
ADV
VDD
NC
CS1
OE
A
A
CS2
A
NC
A
A
NC
DQc
DQc
VDDQ
DQc
DQc
VDDQ
DQd
DQd
VDDQ
DQd
DQd
NC
DQPc
DQc
DQc
DQc
DQc
VDD
DQd
DQd
DQd
DQd
DQPd
A
VSS
VSS
VSS
BWc
VSS
NC
VSS
BWd
VSS
VSS
VSS
LBO
A
VSS
VSS
VSS
BWb
VSS
NC
VSS
BWa
VSS
VSS
VSS
NC
A
DQPb
DQb
DQb
DQb
DQb
VDD
DQa
DQa
DQa
DQa
DQPa
A
DQb
DQb
VDDQ
DQb
DQb
VDDQ
DQa
DQa
VDDQ
DQa
DQa
NC
G
H
J
WE
VDD
CLK
NC
CKE
A1*
A0*
VDD
A
K
L
M
N
P
R
T
NC
NC
A
ZZ
U
VDDQ
TMS
TDI
TCK
TDO
NC
VDDQ
Note : * A0 and A1 are the two least significant bits(LSB) of the address field and set the internal burst counter if burst is desired.
PIN NAME
SYMBOL
PIN NAME
SYMBOL
PIN NAME
A
Address Inputs
VDD
VSS
Power Supply
Ground
A0,A1
ADV
WE
CLK
CKE
CS1
CS2
CS2
Burst Address Inputs
Address Advance/Load
Read/Write Control Input
Clock
Clock Enable
Chip Select
N.C.
No Connect
DQa
DQb
DQc
DQd
Data Inputs/Outputs
Data Inputs/Outputs
Data Inputs/Outputs
Data Inputs/Outputs
Data Inputs/Outputs
Chip Select
Chip Select
DQPa~Pd
BWx
(x=a,b,c,d)
Byte Write Inputs
VDDQ
Output Power Supply
OE
ZZ
LBO
Output Enable
Power Sleep Mode
Burst Mode Control
TCK
TMS
TDI
JTAG Test Clock
JTAG Test Mode Select
JTAG Test Data Input
JTAG Test Data Output
TDO
- 4 -
May 2001
Rev 0.0
K7M323625M
K7M321825M
Preliminary
1Mx36 & 2Mx18 Flow-Through NtRAMTM
(TOP VIEW)
119BGA PACKAGE PIN CONFIGURATIONS
K7M321825M(2Mx18)
1
2
A
3
A
4
5
A
6
A
7
A
B
C
D
E
F
VDDQ
NC
A
VDDQ
NC
CS2
A
A
ADV
VDD
NC
CS1
OE
A
A
CS2
A
NC
A
A
NC
DQb
NC
NC
DQb
NC
DQb
NC
VDD
DQb
NC
DQb
NC
DQPb
A
VSS
VSS
VSS
BWb
VSS
NC
VSS
VSS
VSS
VSS
VSS
LBO
A
VSS
VSS
VSS
VSS
VSS
NC
VSS
BWa
VSS
VSS
VSS
NC
A
DQPa
NC
DQa
NC
DQa
VDD
NC
DQa
NC
DQa
NC
A
NC
DQa
VDDQ
DQa
NC
VDDQ
NC
G
H
J
DQb
VDDQ
NC
WE
VDD
CLK
NC
CKE
A1*
A0*
VDD
A
VDDQ
DQa
NC
K
L
DQb
VDDQ
DQb
NC
M
N
P
R
T
VDDQ
NC
DQa
NC
NC
NC
A
A
ZZ
U
VDDQ
TMS
TDI
TCK
TDO
NC
VDDQ
Note : * A0 and A1 are the two least significant bits(LSB) of the address field and set the internal burst counter if burst is desired.
PIN NAME
SYMBOL
PIN NAME
SYMBOL
PIN NAME
A
Address Inputs
VDD
VSS
Power Supply
Ground
A0,A1
ADV
WE
CLK
CKE
CS1
Burst Address Inputs
Address Advance/Load
Read/Write Control Input
Clock
Clock Enable
Chip Select
No Connect
N.C.
Data Inputs/Outputs
Data Inputs/Outputs
Data Inputs/Outputs
DQa
DQb
DQPa, Pb
CS2
Chip Select
CS2
Chip Select
BWx
(x=a,b)
Byte Write Inputs
Output Power Supply
VDDQ
OE
ZZ
LBO
Output Enable
Power Sleep Mode
Burst Mode Control
TCK
TMS
TDI
JTAG Test Clock
JTAG Test Mode Select
JTAG Test Data Input
JTAG Test Data Output
TDO
- 5 -
May 2001
Rev 0.0
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ZBT SRAM, 1MX36, 6.5ns, CMOS, PQFP100, 14 X 20 MM, ROHS COMPLIANT, TQFP-100
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