K7M323635C-PI750 [SAMSUNG]
ZBT SRAM, 1MX36, 7.5ns, CMOS, PQFP100, 20 X 14 MM, ROHS COMPLIANT, TQFP-100;型号: | K7M323635C-PI750 |
厂家: | SAMSUNG |
描述: | ZBT SRAM, 1MX36, 7.5ns, CMOS, PQFP100, 20 X 14 MM, ROHS COMPLIANT, TQFP-100 静态存储器 内存集成电路 |
文件: | 总22页 (文件大小:418K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
K7M323635C
K7M321835C
1Mx36 & 2Mx18 Flow-Through NtRAMTM
36Mb NtRAMTM Specification
100 TQFP with Pb / Pb-Free
(RoHS compliant)
INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS,
AND IS SUBJECT TO CHANGE WITHOUT NOTICE.
NOTHING IN THIS DOCUMENT SHALL BE CONSTRUED AS GRANTING ANY LICENSE,
EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE,
TO ANY INTELLECTUAL PROPERTY RIGHTS IN SAMSUNG PRODUCTS OR TECHNOLOGY.
ALL INFORMATION IN THIS DOCUMENT IS PROVIDED
ON AS "AS IS" BASIS WITHOUT GUARANTEE OR WARRANTY OF ANY KIND.
1. For updates or additional information about Samsung products, contact your nearest Samsung office.
2. Samsung products are not intended for use in life support, critical care, medical, safety equipment, or simi-
lar applications where Product failure couldresult in loss of life or personal or physical harm, or any military
or defense application, or any governmental procurement to which special terms or provisions may apply.
* Samsung Electronics reserves the right to change products or specification without notice.
Rev. 1.1 June 2007
- 1 -
K7M323635C
K7M321835C
1Mx36 & 2Mx18 Flow-Through NtRAMTM
Document Title
1Mx36 & 2Mx18-Bit Flow Through NtRAMTM
Revision History
Rev. No.
History
Draft Date
Remark
0.0
0.1
0.2
1.0
1.1
1. Initial document.
Jan. 26. 2006
Feb. 16 2006
Apr. 04. 2006
July.14. 2006
June. 10. 2007
Advance
Preliminary
Preliminary
Final
1. Add the overshoot timing
1. Change ordering information
1. Finalize the datasheet
1. Change Access time 7.5ns to 6.5ns
Final
Rev. 1.1 June 2007
- 2 -
K7M323635C
K7M321835C
1Mx36 & 2Mx18 Flow-Through NtRAMTM
36Mb NtRAM (Flow Through) Ordering Information
Org.
VDD (V)
3.3/2.5
3.3/2.5
Speed (ns)
Access Time (ns)
Part Number
K7M321835C-P(Q)1C(I)265
K7M323635C-P(Q)1C(I)265
RoHS Avail.
2Mx18
1Mx36
8.5
8.5
6.5
6.5
√
√
Note 1. P(Q) [Package type] : P-Pb Free, Q-Pb
2. C(I) [Operating Temperature] : C-Commercial, I-Industrial
Rev. 1.1 June 2007
- 3 -
K7M323635C
K7M321835C
1Mx36 & 2Mx18 Flow-Through NtRAMTM
1Mx36 & 2Mx18-Bit Flow Through NtRAMTM
FEATURES
GENERAL DESCRIPTION
• VDD= 2.5 or 3.3V +/- 5% Power Supply.
• Byte Writable Function.
The K7M323635C and K7M321835C are 37,748,736-bits Syn-
chronous Static SRAMs.
The NtRAMTM, or No Turnaround Random Access Memory uti-
lizes all bandwidth in any combination of operating cycles.
Address, data inputs, and all control signals except output
enable and linear burst order are synchronized to input clock.
Burst order control must be tied "High or Low".
Asynchronous inputs include the sleep mode enable(ZZ).
Output Enable controls the outputs at any given time.
Write cycles are internally self-timed and initiated by the rising
edge of the clock input. This feature eliminates complex off-chip
write pulse generation
• Enable clock and suspend operation.
• Single READ/WRITE control pin.
• Self-Timed Write Cycle.
• Three Chip Enable for simple depth expansion with no data
contention .
• A interleaved burst or a linear burst mode.
• Asynchronous output enable control.
• Power Down mode.
• TTL-Level Three-State Outputs.
• 100-TQFP-1420A (Lead and Lead free package)
• Operating in commeical and industrial temperature range.
and provides increased timing flexibility for incoming signals.
For read cycles, Flow-Through SRAM allows output data to
simply flow freely from the memory array.
The K7M323635C and K7M321835C are implemented with
SAMSUNG′s high performance CMOS technology and is avail-
able in 100pin TQFP packages. Multiple power and ground pins
minimize ground bounce.
FAST ACCESS TIMES
Parameter
Sym.
tCYC
tCD
-65
7.5
6.5
3.5
Unit
ns
Cycle Time
Clock Access Time
ns
Output Enable Access
tOE
ns
LOGIC BLOCK DIAGRAM
LBO
~A
BURST
A′0~A′1
A [0:19]or
ADDRESS
COUNTER
A0
1
1Mx36 , 2Mx18
MEMORY
A [0:20]
ADDRESS
REGISTER
A2~A19 or A2~A20
ARRAY
WRITE
ADDRESS
CLK
CKE
K
REGISTER
DATA-IN
REGISTER
K
CS
CS
CS
1
2
2
ADV
WE
CONTROL
LOGIC
BW
x
(x=a,b,c,d or a,b)
BUFFER
OE
ZZ
36 or 18
DQa ~ DQd7 or DQa0 ~ DQb8
DQP0a ~ DQPd
TM
NtRAM
and No Turnaround Random Access MRemeorvy .ar1e t.r1adeJmuarknseof S2a0m0su7ng.
- 4 -
K7M323635C
K7M321835C
1Mx36 & 2Mx18 Flow-Through NtRAMTM
PIN CONFIGURATION(TOP VIEW)
DQPb
80
DQPc
1
DQb7
79
DQc0
2
DQb6
78
DQc1
3
VDDQ
77
VDDQ
4
VSSQ
76
VSSQ
5
DQb5
75
DQc2
6
DQb4
74
DQc3
7
DQb3
73
DQc4
8
DQb2
72
DQc5
9
VSSQ
71
VSSQ
10
VDDQ
70
VDDQ
11
DQb1
DQc6
12
69
100 Pin TQFP
DQb0
68
DQc7
13
VSS
67
Vss
14
VSS
66
VDD
15
(20mm x 14mm)
VDD
16
VDD
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
ZZ
VSS
DQd0
DQd1
VDDQ
VSSQ
DQd2
DQd3
DQd4
DQd5
VSSQ
VDDQ
DQd6
DQd7
DQPd
17
18
19
20
21
22
23
24
25
26
27
28
29
30
DQa7
DQa6
VDDQ
VSSQ
DQa5
DQa4
DQa3
DQa2
VSSQ
VDDQ
DQa1
DQa0
DQPa
K7M323635C (1Mx36)
PIN NAME
SYMBOL
PIN NAME
TQFP PIN NO.
SYMBOL
PIN NAME
TQFP PIN NO.
A0 - A19
Address Inputs
32,33,34,35,36,37,43 VDD
4445,46,47,48,49,50, VSS
81,82,83,84,99,100
Power Supply(+3.3V) 15,16,41,65,91
Ground
14,17,40,66,67,90
ADV
WE
CLK
CKE
CS1
CS2
CS2
Address Advance/Load 85
Read/Write Control Input 88
Clock
Clock Enable
Chip Select
Chip Select
Chip Select
No Connect
38,39,42
N.C.
89
Data Inputs/Outputs
Data Inputs/Outputs
Data Inputs/Outputs
Data Inputs/Outputs
Data Inputs/Outputs
52,53,56,57,58,59,62,63
68,69,72,73,74,75,78,79
2,3,6,7,8,9,12,13
18,19,22,23,24,25,28,29
51,80,1,30
DQa0~a7
DQb0~b7
DQc0~c7
DQd0~d7
DQPa~Pd
87
98
97
92
BWx(x=a,b,c,d) Byte Write Inputs
93,94,95,96
OE
ZZ
LBO
Output Enable
Power Sleep Mode
Burst Mode Control
86
64
31
Output Power Supply 4,11,20,27,54,61,70,77
(2.5V or 3.3V)
VDDQ
VSSQ
Output Ground
5,10,21,26,55,60,71,76
Notes : 1. A0 and A1 are the two least significant bits(LSB) of the address field and set the internal burst counter if burst is desired.
Rev. 1.1 June 2007
- 5 -
K7M323635C
K7M321835C
1Mx36 & 2Mx18 Flow-Through NtRAMTM
PIN CONFIGURATION(TOP VIEW)
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
A10
N.C.
N.C.
N.C.
VDDQ
VSSQ
N.C.
N.C.
DQb8
DQb7
VSSQ
VDDQ
DQb6
DQb5
VSS
1
N.C.
N.C.
VDDQ
VSSQ
N.C.
DQa0
DQa1
DQa2
VSSQ
VDDQ
DQa3
DQa4
VSS
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
100 Pin TQFP
(20mm x 14mm)
VSS
VDD
VDD
VDD
VSS
ZZ
DQb4
DQb3
VDDQ
VSSQ
DQb2
DQb1
DQb0
N.C.
VSSQ
VDDQ
N.C.
N.C.
N.C.
DQa5
DQa6
VDDQ
VSSQ
DQa7
DQa8
N.C.
N.C.
VSSQ
VDDQ
N.C.
N.C.
N.C.
K7M321835C (2Mx18)
PIN NAME
SYMBOL
PIN NAME
TQFP PIN NO.
SYMBOL
PIN NAME
TQFP PIN NO.
A0 - A20
Address Inputs
32,33,34,35,36,37,43 VDD
44,45,46,47,48,49,50, VSS
80,81,82,83,84,99,100
Power Supply(+3.3V) 15,16,41,65,91
Ground
14,17,40,66,67,90
ADV
WE
CLK
CKE
CS1
CS2
CS2
Address Advance/Load 85
Read/Write Control Input 88
Clock
Clock Enable
Chip Select
Chip Select
Chip Select
No Connect
1,2,3,6,7,25,28,29,30,
38,39,42,51,52,53,
56,57,75,78,79,95,96
N.C.
89
87
98
Data Inputs/Outputs
Data Inputs/Outputs
58,59,62,63,68,69,72,73,74
8,9,12,13,18,19,22,23,24
DQa0~a8
DQb0~b8
97
92
BWx(x=a,b) Byte Write Inputs
93,94
86
OE
ZZ
LBO
Output Enable
Power Sleep Mode
Burst Mode Control
Output Power Supply 4,11,20,27,54,61,70,77
(2.5V or 3.3V)
VDDQ
VSSQ
64
31
Output Ground
5,10,21,26,55,60,71,76
Notes : 1. A0 and A1 are the two least significant bits(LSB) of the address field and set the internal burst counter if burst is desired.
Rev. 1.1 June 2007
- 6 -
K7M323635C
K7M321835C
1Mx36 & 2Mx18 Flow-Through NtRAMTM
FUNCTION DESCRIPTION
The K7M323635C and K7M321835C are NtRAMTM designed to sustain 100% bus bandwidth by eliminating turnaround cycle when
there is transition from Read to Write, or vice versa.
All inputs (with the exception of OE, LBO and ZZ) are synchronized to rising clock edges.
All read, write and deselect cycles are initiated by the ADV input. Subsequent burst addresses can be internally generated by the
burst advance pin (ADV). ADV should be driven to Low once the device has been deselected in order to load a new address for next
operation.
Clock Enable(CKE) pin allows the operation of the chip to be suspended as long as necessary. When CKE is high, all synchronous
inputs are ignored and the internal device registers will hold their previous values.
NtRAMTM latches external address and initiates a cycle, when CKE, ADV are driven to low and all three chip enables(CS1, CS2, CS2)
are active. Output Enable(OE) can be used to disable the output at any given time.
Read operation is initiated when at the rising edge of the clock, the address presented to the address inputs are latched in the
address register, CKE is driven low, all three chip enables(CS1, CS2, CS2) are active, the write enable input signals WE are driven
high, and ADV driven low. Data appears at the outputs within the same clock cycle as the address for the data. Also during read oper-
ation OE must be driven low for the device to drive out the requested data.
Write operation occurs when WE is driven low at the rising edge of the clock. BW[d:a] can be used for byte write operation. The Flow
Through NtRAMTM uses a late write cycle to utilize 100% of the bandwidth.
At the first rising edge of the clock, WE and address are registered, and the data associated with that address is required one cycle
later.
Subsequent addresses are generated by ADV High for the burst access as shown below. The starting point of the burst seguence is
provided by the external address. The burst address counter wraps around to its initial state upon completion.
The burst sequence is determined by the state of the LBO pin. When this pin is low, linear burst sequence is selected.
And when this pin is high, Interleaved burst sequence is selected.
During normal operation, ZZ must be driven low. When ZZ is driven high, the SRAM will enter a Power Sleep Mode after 2 cycles. At
this time, internal state of the SRAM is preserved. When ZZ returns to low, the SRAM normally operates after 2 cycles of wake up
time.
BURST SEQUENCE TABLE
(Interleaved Burst, LBO=High)
Case 4
Case 1
Case 2
Case 3
LBO PIN
HIGH
A1
A0
A1
A0
A1
A0
A1
A0
First Address
0
0
1
1
0
1
0
1
0
0
1
1
1
0
1
0
1
1
0
0
0
1
0
1
1
1
0
0
1
0
1
0
Fourth Address
BQ TABLE
(Linear Burst, LBO=Low)
Case 4
Case 1
Case 2
Case 3
LBO PIN
LOW
A1
A0
A1
A0
A1
A0
A1
A0
First Address
0
0
1
1
0
1
0
1
0
1
1
0
1
0
1
0
1
1
0
0
0
1
0
1
1
0
0
1
1
0
1
0
Fourth Address
Note : 1. LBO pin must be tied to High or Low, and Floating State must not be allowed.
Rev. 1.1 June 2007
- 7 -
K7M323635C
K7M321835C
1Mx36 & 2Mx18 Flow-Through NtRAMTM
STATE DIAGRAM FOR NtRAMTM
WRITE
READ
BEGIN
READ
BEGIN
WRITE
WRITE
READ
DESELECT
BURST
READ
BURST
WRITE
BURST
BURST
COMMAND
ACTION
DS
DESELECT
READ
WRITE
BEGIN READ
BEGIN WRITE
BEGIN READ
BURST
BEGIN WRITE
CONTINUE DESELECT
Notes : 1. An IGNORE CLOCK EDGE cycle is not shown is the above diagram. This is because CKE HIGH only blocks the clock(CLK) input and does
not change the state of the device.
2. States change on the rising edge of the clock(CLK)
Rev. 1.1 June 2007
- 8 -
K7M323635C
K7M321835C
1Mx36 & 2Mx18 Flow-Through NtRAMTM
TRUTH TABLES
SYNCHRONOUS TRUTH TABLE
CS1 CS2 CS2 ADV WE BWx OE
CKE CLK
ADDRESS ACCESSED
N/A
OPERATION
Not Selected
H
X
X
X
L
X
L
X
X
H
X
L
L
L
X
X
X
X
H
X
H
X
L
X
X
X
X
X
X
X
X
L
X
X
X
X
L
L
L
L
L
L
L
L
L
L
L
L
L
H
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
N/A
Not Selected
X
X
H
X
H
X
H
X
H
X
X
L
N/A
Not Selected
H
L
N/A
Not Selected Continue
Begin Burst Read Cycle
Continue Burst Read Cycle
NOP/Dummy Read
Dummy Read
External Address
Next Address
External Address
Next Address
External Address
Next Address
N/A
X
L
X
L
H
L
L
H
H
X
X
X
X
X
X
L
X
L
H
L
Begin Burst Write Cycle
Continue Burst Write Cycle
NOP/Write Abort
Write Abort
X
L
X
L
H
L
X
L
L
H
H
X
X
X
X
X
H
X
X
X
Next Address
Current Address
Ignore Clock
Notes : 1. X means "Don′t Care".
2. The rising edge of clock is symbolized by (↑).
3. A continue deselect cycle can only be enterd if a deselect cycle is executed first.
4. WRITE = L means Write operation in WRITE TRUTH TABLE.
WRITE = H means Read operation in WRITE TRUTH TABLE.
5. Operation finally depends on status of asynchronous input pins(ZZ and OE).
WRITE TRUTH TABLE( x36)
WE
H
L
BWa
X
BWb
X
BWc
X
BWd
X
OPERATION
READ
L
H
H
H
WRITE BYTE a
WRITE BYTE b
WRITE BYTE c
WRITE BYTE d
WRITE ALL BYTEs
WRITE ABORT/NOP
L
H
L
H
H
L
H
H
L
H
L
H
H
H
L
L
L
L
L
L
L
H
H
H
H
Notes : 1. X means "Don′t Care".
2. All inputs in this table must meet setup and hold time around the rising edge of CLK(↑).
WRITE TRUTH TABLE(x18)
WE
BWa
X
BWb
OPERATION
H
X
H
L
READ
L
L
WRITE BYTE a
WRITE BYTE b
WRITE ALL BYTEs
WRITE ABORT/NOP
L
H
L
L
L
L
H
H
Notes : 1. X means "Don′t Care".
2. All inputs in this table must meet setup and hold time around the rising edge of CLK(↑).
Rev. 1.1 June 2007
- 9 -
K7M323635C
K7M321835C
1Mx36 & 2Mx18 Flow-Through NtRAMTM
ASYNCHRONOUS TRUTH TABLE
Notes
Operation
ZZ
H
L
OE
I/O STATUS
1. X means "Don′t Care".
Sleep Mode
X
High-Z
DQ
2. Sleep Mode means power Sleep Mode of which stand-by current does
not depend on cycle time.
L
3. Deselected means power Sleep Mode of which stand-by current
depends on cycle time.
Read
L
H
X
High-Z
Write
L
Din, High-Z
High-Z
Deselected
L
X
ABSOLUTE MAXIMUM RATINGS*
PARAMETER
Voltage on VDD Supply Relative to VSS
Voltage on Any Other Pin Relative to VSS
Power Dissipation
SYMBOL
VDD
RATING
-0.3 to 4.6
-0.3 to VDD+0.3
1.6
UNIT
V
VIN
V
PD
W
Storage Temperature
TSTG
TOPR
TOPR
TBIAS
-65 to 150
0 to 70
°C
°C
°C
°C
Commercial
Industrial
Operating Temperature
-40 to 85
-10 to 85
Storage Temperature Range Under Bias
*Notes : Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only
and functional operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not
implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
OPERATING CONDITIONS
PARAMETER
SYMBOL
VDD1
MIN
2.375
2.375
3.135
3.135
0
Typ.
2.5
2.5
3.3
3.3
0
MAX
2.625
2.625
3.465
3.465
0
UNIT
V
V
V
V
V
VDDQ1
VDD2
Supply Voltage
VDDQ2
VSS
Ground
Notes: 1. The above parameters are also guaranteed at industrial temperature range.
2. It should be VDDQ ≤ VDD
CAPACITANCE*(TA=25°C, f=1MHz)
PARAMETER
Input Capacitance
SYMBOL
CIN
TEST CONDITION
VIN=0V
MIN
-
-
MAX
5
7
UNIT
pF
Output Capacitance
COUT
VOUT=0V
pF
*Note : Sampled not 100% tested.
Overshoot Timing
Undershoot Timing
20% tCYC(MIN)
VIH
VDDQ+1.0V
VDDQ+0.5V
VDDQ
VSS
VSS-0.5V
VSS-1.0V
20% tCYC(MIN)
VIL
Rev. 1.1 June 2007
- 10 -
K7M323635C
K7M321835C
1Mx36 & 2Mx18 Flow-Through NtRAMTM
DC ELECTRICAL CHARACTERISTICS
PARAMETER
SYMBOL
TEST CONDITIONS
VDD=Max ; VIN=VSS to VDD
MIN
-2
MAX
+2
UNIT NOTES
Input Leakage Current(except ZZ)
Output Leakage Current
IIL
µA
µA
IOL
Output Disabled,
-2
+2
Device Selected, IOUT=0mA,
ZZ≤VIL , Cycle Time ≥ tCYC Min
Operating Current
Standby Current
ICC
ISB
-
-
-
-
310
140
110
100
mA
mA
mA
mA
1,2
Device deselected, IOUT=0mA, ZZ≤VIL, f=Max,
All Inputs≤0.2V or ≥ VDD-0.2V
Device deselected, IOUT=0mA, ZZ≤0.2V, f=0,
All Inputs=fixed (VDD-0.2V or 0.2V)
ISB1
ISB2
Device deselected, IOUT=0mA, ZZ≥VDD-0.2V,
f=Max, All Inputs≤VIL or ≥VIH
Output Low Voltage(3.3V I/O)
Output High Voltage(3.3V I/O)
Output Low Voltage(2.5V I/O)
Output High Voltage(2.5V I/O)
Input Low Voltage(3.3V I/O)
Input High Voltage(3.3V I/O)
Input Low Voltage(2.5V I/O)
Input High Voltage(2.5V I/O)
VOL
VOH
VOL
VOH
VIL
IOL=8.0mA
IOH=-4.0mA
IOL=1.0mA
IOH=-1.0mA
-
0.4
V
V
V
V
V
V
V
V
2.4
-
-
0.4
-
2.0
-0.3*
2.0
-0.3*
1.7
0.8
VDD+0.3**
0.7
3
3
VIH
VIL
VIH
VDD+0.3**
Notes : 1. The above parameters are also guaranteed at industrial temperature range.
2. Reference AC Operating Conditions and Characteristics for input and timing.
3. Data states are all zero.
4. In Case of I/O Pins, the Max. VIH=VDDQ+0.3V.
TEST CONDITIONS
PARAMETER
Input Pulse Level(for 3.3V I/O)
Input Pulse Level(for 2.5V I/O)
Input Rise and Fall Time(Measured at 20% to 80% for 3.3/2.5V I/O)
Input and Output Timing Reference Levels for 3.3V I/O
Input and Output Timing Reference Levels for 2.5V I/O
Output Load
VALUE
0 to 3.0V
0 to 2.5V
1.0V/ns
1.5V
VDDQ/2
See Fig. 1
* The above parameters are also guaranteed at industrial temperature range.
Output Load(A)
Output Load(B),
(for tLZC, tLZOE, tHZOE & tHZC)
+3.3V for 3.3V I/O
/+2.5V for 2.5V I/O
RL=50Ω
Dout
VL=1.5V for 3.3V I/O
VDDQ/2 for 2.5V I/O
319Ω / 1667Ω
30pF*
Dout
Zo=50Ω
353Ω / 1538Ω
5pF*
* Including Scope and Jig Capacitance
Fig. 1
Rev. 1.1 June 2007
- 11 -
K7M323635C
K7M321835C
1Mx36 & 2Mx18 Flow-Through NtRAMTM
AC TIMING CHARACTERISTICS
-75
PARAMETER
SYMBOL
UNIT
MIN
7.5
-
MAX
Cycle Time
tCYC
tCD
-
ns
ns
Clock Access Time
6.5
Output Enable to Data Valid
Clock High to Output Low-Z
Output Hold from Clock High
Output Enable Low to Output Low-Z
Output Enable High to Output High-Z
Clock High to Output High-Z
Clock High Pulse Width
tOE
-
3.5
ns
tLZC
tOH
2.5
2.5
0
-
ns
-
ns
tLZOE
tHZOE
tHZC
tCH
-
ns
-
3.5
ns
-
3.8
-
ns
2.5
2.5
1.5
1.5
1.5
1.5
1.5
1.5
0.5
0.5
0.5
0.5
0.5
0.5
2
ns
Clock Low Pulse Width
tCL
-
ns
Address Setup to Clock High
CKE Setup to Clock High
tAS
-
ns
tCES
tDS
-
ns
Data Setup to Clock High
-
ns
Write Setup to Clock High (WE, BWX)
Address Advance Setup to Clock High
Chip Select Setup to Clock High
Address Hold from Clock High
CKE Hold from Clock High
tWS
-
ns
tADVS
tCSS
tAH
-
ns
-
ns
-
ns
tCEH
tDH
-
ns
Data Hold from Clock High
-
ns
Write Hold from Clock High (WE, BWX)
Address Advance Hold from Clock High
Chip Select Hold from Clock High
ZZ High to Power Down
tWH
-
ns
tADVH
tCSH
tPDS
tPUS
-
ns
-
ns
-
cycle
cycle
ZZ Low to Power Up
2
-
Notes : 1. The above parameters are also guaranteed at industrial temperature range.
2. All address inputs must meet the specified setup and hold times for all rising clock(CLK) edges when ADV is sampled low and CS is sampled
low. All other synchronous inputs must meet the specified setup and hold times whenever this device is chip selected.
3. Chip selects must be valid at each rising edge of CLK(when ADV is Low) to remain enabled.
4. A write cycle is defined by WE low having been registerd into the device at ADV Low, A Read cycle is defined by WE High with ADV Low,
Both cases must meet setup and hold times.
5. To avoid bus contention, At a given vlotage and temperature tLZC is more than tHZC.
The soecs as shown do not imply bus contention because tLZC is a Min. parameter that is worst case at totally different test conditions
(0°C,3.465V) than tHZC, which is a Max. parameter(worst case at 70°C,3.135V)
It is not possible for two SRAMs on the same board to be at such different voltage and temperatue.
Rev. 1.1 June 2007
- 12 -
K7M323635C
K7M321835C
1Mx36 & 2Mx18 Flow-Through NtRAMTM
SLEEP MODE
SLEEP MODE is a low current, power-down mode in which the device is deselected and current is reduced to ISB2. The duration of
SLEEP MODE is dictated by the length of time the ZZ is in a High state.
After entering SLEEP MODE, all inputs except ZZ become disabled and all outputs go to High-Z
The ZZ pin is an asynchronous, active high input that causes the device to enter SLEEP MODE.
When the ZZ pin becomes a logic High, ISB2 is guaranteed after the time tZZI is met. Any operation pending when entering SLEEP
MODE is not guaranteed to successful complete. Therefore, SLEEP MODE (READ or WRITE) must not be initiated until valid pend-
ing operations are completed. similarly, when exiting SLEEP MODE during tPUS, only a DESELECT or READ cycle should be given
while the SRAM is transitioning out of SLEEP MODE.
SLEEP MODE ELECTRICAL CHARACTERISTICS
DESCRIPTION
Current during SLEEP MODE
CONDITIONS
SYMBOL
ISB2
MIN
MAX
UNITS
mA
ZZ ≥ VIH
TBD
ZZ active to input ignored
tPDS
2
2
cycle
cycle
cycle
tPUS
ZZ inactive to input sampled
ZZ active to SLEEP current
tZZI
2
ZZ inactive to exit SLEEP current
tRZZI
0
SLEEP MODE WAVEFORM
K
tPDS
tPUS
ZZ setup cycle
ZZ recovery cycle
ZZ
tZZI
Isupply
ISB2
tRZZI
All inputs
Deselect or Read Only
Deselect or Read Only
(except ZZ)
Normal
operation
cycle
Outputs
(Q)
High-Z
DON′T CARE
Rev. 1.1 June 2007
- 13 -
K7M323635C
K7M321835C
1Mx36 & 2Mx18 Flow-Through NtRAMTM
Rev. 1.1 June 2007
- 14 -
K7M323635C
K7M321835C
1Mx36 & 2Mx18 Flow-Through NtRAMTM
Rev. 1.1 June 2007
- 15 -
K7M323635C
K7M321835C
1Mx36 & 2Mx18 Flow-Through NtRAMTM
Rev. 1.1 June 2007
- 16 -
K7M323635C
K7M321835C
1Mx36 & 2Mx18 Flow-Through NtRAMTM
Rev. 1.1 June 2007
- 17 -
K7M323635C
K7M321835C
1Mx36 & 2Mx18 Flow-Through NtRAMTM
Rev. 1.1 June 2007
- 18 -
K7M323635C
K7M321835C
1Mx36 & 2Mx18 Flow-Through NtRAMTM
PACKAGE DIMENSIONS
Units ; millimeters/Inches
100-TQFP-1420A (Lead and Lead-Free)
22.00
20.00
±
±
0.30
0.20
0~8
°
+ 0.10
- 0.05
0.127
16.00
14.00
±
0.30
0.10 MAX
±
0.20
(0.83)
0.50 ±0.10
#1
0.65
(0.58)
0.30
±0.10
0.10 MAX
1.40
±0.10
1.60 MAX
0.05 MIN
0.50 ±0.10
Rev. 1.1 June 2007
- 19 -
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14.0X20.0
K7M323635C-PC75
Lead Free
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Lead Free
14.0X20.0
K7M323635C-PI75
Lead Free
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Copyright© 2007 SAMSUNG. All right
part number
life cycle
K7M323635C-PC750
K7M323635C-PC75T
K7M323635C-PI750
PRODUCTION
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MASS
MASS
MASS
die revision
PRODUCTION
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PRODUCTION
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MOQ (large box)
qual sample
720
800
720
2880
4000
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Q3/2004
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N/A
Q4/2005
Q1/2005
N/A
Q1/2006
Q2/2006
N/A
mass production
last time buy
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N/A
N/A
N/A
replacement part
number
Technical File Download
- specification data
file
rev #
size
updated date
Data Sheet
1.1
386KB
2007/08/13
- simulation models
file
rev #
size
updated date
IBIS
IBIS : 3.2,
File : 0.2
140KB
2007/08/13
Verilog
BSDL
0.1
0.0
8KB
2007/08/13
2007/08/13
10KB
RoHS information
For more information, please click the button next to the product name.
material declaration sheet
declaration letter
does not contain hazardous materials defined in China RoHS
contains hazardous materials defined in China RoHS
is Lead-free and RoHS-compliant.
K7M323635C-PC750
K7M323635C-PC75T
K7M323635C-PI750
is Lead-free and RoHS-compliant.
is Lead-free and RoHS-compliant.
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