K7N161845-FI13 [SAMSUNG]
512Kx36 & 1Mx18-Bit Flow Through NtRAM; 512Kx36及1Mx18位流经NtRAM型号: | K7N161845-FI13 |
厂家: | SAMSUNG |
描述: | 512Kx36 & 1Mx18-Bit Flow Through NtRAM |
文件: | 总18页 (文件大小:214K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
K7M163625A
K7M161825A
512Kx36 & 1Mx18 Flow-Through NtRAMTM
Document Title
512Kx36 & 1Mx18-Bit Flow Through NtRAMTM
Revision History
Rev. No.
History
Draft Date
Remark
0.0
0.1
0.2
1. Initial document.
1. Add JTAG Scan Order
Feb. 23. 2001
May. 10. 2001
Aug. 03. 2001
Preliminary
Preliminary
Preliminary
1. Remove bin -90
2. Updated DC characteristics(ICC,ISB,ISB1,ISB2)
1. Add x32 org and industrial temperature .
2. Add 165FBGA package
0.3
Aug. 30. 2001
Preliminary
1.0
2.0
2.1
1. Final spec release
May. 10. 2002
Oct. 26, 2002
April. 04. 2003
Final
Final
Final
1. Add the speed bin (-60)
1. Delete 119BGA package.
2. Correct the Ball Size of 165 FBGA.
3.0
1. Delete x32 Org. and 165FBGA pkg. type.
2. Delete the 6.0ns and 8.5ns speed bin
Nov. 17, 2003
Final
The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the
specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions on the parameters of this device. If you have any ques-
tions, please contact the SAMSUNG branch office near your office, call or contact Headquarters.
- 1 -
Nov. 2003
Rev 3.0
K7M163625A
K7M161825A
512Kx36 & 1Mx18 Flow-Through NtRAMTM
16Mb NtRAM(Flow Through / Pipelined) Ordering Information
Speed
Org.
Part Number
Mode
VDD
FT ; Access Time(ns)
PKG
Temp
Pipelined ; Cycle Time(MHz)
K7M161825A-QC(I)65/75
FlowThrough 3.3
6.5/7.5 ns
C
1Mx18
; Commercial
Temp.Range
K7N161801A-Q(F)C(I)25/20/16/13
K7N161845A-Q(F)C(I)25/20/16/13
K7M163625A-QC(I)65/75
Pipelined
Pipelined
3.3
2.5
250/200/167/133MHz
250/200/167/133MHz
6.5/7.5 ns
Q : 100TQFP
F : 165FBGA
FlowThrough 3.3
I
; Industrial
Temp.Range
512Kx36
K7N163601A-Q(F)C(I)25/20/16/13
K7N163645A-Q(F)C(I)25/20/16/13
Pipelined
Pipelined
3.3
2.5
250/200/167/133MHz
250/200/167/133MHz
- 2 -
Nov. 2003
Rev 3.0
K7M163625A
K7M161825A
512Kx36 & 1Mx18 Flow-Through NtRAMTM
512Kx36 & 1Mx18-Bit Flow Through NtRAMTM
FEATURES
GENERAL DESCRIPTION
• 3.3V+0.165V/-0.165V Power Supply.
• I/O Supply Voltage 3.3V+0.165V/-0.165V for 3.3V I/O
or 2.5V+0.4V/-0.125V for 2.5V I/O
• Byte Writable Function.
• Enable clock and suspend operation.
• Single READ/WRITE control pin.
• Self-Timed Write Cycle.
The K7M163625A and K7M161825A are 18,874,368-bits Syn-
chronous Static SRAMs.
The NtRAMTM, or No Turnaround Random Access Memory uti-
lizes all bandwidth in any combination of operating cycles.
Address, data inputs, and all control signals except output
enable and linear burst order are synchronized to input clock.
Burst order control must be tied "High or Low".
• Three Chip Enable for simple depth expansion with no data
contention .
Asynchronous inputs include the sleep mode enable(ZZ).
Output Enable controls the outputs at any given time.
Write cycles are internally self-timed and initiated by the rising
edge of the clock input. This feature eliminates complex off-chip
write pulse generation
• A interleaved burst or a linear burst mode.
• Asynchronous output enable control.
• Power Down mode.
• TTL-Level Three-State Outputs.
• 100-TQFP-1420A
• Operating in commeical and industrial temperature range.
and provides increased timing flexibility for incoming signals.
For read cycles, Flow-Through SRAM allows output data to
simply flow freely from the memory array.
The K7M163625A and K7M161825A are implemented with
SAMSUNG¢s high performance CMOS technology and is avail-
able in 100pin TQFP packages. Multiple power and ground pins
minimize ground bounce.
FAST ACCESS TIMES
Parameter
Cycle Time
Clock Access Time
Sym.
tCYC
tCD
-65
7.5
6.5
3.5
-75
8.5
7.5
3.5
Unit
ns
ns
Output Enable Access Time tOE
ns
LOGIC BLOCK DIAGRAM
LBO
A0~A1
A2~A18 or A2~A19
BURST
ADDRESS
COUNTER
A¢0~A¢1
A [0:18]or
A [0:19]
512Kx36, 1Mx18
MEMORY
ARRAY
ADDRESS
REGISTER
WRITE
ADDRESS
REGISTER
CLK
CKE
K
DATA-IN
REGISTER
K
CS1
CS2
CS2
ADV
WE
CONTROL
LOGIC
BWx
(x=a,b,c,d or a,b)
BUFFER
OE
ZZ
36 or 18
DQa0 ~ DQd7 or DQa0 ~ DQb8
DQPa ~ DQPd
NtRAMTM and No Turnaround Random Access Memory are trademarks of Samsung.
- 3 -
Nov. 2003
Rev 3.0
K7M163625A
K7M161825A
512Kx36 & 1Mx18 Flow-Through NtRAMTM
PIN CONFIGURATION(TOP VIEW)
NC/DQPc
1
DQPb/NC
DQb7
DQb6
VDDQ
VSSQ
DQb5
DQb4
DQb3
DQb2
VSSQ
VDDQ
DQb1
DQb0
VSS
VSS
VDD
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
DQc0
DQc1
VDDQ
VSSQ
2
3
4
5
DQc2
DQc3
DQc4
DQc5
VSSQ
VDDQ
DQc6
DQc7
Vss
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
100 Pin TQFP
(20mm x 14mm)
VDD
VDD
VSS
ZZ
DQa7
DQa6
VDDQ
VSSQ
DQa5
DQa4
DQa3
DQa2
VSSQ
VDDQ
DQa1
DQa0
DQPa/NC
DQd0
DQd1
VDDQ
VSSQ
DQd2
DQd3
DQd4
DQd5
VSSQ
K7M163625A(512Kx36)
VDDQ
DQd6
DQd7
NC/DQPd
PIN NAME
SYMBOL
PIN NAME
TQFP PIN NO.
SYMBOL
PIN NAME
TQFP PIN NO.
A0 - A18
Address Inputs
32,33,34,35,36,37,44 VDD
45,46,47,48,49,50,81 VSS
82,83,84,99,100
Power Supply(+3.3V) 15,16,41,65,91
Ground
14,17,40,66,67,90
38,39,42,43
ADV
WE
Address Advance/Load
Read/Write Control Input 88
85
No Connect
N.C.
CLK
CKE
CS1
CS2
CS2
Clock
89
Data Inputs/Outputs
Data Inputs/Outputs
Data Inputs/Outputs
Data Inputs/Outputs
Data Inputs/Outputs
52,53,56,57,58,59,62,63
68,69,72,73,74,75,78,79
2,3,6,7,8,9,12,13
18,19,22,23,24,25,28,29
51,80,1,30
DQa0~a7
DQb0~b7
DQc0~c7
DQd0~d7
DQPa~Pd
or NC
Clock Enable
Chip Select
Chip Select
Chip Select
87
98
97
92
BWx(x=a,b,c,d) Byte Write Inputs
93,94,95,96
OE
ZZ
LBO
Output Enable
86
64
31
Power Sleep Mode
Burst Mode Control
Output Power Supply 4,11,20,27,54,61,70,77
(2.5V or 3.3V)
VDDQ
VSSQ
Output Ground
5,10,21,26,55,60,71,76
Notes : 1. A0 and A1 are the two least significant bits(LSB) of the address field and set the internal burst counter if burst is desired.
- 4 -
Nov. 2003
Rev 3.0
K7M163625A
K7M161825A
512Kx36 & 1Mx18 Flow-Through NtRAMTM
PIN CONFIGURATION(TOP VIEW)
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
A10
N.C.
N.C.
N.C.
VDDQ
VSSQ
N.C.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
N.C.
N.C.
VDDQ
VSSQ
N.C.
DQa0
DQa1
DQa2
VSSQ
VDDQ
DQa3
DQa4
VSS
N.C.
DQb8
DQb7
VSSQ
VDDQ
DQb6
DQb5
VSS
VDD
VDD
VSS
DQb4
DQb3
VDDQ
VSSQ
DQb2
DQb1
DQb0
N.C.
VSSQ
VDDQ
N.C.
N.C.
N.C.
100 Pin TQFP
(20mm x 14mm)
VSS
VDD
ZZ
DQa5
DQa6
VDDQ
VSSQ
DQa7
DQa8
N.C.
N.C.
VSSQ
VDDQ
N.C.
N.C.
N.C.
K7M161825A(1Mx18)
PIN NAME
SYMBOL
PIN NAME
Address Inputs
TQFP PIN NO.
SYMBOL
PIN NAME
TQFP PIN NO.
A0 - A19
32,33,34,35,36,37,44 VDD
45,46,47,48,49,50,80 VSS
81,82,83,84,99,100
Power Supply(+3.3V) 15,16,41,65,91
Ground
14,17,40,66,67,90
ADV
WE
Address Advance/Load
Read/Write Control Input 88
Clock
85
No Connect
1,2,3,6,7,25,28,29,30,
38,39,42,43,51,52,53,
56,57,75,78,79,95,96
N.C.
CLK
CKE
CS1
CS2
CS2
89
Clock Enable
Chip Select
Chip Select
Chip Select
87
98
97
Data Inputs/Outputs
Data Inputs/Outputs
58,59,62,63,68,69,72,73,74
8,9,12,13,18,19,22,23,24
DQa0~a8
DQb0~b8
92
BWx(x=a,b) Byte Write Inputs
93,94
86
OE
ZZ
Output Enable
Output Power Supply 4,11,20,27,54,61,70,77
(2.5V or 3.3V)
VDDQ
VSSQ
Power Sleep Mode
Burst Mode Control
64
31
LBO
Output Ground
5,10,21,26,55,60,71,76
Notes : 1. A0 and A1 are the two least significant bits(LSB) of the address field and set the internal burst counter if burst is desired.
- 5 -
Nov. 2003
Rev 3.0
K7M163625A
K7M161825A
512Kx36 & 1Mx18 Flow-Through NtRAMTM
FUNCTION DESCRIPTION
The K7M163625A and K7M161825A are NtRAMTM designed to sustain 100% bus bandwidth by eliminating turnaround cycle when
there is transition from Read to Write, or vice versa.
All inputs (with the exception of OE, LBO and ZZ) are synchronized to rising clock edges.
All read, write and deselect cycles are initiated by the ADV input. Subsequent burst addresses can be internally generated by the
burst advance pin (ADV). ADV should be driven to Low once the device has been deselected in order to load a new address for next
operation.
Clock Enable(CKE) pin allows the operation of the chip to be suspended as long as necessary. When CKE is high, all synchronous
inputs are ignored and the internal device registers will hold their previous values.
NtRAMTM latches external address and initiates a cycle, when CKE, ADV are driven to low and all three chip enables(CS1, CS 2, CS 2)
are active .
Output Enable(OE) can be used to disable the output at any given time.
Read operation is initiated when at the rising edge of the clock, the address presented to the address inputs are latched in the
address register, CKE is driven low, all three chip enables(CS 1, CS2, CS2) are active, the write enable input signals WE are driven
high, and ADV driven low. Data appears at the outputs within the same clock cycle as the address for the data. Also during read
operation OE must be driven low for the device to drive out the requested data.
Write operation occurs when WE is driven low at the rising edge of the clock. BW[d:a] can be used for byte write operation. The Flow
Through NtRAMTM uses a late write cycle to utilize 100% of the bandwidth.
At the first rising edge of the clock, WE and address are registered, and the data associated with that address is required one cycle
later.
Subsequent addresses are generated by ADV High for the burst access as shown below. The starting point of the burst seguence is
provided by the external address. The burst address counter wraps around to its initial state upon completion.
The burst sequence is determined by the state of the LBO pin. When this pin is low, linear burst sequence is selected.
And when this pin is high, Interleaved burst sequence is selected.
During normal operation, ZZ must be driven low. When ZZ is driven high, the SRAM will enter a Power Sleep Mode after 2 cycles. At
this time, internal state of the SRAM is preserved. When ZZ returns to low, the SRAM normally operates after 2 cycles of wake up
time.
BURST SEQUENCE TABLE
(Interleaved Burst, LBO=High)
Case 4
Case 1
Case 2
Case 3
LBO PIN
HIGH
First Address
A1
A0
A1
A0
A1
A0
A1
A0
0
0
1
1
0
1
0
1
0
0
1
1
1
0
1
0
1
1
0
0
0
1
0
1
1
1
0
0
1
0
1
0
Fourth Address
BQ TABLE
(Linear Burst, LBO=Low)
Case 4
Case 1
Case 2
Case 3
LBO PIN
LOW
First Address
A1
A0
A1
A0
A1
A0
A1
A0
0
0
1
1
0
1
0
1
0
1
1
0
1
0
1
0
1
1
0
0
0
1
0
1
1
0
0
1
1
0
1
0
Fourth Address
Note : 1. LBO pin must be tied to High or Low, and Floating State must not be allowed.
- 6 -
Nov. 2003
Rev 3.0
K7M163625A
K7M161825A
512Kx36 & 1Mx18 Flow-Through NtRAMTM
STATE DIAGRAM FOR NtRAMTM
WRITE
READ
BEGIN
READ
BEGIN
WRITE
WRITE
READ
DESELECT
BURST
READ
BURST
WRITE
BURST
BURST
COMMAND
ACTION
DS
DESELECT
READ
WRITE
BEGIN READ
BEGIN WRITE
BEGIN READ
BURST
BEGIN WRITE
CONTINUE DESELECT
Notes : 1. An IGNORE CLOCK EDGE cycle is not shown is the above diagram. This is because CKE HIGH only blocks the clock(CLK) input and does
not change the state of the device.
2. States change on the rising edge of the clock(CLK)
- 7 -
Nov. 2003
Rev 3.0
K7M163625A
K7M161825A
512Kx36 & 1Mx18 Flow-Through NtRAMTM
TRUTH TABLES
SYNCHRONOUS TRUTH TABLE
CS1
H
X
X
X
L
CS2
X
CS 2 ADV WE BWx
OE
X
X
X
X
L
CKE CLK
ADDRESS ACCESSED
N/A
OPERATION
Not Selected
X
X
H
X
L
L
L
X
X
X
X
H
X
H
X
L
X
X
X
X
X
X
X
X
L
L
L
L
L
L
L
L
L
L
L
L
L
H
•
•
•
•
•
•
•
•
•
•
•
•
•
L
N/A
Not Selected
X
L
N/A
Not Selected
X
H
L
N/A
Not Selected Continue
Begin Burst Read Cycle
Continue Burst Read Cycle
NOP/Dummy Read
Dummy Read
H
X
External Address
Next Address
External Address
Next Address
External Address
Next Address
N/A
X
L
X
L
H
L
L
H
X
H
H
X
X
X
X
X
X
L
X
L
H
L
H
X
Begin Burst Write Cycle
Continue Burst Write Cycle
NOP/Write Abort
X
L
X
L
H
L
X
L
L
H
X
H
H
X
X
X
X
X
H
X
X
X
Next Address
Current Address
Write Abort
X
Ignore Clock
Notes : 1. X means "Don¢t Care".
2. The rising edge of clock is symbolized by (• ).
3. A continue deselect cycle can only be enterd if a deselect cycle is executed first.
4. WRITE = L means Write operation in WRITE TRUTH TABLE.
WRITE = H means Read operation in WRITE TRUTH TABLE.
5. Operation finally depends on status of asynchronous input pins(ZZ and OE).
WRITE TRUTH TABLE( x36)
WE
H
L
BWa
X
BWb
BW c
X
BW d
OPERATION
READ
X
H
L
X
H
H
H
L
L
H
WRITE BYTE a
WRITE BYTE b
WRITE BYTE c
WRITE BYTE d
WRITE ALL BYTEs
WRITE ABORT/NOP
L
H
H
L
H
H
H
L
L
L
H
H
L
L
L
L
L
H
H
H
H
Notes : 1. X means "Don¢t Care".
2. All inputs in this table must meet setup and hold time around the rising edge of CLK(• ).
WRITE TRUTH TABLE(x18)
WE
H
L
BWa
BWb
OPERATION
X
L
X
H
L
READ
WRITE BYTE a
WRITE BYTE b
WRITE ALL BYTEs
WRITE ABORT/NOP
L
H
L
L
L
L
H
H
Notes : 1. X means "Don¢t Care".
2. All inputs in this table must meet setup and hold time around the rising edge of CLK(• ).
- 8 -
Nov. 2003
Rev 3.0
K7M163625A
K7M161825A
512Kx36 & 1Mx18 Flow-Through NtRAMTM
ASYNCHRONOUS TRUTH TABLE
Notes
Operation
ZZ
H
L
OE
X
I/O STATUS
1. X means "Don¢t Care".
2. Sleep Mode means power Sleep Mode of which stand-by current does
not depend on cycle time.
3. Deselected means power Sleep Mode of which stand-by current
depends on cycle time.
Sleep Mode
High-Z
DQ
L
Read
L
H
X
High-Z
Write
L
Din, High-Z
High-Z
Deselected
L
X
ABSOLUTE MAXIMUM RATINGS*
PARAMETER
Voltage on VDD Supply Relative to VSS
Voltage on Any Other Pin Relative to VSS
Power Dissipation
SYMBOL
VDD
RATING
-0.3 to 4.6
-0.3 to VDD+0.3
1.6
UNIT
V
VIN
V
PD
W
Storage Temperature
TSTG
TOPR
TOPR
TBIAS
-65 to 150
0 to 70
°C
°C
°C
°C
Commercial
Industrial
Operating Temperature
-40 to 85
-10 to 85
Storage Temperature Range Under Bias
*Notes : Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only
and functional operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not
implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
OPERATING CONDITIONS at 3.3V I/O(0°C £ TA £ 70°C)
PARAMETER
Supply Voltage
Ground
SYMBOL
VDD
MIN
3.135
3.135
0
Typ.
3.3
3.3
0
MAX
3.465
3.465
0
UNIT
V
V
V
VDDQ
VSS
* The above parameters are also guaranteed at industrial temperature range.
OPERATING CONDITIONS at 2.5V I/O(0°C £ TA £ 70°C)
PARAMETER
Supply Voltage
Ground
SYMBOL
VDD
MIN
3.135
2.375
0
Typ.
3.3
2.5
0
MAX
3.465
2.9
UNIT
V
V
V
VDDQ
VSS
0
* The above parameters are also guaranteed at industrial temperature range.
CAPACITANCE*(TA=25°C, f=1MHz)
PARAMETER
SYMBOL
TEST CONDITION
VIN=0V
MIN
MAX
UNIT
Input Capacitance
CIN
-
-
5
7
pF
pF
Output Capacitance
COUT
VOUT=0V
*Note : Sampled not 100% tested.
- 9 -
Nov. 2003
Rev 3.0
K7M163625A
K7M161825A
512Kx36 & 1Mx18 Flow-Through NtRAMTM
DC ELECTRICAL CHARACTERISTICS(VDD=3.3V+0.165V/-0.165V, TA=0°C to +70°C)
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
MAX
UNIT NOTES
Input Leakage Current(except ZZ)
Output Leakage Current
IIL
VDD=Max ; VIN=VSS to VDD
-2
-2
-
+2
mA
mA
IOL
Output Disabled,
+2
Device Selected, IOUT=0mA,
-65
-75
-65
-75
270
250
100
90
Operating Current
ICC
ISB
mA
mA
1,2
ZZ£VIL , Cycle Time ³ tCYC Min
-
Device deselected, IOUT=0mA,
-
ZZ£VIL, f=Max,
-
Device deselected, IOUT=0mA,
ZZ£0.2V, f=0,
ISB1
ISB2
-
-
70
60
mA
mA
Standby Current
All Inputs=fixed (VDD -0.2V or
Device deselected, IOUT=0mA,
ZZ³ VDD-0.2V, f=Max, All
Inputs£VIL or ³ VIH
Output Low Voltage(3.3V I/O)
Output High Voltage(3.3V I/O)
Output Low Voltage(2.5V I/O)
Output High Voltage(2.5V I/O)
Input Low Voltage(3.3V I/O)
Input High Voltage(3.3V I/O)
Input Low Voltage(2.5V I/O)
Input High Voltage(2.5V I/O)
VOL
VOH
VOL
VOH
VIL
IOL=8.0mA
IOH=-4.0mA
IOL=1.0mA
IOH=-1.0mA
-
0.4
V
V
V
V
V
V
V
V
2.4
-
-
0.4
2.0
-0.3*
2.0
-0.3*
1.7
-
0.8
VIH
VIL
VDD+0.3**
0.7
3
3
VIH
VDD+0.3**
Notes : 1. The above parameters are also guaranteed at industrial temperature range.
2. Reference AC Operating Conditions and Characteristics for input and timing.
3. Data states are all zero.
4. In Case of I/O Pins, the Max. VIH=VDDQ +0.3V.
VIH
VSS
VSS-1.0V
20% tCYC (MIN)
TEST CONDITIONS
(VDD=3.3V+0.165V/-0.165V,VDDQ=3.3V+0.165/-0.165V or VDD=3.3V+0.165V/-0.165V,VDDQ=2.5V+0.4V/-0.125V, TA=0to70°C)
PARAMETER
VALUE
0 to 3.0V
0 to 2.5V
1.0V/ns
1.0V/ns
1.5V
Input Pulse Level(for 3.3V I/O)
Input Pulse Level(for 2.5V I/O)
Input Rise and Fall Time(Measured at 20% to 80% for 3.3V I/O)
Input Rise and Fall Time(Measured at 20% to 80% for 2.5V I/O)
Input and Output Timing Reference Levels for 3.3V I/O
Input and Output Timing Reference Levels for 2.5V I/O
Output Load
VDDQ/2
See Fig. 1
* The above parameters are also guaranteed at industrial temperature range.
- 10 -
Nov. 2003
Rev 3.0
K7M163625A
K7M161825A
512Kx36 & 1Mx18 Flow-Through NtRAMTM
Output Load(A)
Output Load(B),
(for tLZC, tLZOE, tHZOE & tHZC)
+3.3V for 3.3V I/O
/+2.5V for 2.5V I/O
RL=50W
Dout
VL=1.5V for 3.3V I/O
319W / 1667W
VDDQ/2 for 2.5V I/O
30pF*
Dout
Zo=50W
353W / 1538W
5pF*
* Including Scope and Jig Capacitance
Fig. 1
AC TIMING CHARACTERISTICS(VDD=3.3V+0.165V/-0.165V, TA=0°C to +70°C)
-65
-75
PARAMETER
SYMBOL
UNIT
MIN
7.5
-
MAX
MIN
8.5
-
MAX
Cycle Time
tCYC
tCD
-
-
ns
ns
Clock Access Time
6.5
7.5
Output Enable to Data Valid
Clock High to Output Low-Z
Output Hold from Clock High
Output Enable Low to Output Low-Z
Output Enable High to Output High-Z
Clock High to Output High-Z
Clock High Pulse Width
tOE
-
3.5
-
3.5
ns
tLZC
tOH
2.5
2.5
0
-
2.5
2.5
0
-
ns
-
-
ns
tLZOE
tHZOE
tHZC
tCH
-
-
ns
-
3.5
-
3.5
ns
-
3.8
-
4.0
ns
2.5
2.5
1.5
1.5
1.5
1.5
1.5
1.5
0.5
0.5
0.5
0.5
0.5
0.5
2
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
2.8
2.8
2.0
2.0
2.0
2.0
2.0
2.0
0.5
0.5
0.5
0.5
0.5
0.5
2
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
ns
Clock Low Pulse Width
tCL
ns
Address Setup to Clock High
CKE Setup to Clock High
tAS
ns
tCES
tDS
ns
Data Setup to Clock High
ns
Write Setup to Clock High (WE, BWX)
Address Advance Setup to Clock High
Chip Select Setup to Clock High
Address Hold from Clock High
CKE Hold from Clock High
tWS
ns
tADVS
tCSS
tAH
ns
ns
ns
tCEH
tDH
ns
Data Hold from Clock High
ns
Write Hold from Clock High (WE, BWX)
Address Advance Hold from Clock High
Chip Select Hold from Clock High
ZZ High to Power Down
tWH
tADVH
tCSH
tPDS
tPUS
ns
ns
ns
cycle
cycle
ZZ Low to Power Up
2
2
Notes : 1. The above parameters are also guaranteed at industrial temperature range.
2. All address inputs must meet the specified setup and hold times for all rising clock(CLK) edges when ADV is sampled low and CS is sampled
low. All other synchronous inputs must meet the specified setup and hold times whenever this device is chip selected.
3. Chip selects must be valid at each rising edge of CLK(when ADV is Low) to remain enabled.
4. A write cycle is defined by WE low having been registerd into the device at ADV Low, A Read cycle is defined by WE High with ADV Low,
Both cases must meet setup and hold times.
5. To avoid bus contention, At a given vlotage and temperature tLZC is more than tHZC.
The soecs as shown do not imply bus contention because tLZC is a Min. parameter that is worst case at totally different test conditions
(0°C,3.465V) than tHZC, which is a Max. parameter(worst case at 70°C,3.135V)
It is not possible for two SRAMs on the same board to be at such different voltage and temperatue.
- 11 -
Nov. 2003
Rev 3.0
K7M163625A
K7M161825A
512Kx36 & 1Mx18 Flow-Through NtRAMTM
SLEEP MODE
SLEEP MODE is a low current, power-down mode in which the device is deselected and current is reduced to ISB2. The duration of
SLEEP MODE is dictated by the length of time the ZZ is in a High state.
After entering SLEEP MODE, all inputs except ZZ become disabled and all outputs go to High-Z
The ZZ pin is an asynchronous, active high input that causes the device to enter SLEEP MODE.
When the ZZ pin becomes a logic High, ISB2 is guaranteed after the time tZZI is met. Any operation pending when entering SLEEP
MODE is not guaranteed to successful complete. Therefore, SLEEP MODE (READ or WRITE) must not be initiated until valid pend-
ing operations are completed. similarly, when exiting SLEEP MODE during tPUS, only a DESELECT or READ cycle should be given
while the SRAM is transitioning out of SLEEP MODE.
SLEEP MODE ELECTRICAL CHARACTERISTICS
DESCRIPTION
Current during SLEEP MODE
CONDITIONS
SYMBOL
ISB2
MIN
MAX
UNITS
mA
ZZ ³ VIH
60
ZZ active to input ignored
tPDS
2
2
cycle
cycle
cycle
tPUS
ZZ inactive to input sampled
ZZ active to SLEEP current
tZZI
2
ZZ inactive to exit SLEEP current
tRZZI
0
SLEEP MODE WAVEFORM
K
tPDS
ZZ setup cycle
tPUS
ZZ recovery cycle
ZZ
tZZI
Isupply
ISB2
tRZZI
All inputs
(except ZZ)
Deselect or Read Only
Deselect or Read Only
Normal
operation
cycle
Outputs
(Q)
High-Z
DON¢T CARE
- 12 -
Nov. 2003
Rev 3.0
K7M163625A
K7M161825A
512Kx36 & 1Mx18 Flow-Through NtRAMTM
- 13 -
Nov. 2003
Rev 3.0
K7M163625A
K7M161825A
512Kx36 & 1Mx18 Flow-Through NtRAMTM
- 14 -
Nov. 2003
Rev 3.0
K7M163625A
K7M161825A
512Kx36 & 1Mx18 Flow-Through NtRAMTM
- 15 -
Nov. 2003
Rev 3.0
K7M163625A
K7M161825A
512Kx36 & 1Mx18 Flow-Through NtRAMTM
- 16 -
Nov. 2003
Rev 3.0
K7M163625A
K7M161825A
512Kx36 & 1Mx18 Flow-Through NtRAMTM
- 17 -
Nov. 2003
Rev 3.0
K7M163625A
K7M161825A
512Kx36 & 1Mx18 Flow-Through NtRAMTM
PACKAGE DIMENSIONS
100-TQFP-1420A
Units ; millimeters/Inches
22.00 ±0.30
20.00 ±0.20
0~8°
0.127+ 0.10
- 0.05
16.00 ± 0.30
0.10 MAX
14.00± 0.20
(0.83)
0.50 ±0.10
#1
0.65
(0.58)
0.30 ± 0.10
0.10 MAX
1.40 ± 0.10
1.60 MAX
0.05 MIN
0.50 ± 0.10
- 18 -
Nov. 2003
Rev 3.0
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