K7N161845A-HC15 [SAMSUNG]
ZBT SRAM, 1MX18, 3.8ns, CMOS, PBGA119;
| 型号： | K7N161845A-HC15 |
| 厂家： | 
SAMSUNG |
| 描述： | ZBT SRAM, 1MX18, 3.8ns, CMOS, PBGA119 静态存储器 |
| 文件： | 总24页 (文件大小：412K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
K7N163645A
K7N161845A
Preliminary
512Kx36 & 1Mx18 Pipelined NtRAMTM
Document Title
512Kx36 & 1Mx18-Bit Pipelined NtRAMTM
Revision History
Draft Date
Remark
Rev. No.
History
Preliminary
Preliminary
Feb. 23. 2001
May. 10. 2001
0.0
1. Initial document.
1. Add JTAG Scan Order
0.1
The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the
specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions on the parameters of this device. If you have any ques-
tions, please contact the SAMSUNG branch office near your office, call or contact Headquarters.
May 2001
Rev 0.1
- 1 -
K7N163645A
K7N161845A
Preliminary
512Kx36 & 1Mx18 Pipelined NtRAMTM
16Mb NtRAM(Flow Through / Pipelined)
Ordering Information
Speed
Org.
Part Number
Mode
VDD
FT ; Access Time(ns)
PKG
Temp
Pipelined ; Cycle Time(MHz)
K7M161825A-Q(H)C65/75/85/90 FlowThrough
3.3
3.3
3.3
2.5
2.5
3.3
3.3
3.3
2.5
2.5
6.5/7.5/8.5/9.0ns
167/150/133MHz
250/225/200MHz
167/150/133MHz
250/225/200MHz
6.5/7.5/8.5/9.0ns
167/150/133MHz
250/225/200MHz
167/150/133MHz
250/225/200MHz
K7N161801A-Q(H)C16/15/13
K7N161809A-Q(H)C25/22/20
K7N161845A-Q(H)C16/15/13
K7N161849A-Q(H)C25/22/20
Pipelined
Pipelined
Pipelined
Pipelined
1Mx18
Q : 100TQFP
H : 119BGA
K7M163625A-Q(H)C65/75/85/90 FlowThrough
K7N163601A-Q(H)C16/15/13
K7N163609A-Q(H)C25/22/20
K7N163645A-Q(H)C16/15/13
K7N163649A-Q(H)C25/22/20
Pipelined
Pipelined
Pipelined
Pipelined
C
512Kx36
(Commercial
Temperature
Range)
Pipelined
(Normal Type)
K7N167245A-HC16/15/13
2.5
2.5
1.8
167/150/133MHz
250/225/200MHz
300/275/250MHz
Pipelined
(Normal Type)
H : 209BGA
256Kx72 K7N167249A-HC25/22/20
K7N167285A-HC30/27/25
Pipelined
(Sigma Type)
May 2001
Rev 0.1
- 2 -
K7N163645A
K7N161845A
Preliminary
512Kx36 & 1Mx18 Pipelined NtRAMTM
512Kx36 & 1Mx18-Bit Pipelined NtRAMTM
FEATURES
• 2.5V ±5% Power Supply.
GENERAL DESCRIPTION
The K7N163645A and K7N161845A are 18,874,368-bits Syn-
• Byte Writable Function.
chronous Static SRAMs.
• Enable clock and suspend operation.
• Single READ/WRITE control pin.
• Self-Timed Write Cycle.
• Three Chip Enable for simple depth expansion with no data
contention .
• A interleaved burst or a linear burst mode.
• Asynchronous output enable control.
• Power Down mode.
The NtRAMT M, or No Turnaround Random Access Memory uti-
lizes all the bandwidth in any combination of operating cycles.
Address, data inputs, and all control signals except output
enable and linear burst order are synchronized to input clock.
Burst order control must be tied "High or Low".
Asynchronous inputs include the sleep mode enable(ZZ).
Output Enable controls the outputs at any given time.
Write cycles are internally self-timed and initiated by the rising
edge of the clock input. This feature eliminates complex off-chip
write pulse generation
• TTL-Level Three-State Outputs.
• 100-TQFP-1420A / 119BGA(7x17 Ball Grid Array Package).
and provides increased timing flexibility for incoming signals.
For read cycles, pipelined SRAM output data is temporarily
stored by an edge triggered output register and then released
to the output buffers at the next rising edge of clock.
The K7N163645A and K7N161845A are implemented with
SAMSUNG¢s high performance CMOS technology and is avail-
able in 100pin TQFP and 119BGA packages. Multiple power
and ground pins minimize ground bounce.
FAST ACCESS TIMES
PARAMETER
Cycle Time
Symbol -16 -15 -13 Unit
tCYC
tCD
6.0 6.7 7.5 ns
3.5 3.8 4.2 ns
3.5 3.8 4.2 ns
Clock Access Time
Output Enable Access Time
tOE
LOGIC BLOCK DIAGRAM
LBO
BURST
ADDRESS
COUNTER
A¢0~A¢1
A [0:18]or
A [0:19]
A
0
~A
1
512Kx36 , 1Mx18
MEMORY
ARRAY
ADDRESS
REGISTER
A2~A18 or A2~A19
WRITE
ADDRESS
REGISTER
WRITE
ADDRESS
REGISTER
DATA-IN
REGISTER
CLK
K
K
K
CKE
DATA-IN
REGISTER
CS
CS
CS
1
2
2
ADV
WE
CONTROL
LOGIC
K
OUTPUT
REGISTER
BWx
(x=a,b,c,d or a,b)
BUFFER
OE
ZZ
36 or 18
DQa0 ~ DQd7 or DQa0 ~ DQb8
DQPa ~ DQPd
TM
NtRAM and No Turnaround Random Access Memory are trademarks of Samsung.
May 2001
Rev 0.1
- 3 -
K7N163645A
K7N161845A
Preliminary
512Kx36 & 1Mx18 Pipelined NtRAMTM
(TOP VIEW)
PIN CONFIGURATION
DQPc
DQc0
DQc1
VDDQ
VSSQ
DQc2
DQc3
DQc4
DQc5
VSSQ
VDDQ
DQc6
DQc7
VDD
1
2
3
4
5
6
7
8
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
DQPb
DQb7
DQb6
VDDQ
VSSQ
DQb5
DQb4
DQb3
DQb2
VSSQ
VDDQ
DQb1
DQb0
VSS
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
100 Pin TQFP
(20mm x 14mm)
VDD
VDD
VDD
ZZ
VDD
VSS
DQd0
DQd1
VDDQ
VSSQ
DQd2
DQd3
DQd4
DQd5
VSSQ
VDDQ
DQd6
DQd7
DQPd
DQa7
DQa6
VDDQ
VSSQ
DQa5
DQa4
DQa3
DQa2
VSSQ
VDDQ
DQa1
DQa0
DQPa
K7N163645A(512Kx36)
PIN NAME
SYMBOL
PIN NAME
TQFP PIN NO.
SYMBOL
PIN NAME
Power Supply
TQFP PIN NO.
A0 - A18
Address Inputs
32,33,34,35,36,37,44 VDD
45,46,47,48,49,50,81
14,15,16,41,65,66,91
(2.5V)
82,83,84,99,100
85
Read/Write Control Input 88
VSS
Ground
17,40,67,90
ADV
WE
Address Advance/Load
N.C.
No Connect
38,39,42,43
CLK
CKE
CS1
CS2
CS2
Clock
89
87
98
97
Clock Enable
Chip Select
Chip Select
Chip Select
DQa0~a7
DQb0~b7
DQc0~c7
DQd0~d7
DQPa~Pd
Data Inputs/Outputs
Data Inputs/Outputs
Data Inputs/Outputs
Data Inputs/Outputs
Data Inputs/Outputs
52,53,56,57,58,59,62,63
68,69,72,73,74,75,78,79
2,3,6,7,8,9,12,13
18,19,22,23,24,25,28,29
51,80,1,30
92
BWx(x=a,b,c,d) Byte Write Inputs
93,94,95,96
OE
ZZ
LBO
Output Enable
Power Sleep Mode
Burst Mode Control
86
64
31
VDDQ
VSSQ
Output Power Supply 4,11,20,27,54,61,70,77
(2.5V)
Output Ground
5,10,21,26,55,60,71,76
Note : A0 and A1 are the two least significant bits(LSB) of the address field and set the internal burst counter if burst is desired.
May 2001
Rev 0.1
- 4 -
K7N163645A
K7N161845A
Preliminary
512Kx36 & 1Mx18 Pipelined NtRAMTM
(TOP VIEW)
PIN CONFIGURATION
N.C.
N.C.
N.C.
VDDQ
VSSQ
N.C.
1
2
3
4
5
6
7
8
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
A10
N.C.
N.C.
VDDQ
VSSQ
N.C.
DQa0
DQa1
DQa2
VSSQ
VDDQ
DQa3
DQa4
VSS
N.C.
DQb8
DQb7
VSSQ
VDDQ
DQb6
DQb5
VDD
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
100 Pin TQFP
VDD
VDD
VDD
ZZ
(20mm x 14mm)
VDD
VSS
DQb4
DQb3
VDDQ
VSSQ
DQb2
DQb1
DQb0
N.C.
VSSQ
VDDQ
N.C.
N.C.
N.C.
DQa5
DQa6
VDDQ
VSSQ
DQa7
DQa8
N.C.
N.C.
VSSQ
VDDQ
N.C.
N.C.
N.C.
K7N161845A(1Mx18)
PIN NAME
SYMBOL
PIN NAME
TQFP PIN NO.
SYMBOL
PIN NAME
Power Supply
TQFP PIN NO.
A0 - A19
Address Inputs
32,33,34,35,36,37,44 VDD
45,46,47,48,49,50,80,
14,15,16,41,65,66,91
(2.5V)
81,82,83,84,99,100
85
Read/Write Control Input 88
VSS
Ground
17,40,67,90
ADV
WE
Address Advance/Load
N.C.
No Connect
1,2,3,6,7,25,28,29,30,
38,39,42,43,51,52,53,
56,57,75,78,79,95,96
CLK
CKE
CS1
CS2
CS2
Clock
89
87
98
97
Clock Enable
Chip Select
Chip Select
Chip Select
DQa0~a8
DQb0~b8
Data Inputs/Outputs
Data Inputs/Outputs
58,59,62,63,68,69,72,73,74
8,9,12,13,18,19,22,23,24
92
BWx(x=a,b) Byte Write Inputs
93,94
86
64
OE
ZZ
Output Enable
Power Sleep Mode
Burst Mode Control
VDDQ
VSSQ
Output Power Supply
(2.5V)
Output Ground
4,11,20,27,54,61,70,77
5,10,21,26,55,60,71,76
LBO
31
Note : A0 and A1 are the two least significant bits(LSB) of the address field and set the internal burst counter if burst is desired.
May 2001
Rev 0.1
- 5 -
K7N163645A
K7N161845A
Preliminary
512Kx36 & 1Mx18 Pipelined NtRAMTM
(TOP VIEW)
119BGA PACKAGE PIN CONFIGURATIONS
K7N163645A(512Kx36)
1
2
3
A
4
5
A
6
7
A
B
C
D
E
F
VDDQ
NC
A
A
A
VDDQ
NC
CS2
A
A
ADV
VDD
NC
CS1
OE
A
A
CS2
A
NC
A
A
NC
DQc
DQc
VDDQ
DQc
DQc
VDDQ
DQd
DQd
VDDQ
DQd
DQd
NC
DQPc
DQc
DQc
DQc
DQc
VDD
DQd
DQd
DQd
DQd
DQPd
A
VSS
VSS
VSS
BWc
VSS
NC
VSS
BWd
VSS
VSS
VSS
LBO
A
VSS
VSS
VSS
BWb
VSS
NC
VSS
BWa
VSS
VSS
VSS
NC
A
DQPb
DQb
DQb
DQb
DQb
VDD
DQa
DQa
DQa
DQa
DQPa
A
DQb
DQb
VDDQ
DQb
DQb
VDDQ
DQa
DQa
VDDQ
DQa
DQa
NC
G
H
J
WE
VDD
CLK
NC
CKE
A1*
A0*
VDD
A
K
L
M
N
P
R
T
NC
NC
NC
ZZ
U
VDDQ
TMS
TDI
TCK
TDO
NC
VDDQ
Note : * A0 and A1 are the two least significant bits(LSB) of the address field and set the internal burst counter if burst is desired.
PIN NAME
SYMBOL
PIN NAME
SYMBOL
PIN NAME
A
Address Inputs
VDD
VSS
Power Supply
Ground
A0,A1
ADV
WE
CLK
CKE
CS1
CS2
CS2
Burst Address Inputs
Address Advance/Load
Read/Write Control Input
Clock
Clock Enable
Chip Select
N.C.
No Connect
DQa
DQb
DQc
DQd
Data Inputs/Outputs
Data Inputs/Outputs
Data Inputs/Outputs
Data Inputs/Outputs
Data Inputs/Outputs
Chip Select
Chip Select
DQPa~Pd
BWx
(x=a,b,c,d)
Byte Write Inputs
VDDQ
Output Power Supply
OE
ZZ
LBO
Output Enable
Power Sleep Mode
Burst Mode Control
TCK
TMS
TDI
JTAG Test Clock
JTAG Test Mode Select
JTAG Test Data Input
JTAG Test Data Output
TDO
May 2001
Rev 0.1
- 6 -
K7N163645A
K7N161845A
Preliminary
512Kx36 & 1Mx18 Pipelined NtRAMTM
(TOP VIEW)
119BGA PACKAGE PIN CONFIGURATIONS
K7N161845A(1Mx18)
1
2
A
3
A
4
5
A
6
A
7
A
B
C
D
E
F
VDDQ
NC
A
VDDQ
NC
CS2
A
A
ADV
VDD
NC
CS1
OE
A
A
CS2
A
NC
A
A
NC
DQb
NC
NC
DQb
NC
DQb
NC
VDD
DQb
NC
DQb
NC
DQPb
A
VSS
VSS
VSS
BWb
VSS
NC
VSS
VSS
VSS
VSS
VSS
LBO
A
VSS
VSS
VSS
VSS
VSS
NC
VSS
BWa
VSS
VSS
VSS
NC
A
DQPa
NC
DQa
NC
DQa
VDD
NC
DQa
NC
DQa
NC
A
NC
DQa
VDDQ
DQa
NC
VDDQ
NC
G
H
J
DQb
VDDQ
NC
WE
VDD
CLK
NC
CKE
A1*
A0*
VDD
NC
TCK
VDDQ
DQa
NC
K
L
DQb
VDDQ
DQb
NC
M
N
P
R
T
VDDQ
NC
DQa
NC
NC
NC
A
A
ZZ
U
VDDQ
TMS
TDI
TDO
NC
VDDQ
Note : * A0 and A1 are the two least significant bits(LSB) of the address field and set the internal burst counter if burst is desired.
PIN NAME
SYMBOL
PIN NAME
SYMBOL
PIN NAME
A
Address Inputs
VDD
VSS
Power Supply
Ground
A0,A1
ADV
WE
CLK
CKE
CS1
Burst Address Inputs
Address Advance/Load
Read/Write Control Input
Clock
Clock Enable
Chip Select
No Connect
N.C.
Data Inputs/Outputs
Data Inputs/Outputs
Data Inputs/Outputs
DQa
DQb
DQPa, Pb
CS2
Chip Select
CS2
Chip Select
BWx
(x=a,b)
Byte Write Inputs
Output Power Supply
VDDQ
OE
ZZ
LBO
Output Enable
Power Sleep Mode
Burst Mode Control
TCK
TMS
TDI
JTAG Test Clock
JTAG Test Mode Select
JTAG Test Data Input
JTAG Test Data Output
TDO
May 2001
Rev 0.1
- 7 -
K7N163645A
K7N161845A
Preliminary
512Kx36 & 1Mx18 Pipelined NtRAMTM
FUNCTION DESCRIPTION
The K7N163645A and K7N161845A are NtRAMTM designed to sustain 100% bus bandwidth by eliminating turnaround cycle when
there is transition from Read to Write, or vice versa.
All inputs (with the exception of OE, LBO and ZZ) are synchronized to rising clock edges.
All read, write and deselect cycles are initiated by the ADV input. Subsequent burst addresses can be internally generated by the
burst advance pin (ADV). ADV should be driven to Low once the device has been deselected in order to load a new address for next
operation.
Clock Enable(CKE) pin allows the operation of the chip to be suspended as long as necessary. When CKE is high, all synchronous
inputs are ignored and the internal device registers will hold their previous values.
T M
NtRAM latches external address and initiates a cycle, when CKE, ADV are driven to low and all three chip enables(CS1, CS2, CS2)
are active .
Output Enable(OE) can be used to disable the output at any given time.
Read operation is initiated when at the rising edge of the clock, the address presented to the address inputs are latched in the
address register, CKE is driven low, all three chip enables(CS1, CS2, CS2) are active, the write enable input signals WE are driven
high, and ADV driven low.The internal array is read between the first rising edge and the second rising edge of the clock and the data
is latched in the output register. At the second clock edge the data is driven out of the SRAM. Also during read operation OE must
be driven low for the device to drive out the requested data.
Write operation occurs when WE is driven low at the rising edge of the clock. BW[d:a] can be used for byte write operation. The pipe-
lined NtRAMTM uses a late-late write cycle to utilize 100% of the bandwidth.
At the first rising edge of the clock, WE and address are registered, and the data associated with that address is required two cycle
later.
Subsequent addresses are generated by ADV High for the burst access as shown below. The starting point of the burst seguence is
provided by the external address. The burst address counter wraps around to its initial state upon completion.
The burst sequence is determined by the state of the LBO pin. When this pin is low, linear burst sequence is selected.
And when this pin is high, Interleaved burst sequence is selected.
During normal operation, ZZ must be driven low. When ZZ is driven high, the SRAM will enter a Power Sleep Mode after 2 cycles. At
this time, internal state of the SRAM is preserved. When ZZ returns to low, the SRAM normally operates after 2 cycles of wake up
time.
(Interleaved Burst, LBO=High)
BURST SEQUENCE TABLE
Case 1
Case 2
Case 3
Case 4
LBO PIN
HIGH
First Address
A 1
A 0
A 1
A0
A 1
A 0
A 1
A 0
0
0
1
1
0
1
0
1
0
0
1
1
1
0
1
0
1
1
0
0
0
1
0
1
1
1
0
0
1
0
1
0
Fourth Address
(Linear Burst, LBO=Low)
Case 4
BQ TABLE
Case 1
Case 2
Case 3
LBO PIN
LOW
First Address
A 1
0
A 0
0
A 1
0
A 0
1
A 1
1
A 0
0
A 1
1
A 0
1
0
1
1
0
1
1
0
0
1
0
1
1
0
0
0
1
Fourth Address
1
1
0
0
0
1
1
0
Note : 1. LBO pin must be tied to High or Low, and Floating State must not be allowed.
May 2001
Rev 0.1
- 8 -
K7N163645A
K7N161845A
Preliminary
512Kx36 & 1Mx18 Pipelined NtRAMTM
STATE DIAGRAM FOR NtRAMTM
WRITE
READ
BEGIN
READ
BEGIN
WRITE
WRITE
READ
DESELECT
BURST
READ
BURST
WRITE
BURST
BURST
COMMAND
ACTION
DS
DESELECT
READ
WRITE
BEGIN READ
BEGIN WRITE
BEGIN READ
BURST
BEGIN WRITE
CONTINUE DESELECT
Notes : 1. An IGNORE CLOCK EDGE cycle is not shown is the above diagram. This is because CKE HIGH only blocks the clock(CLK) input and does
not change the state of the device.
2. States change on the rising edge of the clock(CLK)
May 2001
Rev 0.1
- 9 -
K7N163645A
K7N161845A
Preliminary
512Kx36 & 1Mx18 Pipelined NtRAMTM
TRUTH TABLES
SYNCHRONOUS TRUTH TABLE
CS1
H
X
X
X
L
CS2
X
CS2 ADV WE BWx
OE
X
X
X
X
L
CKE CLK
ADDRESS ACCESSED
N/A
OPERATION
Not Selected
X
X
H
X
L
L
L
X
X
X
X
H
X
H
X
L
X
X
X
X
X
X
X
X
L
L
L
L
L
L
L
L
L
L
L
L
L
H
•
•
•
•
•
•
•
•
•
•
•
•
•
L
N/A
Not Selected
X
L
N/A
Not Selected
X
H
L
N/A
Not Selected Continue
Begin Burst Read Cycle
Continue Burst Read Cycle
NOP/Dummy Read
Dummy Read
H
X
External Address
Next Address
External Address
Next Address
External Address
Next Address
N/A
X
L
X
L
H
L
L
H
X
H
H
X
X
X
X
X
X
L
X
L
H
L
H
X
Begin Burst Write Cycle
Continue Burst Write Cycle
NOP/Write Abort
Write Abort
X
L
X
L
H
L
X
L
L
H
X
H
H
X
X
X
X
X
H
X
X
X
Next Address
Current Address
X
Ignore Clock
Notes : 1. X means "Don¢t Care".
2. The rising edge of clock is symbolized by (• ).
3. A continue deselect cycle can only be enterd if a deselect cycle is executed first.
4. WRITE = L means Write operation in WRITE TRUTH TABLE.
WRITE = H means Read operation in WRITE TRUTH TABLE.
5. Operation finally depends on status of asynchronous input pins(ZZ and OE).
WRITE TRUTH TABLE(x36)
WE
H
L
BWa
X
BWb
BWc
X
BWd
OPERATION
READ
X
H
L
X
H
H
H
L
L
H
WRITE BYTE a
WRITE BYTE b
WRITE BYTE c
WRITE BYTE d
WRITE ALL BYTEs
WRITE ABORT/NOP
L
H
H
L
H
H
H
L
L
L
H
H
L
L
L
L
L
H
H
H
H
Notes : 1. X means "Don¢t Care".
2. All inputs in this table must meet setup and hold time around the rising edge of CLK(• ).
WRITE TRUTH TABLE(x18)
WE
BWa
BWb
OPERATION
H
X
L
X
H
L
READ
L
WRITE BYTE a
WRITE BYTE b
WRITE ALL BYTEs
WRITE ABORT/NOP
L
H
L
L
L
L
H
H
Notes : 1. X means "Don¢t Care".
2. All inputs in this table must meet setup and hold time around the rising edge of CLK(• ).
May 2001
Rev 0.1
- 10 -
K7N163645A
K7N161845A
Preliminary
512Kx36 & 1Mx18 Pipelined NtRAMTM
ASYNCHRONOUS TRUTH TABLE
Notes
OPERATION
ZZ
H
L
OE
I/O STATUS
High-Z
1. X means "Don¢t Care".
2. Sleep Mode means power Sleep Mode of which stand-by current does
not depend on cycle time.
3. Deselected means power Sleep Mode of which stand-by current
depends on cycle time.
Sleep Mode
X
L
DQ
Read
L
H
High-Z
Write
L
X
Din, High-Z
High-Z
Deselected
L
X
ABSOLUTE MAXIMUM RATINGS*
PARAMETER
Voltage on VDD Supply Relative to VSS
Voltage on Any Other Pin Relative to VSS
Power Dissipation
SYMBOL
VDD
RATING
-0.3 to 3.6
-0.3 to VDD+0.3
1.6
UNIT
V
VIN
V
PD
W
Storage Temperature
TSTG
TOPR
TBIAS
-65 to 150
0 to 70
°C
°C
°C
Operating Temperature
Storage Temperature Range Under Bias
-10 to 85
*Note : Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only
and functional operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not
implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
(0°C £ TA £ 70°C)
OPERATING CONDITIONS
PARAMETER
Supply Voltage
Ground
SYMBOL
VDD
MIN
2.375
2.375
0
Typ.
2.5
2.5
0
MAX
2.625
2.625
0
UNIT
V
V
V
VDDQ
VSS
*Note : VDD and VD D Q must be supplied with identical vlotage levels.
(TA=25°C, f=1MHz)
CAPACITANCE*
PARAMETER
SYMBOL
CIN
TEST CONDITION
VIN=0V
MIN
MAX
UNIT
pF
Input Capacitance
-
-
5
7
Output Capacitance
COUT
VOUT=0V
pF
*Note : Sampled not 100% tested.
May 2001
Rev 0.1
- 11 -
K7N163645A
K7N161845A
Preliminary
512Kx36 & 1Mx18 Pipelined NtRAMTM
(VDD=2.5V ±5%, TA=0°C to +70°C)
DC ELECTRICAL CHARACTERISTICS
PARAMETER
SYMBOL
TEST CONDITIONS
VDD=Max ; VIN=VSS to VDD
MIN
MAX
+2
UNIT NOTES
Input Leakage Current(except ZZ)
Output Leakage Current
IIL
-2
-2
-
mA
mA
IOL
Output Disabled,
+2
-16
-15
-13
-16
-15
-13
TBD
TBD
TBD
TBD
TBD
TBD
VDD=Max , IOUT=0mA
Operating Current
ICC
ISB
-
mA
mA
1,2
Cycle Time ³ tCYC Min
-
-
Device deselected, IOUT=0mA,
ZZ£VIL, f=Max,
-
All Inputs£0.2V or ³ VDD-0.2V
-
Standby Current
Device deselected, IOUT=0mA, ZZ£0.2V, f=0,
All Inputs=fixed (VDD-0.2V or 0.2V)
Device deselected, IOUT=0mA, ZZ³ VDD-0.2V,
f=Max, All Inputs£VIL or ³ VIH
ISB1
ISB2
-
-
TBD
TBD
mA
mA
Output Low Voltage
Output High Voltage
Input Low Voltage
Input High Voltage
VOL
VOH
VIL
IOL=1.0mA
IOH=-1.0mA
-
0.4
V
V
V
V
2.0
-
-0.3*
1.7
0.7
VIH
VDD+0.3**
3
Notes : 1. Reference AC Operating Conditions and Characteristics for input and timing.
2. Data states are all zero.
3. In Case of I/O Pins, the Max. VIH=VDDQ+0.3V
VIH
VSS
VSS-0.8V
20% tCYC (MIN)
TEST CONDITIONS
(TA=0 to 70°C, VDD=2.5V ±5%, unless otherwise specified)
PARAMETER
Input Pulse Level
VALUE
0 to 2.5V
1.0V/ns
Input Rise and Fall Time(Measured at 20% to 80%)
Input and Output Timing Reference Levels
Output Load
VDDQ/2
See Fig. 1
May 2001
Rev 0.1
- 12 -
K7N163645A
K7N161845A
Preliminary
512Kx36 & 1Mx18 Pipelined NtRAMTM
Output Load(A)
Output Load(B),
(for tLZC, tLZOE, tHZOE & tHZC)
Dout
RL=50W
+2.5V
VL=VDDQ/2
1667W
30pF*
Dout
Zo=50W
1538W
5pF*
* Including Scope and Jig Capacitance
Fig. 1
AC TIMING CHARACTERISTICS
(VDD=2.5V ±5%, TA=0 to 70°C)
-16
-15
-13
PARAMETER
SYMBOL
UNIT
MIN
6.0
-
MAX
MIN
6.7
-
MAX
MIN
7.5
-
MAX
Cycle Time
tCYC
tCD
-
-
-
ns
ns
Clock Access Time
3.5
3.8
4.2
Output Enable to Data Valid
Clock High to Output Low-Z
Output Hold from Clock High
Output Enable Low to Output Low-Z
Output Enable High to Output High-Z
Clock High to Output High-Z
Clock High Pulse Width
tOE
-
3.5
-
3.8
-
4.2
ns
tLZC
tOH
1.5
1.5
0
-
1.5
1.5
0
-
1.5
1.5
0
-
ns
-
-
-
ns
tLZOE
tHZOE
tHZC
tCH
-
-
-
ns
-
3.0
-
3.0
-
3.5
ns
-
3.0
-
-
3.0
-
3.5
-
ns
2.2
2.2
1.5
1.5
1.5
1.5
1.5
1.5
0.5
0.5
0.5
0.5
0.5
0.5
2
2.5
2.5
1.5
1.5
1.5
1.5
1.5
1.5
0.5
0.5
0.5
0.5
0.5
0.5
2
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
3.0
3.0
1.5
1.5
1.5
1.5
1.5
1.5
0.5
0.5
0.5
0.5
0.5
0.5
2
ns
Clock Low Pulse Width
tCL
-
-
ns
Address Setup to Clock High
CKE Setup to Clock High
tAS
-
-
ns
tCES
tDS
-
-
ns
Data Setup to Clock High
-
-
ns
Write Setup to Clock High (WE, BWX)
Address Advance Setup to Clock High
Chip Select Setup to Clock High
Address Hold from Clock High
CKE Hold from Clock High
Data Hold from Clock High
Write Hold from Clock High (WE, BWX)
Address Advance Hold from Clock High
Chip Select Hold from Clock High
ZZ High to Power Down
tWS
tADVS
tCSS
tAH
-
-
ns
-
-
ns
-
-
ns
-
-
ns
tCEH
tDH
-
-
ns
-
-
ns
tWH
tADVH
tCSH
tPDS
tPUS
-
-
ns
-
-
ns
-
-
ns
-
-
cycle
cycle
ZZ Low to Power Up
2
-
2
2
-
Notes : 1. All address inputs must meet the specified setup and hold times for all rising clock(CLK) edges when ADV is sampled low and CS is sampled
low. All other synchronous inputs must meet the specified setup and hold times whenever this device is chip selected.
2. Chip selects must be valid at each rising edge of CLK(when ADV is Low) to remain enabled.
3. A write cycle is defined by WE low having been registered into the device at ADV Low, A Read cycle is defined by WE High with ADV Low,
Both cases must meet setup and hold times.
4. To avoid bus contention, At a given voltage and temperature tLZC is more than tHZC.
The specs as shown do not imply bus contention because tLZC is a Min. parameter that is worst case at totally different test conditions
(0°C,2.625V) than tHZC , which is a Max. parameter(worst case at 70°C,2.375V)
It is not possible for two SRAMs on the same board to be at such different voltage and temperature.
May 2001
Rev 0.1
- 13 -
K7N163645A
K7N161845A
Preliminary
512Kx36 & 1Mx18 Pipelined NtRAMTM
SLEEP MODE
SLEEP MODE is a low current, power-down mode in which the device is deselected and current is reduced to ISB2. The duration of
SLEEP MODE is dictated by the length of time the ZZ is in a High state.
After entering SLEEP MODE, all inputs except ZZ become disabled and all outputs go to High-Z
The ZZ pin is an asynchronous, active high input that causes the device to enter SLEEP MODE.
When the ZZ pin becomes a logic High, ISB2 is guaranteed after the time tZZI is met. Any operation pending when entering SLEEP
MODE is not guaranteed to successful complete. Therefore, SLEEP MODE (READ or WRITE) must not be initiated until valid pend-
ing operations are completed. similarly, when exiting SLEEP MODE during tPUS, only a DESELECT or READ cycle should be given
while the SRAM is transitioning out of SLEEP MODE.
SLEEP MODE ELECTRICAL CHARACTERISTICS
DESCRIPTION
CONDITIONS
SYMBOL
ISB2
MIN
MAX
UNITS
mA
Current during SLEEP MODE
ZZ ³ VIH
10
ZZ active to input ignored
tPDS
2
2
cycle
cycle
cycle
tPUS
ZZ inactive to input sampled
ZZ active to SLEEP current
tZZI
2
ZZ inactive to exit SLEEP current
tRZZI
0
SLEEP MODE WAVEFORM
K
tPDS
ZZ setup cycle
tPUS
ZZ recovery cycle
ZZ
tZZI
Isupply
ISB2
tRZZI
All inputs
(except ZZ)
Deselect or Read Only
Deselect or Read Only
Normal
operation
cycle
Outputs
(Q)
High-Z
DON¢T CARE
May 2001
Rev 0.1
- 14 -
K7N163645A
K7N161845A
Preliminary
512Kx36 & 1Mx18 Pipelined NtRAMTM
IEEE 1149.1 TEST ACCESS PORT AND BOUNDARY SCAN-JTAG
This part contains an IEEE standard 1149.1 Compatible Teat Access Port(TAP). The package pads are monitored by the Serial Scan
circuitry when in test mode. This is to support connectivity testing during manufacturing and system diagnostics. Internal data is not
driven out of the SRAM under JTAG control. In conformance with IEEE 1149.1, the SRAM contains a TAP controller, Instruction Reg-
ister, Bypass Register and ID register. The TAP controller has a standard 16-state machine that resets internally upon power-up,
therefore, TRST signal is not required. It is possible to use this device without utilizing the TAP. To disable the TAP controller without
interfacing with normal operation of the SRAM, TCK must be tied to VSS to preclude mid level input. TMS and TDI are designed so an
undriven input will produce a response identical to the application of a logic 1, and may be left unconnected. But they may also be
tied to VDD through a resistor. TDO should be left unconnected.
JTAG Instruction Coding
JTAG Block Diagram
IR2 IR1 IR0 Instruction
TDO Output
SAMPLE-Z Boundary Scan Register
IDCODE Identification Register
SAMPLE-Z Boundary Scan Register
Notes
0
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
1
2
1
3
4
3
3
3
0
0
0
BYPASS
SAMPLE
BYPASS
BYPASS
BYPASS
Bypass Register
Boundary Scan Register
Bypass Register
Bypass Register
Bypass Register
1
1
SRAM
CORE
1
1
PI
PI
NOTE :
1. Places DQs in Hi-Z in order to sample all input data regardless of
other SRAM inputs.
2. TDI is sampled as an input to the first ID register to allow for the serial
shift of the external TDI data.
TDI
BYPASS Reg.
TDO
Identification Reg.
Instruction Reg.
3. Bypass register is initiated to VSS when BYPASS instruction is
invoked. The Bypass Register also holds serially loaded TDI when
exiting the Shift DR states.
4. SAMPLE instruction dose not places DQs in Hi-Z.
Control Signals
TAP Controller
TMS
TCK
TAP Controller State Diagram
1
0
Test Logic Reset
0
1
1
0
1
0
Run Test Idle
Select DR
Select IR
0
0
1
1
1
1
Capture DR
Capture IR
0
0
Shift DR
1
Shift IR
1
Exit1 DR
0
Exit1 IR
0
0
0
0
0
Pause DR
1
Pause IR
1
Exit2 DR
1
Exit2 IR
1
1
0
Update DR
0
Update IR
1
May 2001
Rev 0.1
- 15 -
K7N163645A
K7N161845A
Preliminary
512Kx36 & 1Mx18 Pipelined NtRAMTM
SCAN REGISTER DEFINITION
Part
512Kx36
1Mx18
Instruction Register
Bypass Register
1 bits
ID Register
32 bits
Boundary Scan
75 bits
3 bits
3 bits
1 bits
32 bits
75 bits
ID REGISTER DEFINITION
Revision Number
Part
Part Configuration Vendor Definition Samsung JEDEC Code
Start Bit(0)
(31:28)
(27:18)
(17:12)
XXXXXX
XXXXXX
(11: 1)
512Kx36
1Mx18
0000
0000
00111 00100
01000 00011
00001001110
00001001110
1
1
119BGA BOUNDARY SCAN EXIT ORDER(x36
119BGA BOUNDARY SCAN EXIT ORDER(x18)
)
1
2T
1R
4T
4H
5R
5T
5L
NC
NC
CLK
A
4K
4G
4B
4A
4M
3G
3B
3A
2B
4E
3C
2C
2A
2D
1E
2F
1G
2H
1D
2E
2G
1H
2K
1L
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
1
2T
1R
6T
4H
5R
5T
5L
A
NC
A
CLK
A
4K
4G
4B
4A
4M
3G
3B
3A
2B
4E
3C
2C
2A
2D
1E
2F
1G
2H
1D
2E
2G
1H
2K
1L
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
2
2
3
A
ADV
A
3
ADV
A
4
WE
NC
4
WE
NC
A
5
CKE
BWc
A
5
CKE
BWb
A
6
A
6
7
BWa
NC
7
BWa
NC
A
8
7R
6R
7T
6P
7N
6M
7L
A
8
7R
6R
7T
6P
7N
6M
7L
A
9
A
CS2
CS1
A
9
CS2
CS1
A
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
ZZ
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
ZZ
DQPa
DQa
DQa
DQa
DQa
DQa
DQa
DQa
DQa
NC
NC
NC
NC
NC
NC
DQa
DQa
DQa
DQa
NC
DQa
DQa
DQa
DQa
DQPa
NC
NC
NC
NC
NC
A
A
A
A
A
DQPc
DQc
DQc
DQc
DQc
DQc
DQc
DQc
DQc
DQd
DQd
DQd
DQd
DQd
DQd
DQd
DQd
DQPd
BWd
LBO
A
NC
NC
NC
NC
NC
DQb
DQb
DQb
DQb
DQb
DQb
DQb
DQb
DQPb
NC
NC
NC
NC
NC
LBO
A
6K
7P
6N
6L
6K
7P
6N
6L
7K
5J
7K
5J
6H
7G
6F
7E
7D
7H
6G
6E
6D
7B
6C
5C
6A
5B
5A
4F
5G
6B
DQb
DQb
DQb
DQb
DQb
DQb
DQb
DQb
DQPb
NC
6H
7G
6F
7E
6D
7H
6G
6E
7D
7B
6C
5C
6A
5B
5A
4F
5G
6B
2M
1N
1P
1K
2L
2M
1N
2P
1K
2L
2N
2P
3L
2N
1P
3L
A
A
A
A
3R
2R
3T
4N
4P
A
3R
2R
3T
4N
4P
A
A
A
A
A
A
OE
A1
OE
NC
CS2
A1
BWb
CS2
A0
A0
NOTE, NC ; Don¢t Care
May 2001
Rev 0.1
- 16 -
K7N163645A
K7N161845A
Preliminary
512Kx36 & 1Mx18 Pipelined NtRAMTM
JTAG DC OPERATING CONDITIONS
Parameter
Symbol
Min
2.375
1.7
Typ
Max
2.625
VDD+0.3
0.7
Unit
V
Note
Power Supply Voltage
VDD
VIH
VIL
2.5
Input High Level
-
-
-
-
V
Input Low Level
-0.3
2.0
V
Output High Voltage
Output Low Voltage
VOH
VOL
-
V
-
0.4
V
NOTE : The input level of SRAM pin is to follow the SRAM DC specification.
JTAG AC TEST CONDITIONS
Parameter
Symbol
VIH/VIL
TR/TF
Min
Unit
V
Note
Input High/Low Level
2.5/0
Input Rise/Fall Time
1.0/1.0
VDDQ/2
ns
V
Input and Output Timing Reference Level
JTAG AC Characteristics
Parameter
Symbol
Min
50
20
20
5
Max
Unit
Note
TCK Cycle Time
tCHCH
tCHCL
tCLCH
tMVCH
tCHMX
tDVCH
tCHDX
tSVCH
tCHSX
tCLQV
-
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
TCK High Pulse Width
TCK Low Pulse Width
TMS Input Setup Time
TMS Input Hold Time
TDI Input Setup Time
TDI Input Hold Time
-
-
5
-
5
-
5
-
SRAM Input Setup Time
SRAM Input Hold Time
Clock Low to Output Valid
5
-
5
-
0
10
JTAG TIMING DIAGRAM
TCK
tCHCH
tCHCL
tCLCH
tMVCH
tCHMX
TMS
TDI
tDVCH
tCHDX
tCHSX
tSVCH
PI
(SRAM)
tCLQV
TDO
May 2001
Rev 0.1
- 17 -
K7N163645A
K7N161845A
Preliminary
512Kx36 & 1Mx18 Pipelined NtRAMTM
May 2001
Rev 0.1
- 18 -
K7N163645A
K7N161845A
Preliminary
512Kx36 & 1Mx18 Pipelined NtRAMTM
May 2001
Rev 0.1
- 19 -
K7N163645A
K7N161845A
Preliminary
512Kx36 & 1Mx18 Pipelined NtRAMTM
May 2001
Rev 0.1
- 20 -
K7N163645A
K7N161845A
Preliminary
512Kx36 & 1Mx18 Pipelined NtRAMTM
May 2001
Rev 0.1
- 21 -
K7N163645A
K7N161845A
Preliminary
512Kx36 & 1Mx18 Pipelined NtRAMTM
May 2001
Rev 0.1
- 22 -
K7N163645A
K7N161845A
Preliminary
512Kx36 & 1Mx18 Pipelined NtRAMTM
PACKAGE DIMENSIONS
100-TQFP-1420A
Units ; millimeters/Inches
22.00
20.00
±
±
0.30
0.20
0~8°
+0.10
- 0.05
0.127
16.00
14.00
±
0.30
0.10 MAX
±0.20
(0.83)
0.50 ± 0.10
#1
0.65
(0.58)
0.30
± 0.10
0.10 MAX
1.40
±0.10
1.60 MAX
0.05 MIN
0.50 ±0.10
May 2001
Rev 0.1
- 23 -
K7N163645A
K7N161845A
Preliminary
512Kx36 & 1Mx18 Pipelined NtRAMTM
119BGA PACKAGE DIMENSIONS
1.27
1.27
14.00±0.10
22.00±0.10
Indicator of
Ball(1A) Location
20.50±0.10
C0.70
C1.00
0.750±0.15
1.50REF
0.60±0.10
0.60±0.10
NOTE :
1. All Dimensions are in Millimeters.
2. Solder Ball to PCB Offset : 0.10 MAX.
3. PCB to Cavity Offset : 0.10 MAX.
12.50±0.10
May 2001
Rev 0.1
- 24 -
相关型号：
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