K7N403601A-TC150 [SAMSUNG]
ZBT SRAM, 128KX36, 3.8ns, CMOS, PQFP100, 20 X 14 MM, TQFP-100;
| 型号： | K7N403601A-TC150 |
| 厂家： | 
SAMSUNG |
| 描述： | ZBT SRAM, 128KX36, 3.8ns, CMOS, PQFP100, 20 X 14 MM, TQFP-100 静态存储器 内存集成电路 |
| 文件： | 总17页 (文件大小：387K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
K7N403601A
K7N401801A
128Kx36 & 256Kx18 Pipelined NtRAMTM
Document Title
128Kx36 & 256Kx18-Bit Pipelined NtRAMTM
Revision History
Rev.No.
History
Draft Date
Remark
0.0
1. Initial document.
Jan. 20. 2000
April. 03. 2000
Preliminary
Preliminary
0.1
1. Changed DC condition at Icc and ISB.
Icc ; from 350mA to 400mA at -16,
from 340mA to 390mA at -15,
from 310mA to 360mA at -13,
ISB ; from 130mA to 140mA at -16,
from 120mA to 130mA at -15,
from 120mA to 130mA at -13,
1.0
1. Final spec release
May. 15. 2000
Final
2. Changed input & output capacitance.
CIN
; from 6pF to 5pF,
COUT ; from 8pF to 7pF,
The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the
specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions on the parameters of this device. If you have any ques-
tions, please contact the SAMSUNG branch office near your office, call or contact Headquarters.
- 1 -
May 2000
Rev 1.0
K7N403601A
K7N401801A
128Kx36 & 256Kx18 Pipelined NtRAMTM
128Kx36 & 256Kx18-Bit Pipelined NtRAMTM
FEATURES
GENERAL DESCRIPTION
• VDD=3.3V+0.165V/-0.165V Power Supply.
The K7N403601A and K7N401801A are 4,718,592 bits Syn-
• VDDQ Supply Voltage 3.3V+0.165V/-0.165V for 3.3V I/O
chronous Static SRAMs.
The NtRAMTM, or No Turnaround Random Access Memory
utilizes all the bandwidth in any combination of operating
cycles.
or 2.5V+0.4V/-0.125V for 2.5V I/O.
• Byte Writable Function.
• Enable clock and suspend operation.
• Single READ/WRITE control pin.
• Self-Timed Write Cycle.
• Three Chip Enable for simple depth expansion with no datacon-
tention.
• A interleaved burst or a linear burst mode.
• Asynchronous output enable control.
• Power Down mode.
• TTL-Level Three-State Outputs.
• 100-TQFP-1420A Package.
Address, data inputs, and all control signals except output
enable and linear burst order are synchronized to input clock.
Burst order control must be tied "High or Low".
Asynchronous inputs include the sleep mode enable(ZZ).
Output Enable controls the outputs at any given time.
Write cycles are internally self-timed and initiated by the rising
edge of the clock input. This feature eliminates complex off-
chip write pulse generation
and provides increased timing flexibility for incomming sig-
nals.
For read cycles, pipelined SRAM output data is temporarily
stored by an edge trigered output register and then released
to the output bufferes at the next rising edge of clock.
The K7N403601A and K7N401801A are implemented with
SAMSUNG¢s high performance CMOS technology and is
available in 100pin TQFP packages. Multiple power and
ground pins minimize ground bounce.
FAST ACCESS TIMES
PARAMETER
Cycle Time
Symbol -16 -15 -13 Unit
tCYC
tCD
6.0 6.7 7.5
3.5 3.8 4.2
3.5 3.8 4.2
ns
ns
ns
Clock Access Time
Output Enable Access Time
tOE
LOGIC BLOCK DIAGRAM
LBO
BURST
ADDRESS
COUNTER
A¢0~A¢1
A [0:16]or
A [0:17]
A0~A1
128Kx36 , 256Kx18
MEMORY
ADDRESS
REGISTER
A2~A16 or A2~A17
ARRAY
WRITE
ADDRESS
REGISTER
WRITE
ADDRESS
REGISTER
DATA-IN
CLK
K
K
K
REGISTER
CKE
DATA-IN
REGISTER
CS1
CS2
CS2
ADV
WE
CONTROL
LOGIC
OUTPUT
K
BWx
(x=a,b,c,d or a,b)
REGISTER
BUFFER
OE
ZZ
36 or 18
DQa0 ~ DQd7 or DQa0 ~ DQb8
DQPa ~ DQPd
NtRAMTM and No Turnaround Random Access Memory are trademarks of Samsung,
- 2 -
May 2000
Rev 1.0
K7N403601A
K7N401801A
128Kx36 & 256Kx18 Pipelined NtRAMTM
PIN CONFIGURATION(TOP VIEW)
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
DQPb
DQb7
DQb6
VDDQ
VSSQ
DQb5
DQb4
DQb3
DQb2
VSSQ
VDDQ
DQb1
DQb0
VSS
DQPc
DQc0
DQc1
VDDQ
VSSQ
DQc2
DQc3
DQc4
DQc5
VSSQ
VDDQ
DQc6
DQc7
VDD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
100 Pin TQFP
VDD
VDD
ZZ
VDD
VDD
VSS
(20mm x 14mm)
DQa7
DQa6
VDDQ
VSSQ
DQa5
DQa4
DQa3
DQa2
VSSQ
VDDQ
DQa1
DQa0
DQPa
DQd0
DQd1
VDDQ
VSSQ
DQd2
DQd3
DQd4
DQd5
VSSQ
VDDQ
DQd6
DQd7
DQPd
K7N403601A(128Kx36)
PIN NAME
SYMBOL
PIN NAME
TQFP PIN NO.
SYMBOL
PIN NAME
TQFP PIN NO.
A0 - A16
Address Inputs
32,33,34,35,36,37
44,45,46,47,48,49
50,81,82,99,100
85
VDD
VSS
N.C.
Power Supply(+3.3V) 14,15,16,41,65,66,91
Ground
17,40,67,90
No Connect
38,39,42,43,83,84
ADV
WE
Address Advance/Load
Read/Write Control Input 88
Clock
Clock Enable
Chip Select
Chip Select
Chip Select
DQa0~a7
DQb0~b7
DQc0~c7
DQd0~d7
DQPa~Pd
Data Inputs/Outputs
52,53,56,57,58,59,62,63
68,69,72,73,74,75,78,79
2,3,6,7,8,9,12,13
CLK
CKE
CS1
CS2
CS2
89
87
98
97
18,19,22,23,24,25,28,29
51,80,1,30
92
BWx(x=a,b,c,d) Byte Write Inputs
93,94,95,96
VDDQ
VSSQ
Output Power Supply 4,11,20,27,54,61,70,77
(2.5V or 3.3V)
OE
ZZ
Output Enable
Power Sleep Mode
Burst Mode Control
86
64
31
Output Ground
5,10,21,26,55,60,71,76
LBO
Notes : 1. The pin 83 is reserved for address bit for the 8Mb NtRAM.
2. A0 and A1 are the two least significant bits(LSB) of the address field and set the internal burst counter if burst is desired.
- 3 -
May 2000
Rev 1.0
K7N403601A
K7N401801A
128Kx36 & 256Kx18 Pipelined NtRAMTM
PIN CONFIGURATION(TOP VIEW)
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
A10
N.C.
N.C.
N.C.
VDDQ
VSSQ
N.C.
N.C.
DQb8
DQb7
VSSQ
VDDQ
DQb6
DQb5
VDD
1
2
3
4
5
6
7
8
N.C.
N.C.
VDDQ
VSSQ
N.C.
DQa0
DQa1
DQa2
VSSQ
VDDQ
DQa3
DQa4
VSS
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
100 Pin TQFP
VDD
VDD
ZZ
VDD
VDD
VSS
(20mm x 14mm)
DQa5
DQa6
VDDQ
VSSQ
DQa7
DQa8
N.C.
N.C.
VSSQ
VDDQ
N.C.
N.C.
N.C.
DQb4
DQb3
VDDQ
VSSQ
DQb2
DQb1
DQb0
N.C.
VSSQ
VDDQ
N.C.
N.C.
N.C.
K7N401801A(256Kx18)
PIN NAME
SYMBOL
PIN NAME
TQFP PIN NO.
SYMBOL
PIN NAME
TQFP PIN NO.
A0 - A17
Address Inputs
32,33,34,35,36,37,
44,45,46,47,48,49
50,80,81,82,99,100
85
VDD
VSS
N.C.
Power Supply(+3.3V) 14,15,16,41,65,66,91
Ground
17,40,67,90
No Connect
1,2,3,6,7,25,28,29,30,
38,39,42,43,51,52,53,
56,57,75,78,79,83,84
95,96
ADV
WE
Address Advance/Load
Read/Write Control Input 88
Clock
Clock Enable
Chip Select
Chip Select
Chip Select
CLK
CKE
CS1
CS2
CS2
89
87
98
97
DQa0~a8
DQb0~b8
Data Inputs/Outputs 58,59,62,63,68,69,72,73,74
8,9,12,13,18,19,22,23,24
92
BWx(x=a,b) Byte Write Inputs
93,94
86
64
OE
ZZ
Output Enable
Power Sleep Mode
Burst Mode Control
VDDQ
VSSQ
Output Power Supply 4,11,20,27,54,61,70,77
(2.5V or 3.3V)
LBO
31
Output Ground
5,10,21,26,55,60,71,76
Notes : 1. The pin 83 is reserved for address bit for the 8Mb NtRAM.
2. A0 and A1 are the two least significant bits(LSB) of the address field and set the internal burst counter if burst is desired.
- 4 -
May 2000
Rev 1.0
K7N403601A
K7N401801A
128Kx36 & 256Kx18 Pipelined NtRAMTM
FUNCTION DESCRIPTION
The K7N403601A and K7N401801A are NtRAMTM designed to sustain 100% bus bandwidth by eliminating turnaround cycle when
there is transition from Read to Write, or vice versa.
All inputs (with the exception of OE, LBO and ZZ) are synchronized to rising clock edges.
All read, write and deselect cycles are initiated by the ADV input. Subsequent burst addresses can be internally generated by the
burst advance pin (ADV). ADV should be driven to Low once the device has been deselected in order to load a new address for next
operation.
Clock Enable(CKE) pin allows the operation of the chip to be suspended as long as necessary. When CKE is high, all synchronous
inputs are ignored and the internal device registers will hold their previous values.
NtRAMTM latches external address and initiates a cycle, when CKE, ADV are driven to low and all three chip enables(CS1, CS2, CS2)
are active .
Output Enable(OE) can be used to disable the output at any given time.
Read operation is initiated when at the rising edge of the clock, the address presented to the address inputs are latched in the
address register, CKE is driven low, all three chip enables(CS1, CS2, CS2) are active, the write enable input signals WE are driven
high, and ADV driven low.The internal array is read between the first rising edge and the second rising edge of the clock and the data
is latched in the output register. At the second clock edge the data is driven out of the SRAM. Also during read operation OE must
be driven low for the device to drive out the requested data.
Write operation occurs when WE is driven low at the rising edge of the clock. BW[d:a] can be used for byte write operation. The pipe-
lined NtRAMTM uses a late-late write cycle to utilize 100% of the bandwidth.
At the first rising edge of the clock, WE and address are registered, and the data associated with that address is required two cycle
later.
Subsequent addresses are generated by ADV High for the burst access as shown below. The starting point of the burst seguence is
provided by the external address. The burst address counter wraps around to its initial state upon completion.
The burst sequence is determined by the state of the LBO pin. When this pin is low, linear burst sequence is selected.
And when this pin is high, Interleaved burst sequence is selected.
During normal operation, ZZ must be driven low. When ZZ is driven high, the SRAM will enter a Power Sleep Mode after 2 cycles. At
this time, internal state of the SRAM is preserved. When ZZ returns to low, the SRAM normally operates after 2 cycles of wake up
time.
BURST SEQUENCE TABLE
(Interleaved Burst, LBO=High)
Case 4
Case 1
Case 2
Case 3
LBO PIN
HIGH
First Address
A1
A0
A1
A0
A1
A0
A1
A0
0
0
1
1
0
1
0
1
0
0
1
1
1
0
1
0
1
1
0
0
0
1
0
1
1
1
0
0
1
0
1
0
Fourth Address
Note : 1. LBO pin must be tied to High or Low, and Floating State must not be allowed.
BQ TABLE
(Linear Burst, LBO=Low)
Case 4
Case 1
Case 2
Case 3
LBO PIN
LOW
First Address
A1
A0
A1
A0
A1
A0
A1
A0
0
0
1
1
0
1
0
1
0
1
1
0
1
0
1
0
1
1
0
0
0
1
0
1
1
0
0
1
1
0
1
0
Fourth Address
Note : 1. LBO pin must be tied to High or Low, and Floating State must not be allowed.
- 5 -
May 2000
Rev 1.0
K7N403601A
K7N401801A
128Kx36 & 256Kx18 Pipelined NtRAMTM
STATE DIAGRAM FOR NtRAMTM
WRITE
READ
BEGIN
READ
BEGIN
WRITE
WRITE
READ
DESELECT
BURST
READ
BURST
WRITE
BURST
BURST
COMMAND
ACTION
DS
DESELECT
READ
WRITE
BEGIN READ
BEGIN WRITE
BEGIN READ
BURST
BEGIN WRITE
CONTINUE DESELECT
Notes : 1. An IGNORE CLOCK EDGE cycle is not shown is the above diagram. This is because CKE HIGH only blocks the clock(CLK) input and does
not change the state of the device.
2. States change on the rising edge of the clock(CLK)
- 6 -
May 2000
Rev 1.0
K7N403601A
K7N401801A
128Kx36 & 256Kx18 Pipelined NtRAMTM
TRUTH TABLES
SYNCHRONOUS TRUTH TABLE
CS1 CS2 CS2 ADV WE BWx OE
CKE CLK
ADDRESS ACCESSED
N/A
OPERATION
Not Selected
H
X
X
X
L
X
L
X
X
H
X
L
L
L
X
X
X
X
H
X
H
X
L
X
X
X
X
X
X
X
X
L
X
X
X
X
L
L
L
L
L
L
L
L
L
L
L
L
L
H
•
•
•
•
•
•
•
•
•
•
•
•
•
N/A
Not Selected
X
X
H
X
H
X
H
X
H
X
X
L
N/A
Not Selected
H
L
N/A
Not Selected Continue
Begin Burst Read Cycle
Continue Burst Read Cycle
NOP/Dummy Read
Dummy Read
External Address
Next Address
External Address
Next Address
External Address
Next Address
N/A
X
L
X
L
H
L
L
H
H
X
X
X
X
X
X
L
X
L
H
L
Begin Burst Write Cycle
Continue Burst Write Cycle
NOP/Write Abort
Write Abort
X
L
X
L
H
L
X
L
L
H
H
X
X
X
X
X
H
X
X
X
Next Address
Current Address
Ignore Clock
Notes : 1. X means "Don¢t Care".
2. The rising edge of clock is symbolized by (• ).
3. A continue deselect cycle can only be enterd if a deselect cycle is executed first.
4. WRITE = L means Write operation in WRITE TRUTH TABLE.
WRITE = H means Read operation in WRITE TRUTH TABLE.
5. Operation finally depends on status of asynchronous input pins(ZZ and OE).
WRITE TRUTH TABLE(x36)
WE
H
L
BWa
X
BWb
X
BWc
X
BWd
X
OPERATION
READ
L
H
H
H
WRITE BYTE a
WRITE BYTE b
WRITE BYTE c
WRITE BYTE d
WRITE ALL BYTEs
WRITE ABORT/NOP
L
H
L
H
H
L
H
H
L
H
L
H
H
H
L
L
L
L
L
L
L
H
H
H
H
Notes : 1. X means "Don¢t Care".
2. All inputs in this table must meet setup and hold time around the rising edge of CLK(• ).
WRITE TRUTH TABLE(x18)
WE
BWa
BWb
OPERATION
H
X
L
X
H
L
READ
L
WRITE BYTE a
WRITE BYTE b
WRITE ALL BYTEs
WRITE ABORT/NOP
L
H
L
L
L
L
H
H
Notes : 1. X means "Don¢t Care".
2. All inputs in this table must meet setup and hold time around the rising edge of CLK(• ).
- 7 -
May 2000
Rev 1.0
K7N403601A
K7N401801A
128Kx36 & 256Kx18 Pipelined NtRAMTM
ASYNCHRONOUS TRUTH TABLE
Notes
OPERATION
ZZ
H
L
OE
X
I/O STATUS
1. X means "Don¢t Care".
2. Sleep Mode means power Sleep Mode of which stand-by current does
not depend on cycle time.
3. Deselected means power Sleep Mode of which stand-by current
depends on cycle time.
Sleep Mode
High-Z
DQ
L
Read
L
H
X
High-Z
Write
L
Din, High-Z
High-Z
Deselected
L
X
ABSOLUTE MAXIMUM RATINGS*
PARAMETER
Voltage on VDD Supply Relative to VSS
Voltage on Any Other Pin Relative to VSS
Power Dissipation
SYMBOL
VDD
RATING
-0.3 to 4.6
-0.3 to VDD+0.5
1.4
UNIT
V
VIN
V
PD
W
Storage Temperature
TSTG
TOPR
TBIAS
-65 to 150
0 to 70
°C
°C
°C
Operating Temperature
Storage Temperature Range Under Bias
-10 to 85
*Notes : Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only
and functional operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not
implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
OPERATING CONDITIONS at 3.3V I/O(0°C £ TA £ 70°C)
PARAMETER
Supply Voltage
Ground
SYMBOL
VDD
MIN
3.135
3.135
0
Typ.
3.3
3.3
0
MAX
3.465
3.465
0
UNIT
V
V
V
VDDQ
VSS
OPERATING CONDITIONS at 2.5V I/O(0°C £ TA £ 70°C)
PARAMETER
Supply Voltage
Ground
SYMBOL
VDD
MIN
3.135
2.375
0
Typ.
3.3
2.5
0
MAX
3.465
2.9
UNIT
V
V
V
VDDQ
VSS
0
CAPACITANCE*(TA=25°C, f=1MHz)
PARAMETER
Input Capacitance
SYMBOL
TEST CONDITION
VIN=0V
MIN
MAX
UNIT
CIN
-
-
5
7
pF
pF
Output Capacitance
COUT
VOUT=0V
*Note : Sampled not 100% tested.
- 8 -
May 2000
Rev 1.0
K7N403601A
K7N401801A
128Kx36 & 256Kx18 Pipelined NtRAMTM
DC ELECTRICAL CHARACTERISTICS(VDD=3.3V+0.165V/-0.165V, TA=0°C to +70°C)
MIN
MAX
PARAMETER
SYMBOL
TEST CONDITIONS
UNIT NOTES
Input Leakage Current(except ZZ)
Output Leakage Current
IIL
VDD=Max ; VIN=VSS to VDD
-2
+2
mA
mA
IOL
Output Disabled,
-2
-
+2
-16
-15
-13
-16
-15
400
390
360
140
130
ICC
ISB
VDD=Max IOUT=0mA
Cycle Time ³ tCYC Min
Operating Current
Standby Current
-
mA
mA
1,2
-
-
Device deselected, IOUT=0mA,
ZZ£VIL, f=Max,
All Inputs£0.2V or ³ VDD-0.2V
-
-13
-
-
130
100
Device deselected, IOUT=0mA, ZZ£0.2V, f=0,
All Inputs=fixed (VDD-0.2V or 0.2V)
ISB1
ISB2
mA
mA
Device deselected, IOUT=0mA, ZZ³ VDD-0.2V,
f=Max, All Inputs£VIL or ³ VIH
-
50
Output Low Voltage(3.3V I/O)
Output High Voltage(3.3V I/O)
Output Low Voltage(2.5V I/O)
Output High Voltage(2.5V I/O)
Input Low Voltage(3.3V I/O)
Input High Voltage(3.3V I/O)
Input Low Voltage(2.5V I/O)
Input High Voltage(2.5V I/O)
VOL
VOH
VOL
VOH
VIL
IOL=8.0mA
IOH=-4.0mA
IOL=1.0mA
IOH=-1.0mA
-
0.4
V
V
V
V
V
V
V
V
2.4
-
-
0.4
-
2.0
-0.3*
2.0
-0.3*
1.7
0.8
VIH
VDD+0.5**
0.7
3
3
VIL
VIH
VDD+0.5**
Notes : 1. Reference AC Operating Conditions and Characteristics for input and timing.
2. Data states are all zero.
3. In Case of I/O Pins, the Max. VIH=VDDQ+0.3V
VIH
VSS
VSS-1.0V
20% tCYC(MIN)
TEST CONDITIONS
(VDD=3.3V+0.165V/-0.165V,VDDQ=3.3V+0.165/-0.165V or VDD=3.3V+0.165V/-0.165V,VDDQ=2.5V+0.4V/-0.125V, T
A=0to70°C)
PARAMETER
VALUE
0 to 3.0V
0 to 2.5V
1.0V/ns
1.0V/ns
1.5V
Input Pulse Level(for 3.3V I/O)
Input Pulse Level(for 2.5V I/O)
Input Rise and Fall Time(Measured at 20% to 80% for 3.3V I/O)
Input Rise and Fall Time(Measured at 20% to 80% for 2.5V I/O)
Input and Output Timing Reference Levels for 3.3V I/O
Input and Output Timing Reference Levels for 2.5V I/O
Output Load
VDDQ/2
See Fig. 1
- 9 -
May 2000
Rev 1.0
K7N403601A
K7N401801A
128Kx36 & 256Kx18 Pipelined NtRAMTM
Output Load(A)
Output Load(B),
(for tLZC, tLZOE, tHZOE & tHZC)
+3.3V for 3.3V I/O
/+2.5V for 2.5V I/O
RL=50W
Dout
VL=1.5V for 3.3V I/O
319W / 1667W
VDDQ/2 for 2.5V I/O
30pF*
Dout
Zo=50W
353W / 1538W
5pF*
* Including Scope and Jig Capacitance
Fig. 1
AC TIMING CHARACTERISTICS(VDD=3.3V+0.165V/-0.165V, TA=0°C to +70°C)
-16
-15
-13
PARAMETER
Symbol
UNIT
Max
Min
6.0
-
Max
Min
6.7
-
Max
Min
7.5
-
Cycle Time
tCYC
tCD
-
-
-
ns
ns
Clock Access Time
3.5
3.8
4.2
Output Enable to Data Valid
Clock High to Output Low-Z
Output Hold from Clock High
Output Enable Low to Output Low-Z
Output Enable High to Output High-Z
Clock High to Output High-Z
Clock High Pulse Width
tOE
-
3.5
-
3.8
-
4.2
ns
tLZC
tOH
1.5
1.5
0
-
1.5
1.5
0
-
1.5
1.5
0
-
ns
-
-
-
ns
tLZOE
tHZOE
tHZC
tCH
-
-
-
ns
-
3.5
-
3.5
-
3.8
ns
-
3.5
-
-
3.5
-
-
3.8
-
ns
2.5
2.5
1.5
1.5
1.5
1.5
1.5
1.5
0.5
0.5
0.5
0.5
0.5
0.5
2
2.5
2.5
1.5
1.5
1.5
1.5
1.5
1.5
0.5
0.5
0.5
0.5
0.5
0.5
2
3.0
3.0
1.5
1.5
1.5
1.5
1.5
1.5
0.5
0.5
0.5
0.5
0.5
0.5
2
ns
Clock Low Pulse Width
tCL
-
-
-
ns
Address Setup to Clock High
CKE Setup to Clock High
tAS
-
-
-
ns
tCES
tDS
-
-
-
ns
Data Setup to Clock High
-
-
-
ns
Write Setup to Clock High (WE, BWX)
Address Advance Setup to Clock High
Chip Select Setup to Clock High
Address Hold from Clock High
CKE Hold from Clock High
tWS
-
-
-
ns
tADVS
tCSS
tAH
-
-
-
ns
-
-
-
ns
-
-
-
ns
tCEH
tDH
-
-
-
ns
Data Hold from Clock High
-
-
-
ns
Write Hold from Clock High (WE, BWEX)
Address Advance Hold from Clock High
Chip Select Hold from Clock High
ZZ High to Power Down
tWH
-
-
-
ns
tADVH
tCSH
tPDS
tPUS
-
-
-
ns
-
-
-
ns
-
-
-
cycle
cycle
ZZ Low to Power Up
2
-
2
-
2
-
Notes : 1. All address inputs must meet the specified setup and hold times for all rising clock(CLK) edges when ADV is sampled low and CS is sampled
low. All other synchronous inputs must meet the specified setup and hold times whenever this device is chip selected.
2. Chip selects must be valid at each rising edge of CLK(when ADV is Low) to remain enabled.
3. A write cycle is defined by WE low having been registered into the device at ADV Low, A Read cycle is defined by WE High with ADV Low,
Both cases must meet setup and hold times.
4. To avoid bus contention, At a given voltage and temperature tLZC is more than tHZC.
The specs as shown do not imply bus contention because tLZC is a Min. parameter that is worst case at totally different test conditions
(0°C,3.465V) than tHZC, which is a Max. parameter(worst case at 70°C,3.135V)
It is not possible for two SRAMs on the same board to be at such different voltage and temperature.
- 10 -
May 2000
Rev 1.0
K7N403601A
K7N401801A
128Kx36 & 256Kx18 Pipelined NtRAMTM
SLEEP MODE
SLEEP MODE is a low current, power-down mode in which the device is deselected and current is reduced to ISB2. The duration of
SLEEP MODE is dictated by the length of time the ZZ is in a High state.
After entering SLEEP MODE, all inputs except ZZ become disabled and all outputs go to High-Z
The ZZ pin is an asynchronous, active high input that causes the device to enter SLEEP MODE.
When the ZZ pin becomes a logic High, ISB2 is guaranteed after the time tZZI is met. Any operation pending when entering SLEEP
MODE is not guaranteed to successful complete. Therefore, SLEEP MODE (READ or WRITE) must not be initiated until valid pend-
ing operations are completed. similarly, when exiting SLEEP MODE during tPUS, only a DESELECT or READ cycle should be given
while the SRAM is transitioning out of SLEEP MODE.
SLEEP MODE ELECTRICAL CHARACTERISTICS
DESCRIPTION
Current during SLEEP MODE
CONDITIONS
SYMBOL
ISB2
MIN
MAX
UNITS
mA
ZZ ³ VIH
10
ZZ active to input ignored
tPDS
2
2
cycle
cycle
cycle
ZZ inactive to input sampled
ZZ active to SLEEP current
ZZ inactive to exit SLEEP current
tPUS
tZZI
2
tRZZI
0
SLEEP MODE WAVEFORM
K
tPDS
ZZ setup cycle
tPUS
ZZ recovery cycle
ZZ
tZZI
Isupply
ISB2
tRZZI
All inputs
(except ZZ)
Deselect or Read Only
Deselect or Read Only
Normal
operation
cycle
Outputs
(Q)
High-Z
DON¢T CARE
- 11 -
May 2000
Rev 1.0
K7N403601A
K7N401801A
128Kx36 & 256Kx18 Pipelined NtRAMTM
- 12 -
May 2000
Rev 1.0
K7N403601A
K7N401801A
128Kx36 & 256Kx18 Pipelined NtRAMTM
- 13 -
May 2000
Rev 1.0
K7N403601A
K7N401801A
128Kx36 & 256Kx18 Pipelined NtRAMTM
- 14 -
May 2000
Rev 1.0
K7N403601A
K7N401801A
128Kx36 & 256Kx18 Pipelined NtRAMTM
- 15 -
May 2000
Rev 1.0
K7N403601A
K7N401801A
128Kx36 & 256Kx18 Pipelined NtRAMTM
- 16 -
May 2000
Rev 1.0
K7N403601A
K7N401801A
128Kx36 & 256Kx18 Pipelined NtRAMTM
PACKAGE DIMENSIONS
Units ; millimeters/Inches
100-TQFP-1420A
22.00 ±0.30
20.00 ±0.20
0~8°
+ 0.10
- 0.05
0.127
16.00 ±0.30
0.10 MAX
14.00 ±0.20
(0.83)
0.50 ±0.10
#1
0.65
(0.58)
0.30 ±0.10
0.10 MAX
1.40 ±0.10
1.60 MAX
0.05 MIN
0.50 ±0.10
- 17 -
May 2000
Rev 1.0
相关型号：
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