K7N801801A-EC15 [SAMSUNG]
ZBT SRAM, 512KX18, 3.8ns, CMOS, PBGA119;
| 型号： | K7N801801A-EC15 |
| 厂家： | 
SAMSUNG |
| 描述： | ZBT SRAM, 512KX18, 3.8ns, CMOS, PBGA119 时钟 静态存储器 内存集成电路 |
| 文件： | 总20页 (文件大小：459K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
K7N803601A
K7N801801A
256Kx36 & 512Kx18 Pipelined NtRAMTM
Document Title
256Kx36-Bit Pipelined NtRAMTM
Revision History
Rev. No.
History
Draft Date
Remark
0.0
1.0
1. Initial document.
May. 24. 2000
July. 03. 2000
Preliminary
Final
1. Final spec Release.
2. Add 119BGA(7x17 Ball Grid Array Package)
The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the
specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions on the parameters of this device. If you have any ques-
tions, please contact the SAMSUNG branch office near your office, call or contact Headquarters.
- 1 -
July 2000
Rev 1.0
K7N803601A
K7N801801A
256Kx36 & 512Kx18 Pipelined NtRAMTM
256Kx36-Bit Pipelined NtRAMTM
FEATURES
GENERAL DESCRIPTION
• 3.3V+0.165V/-0.165V Power Supply.
• I/O Supply Voltage 3.3V+0.165V/-0.165V for 3.3V I/O
or 2.5V+0.4V/-0.125V for 2.5V I/O.
• Byte Writable Function.
• Enable clock and suspend operation.
• Single READ/WRITE control pin.
• Self-Timed Write Cycle.
The K7N803601A and K7N801801A is 9,437,184 bits
Synchronous Static SRAMs.
The NtRAMTM, or No Turnaround Random Access Mem-
ory utilizes all the bandwidth in any combination of operat-
ing cycles.
Address, data inputs, and all control signals except output
enable and linear burst order are synchronized to input
• Three Chip Enable for simple depth expansion with no data conten-
tion .
clock.
Burst order control must be tied "High or Low".
Asynchronous inputs include the sleep mode enable(ZZ).
Output Enable controls the outputs at any given time.
Write cycles are internally self-timed and initiated by the
rising edge of the clock input. This feature eliminates com-
plex off-chip write pulse generation
• A interleaved burst or a linear burst mode.
• Asynchronous output enable control.
• Power Down mode.
•100-TQFP-1420A /119BGA(7x17 Ball Grid Array Package).
FAST ACCESS TIMES
and provides increased timing flexibility for incoming sig-
nals.
PARAMETER
Cycle Time
Symbol -16 -15 -13 -10 Unit
For read cycles, pipelined SRAM output data is tempo-
rarily stored by an edge triggered output register and then
released to the output buffers at the next rising edge of
clock.
tCYC
tCD
6.0 6.7 7.5 10 ns
3.5 3.8 4.2 5.0 ns
3.5 3.8 3.8 3.8 ns
Clock Access Time
Output Enable Access Time
tOE
The K7N803601A and K7N801801A is implemented with
SAMSUNG¢s high performance CMOS technology and is
available in 100pin TQFP and 119BGA packages. Multi-
ple power and ground pins minimize ground bounce.
LOGIC BLOCK DIAGRAM
LBO
BURST
A¢0~A¢1
ADDRESS
A0~A1
256Kx36
MEMORY
ARRAY
COUNTER
A [0:17]
ADDRESS
REGISTER
A2~A17
WRITE
ADDRESS
REGISTER
WRITE
ADDRESS
REGISTER
DATA-IN
CLK
K
K
K
REGISTER
CKE
DATA-IN
REGISTER
CS1
CS2
CS2
ADV
WE
CONTROL
LOGIC
OUTPUT
K
BWx
(x=a,b,c,d)
REGISTER
BUFFER
OE
ZZ
36
DQa0 ~ DQd7
DQPa ~ DQPd
NtRAMTM and No Turnaround Random Access Memory are trademarks of Samsung,
and its architecture and functionalities are supported by NEC and Toshiba.
- 2 -
July 2000
Rev 1.0
K7N803601A
K7N801801A
256Kx36 & 512Kx18 Pipelined NtRAMTM
PIN CONFIGURATION(TOP VIEW)
DQPc
1
DQPb
DQb7
DQb6
VDDQ
VSSQ
DQb5
DQb4
DQb3
DQb2
VSSQ
VDDQ
DQb1
DQb0
VSS
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
DQc0
2
DQc1
3
VDDQ
4
VSSQ
5
DQc2
6
DQc3
7
DQc4
8
DQc5
9
VSSQ
10
VDDQ
11
DQc6
12
100 Pin TQFP
DQc7
13
VDD
14
VDD
15
VDD
VDD
ZZ
(20mm x 14mm)
VDD
16
VSS
17
DQd0
18
DQa7
DQa6
VDDQ
VSSQ
DQa5
DQa4
DQa3
DQa2
VSSQ
VDDQ
DQa1
DQa0
DQPa
DQd1
19
K7N803601A(256Kx36)
VDDQ
VSSQ
DQd2
DQd3
DQd4
DQd5
VSSQ
VDDQ
DQd6
DQd7
DQPd
20
21
22
23
24
25
26
27
28
29
30
PIN NAME
SYMBOL
PIN NAME
TQFP PIN NO.
SYMBOL
PIN NAME
TQFP PIN NO.
A0 - A17
Address Inputs
32,33,34,35,36,37,44 VDD
45,46,47,48,49,50,81 VSS
Power Supply(+3.3V) 14,15,16,41,65,66,91
Ground
17,40,67,90
82,83,99,100
85
Read/Write Control Input 88
N.C.
No Connect
38,39,42,43,84
ADV
WE
Address Advance/Load
DQa0~a7
DQb0~b7
DQc0~c7
DQd0~d7
DQPa~Pd
Data Inputs/Outputs 52,53,56,57,58,59,62,63
68,69,72,73,74,75,78,79
2,3,6,7,8,9,12,13
CLK
CKE
CS1
CS2
CS2
Clock
89
87
98
97
Clock Enable
Chip Select
Chip Select
Chip Select
18,19,22,23,24,25,28,29
51,80,1,30
92
BWx(x=a,b,c,d) Byte Write Inputs
93,94,95,96
VDDQ
VSSQ
Output Power Supply 4,11,20,27,54,61,70,77
(3.3V or 2.5V)
OE
ZZ
Output Enable
Power Sleep Mode
Burst Mode Control
86
64
31
Output Ground
5,10,21,26,55,60,71,76
LBO
Notes : 1. The pin 84 is reserved for address bit for the 16Mb NtRAM.
2. A0 and A1 are the two least significant bits(LSB) of the address field and set the internal burst counter if burst is desired.
- 3 -
July 2000
Rev 1.0
K7N803601A
K7N801801A
256Kx36 & 512Kx18 Pipelined NtRAMTM
PIN CONFIGURATION(TOP VIEW)
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
A10
N.C.
N.C.
N.C.
VDDQ
VSSQ
N.C.
N.C.
DQb8
DQb7
VSSQ
VDDQ
DQb6
DQb5
VDD
1
2
3
4
5
6
7
8
N.C.
N.C.
VDDQ
VSSQ
N.C.
DQa0
DQa1
DQa2
VSSQ
VDDQ
DQa3
DQa4
VSS
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
100 Pin TQFP
VDD
VDD
ZZ
VDD
VDD
VSS
(20mm x 14mm)
DQa5
DQa6
VDDQ
VSSQ
DQa7
DQa8
N.C.
N.C.
VSSQ
VDDQ
N.C.
N.C.
N.C.
DQb4
DQb3
VDDQ
VSSQ
DQb2
DQb1
DQb0
N.C.
VSSQ
VDDQ
N.C.
N.C.
N.C.
K7N801801A(512Kx18)
PIN NAME
SYMBOL
PIN NAME
Address Inputs
TQFP PIN NO.
SYMBOL
PIN NAME
TQFP PIN NO.
A0 - A18
32,33,34,35,36,37,44 VDD
45,46,47,48,49,50,80 VSS
Power Supply(+3.3V) 14,15,16,41,65,66,91
Ground
17,40,67,90
81,82,83,99,100
85
Read/Write Control Input 88
N.C.
No Connect
1,2,3,6,7,25,28,29,30,
38,39,42,43,51,52,53,
56,57,75,78,79,84,95,96
ADV
WE
Address Advance/Load
CLK
CKE
CS1
CS2
CS2
Clock
89
87
98
97
Clock Enable
Chip Select
Chip Select
Chip Select
DQa0~a8
DQb0~b8
Data Inputs/Outputs
58,59,62,63,68,69,72,73,74
8,9,12,13,18,19,22,23,24
92
BWx(x=a,b) Byte Write Inputs
93,94
86
64
VDDQ
VSSQ
Output Power Supply 4,11,20,27,54,61,70,77
(3.3V or 2.5V)
OE
ZZ
Output Enable
Power Sleep Mode
Burst Mode Control
Output Ground
5,10,21,26,55,60,71,76
LBO
31
Notes : 1. The pin 84 is reserved for address bit for the 16Mb NtRAM.
2. A0 and A1 are the two least significant bits(LSB) of the address field and set the internal burst counter if burst is desired.
- 4 -
July 2000
Rev 1.0
K7N803601A
K7N801801A
256Kx36 & 512Kx18 Pipelined NtRAMTM
119BGA PACKAGE PIN CONFIGURATIONS(TOP VIEW)
K7N803601A(256Kx36)
1
2
A
3
A
4
5
A
6
A
7
A
B
C
D
E
F
VDDQ
NC
NC**
ADV
VDD
NC
CS1
OE
A
VDDQ
NC
CS2
A
A
A
CS2
A
NC
A
A
NC
DQc
DQc
VDDQ
DQc
DQc
VDDQ
DQd
DQd
VDDQ
DQd
DQd
NC
DQPc
DQc
DQc
DQc
DQc
VDD
DQd
DQd
DQd
DQd
DQPd
A
VSS
VSS
VSS
BWc
VSS
NC
VSS
BWd
VSS
VSS
VSS
LBO
A
VSS
VSS
VSS
BWb
VSS
NC
VSS
BWa
VSS
VSS
VSS
NC
A
DQPb
DQb
DQb
DQb
DQb
VDD
DQa
DQa
DQa
DQa
DQPa
A
DQb
DQb
VDDQ
DQb
DQb
VDDQ
DQa
DQa
VDDQ
DQa
DQa
NC
G
H
J
WE
VDD
CLK
NC
CKE
A1*
A0*
VDD
A
K
L
M
N
P
R
T
NC
NC
NC
ZZ
U
VDDQ
NC
NC
NC
NC
NC
VDDQ
Note : * A0 and A1 are the two least significant bits(LSB) of the address field and set the internal burst counter if burst is desired.
** Pin 4A is reserved for address expansion to 16Mb.
PIN NAME
SYMBOL
PIN NAME
SYMBOL
PIN NAME
A
Address Inputs
VDD
VSS
Power Supply
Ground
A0,A1
ADV
WE
CLK
CKE
CS1
Burst Address Inputs
Address Advance/Load
Read/Write Control Input
Clock
Clock Enable
Chip Select
N.C.
No Connect
DQa
DQb
DQc
DQd
Data Inputs/Outputs
Data Inputs/Outputs
Data Inputs/Outputs
Data Inputs/Outputs
Data Inputs/Outputs
CS2
CS2
Chip Select
Chip Select
DQPa~Pd
BWx
(x=a,b,c,d)
Byte Write Inputs
VDDQ
Output Power Supply
OE
ZZ
LBO
Output Enable
Power Sleep Mode
Burst Mode Control
- 5 -
July 2000
Rev 1.0
K7N803601A
K7N801801A
256Kx36 & 512Kx18 Pipelined NtRAMTM
119BGA PACKAGE PIN CONFIGURATIONS(TOP VIEW)
K7N801801A(512Kx18)
1
2
A
3
A
4
5
A
6
A
7
A
B
C
D
E
F
VDDQ
NC
NC**
ADV
VDD
NC
VDDQ
NC
CS2
A
A
A
CS2
A
NC
A
A
NC
DQb
NC
NC
DQb
NC
DQb
NC
VDD
DQb
NC
DQb
NC
DQPb
A
VSS
VSS
VSS
BWb
VSS
NC
VSS
VSS
VSS
VSS
VSS
LBO
A
VSS
VSS
VSS
VSS
VSS
NC
VSS
BWa
VSS
VSS
VSS
NC
A
DQPa
NC
DQa
NC
DQa
VDD
NC
DQa
NC
DQa
NC
A
NC
CS1
OE
DQa
VDDQ
DQa
NC
VDDQ
NC
G
H
J
A
DQb
VDDQ
NC
WE
VDD
CLK
NC
VDDQ
DQa
NC
K
L
DQb
VDDQ
DQb
NC
M
N
P
R
T
CKE
A1*
VDDQ
NC
A0*
DQa
NC
NC
VDD
NC
NC
A
A
ZZ
U
VDDQ
NC
NC
NC
NC
NC
VDDQ
Note : * A0 and A1 are the two least significant bits(LSB) of the address field and set the internal burst counter if burst is desired.
** Pin 4A is reserved for address expansion to 16Mb.
PIN NAME
SYMBOL
PIN NAME
SYMBOL
PIN NAME
A
Address Inputs
VDD
VSS
Power Supply
Ground
A0,A1
ADV
WE
CLK
CKE
CS1
Burst Address Inputs
Address Advance/Load
Read/Write Control Input
Clock
Clock Enable
Chip Select
No Connect
N.C.
Data Inputs/Outputs
Data Inputs/Outputs
Data Inputs/Outputs
DQa
DQb
DQPa, Pb
CS2
Chip Select
CS2
Chip Select
BWx
(x=a,b)
Byte Write Inputs
Output Power Supply
VDDQ
OE
ZZ
LBO
Output Enable
Power Sleep Mode
Burst Mode Control
- 6 -
July 2000
Rev 1.0
K7N803601A
K7N801801A
256Kx36 & 512Kx18 Pipelined NtRAMTM
FUNCTION DESCRIPTION
The K7N803601A and K7N801801A is NtRAMTM designed to sustain 100% bus bandwidth by eliminating turnaround cycle when
there is transition from Read to Write, or vice versa.
All inputs (with the exception of OE, LBO and ZZ) are synchronized to rising clock edges.
All read, write and deselect cycles are initiated by the ADV input. Subsequent burst addresses can be internally generated by the
burst advance pin (ADV). ADV should be driven to Low once the device has been deselected in order to load a new address for next
operation.
Clock Enable(CKE) pin allows the operation of the chip to be suspended as long as necessary. When CKE is high, all synchronous
inputs are ignored and the internal device registers will hold their previous values.
NtRAMTM latches external address and initiates a cycle, when CKE, ADV are driven to low and all three chip enables(CS1, CS2, CS2)
are active .
Output Enable(OE) can be used to disable the output at any given time.
Read operation is initiated when at the rising edge of the clock, the address presented to the address inputs are latched in the
address register, CKE is driven low, all three chip enables(CS1, CS2, CS2) are active, the write enable input signals WE are driven
high, and ADV driven low.The internal array is read between the first rising edge and the second rising edge of the clock and the data
is latched in the output register. At the second clock edge the data is driven out of the SRAM. Also during read operation OE must
be driven low for the device to drive out the requested data.
Write operation occurs when WE is driven low at the rising edge of the clock. BW[d:a] can be used for byte write operation. The pipe-
lined NtRAMTM uses a late-late write cycle to utilize 100% of the bandwidth.
At the first rising edge of the clock, WE and address are registered, and the data associated with that address is required two cycle
later.
Subsequent addresses are generated by ADV High for the burst access as shown below. The starting point of the burst seguence is
provided by the external address. The burst address counter wraps around to its initial state upon completion.
The burst sequence is determined by the state of the LBO pin. When this pin is low, linear burst sequence is selected.
And when this pin is high, Interleaved burst sequence is selected.
During normal operation, ZZ must be driven low. When ZZ is driven high, the SRAM will enter a Power Sleep Mode after 2 cycles. At
this time, internal state of the SRAM is preserved. When ZZ returns to low, the SRAM normally operates after 2 cycles of wake up
time.
BURST SEQUENCE TABLE
(Interleaved Burst, LBO=High)
Case 4
Case 1
Case 2
Case 3
LBO PIN
HIGH
First Address
A1
A0
A1
A0
A1
A0
A1
A0
0
0
1
1
0
1
0
1
0
0
1
1
1
0
1
0
1
1
0
0
0
1
0
1
1
1
0
0
1
0
1
0
Fourth Address
BQ TABLE
(Linear Burst, LBO=Low)
Case 4
Case 1
Case 2
Case 3
LBO PIN
LOW
First Address
A1
A0
A1
A0
A1
A0
A1
A0
0
0
1
1
0
1
0
1
0
1
1
0
1
0
1
0
1
1
0
0
0
1
0
1
1
0
0
1
1
0
1
0
Fourth Address
Note : 1. LBO pin must be tied to High or Low, and Floating State must not be allowed.
- 7 -
July 2000
Rev 1.0
K7N803601A
K7N801801A
256Kx36 & 512Kx18 Pipelined NtRAMTM
STATE DIAGRAM FOR NtRAMTM
WRITE
READ
BEGIN
READ
BEGIN
WRITE
WRITE
READ
DESELECT
BURST
READ
BURST
WRITE
BURST
BURST
COMMAND
ACTION
DS
DESELECT
READ
WRITE
BEGIN READ
BEGIN WRITE
BEGIN READ
BURST
BEGIN WRITE
CONTINUE DESELECT
Notes : 1. An IGNORE CLOCK EDGE cycle is not shown is the above diagram. This is because CKE HIGH only blocks the clock(CLK) input and does
not change the state of the device.
2. States change on the rising edge of the clock(CLK)
- 8 -
July 2000
Rev 1.0
K7N803601A
K7N801801A
256Kx36 & 512Kx18 Pipelined NtRAMTM
TRUTH TABLES
SYNCHRONOUS TRUTH TABLE
CS1
H
X
X
X
L
CS2
X
CS2 ADV WE BWx OE
CKE CLK
ADDRESS ACCESSED
N/A
OPERATION
Not Selected
X
X
H
X
L
L
L
X
X
X
X
H
X
H
X
L
X
X
X
X
X
X
X
X
L
X
X
X
X
L
L
L
L
L
L
L
L
L
L
L
L
L
H
•
•
•
•
•
•
•
•
•
•
•
•
•
L
N/A
Not Selected
X
L
N/A
Not Selected
X
H
L
N/A
Not Selected Continue
Begin Burst Read Cycle
Continue Burst Read Cycle
NOP/Dummy Read
Dummy Read
H
X
External Address
Next Address
External Address
Next Address
External Address
Next Address
N/A
X
L
X
L
H
L
L
H
X
H
H
X
X
X
X
X
X
L
X
L
H
L
H
X
Begin Burst Write Cycle
Continue Burst Write Cycle
NOP/Write Abort
Write Abort
X
L
X
L
H
L
X
L
L
H
X
H
H
X
X
X
X
X
H
X
X
X
Next Address
Current Address
X
Ignore Clock
Notes : 1. X means "Don¢t Care".
2. The rising edge of clock is symbolized by (• ).
3. A continue deselect cycle can only be enterd if a deselect cycle is executed first.
4. WRITE = L means Write operation in WRITE TRUTH TABLE.
WRITE = H means Read operation in WRITE TRUTH TABLE.
5. Operation finally depends on status of asynchronous input pins(ZZ and OE).
WRITE TRUTH TABLE(x36)
WE
H
L
BWa
X
BWb
X
BWc
X
BWd
X
OPERATION
READ
L
H
H
H
WRITE BYTE a
WRITE BYTE b
WRITE BYTE c
WRITE BYTE d
WRITE ALL BYTEs
WRITE ABORT/NOP
L
H
L
H
H
L
H
H
L
H
L
H
H
H
L
L
L
L
L
L
L
H
H
H
H
Notes : 1. X means "Don¢t Care".
2. All inputs in this table must meet setup and hold time around the rising edge of CLK(• ).
- 9 -
July 2000
Rev 1.0
K7N803601A
K7N801801A
256Kx36 & 512Kx18 Pipelined NtRAMTM
ASYNCHRONOUS TRUTH TABLE
Notes
Operation
ZZ
H
L
OE
X
I/O STATUS
1. X means "Don¢t Care".
2. Sleep Mode means power Sleep Mode of which stand-by current does
not depend on cycle time.
3. Deselected means power Sleep Mode of which stand-by current
depends on cycle time.
Sleep Mode
High-Z
DQ
L
Read
L
H
X
High-Z
Write
L
Din, High-Z
High-Z
Deselected
L
X
ABSOLUTE MAXIMUM RATINGS*
PARAMETER
Voltage on VDD Supply Relative to VSS
Voltage on Any Other Pin Relative to VSS
Power Dissipation
SYMBOL
VDD
RATING
-0.3 to 4.6
-0.3 to 4.6
1.6
UNIT
V
VIN
V
PD
W
Storage Temperature
TSTG
TOPR
TBIAS
-65 to 150
0 to 70
°C
°C
°C
Operating Temperature
Storage Temperature Range Under Bias
-10 to 85
*Notes : Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only
and functional operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not
implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
OPERATING CONDITIONS at 3.3V I/O(0°C £ TA £ 70°C)
PARAMETER
Supply Voltage
Ground
SYMBOL
VDD
MIN
3.135
3.135
0
Typ.
3.3
3.3
0
MAX
3.465
3.465
0
UNIT
V
V
V
VDDQ
VSS
OPERATING CONDITIONS at 2.5V I/O(0°C £ TA £ 70°C)
PARAMETER
Supply Voltage
Ground
SYMBOL
VDD
MIN
3.135
2.375
0
Typ.
3.3
2.5
0
MAX
3.465
2.9
UNIT
V
V
V
VDDQ
VSS
0
CAPACITANCE*(TA=25°C, f=1MHz)
PARAMETER
SYMBOL
TEST CONDITION
VIN=0V
MIN
MAX
UNIT
pF
Input Capacitance
CIN
-
-
6
8
Output Capacitance
COUT
VOUT=0V
pF
*Note : Sampled not 100% tested.
- 10 -
July 2000
Rev 1.0
K7N803601A
K7N801801A
256Kx36 & 512Kx18 Pipelined NtRAMTM
DC ELECTRICAL CHARACTERISTICS(VDD=3.3V+0.165V/-0.165V, TA=0°C to +70°C)
MIN
MAX
PARAMETER
SYMBOL
TEST CONDITIONS
VDD=Max ; VIN=VSS to VDD
UNIT NOTES
Input Leakage Current(except ZZ)
Output Leakage Current
IIL
-2
-2
-
+2
mA
mA
IOL
Output Disabled, Vout=VSS to VDDQ
+2
-16
-15
-13
-10
-16
-15
-13
-10
420
410
380
350
160
150
130
120
-
Device Selected, IOUT=0mA,
Operating Current
ICC
ISB
mA
mA
1,2
ZZ£VIL , Cycle Time ³ tCYC Min
-
-
-
Device deselected, IOUT=0mA,
ZZ£VIL, f=Max, All Inputs£0.2V or ³
VDD-0.2V
-
-
-
Standby Current
Device deselected, IOUT=0mA, ZZ£0.2V,
ISB1
ISB2
-
-
100
50
mA
mA
f=0, All Inputs=fixed (VDD-0.2V or 0.2V)
Device deselected, IOUT=0mA, ZZ³ VDD-0.2V,
f=Max, All Inputs£VIL or ³ VIH
Output Low Voltage(3.3V I/O)
Output High Voltage(3.3V I/O)
Output Low Voltage(2.5V I/O)
Output High Voltage(2.5V I/O)
Input Low Voltage(3.3V I/O)
Input High Voltage(3.3V I/O)
Input Low Voltage(2.5V I/O)
Input High Voltage(2.5V I/O)
VOL
VOH
VOL
VOH
VIL
IOL=8.0mA
IOH=-4.0mA
IOL=1.0mA
IOH=-1.0mA
-
0.4
V
V
V
V
V
V
V
V
2.4
-
-
0.4
-
2.0
-0.3*
2.0
-0.3*
1.7
0.8
VDD+0.5**
0.7
3
3
VIH
VIL
VIH
VDD+0.5**
Notes : 1. Reference AC Operating Conditions and Characteristics for input and timing.
2. Data states are all zero.
3. In Case of I/O Pins, the Max. VIH=VDDQ+0.3V
VIH
VSS
VSS-1.0V
20% tCYC(MIN)
TEST CONDITIONS
(VDD=3.3V+0.165V/-0.165V,VDDQ=3.3V+0.165/-0.165V or VDD=3.3V+0.165V/-0.165V,VDDQ=2.5V+0.4V/-0.125V, TA=0to70°C)
Parameter
Value
0 to 3.0V
0 to 2.5V
1.0V/ns
1.0V/ns
1.5V
Input Pulse Level(for 3.3V I/O)
Input Pulse Level(for 2.5V I/O)
Input Rise and Fall Time(Measured at 20% to 80% for 3.3V I/O)
Input Rise and Fall Time(Measured at 20% to 80% for 2.5V I/O)
Input and Output Timing Reference Levels for 3.3V I/O
Input and Output Timing Reference Levels for 2.5V I/O
Output Load
VDDQ/2
See Fig. 1
- 11 -
July 2000
Rev 1.0
K7N803601A
K7N801801A
Output Load(A)
256Kx36 & 512Kx18 Pipelined NtRAMTM
Output Load(B),
(for tLZC, tLZOE, tHZOE & tHZC)
+3.3V for 3.3V I/O
/+2.5V for 2.5V I/O
RL=50W
Dout
VL=1.5V for 3.3V I/O
319W / 1667W
VDDQ/2 for 2.5V I/O
30pF*
Dout
Zo=50W
353W / 1538W
5pF*
* Including Scope and Jig Capacitance
Fig. 1
AC TIMING CHARACTERISTICS(VDD=3.3V+0.165V/-0.165V, TA=0 to 70°C)
-16
-15
-13
-10
PARAMETER
SYMBOL
UNIT
MIN
6.0
-
MAX
MIN
6.7
-
MAX
MIN
7.5
-
MAX
MIN
10.0
-
MAX
Cycle Time
tCYC
tCD
-
-
-
-
ns
ns
Clock Access Time
3.5
3.8
4.2
5.0
Output Enable to Data Valid
Clock High to Output Low-Z
Output Hold from Clock High
Output Enable Low to Output Low-Z
Output Enable High to Output High-Z
Clock High to Output High-Z
Clock High Pulse Width
tOE
-
3.5
-
3.8
-
4.2
-
5.0
ns
tLZC
tOH
1.5
1.5
0
-
1.5
1.5
0
-
1.5
1.5
0
-
1.5
1.5
0
-
ns
-
-
-
-
ns
tLZOE
tHZOE
tHZC
tCH
-
-
-
-
ns
-
3.0
-
3.0
-
3.5
-
3.5
ns
-
3.0
-
-
3.0
-
-
3.5
-
-
3.5
-
ns
2.2
2.2
1.5
1.5
1.5
1.5
1.5
1.5
0.5
0.5
0.5
0.5
0.5
0.5
2
2.5
2.5
1.5
1.5
1.5
1.5
1.5
1.5
0.5
0.5
0.5
0.5
0.5
0.5
2
3.0
3.0
1.5
1.5
1.5
1.5
1.5
1.5
0.5
0.5
0.5
0.5
0.5
0.5
2
3.0
3.0
1.5
1.5
1.5
1.5
1.5
1.5
0.5
0.5
0.5
0.5
0.5
0.5
2
ns
Clock Low Pulse Width
tCL
-
-
-
-
ns
Address Setup to Clock High
CKE Setup to Clock High
tAS
-
-
-
-
ns
tCES
tDS
-
-
-
-
ns
Data Setup to Clock High
-
-
-
-
ns
Write Setup to Clock High (WE, BWX)
Address Advance Setup to Clock High
Chip Select Setup to Clock High
Address Hold from Clock High
CKE Hold from Clock High
tWS
-
-
-
-
ns
tADVS
tCSS
tAH
-
-
-
-
ns
-
-
-
-
ns
-
-
-
-
ns
tCEH
tDH
-
-
-
-
ns
Data Hold from Clock High
-
-
-
-
ns
Write Hold from Clock High (WE, BWEX)
Address Advance Hold from Clock High
Chip Select Hold from Clock High
ZZ High to Power Down
tWH
-
-
-
-
ns
tADVH
tCSH
tPDS
tPUS
-
-
-
-
ns
-
-
-
-
ns
-
-
-
-
cycle
cycle
ZZ Low to Power Up
2
-
2
-
2
-
2
-
Notes : 1. All address inputs must meet the specified setup and hold times for all rising clock(CLK) edges when ADV is sampled low and CS is sampled
low. All other synchronous inputs must meet the specified setup and hold times whenever this device is chip selected.
2. Chip selects must be valid at each rising edge of CLK(when ADV is Low) to remain enabled.
3. A write cycle is defined by WE low having been registered into the device at ADV Low, A Read cycle is defined by WE High with ADV Low,
Both cases must meet setup and hold times.
4. To avoid bus contention, At a given voltage and temperature tLZC is more than tHZC.
The specs as shown do not imply bus contention because tLZC is a Min. parameter that is worst case at totally different test conditions
(0°C,3.465V) than tHZC, which is a Max. parameter(worst case at 70°C,3.135V)
It is not possible for two SRAMs on the same board to be at such different voltage and temperature.
- 12 -
July 2000
Rev 1.0
K7N803601A
K7N801801A
256Kx36 & 512Kx18 Pipelined NtRAMTM
SLEEP MODE
SLEEP MODE is a low current, power-down mode in which the device is deselected and current is reduced to ISB2. The duration of
SLEEP MODE is dictated by the length of time the ZZ is in a High state.
After entering SLEEP MODE, all inputs except ZZ become disabled and all outputs go to High-Z
The ZZ pin is an asynchronous, active high input that causes the device to enter SLEEP MODE.
When the ZZ pin becomes a logic High, ISB2 is guaranteed after the time tZZI is met. Any operation pending when entering SLEEP
MODE is not guaranteed to successful complete. Therefore, SLEEP MODE (READ or WRITE) must not be initiated until valid pend-
ing operations are completed. similarly, when exiting SLEEP MODE during tPUS, only a DESELECT or READ cycle should be given
while the SRAM is transitioning out of SLEEP MODE.
SLEEP MODE ELECTRICAL CHARACTERISTICS
DESCRIPTION
Current during SLEEP MODE
CONDITIONS
SYMBOL
ISB2
MIN
MAX
UNITS
mA
ZZ ³ VIH
10
ZZ active to input ignored
tPDS
2
2
cycle
cycle
cycle
ZZ inactive to input sampled
ZZ active to SLEEP current
ZZ inactive to exit SLEEP current
tPUS
tZZI
2
tRZZI
0
SLEEP MODE WAVEFORM
K
tPDS
ZZ setup cycle
tPUS
ZZ recovery cycle
ZZ
tZZI
Isupply
ISB2
tRZZI
All inputs
(except ZZ)
Deselect or Read Only
Deselect or Read Only
Normal
operation
cycle
Outputs
(Q)
High-Z
DON¢T CARE
- 13 -
July 2000
Rev 1.0
K7N803601A
K7N801801A
256Kx36 & 512Kx18 Pipelined NtRAMTM
- 14 -
July 2000
Rev 1.0
K7N803601A
K7N801801A
256Kx36 & 512Kx18 Pipelined NtRAMTM
- 15 -
July 2000
Rev 1.0
K7N803601A
K7N801801A
256Kx36 & 512Kx18 Pipelined NtRAMTM
- 16 -
July 2000
Rev 1.0
K7N803601A
K7N801801A
256Kx36 & 512Kx18 Pipelined NtRAMTM
- 17 -
July 2000
Rev 1.0
K7N803601A
K7N801801A
256Kx36 & 512Kx18 Pipelined NtRAMTM
- 18 -
July 2000
Rev 1.0
K7N803601A
K7N801801A
256Kx36 & 512Kx18 Pipelined NtRAMTM
PACKAGE DIMENSIONS
Units ; millimeters/Inches
100-TQFP-1420A
22.00 ±0.30
20.00 ±0.20
0~8°
+ 0.10
- 0.05
0.127
16.00 ±0.30
0.10 MAX
14.00 ±0.20
(0.83)
0.50 ±0.10
#1
0.65
(0.58)
0.30 ±0.10
0.10 MAX
1.40 ±0.10
1.60 MAX
0.05 MIN
0.50 ±0.10
- 19 -
July 2000
Rev 1.0
K7N803601A
K7N801801A
256Kx36 & 512Kx18 Pipelined NtRAMTM
119BGA PACKAGE DIMENSIONS
1.27
1.27
14.00±0.10
22.00±0.10
Indicator of
Ball(1A) Location
20.50±0.10
C0.70
C1.00
0.750±0.15
1.50REF
0.60±0.10
0.60±0.10
Notes
1. All Dimensions are in Millimeters.
2. Solder Ball to PCB Offset : 0.10 MAX.
3. PCB to Cavity Offset : 0.10 MAX.
12.50±0.10
- 20 -
July 2000
Rev 1.0
相关型号：
K7N801801B-PC160
ZBT SRAM, 512KX18, 3.5ns, CMOS, PQFP100, 20 X 14 MM, ROHS COMPLIANT, TQFP-100
SAMSUNG
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