K7N801809B-HC20_技术文档

K7N803609B

K7N803209B

K7N801809B

256Kx36/x32 & 512Kx18 Pipelined NtRAM^TM

Document Title

256Kx36 & 256Kx32 & 512Kx18-Bit Pipelined NtRAM^TM

Revision History

Rev. No.

History

Draft Date

Remark

0.0

0.1

0.2

1.0

1. Initial document.

May. 18. 2001

Aug. 11. 2001

Aug. 28. 2001

Nov. 16. 2001

Preliminary

Final

1. Add x32 org part and industrial temperature part

1. change scan order(1) form 4T to 6T at 119BGA(x18)

1. Final spec release

2. Change ISB2 form 50mA to 60mA

The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the

specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions on the parameters of this device. If you have any ques-

tions, please contact the SAMSUNG branch office near your office, call or contact Headquarters.

- 1 -

Nov 2001

Rev 1.0

K7N803609B

K7N803209B

K7N801809B

256Kx36/x32 & 512Kx18 Pipelined NtRAM^TM

8Mb NtRAM(Flow Through / Pipelined) Ordering Information

Speed

Org.

Part Number

Mode

VDD

FT ; Access Time(ns)

PKG

Temp

Pipelined ; Cycle Time(MHz)

K7M801825B-Q(H)C(I)65/75/85 FlowThrough

3.3

2.5

3.3

2.5

3.3

2.5

6.5/7.5/8.5 ns

167/133 MHz

K7N801801B-Q(H)C(I)16/13

K7N801809B-Q(H)C(I)25/22/20

K7N801845B-Q(H)C(I)16/13

K7N801849B-Q(H)C(I)25/22/20

K7M803225B-QC(I)65/75/85

K7N803201B-QC(I)16/13

Pipelined

FlowThrough

Pipelined

512Kx18

250/225/200 MHz

167/133 MHz

250/225/200 MHz

6.5/7.5/8.5 ns

C:

Commercial

Temperature

Range

Q:

100TQFP

167/133 MHz

256Kx32

256Kx36

I:

K7N803209B-QC(I)25/22/20

K7N803245B-QC(I)C16/13

K7N803249B-QC(I)25/22/20

250/225/200 MHz

167/133 MHz

H:

119BGA

Industrial

Temperature

Range

250/225/200 MHz

6.5/7.5/8.5 ns

K7M803625B-Q(H)C(I)65/75/85 FlowThrough

K7N803601B-Q(H)C(I)16/13

K7N803609B-Q(H)C(I)25/22/20

K7N803645B-Q(H)C(I)16/13

K7N803649B-Q(H)C(I)25/22/20

Pipelined

167/133 MHz

250/225/200 MHz

167/133 MHz

250/225/200 MHz

- 2 -

Nov 2001

Rev 1.0

K7N803609B

K7N803209B

K7N801809B

256Kx36/x32 & 512Kx18 Pipelined NtRAM^TM

256Kx36 & 512Kx18-Bit Pipelined NtRAM^TM

FEATURES

GENERAL DESCRIPTION

• 3.3V+0.165V/-0.165V Power Supply.

• I/O Supply Voltage 3.3V+0.165V/-0.165V for 3.3V I/O

or 2.5V+0.4V/-0.125V for 2.5V I/O.

• Byte Writable Function.

• Enable clock and suspend operation.

• Single READ/WRITE control pin.

• Self-Timed Write Cycle.

• Three Chip Enable for simple depth expansion with no data conten-

tion .

The K7N803609B, K7N803209B and K7N801809B are

9,437,184 bits Synchronous Static SRAMs.

The NtRAM^TM, or No Turnaround Random Access Mem-

ory utilizes all the bandwidth in any combination of operat-

ing cycles.

Address, data inputs, and all control signals except output

enable and linear burst order are synchronized to input

clock.

Burst order control must be tied "High or Low".

Asynchronous inputs include the sleep mode enable(ZZ).

Output Enable controls the outputs at any given time.

Write cycles are internally self-timed and initiated by the

rising edge of the clock input. This feature eliminates com-

plex off-chip write pulse generation

• A interleaved burst or a linear burst mode.

• Asynchronous output enable control.

• Power Down mode.

•100-TQFP-1420A /119BGA(7x17 Ball Grid Array Package) .

• Operating in commeical and industrial temperature range.

FAST ACCESS TIMES

and provides increased timing flexibility for incoming sig-

nals.

PARAMETER

Cycle Time

Symbol -25

-22

4.4

2.8

-20 Unit

For read cycles, pipelined SRAM output data is tempo-

rarily stored by an edge triggered output register and then

released to the output buffers at the next rising edge of

clock.

tCYC

tCD

4.0

2.6

5.0

3.2

ns

Clock Access Time

Output Enable Access Time

tOE

The K7N803609B, K7N803209B and K7N801809B are

implemented with SAMSUNG¢s high performance CMOS

technology and is available in 100pin TQFP and 119BGA

packages(100pin TQFP only for K7N803201B).

Multiple power and ground pins minimize ground bounce.

LOGIC BLOCK DIAGRAM

LBO

BURST

ADDRESS

COUNTER

A¢0~A¢1

A [0:17] or

A [0:18]

A0~A1

256Kx36/32 , 512Kx18

MEMORY

ADDRESS

REGISTER

A2~A17 or A2~A18

ARRAY

WRITE

ADDRESS

REGISTER

WRITE

ADDRESS

REGISTER

DATA-IN

CLK

CKE

K

REGISTER

K

DATA-IN

REGISTER

CS1

CS2

ADV

WE

CONTROL

LOGIC

OUTPUT

K

BWx

(x=a,b,c,d or a,b)

REGISTER

BUFFER

OE

ZZ

36/32 or 18

DQa0 ~ DQd7 or DQa0 ~ DQb8

DQPa ~ DQPd

NtRAM^TMand No Turnaround Random Access Memory are trademarks of Samsung,

and its architecture and functionalities are supported by NEC and Toshiba.

- 3 -

Nov 2001

Rev 1.0

K7N803609B

K7N803209B

K7N801809B

256Kx36/x32 & 512Kx18 Pipelined NtRAM^TM

PIN CONFIGURATION(TOP VIEW)

DQPc/NC

1

DQPb/NC

DQb7

DQb6

VDDQ

VSSQ

DQb5

DQb4

DQb3

DQb2

VSSQ

VDDQ

DQb1

DQb0

VSS

80

79

78

77

76

75

74

73

72

71

70

69

68

67

66

65

64

63

62

61

60

59

58

57

56

55

54

53

52

51

DQc0

2

DQc1

3

VDDQ

4

VSSQ

5

DQc2

6

DQc3

7

DQc4

8

DQc5

9

VSSQ

10

VDDQ

11

DQc6

12

100 Pin TQFP

DQc7

13

VDD

14

VDD

15

VDD

ZZ

(20mm x 14mm)

VDD

16

VSS

17

DQd0

18

DQa7

DQa6

VDDQ

VSSQ

DQa5

DQa4

DQa3

DQa2

VSSQ

VDDQ

DQa1

DQa0

DQPa/NC

DQd1

19

K7N803609B(256Kx36)

K7N803209B(256Kx32)

VDDQ

VSSQ

DQd2

DQd3

DQd4

DQd5

VSSQ

VDDQ

DQd6

20

21

22

23

24

25

26

27

28

29

30

DQd7

DQPd/NC

PIN NAME

SYMBOL

PIN NAME

TQFP PIN NO.

SYMBOL

PIN NAME

TQFP PIN NO.

A0 - A17

Address Inputs

32,33,34,35,36,37,44 VDD

45,46,47,48,49,50,81 VSS

Power Supply(+3.3V) 14,15,16,41,65,66,91

Ground

17,40,67,90

82,83,99,100

85

Read/Write Control Input 88

N.C.

No Connect

38,39,42,43,84

ADV

WE

Address Advance/Load

DQa0~a7

DQb0~b7

DQc0~c7

DQd0~d7

DQPa~Pd

/NC

Data Inputs/Outputs 52,53,56,57,58,59,62,63

68,69,72,73,74,75,78,79

2,3,6,7,8,9,12,13

CLK

CKE

CS1

CS2

Clock

89

87

98

97

Clock Enable

Chip Select

18,19,22,23,24,25,28,29

51,80,1,30

92

BWx(x=a,b,c,d) Byte Write Inputs

93,94,95,96

VDDQ

Output Power Supply 4,11,20,27,54,61,70,77

(3.3V or 2.5V)

OE

ZZ

Output Enable

Power Sleep Mode

Burst Mode Control

86

64

31

VSSQ

Output Ground

5,10,21,26,55,60,71,76

LBO

Notes : 1. The pin 84 is reserved for address bit for the 16Mb NtRAM.

2. A0 and A1 are the two least significant bits(LSB) of the address field and set the internal burst counter if burst is desired.

3. DQPa~DQPd are NC for K7M803209B

- 4 -

Nov 2001

Rev 1.0

K7N803609B

K7N803209B

K7N801809B

256Kx36/x32 & 512Kx18 Pipelined NtRAM^TM

PIN CONFIGURATION(TOP VIEW)

80

79

78

77

76

75

74

73

72

71

70

69

68

67

66

65

64

63

62

61

60

59

58

57

56

55

54

53

52

51

A10

N.C.

VDDQ

VSSQ

N.C.

DQb8

DQb7

VSSQ

VDDQ

DQb6

DQb5

VDD

1

2

3

4

5

6

7

8

N.C.

VDDQ

VSSQ

N.C.

DQa0

DQa1

DQa2

VSSQ

VDDQ

DQa3

DQa4

VSS

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

100 Pin TQFP

VDD

ZZ

VDD

VSS

(20mm x 14mm)

DQa5

DQa6

VDDQ

VSSQ

DQa7

DQa8

N.C.

VSSQ

VDDQ

N.C.

DQb4

DQb3

VDDQ

VSSQ

DQb2

DQb1

DQb0

N.C.

VSSQ

VDDQ

N.C.

K7N801809B(512Kx18)

PIN NAME

SYMBOL

PIN NAME

Address Inputs

TQFP PIN NO.

SYMBOL

PIN NAME

TQFP PIN NO.

A0 - A18

32,33,34,35,36,37,44 VDD

45,46,47,48,49,50,80 VSS

Power Supply(+3.3V) 14,15,16,41,65,66,91

Ground

17,40,67,90

81,82,83,99,100

85

Read/Write Control Input 88

N.C.

No Connect

1,2,3,6,7,25,28,29,30,

38,39,42,43,51,52,53,

56,57,75,78,79,84,95,96

ADV

WE

Address Advance/Load

CLK

CKE

CS1

CS2

Clock

89

87

98

97

Clock Enable

Chip Select

DQa0~a8

DQb0~b8

Data Inputs/Outputs

58,59,62,63,68,69,72,73,74

8,9,12,13,18,19,22,23,24

92

BWx(x=a,b) Byte Write Inputs

93,94

86

64

VDDQ

VSSQ

Output Power Supply 4,11,20,27,54,61,70,77

(3.3V or 2.5V)

OE

ZZ

Output Enable

Power Sleep Mode

Burst Mode Control

Output Ground

5,10,21,26,55,60,71,76

LBO

31

Notes : 1. The pin 84 is reserved for address bit for the 16Mb NtRAM.

2. A0 and A1 are the two least significant bits(LSB) of the address field and set the internal burst counter if burst is desired.

- 5 -

Nov 2001

Rev 1.0

K7N803609B

K7N803209B

K7N801809B

256Kx36/x32 & 512Kx18 Pipelined NtRAM^TM

119BGA PACKAGE PIN CONFIGURATIONS(TOP VIEW)

K7N803609B(256Kx36)

1

2

3

A

4

5

A

6

A

7

A

B

C

D

E

F

VDDQ

NC

A

NC**

ADV

VDD

NC

VDDQ

NC

CS2

A

CS2

A

NC

A

NC

DQc

VDDQ

DQc

VDDQ

DQd

VDDQ

DQd

NC

DQPc

DQc

VDD

DQd

DQPd

A

VSS

BWc

VSS

NC

VSS

BWd

VSS

LBO

A

VSS

BWb

VSS

NC

VSS

BWa

VSS

NC

A

DQPb

DQb

VDD

DQa

DQPa

A

DQb

VDDQ

DQb

VDDQ

DQa

VDDQ

DQa

NC

CS1

OE

G

H

J

A

WE

VDD

CLK

NC

K

L

M

N

P

R

T

CKE

A1*

A0*

VDD

A

NC

ZZ

U

VDDQ

TMS

TDI

TCK

TDO

NC

VDDQ

Note : * A0 and A1 are the two least significant bits(LSB) of the address field and set the internal burst counter if burst is desired.

** Pin 4A is reserved for address expansion to 16Mb.

PIN NAME

SYMBOL

PIN NAME

SYMBOL

PIN NAME

A

Address Inputs

VDD

VSS

Power Supply

Ground

A0,A1

ADV

WE

CLK

CKE

CS1

Burst Address Inputs

Address Advance/Load

Read/Write Control Input

Clock

Clock Enable

Chip Select

N.C.

No Connect

DQa

DQb

DQc

DQd

Data Inputs/Outputs

CS2

Chip Select

DQPa~Pd

BWx

(x=a,b,c,d)

Byte Write Inputs

VDDQ

Output Power Supply

OE

ZZ

LBO

Output Enable

Power Sleep Mode

Burst Mode Control

TCK

TMS

TDI

JTAG Test Clock

JTAG Test Mode Select

JTAG Test Data Input

JTAG Test Data Output

TDO

- 6 -

Nov 2001

Rev 1.0

K7N803609B

K7N803209B

K7N801809B

256Kx36/x32 & 512Kx18 Pipelined NtRAM^TM

119BGA PACKAGE PIN CONFIGURATIONS(TOP VIEW)

K7N801809B(512Kx18)

1

2

A

3

A

4

5

A

6

A

7

A

B

C

D

E

F

VDDQ

NC

NC**

ADV

VDD

NC

VDDQ

NC

CS2

A

CS2

A

NC

A

NC

DQb

NC

DQb

NC

DQb

NC

VDD

DQb

NC

DQb

NC

DQPb

A

VSS

BWb

VSS

NC

VSS

LBO

A

VSS

NC

VSS

BWa

VSS

NC

A

DQPa

NC

DQa

NC

DQa

VDD

NC

DQa

NC

DQa

NC

A

NC

CS1

OE

DQa

VDDQ

DQa

NC

VDDQ

NC

G

H

J

A

DQb

VDDQ

NC

WE

VDD

CLK

NC

VDDQ

DQa

NC

K

L

DQb

VDDQ

DQb

NC

M

N

P

R

T

CKE

A1*

VDDQ

NC

A0*

DQa

NC

VDD

NC

A

ZZ

U

VDDQ

TMS

TDI

TCK

TDO

NC

VDDQ

Note : * A0 and A1 are the two least significant bits(LSB) of the address field and set the internal burst counter if burst is desired.

** Pin 4A is reserved for address expansion to 16Mb.

PIN NAME

SYMBOL

PIN NAME

SYMBOL

PIN NAME

A

Address Inputs

VDD

VSS

Power Supply

Ground

A0,A1

ADV

WE

CLK

CKE

CS1

Burst Address Inputs

Address Advance/Load

Read/Write Control Input

Clock

Clock Enable

Chip Select

No Connect

N.C.

Data Inputs/Outputs

DQa

DQb

DQPa, Pb

CS2

Chip Select

CS2

Chip Select

BWx

(x=a,b)

Byte Write Inputs

Output Power Supply

VDDQ

OE

ZZ

LBO

Output Enable

Power Sleep Mode

Burst Mode Control

TCK

TMS

TDI

JTAG Test Clock

JTAG Test Mode Select

JTAG Test Data Input

JTAG Test Data Output

TDO

- 7 -

Nov 2001

Rev 1.0

K7N803609B

K7N803209B

K7N801809B

256Kx36/x32 & 512Kx18 Pipelined NtRAM^TM

FUNCTION DESCRIPTION

The K7N803609B, K7N803209B and K7N801809B is NtRAM^TMdesigned to sustain 100% bus bandwidth by eliminating turnaround

cycle when there is transition from Read to Write, or vice versa.

All inputs (with the exception of OE, LBO and ZZ) are synchronized to rising clock edges.

All read, write and deselect cycles are initiated by the ADV input. Subsequent burst addresses can be internally generated by the

burst advance pin (ADV). ADV should be driven to Low once the device has been deselected in order to load a new address for next

operation.

Clock Enable(CKE) pin allows the operation of the chip to be suspended as long as necessary. When CKE is high, all synchronous

inputs are ignored and the internal device registers will hold their previous values.

NtRAM^TMlatches external address and initiates a cycle, when CKE, ADV are driven to low and all three chip enables(CS1, CS2, CS2)

are active .

Output Enable(OE) can be used to disable the output at any given time.

Read operation is initiated when at the rising edge of the clock, the address presented to the address inputs are latched in the

address register, CKE is driven low, all three chip enables(CS1, CS2, CS2) are active, the write enable input signals WE are driven

high, and ADV driven low.The internal array is read between the first rising edge and the second rising edge of the clock and the data

is latched in the output register. At the second clock edge the data is driven out of the SRAM. Also during read operation OE must

be driven low for the device to drive out the requested data.

Write operation occurs when WE is driven low at the rising edge of the clock. BW[d:a] can be used for byte write operation. The pipe-

lined NtRAM^TMuses a late-late write cycle to utilize 100% of the bandwidth.

At the first rising edge of the clock, WE and address are registered, and the data associated with that address is required two cycle

later.

Subsequent addresses are generated by ADV High for the burst access as shown below. The starting point of the burst seguence is

provided by the external address. The burst address counter wraps around to its initial state upon completion.

The burst sequence is determined by the state of the LBO pin. When this pin is low, linear burst sequence is selected.

And when this pin is high, Interleaved burst sequence is selected.

During normal operation, ZZ must be driven low. When ZZ is driven high, the SRAM will enter a Power Sleep Mode after 2 cycles. At

this time, internal state of the SRAM is preserved. When ZZ returns to low, the SRAM normally operates after 2 cycles of wake up

time.

BURST SEQUENCE TABLE

(Interleaved Burst, LBO=High)

Case 4

Case 1

Case 2

Case 3

LBO PIN

HIGH

First Address

A1

A0

A1

A0

A1

A0

A1

A0

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

Fourth Address

BQ TABLE

(Linear Burst, LBO=Low)

Case 4

Case 1

Case 2

Case 3

LBO PIN

LOW

First Address

A1

A0

A1

A0

A1

A0

A1

A0

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

Fourth Address

Note : 1. LBO pin must be tied to High or Low, and Floating State must not be allowed.

- 8 -

Nov 2001

Rev 1.0

K7N803609B

K7N803209B

K7N801809B

256Kx36/x32 & 512Kx18 Pipelined NtRAM^TM

STATE DIAGRAM FOR NtRAM^TM

WRITE

READ

BEGIN

READ

BEGIN

WRITE

READ

DESELECT

BURST

READ

BURST

WRITE

BURST

COMMAND

ACTION

DS

DESELECT

READ

WRITE

BEGIN READ

BEGIN WRITE

BEGIN READ

BURST

BEGIN WRITE

CONTINUE DESELECT

Notes : 1. An IGNORE CLOCK EDGE cycle is not shown is the above diagram. This is because CKE HIGH only blocks the clock(CLK) input and does

not change the state of the device.

2. States change on the rising edge of the clock(CLK)

- 9 -

Nov 2001

Rev 1.0

K7N803609B

K7N803209B

K7N801809B

256Kx36/x32 & 512Kx18 Pipelined NtRAM^TM

TRUTH TABLES

SYNCHRONOUS TRUTH TABLE

CS1

H

X

L

CS2

X

CS2 ADV WE BWx OE

CKE CLK

ADDRESS ACCESSED

N/A

OPERATION

Not Selected

X

H

X

L

X

H

X

H

X

L

X

L

X

L

H

•

L

N/A

Not Selected

X

L

N/A

Not Selected

X

H

L

N/A

Not Selected Continue

Begin Burst Read Cycle

Continue Burst Read Cycle

NOP/Dummy Read

Dummy Read

H

X

External Address

Next Address

External Address

Next Address

External Address

Next Address

N/A

X

L

X

L

H

L

H

X

H

X

L

X

L

H

L

H

X

Begin Burst Write Cycle

Continue Burst Write Cycle

NOP/Write Abort

Write Abort

X

L

X

L

H

L

X

L

H

X

H

X

H

X

Next Address

Current Address

X

Ignore Clock

Notes : 1. X means "Don¢t Care".

2. The rising edge of clock is symbolized by (• ).

3. A continue deselect cycle can only be enterd if a deselect cycle is executed first.

4. WRITE = L means Write operation in WRITE TRUTH TABLE.

WRITE = H means Read operation in WRITE TRUTH TABLE.

5. Operation finally depends on status of asynchronous input pins(ZZ and OE).

WRITE TRUTH TABLE(x36/32)

WE

H

L

BWa

X

BWb

X

BWc

X

BWd

X

OPERATION

READ

L

H

WRITE BYTE a

WRITE BYTE b

WRITE BYTE c

WRITE BYTE d

WRITE ALL BYTEs

WRITE ABORT/NOP

L

H

L

H

L

H

L

H

L

H

L

H

Notes : 1. X means "Don¢t Care".

2. All inputs in this table must meet setup and hold time around the rising edge of CLK(• ).

- 10 -

Nov 2001

Rev 1.0

K7N803609B

K7N803209B

K7N801809B

256Kx36/x32 & 512Kx18 Pipelined NtRAM^TM

ASYNCHRONOUS TRUTH TABLE

Notes

Operation

ZZ

H

L

OE

X

I/O STATUS

1. X means "Don¢t Care".

2. Sleep Mode means power Sleep Mode of which stand-by current does

not depend on cycle time.

3. Deselected means power Sleep Mode of which stand-by current

depends on cycle time.

Sleep Mode

High-Z

DQ

L

Read

L

H

X

High-Z

Write

L

Din, High-Z

High-Z

Deselected

L

X

ABSOLUTE MAXIMUM RATINGS*

PARAMETER

Voltage on VDD Supply Relative to VSS

Voltage on Any Other Pin Relative to VSS

Power Dissipation

SYMBOL

VDD

RATING

-0.3 to 4.6

-0.3 to VDD+0.3

1.6

UNIT

V

VIN

V

PD

W

Storage Temperature

TSTG

TOPR

TBIAS

-65 to 150

0 to 70

°C

Commercial

Industrial

Operating Temperature

-40 to 85

-10 to 85

Storage Temperature Range Under Bias

*Notes : Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only

and functional operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not

implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.

OPERATING CONDITIONS at 3.3V I/O(0°C £ TA £ 70°C)

PARAMETER

Supply Voltage

Ground

SYMBOL

MIN

3.135

0

Typ.

3.3

0

MAX

3.465

0

UNIT

VDD

V

VDDQ

VSS

* The above parameters are also guaranteed at industrial temperature range.

OPERATING CONDITIONS at 2.5V I/O(0°C £ TA £ 70°C)

PARAMETER

Supply Voltage

Ground

SYMBOL

VDD

MIN

3.135

2.375

0

Typ.

3.3

2.5

0

MAX

3.465

2.9

UNIT

V

VDDQ

VSS

0

* The above parameters are also guaranteed at industrial temperature range.

CAPACITANCE*(TA=25°C, f=1MHz)

PARAMETER

SYMBOL

TEST CONDITION

VIN=0V

MIN

MAX

UNIT

pF

Input Capacitance

CIN

-

5

7

Output Capacitance

COUT

VOUT=0V

pF

*Note : Sampled not 100% tested.

- 11 -

Nov 2001

Rev 1.0

K7N803609B

K7N803209B

K7N801809B

256Kx36/x32 & 512Kx18 Pipelined NtRAM^TM

DC ELECTRICAL CHARACTERISTICS(VDD=3.3V+0.165V/-0.165V, TA=0°C to +70°C)

MIN

MAX

PARAMETER

SYMBOL

TEST CONDITIONS

VDD=Max ; VIN=VSS to VDD

UNIT NOTES

Input Leakage Current(except ZZ)

Output Leakage Current

IIL

-2

-

+2

mA

IOL

Output Disabled, Vout=VSS to VDDQ

+2

-25

-22

-20

-25

-22

-20

470

440

400

170

160

150

Device Selected, IOUT=0mA,

Operating Current

Standby Current

ICC

ISB

-

mA

1,2

ZZ£VIL , Cycle Time ³ tCYC Min

-

Device deselected, IOUT=0mA,

ZZ£VIL, f=Max, All Inputs£0.2V or ³

VDD-0.2V

-

Device deselected, IOUT=0mA, ZZ£0.2V,

ISB1

ISB2

-

100

60

mA

f=0, All Inputs=fixed (VDD-0.2V or 0.2V)

Device deselected, IOUT=0mA, ZZ³ VDD-0.2V,

f=Max, All Inputs£VIL or ³ VIH

Output Low Voltage(3.3V I/O)

Output High Voltage(3.3V I/O)

Output Low Voltage(2.5V I/O)

Output High Voltage(2.5V I/O)

Input Low Voltage(3.3V I/O)

Input High Voltage(3.3V I/O)

Input Low Voltage(2.5V I/O)

Input High Voltage(2.5V I/O)

VOL

VOH

VOL

VOH

VIL

IOL=8.0mA

IOH=-4.0mA

IOL=1.0mA

IOH=-1.0mA

-

0.4

V

2.4

-

0.4

-

2.0

-0.3*

2.0

-0.3*

1.7

0.8

VDD+0.3**

0.7

3

VIH

VIL

VIH

VDD+0.3**

Notes : 1. The above parameters are also guaranteed at industrial temperature range.

2. Reference AC Operating Conditions and Characteristics for input and timing.

3. Data states are all zero.

4. In Case of I/O Pins, the Max. VIH=VDDQ+0.3V

VIH

VSS

VSS-1.0V

20% tCYC(MIN)

TEST CONDITIONS

(VDD=3.3V+0.165V/-0.165V,VDDQ=3.3V+0.165/-0.165V or VDD=3.3V+0.165V/-0.165V,VDDQ=2.5V+0.4V/-0.125V, TA=0to70°C)

Parameter

Value

0 to 3.0V

0 to 2.5V

1.0V/ns

1.5V

Input Pulse Level(for 3.3V I/O)

Input Pulse Level(for 2.5V I/O)

Input Rise and Fall Time(Measured at 20% to 80% for 3.3V I/O)

Input Rise and Fall Time(Measured at 20% to 80% for 2.5V I/O)

Input and Output Timing Reference Levels for 3.3V I/O

Input and Output Timing Reference Levels for 2.5V I/O

Output Load

VDDQ/2

See Fig. 1

* The above parameters are also guaranteed at industrial temperature range.

- 12 -

Nov 2001

Rev 1.0

K7N803609B

K7N803209B

K7N801809B

256Kx36/x32 & 512Kx18 Pipelined NtRAM^TM

Output Load(A)

Output Load(B),

(for tLZC, tLZOE, tHZOE & tHZC)

+3.3V for 3.3V I/O

/+2.5V for 2.5V I/O

RL=50W

30pF*

Dout

VL=1.5V for 3.3V I/O

VDDQ/2 for 2.5V I/O

319W / 1667W

Dout

Zo=50W

353W / 1538W

5pF*

* Including Scope and Jig Capacitance

Fig. 1

AC TIMING CHARACTERISTICS(VDD=3.3V+0.165V/-0.165V, TA=0 to 70°C)

-25

-22

-20

PARAMETER

SYMBOL

UNIT

MAX

MIN

4.0

-

MAX

MIN

4.4

-

MAX

MIN

5.0

-

Cycle Time

tCYC

tCD

-

ns

Clock Access Time

2.6

2.8

3.2

Output Enable to Data Valid

Clock High to Output Low-Z

Output Hold from Clock High

Output Enable Low to Output Low-Z

Output Enable High to Output High-Z

Clock High to Output High-Z

Clock High Pulse Width

tOE

-

2.6

-

2.8

-

3.2

ns

tLZC

tOH

0.8

0

-

1.0

0

-

1.0

0

-

ns

-

ns

tLZOE

tHZOE

tHZC

tCH

-

ns

-

2.6

-

2.8

-

3.0

-

2.6

-

2.8

-

3.0

-

ns

1.7

1.2

0.3

2

2.0

1.4

0.4

2

2.0

1.4

0.4

2

ns

Clock Low Pulse Width

tCL

-

ns

Address Setup to Clock High

CKE Setup to Clock High

tAS

-

ns

tCES

tDS

-

ns

Data Setup to Clock High

-

ns

Write Setup to Clock High (WE, BWX)

Address Advance Setup to Clock High

Chip Select Setup to Clock High

Address Hold from Clock High

CKE Hold from Clock High

tWS

-

ns

tADVS

tCSS

tAH

-

ns

-

ns

-

ns

tCEH

tDH

-

ns

Data Hold from Clock High

-

ns

Write Hold from Clock High (WE, BWEX)

Address Advance Hold from Clock High

Chip Select Hold from Clock High

ZZ High to Power Down

tWH

-

ns

tADVH

tCSH

tPDS

tPUS

-

ns

-

ns

-

cycle

ZZ Low to Power Up

2

-

2

-

2

-

Notes : 1. The above parameters are also guaranteed at industrial temperature range.

2. All address inputs must meet the specified setup and hold times for all rising clock(CLK) edges when ADV is sampled low and CS is sampled

low. All other synchronous inputs must meet the specified setup and hold times whenever this device is chip selected.

3. Chip selects must be valid at each rising edge of CLK(when ADV is Low) to remain enabled.

4. A write cycle is defined by WE low having been registered into the device at ADV Low, A Read cycle is defined by WE High with ADV Low,

Both cases must meet setup and hold times.

5. To avoid bus contention, At a given voltage and temperature tLZC is more than tHZC.

The specs as shown do not imply bus contention because tLZC is a Min. parameter that is worst case at totally different test conditions

(0°C,3.465V) than tHZC, which is a Max. parameter(worst case at 70°C,3.135V)

It is not possible for two SRAMs on the same board to be at such different voltage and temperature.

- 13 -

Nov 2001

Rev 1.0

K7N803609B

K7N803209B

K7N801809B

256Kx36/x32 & 512Kx18 Pipelined NtRAM^TM

SLEEP MODE

SLEEP MODE is a low current, power-down mode in which the device is deselected and current is reduced to ISB2. The duration of

SLEEP MODE is dictated by the length of time the ZZ is in a High state.

After entering SLEEP MODE, all inputs except ZZ become disabled and all outputs go to High-Z

The ZZ pin is an asynchronous, active high input that causes the device to enter SLEEP MODE.

When the ZZ pin becomes a logic High, ISB2 is guaranteed after the time tZZI is met. Any operation pending when entering SLEEP

MODE is not guaranteed to successful complete. Therefore, SLEEP MODE (READ or WRITE) must not be initiated until valid pend-

ing operations are completed. similarly, when exiting SLEEP MODE during tPUS, only a DESELECT or READ cycle should be given

while the SRAM is transitioning out of SLEEP MODE.

SLEEP MODE ELECTRICAL CHARACTERISTICS

DESCRIPTION

Current during SLEEP MODE

CONDITIONS

SYMBOL

ISB2

MIN

MAX

UNITS

mA

ZZ ³ VIH

10

ZZ active to input ignored

tPDS

2

cycle

ZZ inactive to input sampled

ZZ active to SLEEP current

ZZ inactive to exit SLEEP current

tPUS

tZZI

2

tRZZI

0

SLEEP MODE WAVEFORM

K

tPDS

ZZ setup cycle

tPUS

ZZ recovery cycle

ZZ

tZZI

Isupply

ISB2

tRZZI

All inputs

(except ZZ)

Deselect or Read Only

Normal

operation

cycle

Outputs

(Q)

High-Z

DON¢T CARE

- 14 -

Nov 2001

Rev 1.0

K7N803609B

K7N803209B

K7N801809B

256Kx36/x32 & 512Kx18 Pipelined NtRAM^TM

IEEE 1149.1 TEST ACCESS PORT AND BOUNDARY SCAN-JTAG

This part contains an IEEE standard 1149.1 Compatible Test Access Port(TAP). The package pads are monitored by the Serial Scan

circuitry when in test mode. This is to support connectivity testing during manufacturing and system diagnostics. Internal data is not

driven out of the SRAM under JTAG control. In conformance with IEEE 1149.1, the SRAM contains a TAP controller, Instruction Reg-

ister, Bypass Register and ID register. The TAP controller has a standard 16-state machine that resets internally upon power-up,

therefore, TRST signal is not required. It is possible to use this device without utilizing the TAP. To disable the TAP controller without

interfacing with normal operation of the SRAM, TCK must be tied to VSS to preclude mid level input. TMS and TDI are designed so an

undriven input will produce a response identical to the application of a logic 1, and may be left unconnected. But they may also be

tied to VDD through a resistor. TDO should be left unconnected.

JTAG Block Diagram

JTAG Instruction Coding

IR2 IR1 IR0 Instruction

TDO Output

Notes

0

1

0

1

0

1

0

1

0

1

0

1

EXTEST

IDCODE

SAMPLE-Z

BYPASS

SAMPLE

Boundary Scan Register

Identification Register

Boundary Scan Register

Bypass Register

1

3

2

4

5

6

4

0

1

Boundary Scan Register

1

RESERVED Do Not Use

SRAM

CORE

1

BYPASS

Bypass Register

NOTE :

1. Places DQs in Hi-Z in order to sample all input data regardless of other

SRAM inputs. This instruction is not IEEE 1149.1 compliant.

TDI

BYPASS Reg.

2. Places DQs in Hi-Z in order to sample all input data regardless of other

SRAM inputs.

TDO

Identification Reg.

Instruction Reg.

3. TDI is sampled as an input to the first ID register to allow for the serial shift

of the external TDI data.

4. Bypass register is initiated to VSS when BYPASS instruction is invoked. The

Bypass Register also holds serially loaded TDI when exiting the Shift DR

states.

Control Signals

TAP Controller

TMS

TCK

5. SAMPLE instruction dose not places DQs in Hi-Z.

6. This instruction is reserved for future use.

TAP Controller State Diagram

1

0

Test Logic Reset

0

1

0

Run Test Idle

Select DR

0

Select IR

0

1

Capture DR

0

Capture IR

0

Shift DR

1

Shift IR

1

Exit1 DR

0

Exit1 IR

0

Pause DR

1

Pause IR

1

Exit2 DR

1

Exit2 IR

1

0

Update DR

0

Update IR

1

- 15 -

Nov 2001

Rev 1.0

K7N803609B

K7N803209B

K7N801809B

256Kx36/x32 & 512Kx18 Pipelined NtRAM^TM

SCAN REGISTER DEFINITION

Part

Instruction Register

Bypass Register

1 bits

ID Register

32 bits

Boundary Scan

70 bits

256Kx36

512Kx18

3 bits

1 bits

32 bits

70 bits

ID REGISTER DEFINITION

Revision Number Part Configuration Vendor Definition Samsung JEDEC Code

Part

Start Bit(0)

(31:28)

(27:18)

(17:12)

XXXXXX

(11: 1)

256Kx36

512Kx18

0000

00110 00100

00111 00011

00001001110

1

0000

119BGA BOUNDARY SCAN EXIT ORDER(x36)

119BGA BOUNDARY SCAN EXIT ORDER(x18)

36

37

38

39

40

41

42

43

44

45

46

47

48

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

64

65

66

67

68

69

70

4B

4E

4H

3G

3C

3B

3A

2B

2C

2A

2D

1E

2F

1G

2H

1D

2E

2G

1H

2K

1L

ADV

CS1

WE

BWc

A

OE

A

4F

4G

4K

4M

4A

5G

5C

5B

5A

6B

6A

6C

6D

6E

6G

7H

7D

7E

6F

7G

6H

7K

6L

35

34

33

32

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

15

14

13

12

11

10

9

36

37

38

39

40

41

42

43

44

45

46

47

48

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

64

65

66

67

68

69

70

4B

4E

4H

3G

3C

3B

3A

2B

2C

2A

2D

1E

2F

1G

2H

1D

2E

2G

1H

2K

1L

ADV

CS1

WE

BWb

A

OE

A

4F

4G

4K

4M

4A

5G

5C

5B

5A

6B

6A

6C

7D

6E

6G

7H

6D

7E

6F

7G

6H

7K

6L

35

34

33

32

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

15

14

13

12

11

10

9

CLK

CKE

NC

CLK

CKE

NC

A

BWb

A

CS2

A

CS2

A

CS2

A

CS2

A

DQPc

DQc

DQd

DQPd

LBO

BWd

A

NC

DQb

DQPb

NC

LBO

NC

A

DQPb

DQb

DQa

DQPa

ZZ

NC

DQPa

DQa

NC

ZZ

2M

1N

1P

1K

2L

2M

1N

2P

1K

2L

6N

7P

6K

7L

6N

7P

6K

7L

2N

2P

3R

3L

2N

1P

3R

3L

6M

7N

6P

7T

6R

5L

8

6M

7N

6P

7T

6R

5L

8

7

6

2R

3T

4N

4P

2T

5

2R

3T

4N

4P

2T

5

A

4

A

4

A1

BWa

A

3

A1

BWa

A

3

A0

5T

4T

2

A0

5T

6T

2

NC

A

1

A

1

NOTE : NC ; Dont’ care.

- 16 -

Nov 2001

Rev 1.0

K7N803609B

K7N803209B

K7N801809B

256Kx36/x32 & 512Kx18 Pipelined NtRAM^TM

JTAG DC OPERATING CONDITIONS

Parameter

Power Supply Voltage

Symbol

Min

3.135

2.0 / 1.7

-0.3

Typ

Max

3.465

Unit

V

Note

VDD

VIH

3.3

Input High Level ( 3.3V I/O / 2.5V I/O )

Input Low Level ( 3.3V I/O / 2.5V I/O )

Output High Voltage ( 3.3V I/O / 2.5V I/O )

Output Low Voltage ( 3.3V I/O / 2.5V I/O )

-

VDD+0.3

0.8 / 0.7

-

V

1

VIL

V

VOH

VOL

2.4 / 2.0

-

V

0.4 / 0.4

V

NOTE : The input level of SRAM pin is to follow the SRAM DC specification.

1. In Case of I/O Pins, the Max. VIH=VDDQ+0.3V

JTAG AC TEST CONDITIONS

Parameter

Symbol

VIH/VIL

TR/TF

Min

Unit

V

Note

Input High/Low Level ( 3.3V I/O / 2.5V I/O )

Input Rise/Fall Time ( 3.3V I/O / 2.5V I/O )

Input and Output Timing Reference Level

3.0 / 0 , 2.5 / 0

1.0 / 1.0 , 1.0 /1 .0

VDDQ/2

ns

V

JTAG AC Characteristics

Parameter

TCK Cycle Time

Symbol

Min

50

20

5

Max

Unit

Note

tCHCH

tCHCL

tCLCH

tMVCH

tCHMX

tDVCH

tCHDX

tSVCH

tCHSX

tCLQV

-

ns

TCK High Pulse Width

TCK Low Pulse Width

TMS Input Setup Time

TMS Input Hold Time

TDI Input Setup Time

TDI Input Hold Time

5

SRAM Input Setup Time

SRAM Input Hold Time

Clock Low to Output Valid

5

0

10

JTAG TIMING DIAGRAM

TCK

tCHCH

tCHCL

tCLCH

tMVCH

tCHMX

tCHDX

TMS

TDI

tDVCH

tSVCH

tCHSX

PI

(SRAM)

tCLQV

TDO

- 17 -

Nov 2001

Rev 1.0

K7N803609B

K7N803209B

K7N801809B

256Kx36/x32 & 512Kx18 Pipelined NtRAM^TM

- 18 -

Nov 2001

Rev 1.0

K7N803609B

K7N803209B

K7N801809B

256Kx36/x32 & 512Kx18 Pipelined NtRAM^TM

- 19 -

Nov 2001

Rev 1.0

K7N803609B

K7N803209B

K7N801809B

256Kx36/x32 & 512Kx18 Pipelined NtRAM^TM

- 20 -

Nov 2001

Rev 1.0

K7N803609B

K7N803209B

K7N801809B

256Kx36/x32 & 512Kx18 Pipelined NtRAM^TM

- 21 -

Nov 2001

Rev 1.0

K7N803609B

K7N803209B

K7N801809B

256Kx36/x32 & 512Kx18 Pipelined NtRAM^TM

- 22 -

Nov 2001

Rev 1.0

K7N803609B

K7N803209B

K7N801809B

256Kx36/x32 & 512Kx18 Pipelined NtRAM^TM

PACKAGE DIMENSIONS

Units ; millimeters/Inches

100-TQFP-1420A

22.00 ±0.30

20.00 ±0.20

0~8°

+ 0.10

- 0.05

0.127

16.00 ±0.30

0.10 MAX

14.00 ±0.20

(0.83)

0.50 ±0.10

#1

0.65

(0.58)

0.30 ±0.10

0.10 MAX

1.40 ±0.10

1.60 MAX

0.05 MIN

0.50 ±0.10

- 23 -

Nov 2001

Rev 1.0

K7N803609B

K7N803209B

K7N801809B

256Kx36/x32 & 512Kx18 Pipelined NtRAM^TM

119BGA PACKAGE DIMENSIONS

1.27

14.00±0.10

22.00±0.10

Indicator of

Ball(1A) Location

20.50±0.10

C0.70

C1.00

0.750±0.15

1.50REF

0.60±0.10

Notes

1. All Dimensions are in Millimeters.

2. Solder Ball to PCB Offset : 0.10 MAX.

3. PCB to Cavity Offset : 0.10 MAX.

12.50±0.10

- 24 -

Nov 2001

Rev 1.0


型号：	K7N801809B-HC20
厂家：	SAMSUNG
描述：	ZBT SRAM, 512KX18, 3.2ns, CMOS, PBGA119, BGA-119 静态存储器内存集成电路
文件：	总24页 (文件大小：536K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

K7N801809B-HC20 [SAMSUNG]

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