K7Q323682M-FC10 [SAMSUNG]
QDR SRAM, 1MX36, 3ns, CMOS, PBGA165, FBGA-165;
| 型号： | K7Q323682M-FC10 |
| 厂家： | 
SAMSUNG |
| 描述： | QDR SRAM, 1MX36, 3ns, CMOS, PBGA165, FBGA-165 时钟 静态存储器 内存集成电路 |
| 文件： | 总17页 (文件大小：506K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
K7Q323682M
K7Q321882M
Preliminary
1Mx36 & 2Mx18 QDRTM b2 SRAM
Document Title
1Mx36-bit, 2Mx18-bit QDRTM SRAM
Revision History
Rev. No.
History
Draft Date
Remark
Advance
Advance
0.0
1. Initial document.
Sep, 5 2001
Nov. 20. 2001
0.1
1. Changed Pin configuration at x36 organization.
- 9F ; from Q14 to D14 .
- 10F ; from D14 to Q14 .
0.2
0.3
1. Reserved pin for high density name change from NC to Vss/SA
1. Correct AC timing characteristics( tKHCK of -20part ; 0.0 to 2.0 )
Preliminary
Preliminary
Dec. 20. 2001
Oct. 23, 2002
The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the
specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions on the parameters of this device. If you have any ques-
tions, please contact the SAMSUNG branch office near your office, call or contact Headquarters.
Oct 2002
Rev 0.3
- 1 -
K7Q323682M
K7Q321882M
Preliminary
1Mx36 & 2Mx18 QDRTM b2 SRAM
1Mx36-bit, 2Mx18-bit QDRTM SRAM
FEATURES
• 1.8V+0.1V/-0.1V Power Supply.
• I/O Supply Voltage 1.5V+0.1V/-0.1V for 1.5V I/O, 1.8V+0.1V/
-0.1V for 1.8V I/O.
Part
Number
Cycle Access
Organization
Unit
Time
Time
• Separate independent read and write data ports
with concurrent read and write operation
• HSTL I/O.
K7Q323682M-FC20
K7Q323682M-FC16
K7Q323682M-FC13
K7Q323682M-FC10
K7Q321882M-FC20
K7Q321882M-FC16
K7Q321882M-FC13
K7Q321882M-FC10
5.0
6.0
2.2
2.5
3.0
3.0
2.2
2.5
3.0
3.0
ns
ns
ns
ns
ns
ns
ns
ns
X36
• Full data coherency, providing most current data .
• Synchronous pipeline read with self timed early write.
• Registered address, control and data input/output.
• DDR(Double Data Rate) Interface on read and write ports.
• Fixed 2-bit burst for both read and write operation.
• Clock-stop supports to reduce current.
• Two input clocks(K and K) for accurate DDR timing at clock
rising edges only.
7.5
10.0
5.0
6.0
X18
7.5
10.0
• Two input clocks for output data(C and C) to minimize
clock-skew and flight-time mismatches.
• Single address bus.
• Byte writable function.
• Sepatate read/write control pin(R and W)
• Simple depth expansion with no data contention.
• Programmable output impedance.
• JTAG 1149.1 compatible test access port.
• 165FBGA(11x15 ball aray FBGA) with body size of 15x17mm
FUNCTIONAL BLOCK DIAGRAM
36 (or 18)
19 (or 20)
DATA
REG
D(Data in)
36 (or 18)
36 (or 18)
WRITE DRIVER
19
(or 20)
ADD
REG
ADDRESS
R
1Mx36
2Mx18
MEMORY
ARRAY
72
(or 36)
72
(or 36)
36 (or 18)
Q(Data Out)
CTRL
LOGIC
W
BWX
4(or 2)
K
K
CLK
GEN
C
C
SELECT OUTPUT CONTROL
Notes: 1. Numbers in ( ) are for x18 device.
QDR SRAM and Quad Data Rate comprise a new family of products developed by Cypress, Hitachi, IDT, Micron, NEC and Samsung technology.
Oct 2002
Rev 0.3
- 2 -
K7Q323682M
K7Q321882M
Preliminary
1Mx36 & 2Mx18 QDRTM b2 SRAM
PIN CONFIGURATIONS(TOP VIEW) K7Q321882M(2Mx18)
1
2
VSS/SA*
Q9
3
4
5
6
7
8
9
SA
10
VSS/SA*
NC
11
NC
Q8
D8
D7
Q6
Q5
D5
ZQ
D4
Q3
Q2
D2
D1
Q0
TDI
A
B
C
D
E
F
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
TDO
SA
W
BW1
NC
K
NC
R
D9
SA
K
BW0
SA
SA
NC
NC
NC
NC
NC
NC
VDDQ
NC
NC
NC
NC
NC
NC
SA
NC
D10
Q10
Q11
D12
Q13
VDDQ
D14
Q14
D15
D16
Q16
Q17
SA
VSS
SA
SA
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
SA
C
VSS
VSS
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VSS
VSS
SA
Q7
D11
NC
VSS
VSS
VSS
VDD
VDD
VDD
VDD
VDD
VSS
VSS
SA
VSS
VSS
VDD
VDD
VDD
VDD
VDD
VSS
VSS
SA
NC
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VSS
D6
Q12
D13
VREF
NC
NC
G
H
J
NC
VREF
Q4
K
L
NC
D3
Q15
NC
NC
M
N
P
R
Q1
D17
NC
VSS
NC
SA
SA
SA
D0
TCK
SA
SA
C
SA
SA
TMS
Notes: 1. * Checked No Connect(NC) pins are reserved for higher density address, i.e. 10A for 64Mb and 2A for 128Mb.
2. BW0 controls write to D0:D8 and BW1 controls write to D9:D17.
PIN NAME
SYMBOL
K, K
PIN NUMBERS
DESCRIPTION
NOTE
6B, 6A
6P, 6R
Input Clock
C, C
Input Clocks for Output data
Address Inputs
1
SA
3A,9A,4B,8B,5C-7C,5N-7N,4P,5P,7P,8P,3R-5R,7R-9R
10P,11N,11M,10K,11J,11G,10E,11D,11C,3B,3C,2D,
3F,2G,3J,3L,3M,2N
Data Inputs
D0-17
Q0-17
11P,10M,11L,11K,10J,11F,11E,10C,11B,2B,3D,3E,
2F,3G,3K,2L,3N,3P
Data Outputs
W
R
4A
Write Control
Read Control
8A
BW0, BW1
VREF
ZQ
7B, 5A
Byte Write Control
2H,10H
11H
Input Reference Voltage
Output Driver Impedance Control Input
Power Supply ( 1.8 V )
2
VDD
5F,7F,5G,7G,5H,7H,5J,7J,5K,7K
4E,8E,4F,8F,4G,8G,3H,4H,8H,9H,4J,8J,4K,8K,4L,8L
VDDQ
Output Power Supply (1.5V or 1.8V)
2A,10A,4C,8C,4D-8D,5E-7E,
6F,6G,6H,6J,6K,5L-7L,4M-8M,4N,8N
VSS
Ground
TMS
TDI
10R
11R
2R
JTAG Test Mode Select
JTAG Test Data Input
JTAG Test Clock
TCK
TDO
1R
JTAG Test Data Output
1A,7A,11A,1B,5B,9B,10B,1C,2C,9C,1D,9D,10D,
1E,2E,9E,1F,9F,10F,1G,9G,10G,1H,1J,2J,9J,1K,
2K,9J,1L,9L,10L,1M,2M,9M,1N,9N,10N,1P,2P,9P
NC
No Connect
3
Notes: 1. C, C, K or K cannot be set to VREF voltage.
2. When ZQ pin is directly connected to VDD output impedance is set to minimum value and it cannot be connected to ground or left unconnected.
3. Not connected to chip pad internally.
Oct 2002
Rev 0.3
- 3 -
K7Q323682M
K7Q321882M
Preliminary
1Mx36 & 2Mx18 QDRTM b2 SRAM
PIN CONFIGURATIONS(TOP VIEW) K7Q323682M(1Mx36)
1
2
3
4
5
6
7
8
9
10
VSS/SA*
Q17
Q7
11
NC
Q8
D8
D7
Q6
Q5
D5
ZQ
D4
Q3
Q2
D2
D1
Q0
TDI
A
B
C
D
E
F
NC
VSS/SA* NC/SA*
W
BW2
BW3
SA
K
BW1
BW0
SA
R
SA
Q27
D27
D28
Q29
Q30
D30
NC
Q18
Q28
D20
D29
Q21
D22
VREF
Q31
D32
Q24
Q34
D26
D35
TCK
D18
D19
Q19
Q20
D21
Q22
VDDQ
D23
Q23
D24
D25
Q25
Q26
SA
SA
K
SA
D17
D16
Q16
Q15
D14
Q13
VDDQ
D12
Q12
D11
D10
Q10
Q9
VSS
SA
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
SA
C
VSS
VSS
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VSS
VSS
SA
VSS
VSS
VSS
VDD
VDD
VDD
VDD
VDD
VSS
VSS
SA
VSS
VSS
VDD
VDD
VDD
VDD
VDD
VSS
VSS
SA
D15
D6
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VSS
Q14
D13
VREF
Q4
G
H
J
D31
Q32
Q33
D33
D34
Q35
TDO
K
L
D3
Q11
Q1
M
N
P
R
VSS
D9
SA
SA
SA
D0
SA
SA
C
SA
SA
SA
TMS
Notes : 1. * Checked No Connect(NC) pins are reserved for higher density address, i.e. 3A for 64Mb, 10A for 128Mb and 2A for 256Mb.
2. BW0 controls write to D0:D8, BW1 controls write to D9:D17, BW2 controls write to D18:D26 and BW3 controls write to D27:D35.
PIN NAME
SYMBOL
K, K
PIN NUMBERS
DESCRIPTION
Input Clock
NOTES
6B, 6A
6P, 6R
C, C
Input Clocks for Output data
Address Inputs
1
SA
9A,4B,8B,5C-7C,5N-7N,4P,5P,7P,8P,3R-5R,7R-9R
10P,11N,11M,10K,11J,11G,10E,11D,11C,10N,9M,9L
9J,10G,9F,10D,9C,9B,3B,3C,2D,3F,2G,3J,3L,3M,2N
1C,1D,2E,1G,1J,2K,1M,1N,2P
D0-35
Q0-35
Data Inputs
11P,10M,11L,11K,10J,11F,11E,10C,11B,9P,9N,10L
9K,9G,10F,9E,9D,10B,2B,3D,3E,2F,3G,3K,2L,3N
3P,1B,2C,1E,1F,2J,1K,1L,2M,1P
Data Outputs
W
4A
Write Control Pin
Read Control Pin
R
8A
BW0, BW1,BW2, BW3
7B,7A,5A,5B
Byte Write Control Pin
VREF
ZQ
2H,10H
11H
Input Reference Voltage
Output Driver Impedance Control Input
Power Supply ( 1.8 V )
2
VDD
VDDQ
5F,7F,5G,7G,5H,7H,5J,7J,5K,7K
4E,8E,4F,8F,4G,8G,3H,4H,8H,9H,4J,8J,4K,8K,4L,8L
Output Power Supply (1.5V or 1.8V)
2A,10A,4C,8C,4D-8D,5E-7E,
6F,6G,6H,6J,6K,5L-7L,4M-8M,4N,8N
VSS
Ground
TMS
TDI
10R
JTAG Test Mode Select
JTAG Test Data Input
JTAG Test Clock
11R
TCK
TDO
NC
2R
1R
JTAG Test Data Output
No Connect
1A,3A,11A,1H
3
Notes: 1. C, C, K or K cannot be set to VREF voltage.
2. When ZQ pin is directly connected to VDD output impedance is set to minimum value and it cannot be connected to ground or left unconnected.
3. Not connected to chip pad internally.
Oct 2002
Rev 0.3
- 4 -
K7Q323682M
K7Q321882M
Preliminary
1Mx36 & 2Mx18 QDRTM b2 SRAM
GENERAL DESCRIPTION
The K7Q323682M and K7Q321882M are 37,748,736-bits QDR(Quad Data Rate) Synchronous Pipelined Burst SRAMs.
They are organized as 1,048,576 words by 36bits for K7Q323682M and 2,097,152 words by 18 bits for K7Q321882M.
The QDR operation is possible by supporting DDR read and write operations through separate data output and input ports
with the same cycle. Memory bandwidth is maxmized as data can be transfered into sram
on every rising edge of K and K, and transfered out of sram on every rising edge of C and C.
And totally independent read and write ports eliminate the need for high speed bus turn around.
Address, data inputs, and all control signals are synchronized to the input clock ( K or K ).
Normally data outputs are synchronized to output clocks ( C and C ), but when C and C are tied high,
the data outputs are synchronized to the input clocks ( K and K ).
Read address is registered on rising edges of the input K clocks, and write address is
registered on rising edges of the input K clocks.
Common address bus is used to access address both for read and write operations.
The internal burst counter is fiexd to 2-bit sequential for both read and write operations.
Synchronous pipeline read and early write enable high speed operations.
Simple depth expansion is accomplished by using R and W for port selection.
Byte write operation is supported with BW0 and BW1 ( BW2 and BW3 ) pins.
IEEE 1149.1 serial boundary scan (JTAG) simplifies monitoriing package pads attachment status with system.
The K7Q323682M and K7Q321882M are implemented with SAMSUNG's high performance 6T CMOS technology and is available
in 165pin FBGA packages. Multiple power and ground pins minimize ground bounce.
Read Operations
Read cycles are initiated by activating R at the rising edge of the positive input clock K.
Address is presented and stored in the read address register synchronized with K clock.
For 2-bit burst DDR operation, it will access two 36-bit or 18-bit data words with each read command.
The first pipelined data is transfered out of the device triggered by C clock following next K clock rising edge.
Next burst data is triggered by the rising edge of following C clock rising edge.
Continuous read operations are initiated with K clock rising edge.
And pipelined data are transferred out of device on every rising edge of both C and C clocks.
In case C and C tied to high, output data are triggered by K and K instead of C and C.
When the R is disabled after a read operation, the K7Q323682M and K7Q321882M will first complete burst read operation
before entering into deselect mode at the next K clock rising edge.
Then output drivers disabled automatically to high impedance state.
Oct 2002
Rev 0.3
- 5 -
K7Q323682M
K7Q321882M
Preliminary
1Mx36 & 2Mx18 QDRTM b2 SRAM
Write Operations
Write cycles are initiated by activating W at the rising edge of the positive input clock K.
Address is presented and stored in the write address register synchronized with following K clock.
For 2-bit burst DDR operation, it will write two 36-bit or 18-bit data words with each write command.
The first "early" data is transfered and registered in to the device synchronous with same K clock rising edge with W presented.
Next burst data is transfered and registered synchronous with following K clock rising edge.
Continuous write operations are initiated with K rising edge.
And "early writed" data is presented to the device on every rising edge of both K and K clocks.
When the W is disabled, the K7Q323682M and K7Q321882M will enter into deselect mode.
The device disregards input data presented on the same cycle W disabled.
The K7Q323682M and K7Q321882M support byte write operations.
With activating BW0 or BW1 ( BW2 or BW3 ) in write cycle, only one byte of input data is presented.
In K7Q321882M, BW0 controls write operation to D0:D8, BW1 controls write operation to D9:D17.
And in K7Q323682M BW2 controls write operation to D18:D26, BW3 controls write operation to D27:D35.
Programmable Impedance Output Buffer Operation
The designer can program the SRAM's output buffer impedance by terminating the ZQ pin to VSS through a precision resistor(RQ).
The value of RQ (within 15%) is five times the output impedance desired.
For example, 250W resistor will give an output impedance of 50W.
Impedance updates occur early in cycles that do not activate the outputs, such as deselect cycles.
In all cases impedance updates are transparent to the user and do not produce access time "push-outs"
or other anomalous behavior in the SRAM.
There are no power up requirements for the SRAM. However, to guarantee optimum output driver impedance after power up,
the SRAM needs 1024 non-read cycles.
Single Clock Mode
The K7Q323682M and K7Q321882M can be used with the single clock pair K and K.
In this mode, C and C must be tied high during power up and this single clock pair control both the input and output registers.
C and C cannot be tied high during operation.
System flight time and clock skew could not be compensated in single clock mode.
Depth Expansion
Separate input and output ports enables easy depth expansion.
Each port can be selected and deselected independently
and read and write operation do not affect each other.
Before chip deselected, all read and write pending operations are completed.
Oct 2002
Rev 0.3
- 6 -
K7Q323682M
K7Q321882M
Preliminary
1Mx36 & 2Mx18 QDRTM b2 SRAM
STATE DIAGRAM
POWER-UP
READ
WRITE
READ NOP
READ
WRITE NOP
WRITE
LOAD NEW
READ ADDRESS
LOAD NEW
WRITE ADDRESS
WRITE
READ
ALWAYS
(FIXED)
ALWAYS
(FIXED)
READ
WRITE
DDR WRITE
DDR READ
Notes: 1. Internal burst counter is fixed as 2-bit linear, i.e. when first address is A0+0, next internal burst address is A0+1.
2. "READ" refers to read active status with R=Low, "READ" refers to read inactive status with R=high. "WRITE" and "WRITE" are the same case.
3. Read and write state machine can be active simultaneously.
4. State machine control timing sequence is controlled by K.
Oct 2002
Rev 0.3
- 7 -
K7Q323682M
K7Q321882M
Preliminary
1Mx36 & 2Mx18 QDRTM b2 SRAM
TRUTH TABLES
SYNCHRONOUS TRUTH TABLE
D
Q
K
R
W
OPERATION
D(A0)
D(A1)
Q(A0)
Previous state
High-Z
Q(A1)
Previous state
High-Z
Stopped
X
H
L
X
H
X
L
Previous state
Previous state
Clock Stop
No Operation
Read
•
•
•
X
X
X
X
DOUT at C(t+1)
X
DOUT at C(t+1)
X
X
Din at K(t)
Din at K(t)
Write
Notes: 1. X means "Don¢t Care".
2. The rising edge of clock is symbolized by ( • ).
3. Before enter into clock stop status, all pending read and write operations will be completed.
WRITE TRUTH TABLE(x18)
K
K
W
H
H
L
BW0
X
BW1
X
OPERATION
READ/NOP
READ/NOP
•
•
X
X
•
•
•
•
L
L
WRITE ALL BYTEs ( K• )
WRITE ALL BYTEs ( K• )
WRITE BYTE 0 ( K• )
WRITE BYTE 0 ( K• )
WRITE BYTE 1 ( K• )
WRITE BYTE 1 ( K• )
WRITE NOTHING ( K• )
WRITE NOTHING ( K• )
•
L
L
L
L
L
H
H
L
•
L
L
L
H
H
H
H
•
L
L
L
H
H
•
L
Notes: 1. X means "Don¢t Care".
2. All inputs in this table must meet setup and hold time around the rising edge of CLK( • ).
WRITE TRUTH TABLE(x36)
K
K
W
H
H
L
L
L
L
L
L
L
L
L
L
BW0
X
BW1
X
BW2
X
BW3
X
OPERATION
READ/NOP
•
•
X
X
X
X
READ/NOP
•
•
•
•
•
L
L
L
L
WRITE ALL BYTEs ( K• )
WRITE ALL BYTEs ( K• )
WRITE BYTE 0 ( K• )
WRITE BYTE 0 ( K• )
WRITE BYTE 1 ( K• )
WRITE BYTE 1 ( K• )
WRITE BYTE 2 and BYTE 3 ( K• )
WRITE BYTE 2 and BYTE 3 ( K• )
WRITE NOTHING ( K• )
WRITE NOTHING ( K• )
•
L
L
L
L
L
H
H
L
H
H
H
H
L
H
H
H
H
L
•
L
H
H
H
H
H
H
•
L
H
H
H
H
•
L
L
H
H
H
H
•
Notes: 1. X means "Don¢t Care".
2. All inputs in this table must meet setup and hold time around the rising edge of CLK( • ).
Oct 2002
Rev 0.3
- 8 -
K7Q323682M
K7Q321882M
Preliminary
1Mx36 & 2Mx18 QDRTM b2 SRAM
ABSOLUTE MAXIMUM RATINGS*
PARAMETER
Voltage on VDD Supply Relative to VSS
Voltage on VDDQ Supply Relative to VSS
Voltage on Input Pin Relative to VSS
Power Dissipation
SYMBOL
VDD
RATING
-0.5 to 2.9
-0.5 to VDD
-0.5 to VDD+0.3
TBD
UNIT
V
VDDQ
VIN
V
V
PD
W
Storage Temperature
TSTG
TOPR
TBIAS
-65 to 150
0 to 70
°C
°C
°C
Operating Temperature
Storage Temperature Range Under Bias
-10 to 85
*Note: 1. Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating
only and functional operation of the device at these or any other conditions above those indicated in the operating sections of this specification
is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
2. VDDQ must not exceed VDD during normal operation.
DC ELECTRICAL CHARACTERISTICS(VDD=1.8V ±0.1V, TA=0°C to +70°C)
PARAMETER
Input Leakage Current
Output Leakage Current
SYMBOL
TEST CONDITIONS
VDD=Max ; VIN=VSS to VDDQ
Output Disabled,
MIN
MAX
+2
UNIT NOTES
IIL
-2
mA
mA
IOL
-2
+2
-20
-16
-13
-10
-20
-16
-13
-10
-20
-16
-13
-10
-
TBD
-
TBD
VDD=Max , IOUT=0mA
Operating Current (x18): DDR
Operating Current (x36): DDR
Standby Current(NOP): DDR
ICC
ICC
mA
mA
mA
1,5
1,5
1,6
Cycle Time ³ tKHKH Min
-
TBD
-
TBD
-
TBD
-
TBD
VDD=Max , IOUT=0mA
Cycle Time ³ tKHKH Min
-
TBD
-
TBD
-
TBD
Device deselected,
-
TBD
IOUT=0mA, f=Max,
ISB1
-
TBD
All Inputs£0.2V or ³ VDD-0.2V
-
TBD
Output High Voltage
Output Low Voltage
Output High Voltage
Output Low Voltage
Input Low Voltage
Input High Voltage
VOH1
VOL1
VOH2
VOL2
VIL
VDDQ/2-0.12
VDDQ/2-0.12
VDDQ-0.2
VSS
VDDQ/2+0.12
VDDQ/2+0.12
VDDQ
0.2
V
V
V
V
V
V
2,7
3,7
4
IOH=-1.0mA
IOL=1.0mA
4
-0.3
VREF-0.1
VDDQ+0.3
8,9
8,10
VIH
VREF+0.1
Notes: 1. Minimum cycle. IOUT=0mA.
2. |IOH|=(VDDQ/2)/(RQ/5)±15% @VOH=VDDQ/2 for 175W £ RQ £ 350W.
3. |IOL|=(VDDQ/2)/(RQ/5)±15% @VOL=VDDQ/2 for 175W £ RQ £ 350W.
4. Minimum Impedance Mode when ZQ pin is connected to VSS.
5. Operating current is calculated with 50% read cycles and 50% write cycles.
6. Standby Current is only after all pending read and write burst opeactions are completed.
7. Programmable Impedance Mode.
8. These are DC test criteria. DC design criteria is VREF±50mV. The AC VIH/VIL levels are defined separately for measuring
timing parameters.
9. VIL (Min)DC=-0.3V, VIL (Min)AC=-1.5V(pulse width £ 3ns).
10. VIH (Max)DC=VDDQ+0.3, VIH (Max)AC=VDDQ+0.85V(pulse width £ 3ns).
Oct 2002
Rev 0.3
- 9 -
K7Q323682M
K7Q321882M
Preliminary
1Mx36 & 2Mx18 QDRTM b2 SRAM
Overershoot Timing
Undershoot Timing
20% tKHKH(MIN)
VIH
VDDQ+0.5V
VDDQ
VSS
VSS-0.5V
20% tKHKH(MIN)
VIL
Note: For power-up, VIH £ VDDQ+0.3V and VDD £ 1.7V and VDDQ £ 1.4V for t £ 200ms
OPERATING CONDITIONS (0°C £ TA £ 70°C)
PARAMETER
SYMBOL
MIN
1.7
1.4
0.68
0
MAX
1.9
1.9
0.95
0
UNIT
VDD
V
V
V
V
Supply Voltage
VDDQ
VREF
Reference Voltage
Ground
VSS
AC TIMING CHARACTERISTICS(VDD=1.8V±0.1V, TA=0°C to +70°C)
-20
-16
-13
-10
PARAMETER
SYMBOL
UNITS NOTES
MIN MAX MIN MAX MIN MAX MIN MAX
Clock
Clock Cycle Time(K, K, C, C)
Clock HIGH time (K, K, C, C)
Clock LOW time (K, K, C, C)
Clock to clock (K• ® K• , C• ® C• )
Clock to data clock (K• ® C• , K• ® C• )
Output Times
tKHKH
tKHKL
tKLKH
tKHKH
tKHCH
5
6
7.5
3.0
3.0
3.4
0.0
10
3.5
3.5
4.6
0.0
ns
ns
ns
ns
ns
2.0
2.0
2.2
0.0
2.4
2.4
2.7
0.0
2.75
2.0
3.3
2.0
4.1
2.5
5.4
3.0
C, C High to Output Valid
C, C High to Output Hold
tCHQV
tCHQX
tCHQZ
tCHQX1
2.2
2.2
2.5
2.5
3.0
3.0
3.0
3.0
ns
ns
ns
ns
3
3
3
3
1.0
1.0
1.2
1.2
1.2
1.2
1.2
1.2
C High to Output High-Z
C High to Output Low-Z
Setup Times
Address valid to K rising edge
Control inputs valid to K rising edge
Data-in valid to K, K rising edge
Hold Times
tAVKH
tIVKH
0.6
0.6
0.6
0.7
0.7
0.7
0.8
0.8
0.8
1.0
1.0
1.0
ns
ns
ns
2
tDVKH
K rising edge to address hold
K rising edge to control inputs hold
K, K rising edge to data-in hold
tKHAX
tKHIX
0.6
0.6
0.6
0.7
0.7
0.7
0.8
0.8
0.8
1.0
1.0
1.0
v
ns
ns
tKHDX
Notes: 1. All address inputs must meet the specified setup and hold times for all latching clock edges.
2. Control signals are R, W, BW0, BW1 and (BW2, BW3, also for x36)
3. If C, C are tied high, K, K become the references for C, C timing parameters.
4. To avoid bus contention, at a given voltage and temperature tCHQX1 is bigger than tCHQZ.
The specs as shown do not imply bus contention beacuse tCHQX1 is a MIN parameter that is worst case at totally different test conditions
(0°C, 1.9V) than tCHQZ, which is a MAX parameter(worst case at 70°C, 1.7V)
It is not possible for two SRAMs on the same board to be at such different voltage and temperature.
Oct 2002
Rev 0.3
- 10 -
K7Q323682M
K7Q321882M
Preliminary
1Mx36 & 2Mx18 QDRTM b2 SRAM
AC TEST CONDITIONS
Parameter
Core Power Supply Voltage
Output Power Supply Voltage
Input High/Low Level
Symbol
VDD
Value
1.7~1.9
1.4~1.9
1.25/0.25
0.75
Unit
V
AC TEST OUTPUT LOAD
VDDQ
VIH/VIL
VREF
V
0.75V
VREF
VDDQ/2
50W
V
Input Reference Level
V
SRAM
Zo=50W
Input Rise/Fall Time
TR/TF
0.3/0.3
VDDQ/2
ns
V
Output Timing Reference Level
250W
ZQ
Note: Parameters are tested with RQ=250W
PIN CAPACITANCE
PRMETER
Address Control Input Capacitance
Input and Output Capacitance
Clock Capaucitance
SYMBOL
CIN
TESTCONDITION
TYP
MAX
Unit
pF
NOTES
VIN=0V
VOUT=0V
-
4
6
5
5
7
6
COUT
pF
CCLK
pF
Note: 1. Parameters are tested with RQ=250W and VDDQ=1.5V.
2. Periodically sampled and not 100% tested.
THERMAL RESISTANCE
PRMETER
Junction to Ambient
SYMBOL
TYP
TBD
TBD
TBD
Unit
°C/W
°C/W
°C/W
NOTES
qJA
qJC
qJB
Junction to Case
Junction to Pins
Note: Junction temperature is a function of on-chip power dissipation, package thermal impedance, mounting site temperature and mounting site
thermal impedance. TJ=TA + PD x qJA
APPLICATION INRORMATION
2Mx18
SRAM#1
SRAM#4
R=250W
R=250W
ZQ
ZQ
Vt
Q0-17
Q0-17
D0-17
SA
D0-17
SA
R W BW0 BW1 C C K K
RW BW0 BW1 C C K K
R
Data In
Data Out
Address
R
Vt
Vt
R
W
BW0-7
MEMORY
CONTROLLER
Return CLK
Vt
Vt
Source CLK
Return CLK
Source CLK
R=50W Vt=VREF
Oct 2002
Rev 0.3
- 11 -
K7Q323682M
K7Q321882M
Preliminary
1Mx36 & 2Mx18 QDRTM b2 SRAM
TIMING WAVE FORMS OF READ AND NOP
READ
READ
NOP
READ
tKHKH
tKLKH
K
tKHKL
tKHKH
K
tAVKH tKHAX
A1
A2
A3
SA
tIVKH tKHIX
R
tCHQX1
Q(Data Out)
C
Q1-1
Q1-2
Q2-1
Q2-2
Q3-1
Q3-2
tCHQX
tKHCH
tCHQZ
tCHQV
C
tCHQV
Don¢t Care
Undefined
Note: 1. Q1-1 refers to output from address A1+0, Q1-2 refers to output from address A1+1 i.e. the next internal burst address following A1+0.
2. Outputs are disabled(High-Z) one cycle after a NOP.
TIMING WAVE FORMS OF WRITE AND NOP
WRITE
WRITE
NOP
WRITE
NOP
tKHKH
tKLKH
K
tKHKL
tKHKH
K
tAVKH
tKHAX
A1
A2
A3
SA
tIVKH tKHIX
W
tKHIX
D(Data In)
D1-1
D1-2
D2-1
D2-2
D3-1
D3-2
tDVKH
tKHDX
Oct 2002
Rev 0.3
- 12 -
K7Q323682M
K7Q321882M
Preliminary
1Mx36 & 2Mx18 QDRTM b2 SRAM
TIMING WAVE FORMS OF READ, WRITE AND NOP
READ
WRITE READ
WRITE READ
WRITE
NOP
WRITE
K
K
A1
A2
A3
A4
A5
A6
A7
SA
W
R
D(Data In)
Q(Data Out)
D2-1
D2-2
D4-1
D4-2
D6-1
D6-2
D7-1
D7-2
Q1-1
Q1-2
Q3-1
Q3-2
Q5-1
Q5-2
C
C
Don¢t Care
Undefined
Note: 1. Q1-1 refers to output from address A1+0, Q1-2 refers to output from address A1+1 i.e. the next internal burst address following A1+0.
2. Outputs are disabled(High-Z) one cycle after a NOP.
3. If address A1=A2, data Q1-1=D2-1, data Q1-2=D2-2. Write data is forwarded immediately as read results.
4. BWx are assumed active.
Oct 2002
Rev 0.3
- 13 -
K7Q323682M
K7Q321882M
Preliminary
1Mx36 & 2Mx18 QDRTM b2 SRAM
IEEE 1149.1 TEST ACCESS PORT AND BOUNDARY SCAN-JTAG
This part contains an IEEE standard 1149.1 Compatible Test Access Port(TAP). The package pads are monitored by the Serial Scan
circuitry when in test mode. This is to support connectivity testing during manufacturing and system diagnostics. Internal data is not
driven out of the SRAM under JTAG control. In conformance with IEEE 1149.1, the SRAM contains a TAP controller, Instruction Reg-
ister, Bypass Register and ID register. The TAP controller has a standard 16-state machine that resets internally upon power-up,
therefore, TRST signal is not required. It is possible to use this device without utilizing the TAP. To disable the TAP controller without
interfacing with normal operation of the SRAM, TCK must be tied to VSS to preclude mid level input. TMS and TDI are designed so an
undriven input will produce a response identical to the application of a logic 1, and may be left unconnected. But they may also be
tied to VDD through a resistor. TDO should be left unconnected.
JTAG Block Diagram
JTAG Instruction Coding
IR2 IR1 IR0 Instruction
TDO Output
Notes
0
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
EXTEST
IDCODE
SAMPLE-Z
BYPASS
SAMPLE
Boundary Scan Register
Identification Register
Boundary Scan Register
Bypass Register
1
3
2
4
5
6
4
4
0
0
0
1
Boundary Scan Register
1
RESERVED Do Not Use
SRAM
CORE
1
1
BYPASS
BYPASS
Bypass Register
Bypass Register
NOTE :
1. Places DQs in Hi-Z in order to sample all input data regardless of other
SRAM inputs. This instruction is not IEEE 1149.1 compliant.
TDI
BYPASS Reg.
2. Places DQs in Hi-Z in order to sample all input data regardless of other
SRAM inputs.
TDO
Identification Reg.
Instruction Reg.
3. TDI is sampled as an input to the first ID register to allow for the serial shift
of the external TDI data.
4. Bypass register is initiated to VSS when BYPASS instruction is invoked. The
Bypass Register also holds serially loaded TDI when exiting the Shift DR
states.
Control Signals
TAP Controller
TMS
TCK
5. SAMPLE instruction dose not places DQs in Hi-Z.
6. This instruction is reserved for future use.
TAP Controller State Diagram
1
0
Test Logic Reset
0
1
1
0
1
Run Test Idle
Select DR
0
Select IR
0
1
1
1
1
Capture DR
0
Capture IR
0
0
Shift DR
1
Shift IR
1
Exit1 DR
0
Exit1 IR
0
0
0
0
0
Pause DR
1
Pause IR
1
Exit2 DR
1
Exit2 IR
1
1
0
Update DR
0
Update IR
1
Oct 2002
Rev 0.3
- 14 -
K7Q323682M
K7Q321882M
Preliminary
1Mx36 & 2Mx18 QDRTM b2 SRAM
SCAN REGISTER DEFINITION
Part
1Mx36
2Mx18
4Mx8
Instruction Register
Bypass Register
ID Register
32 bits
Boundary Scan
108 bits
3 bits
3 bits
3 bits
1 bit
1 bit
1 bit
32 bits
108 bits
32 bits
108 bits
ID REGISTER DEFINITION
Revision Number
Part Configuration
(28:12)
Samsung JEDEC Code
(11: 1)
Part
Start Bit(0)
(31:29)
1Mx36
2Mx18
000
00def0wx0t0q0b0s0
00def0wx0t0q0b0s0
00def0wx0t0q0b0s0
00001001110
00001001110
00001001110
1
1
1
000
4Mx8
000
Note : Part Configuration
/def=010 for 32Mb, /wx=11 for x36, 10 for x18, 01 for x8
/t=1 for DLL Ver., 0 for non-DLL Ver. /q=1 for DDR, 0 for DDR /b=1 for 4Bit Burst, 0 for 2Bit Burst /s=1 for Separate I/O, 0 for Common I/O
BOUNDARY SCAN EXIT ORDER
ORDER
PIN ID
ORDER
PIN ID
ORDER
73
PIN ID
2C
3E
2D
2E
1E
2F
1
6R
6P
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
10D
9E
74
2
75
3
6N
10C
11D
9C
9D
11B
11C
9B
76
4
7P
77
5
7N
78
6
7R
79
3F
7
8R
80
1G
1F
8
8P
81
9
9R
82
3G
2G
1H
1J
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
11P
10P
10N
9P
10B
11A
10A
9A
83
84
85
86
2J
10M
11N
9M
8B
87
3K
3J
7C
6C
8A
88
89
2K
1K
2L
9N
90
11L
11M
9L
7A
91
7B
92
3L
6B
93
1M
1L
10L
11K
10K
9J
6A
94
5B
95
3N
3M
1N
2M
3P
2N
2P
1P
3R
4R
4P
5P
5N
5R
5A
96
4A
97
9K
5C
4B
98
10J
11J
11H
10G
9G
99
3A
100
101
102
103
104
105
106
107
108
2A
1A
2B
11F
11G
9F
3B
1C
1B
10F
11E
10E
3D
3C
1D
Note: 1. NC pins are read as "X" ( i.e. don¢t care.)
Oct 2002
Rev 0.3
- 15 -
K7Q323682M
K7Q321882M
Preliminary
1Mx36 & 2Mx18 QDRTM b2 SRAM
JTAG DC OPERATING CONDITIONS
Parameter
Power Supply Voltage
Symbol
Min
1.7
Typ
Max
1.9
Unit
V
Note
VDD
VIH
1.8
Input High Level
1.3
-
-
-
-
VDD+0.3
0.5
V
Input Low Level
VIL
-0.3
1.4
V
Output High Voltage(IOH=-2mA)
Output Low Voltage(IOL=2mA)
VOH
VOL
VDD
V
VSS
0.4
V
Note: 1. The input level of SRAM pin is to follow the SRAM DC specification.
JTAG AC TEST CONDITIONS
Parameter
Input High/Low Level
Symbol
VIH/VIL
TR/TF
Min
1.3/0.5
1.0/1.0
0.9
Unit
V
Note
Input Rise/Fall Time
ns
V
Input and Output Timing Reference Level
Note: 1. See SRAM AC test output load on page 11.
1
JTAG AC Characteristics
Parameter
TCK Cycle Time
Symbol
Min
50
20
20
5
Max
Unit
Note
tCHCH
tCHCL
tCLCH
tMVCH
tCHMX
tDVCH
tCHDX
tSVCH
tCHSX
tCLQV
-
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
TCK High Pulse Width
TCK Low Pulse Width
TMS Input Setup Time
TMS Input Hold Time
TDI Input Setup Time
TDI Input Hold Time
-
-
5
-
5
-
5
-
SRAM Input Setup Time
SRAM Input Hold Time
Clock Low to Output Valid
5
-
5
-
0
10
JTAG TIMING DIAGRAM
TCK
tCHCH
tCLCH
tCHCL
tMVCH
tCHMX
TMS
TDI
tDVCH
tSVCH
tCHDX
tCHSX
PI
(SRAM)
tCLQV
TDO
Oct 2002
Rev 0.3
- 16 -
K7Q323682M
K7Q321882M
Preliminary
1Mx36 & 2Mx18 QDRTM b2 SRAM
165 FBGA PACKAGE DIMENSIONS
15mm x 17mm Body, 1.0mm Bump Pitch, 11x15 Ball Array
A
B
Top View
C
Side View
D
A
F
E
B
G
Bottom View
Æ H
E
Symbol
Value
17 ± 0.1
Units
mm
Note
Symbol
Value
1.0
Units
mm
Note
A
B
C
D
E
F
15 ± 0.1
mm
14.0
mm
1.3 ± 0.1
0.35 ± 0.05
mm
G
H
10.0
mm
mm
0.45 ± 0.05
mm
Oct 2002
Rev 0.3
- 17 -
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