K8D3216UTC-FC07 [SAMSUNG]
Flash, 2MX16, 70ns, PBGA48;型号: | K8D3216UTC-FC07 |
厂家: | SAMSUNG |
描述: | Flash, 2MX16, 70ns, PBGA48 |
文件: | 总44页 (文件大小:1251K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
K8D3x16UTC / K8D3x16UBC
NOR FLASH MEMORY
Document Title
32M Bit (4M x8/2M x16) Dual Bank NOR Flash Memory
Revision History
Revision No. History
Draft Date
Remark
0.0
1.0
1.1
Initial Draft
June 18, 2002
Preliminary
Final Specification
November 13, 2002
Not support 48TSOP1 Package
Not support 16M/16M BANK partition
November 18, 2003 Final
July 16, 2004
1.2
1.3
1.4
1.5
1.6
1.7
Support 48TSOP1 Package
Support 48TSOP1 Lead Free Package
Support 48FBGA Leaded/Lead Free Package
Complement status flag check algorithm
tCS timing is modified
September 16,
2004
March 16, 2005
June 2, 2005
August 25,2006
September 7, 2006
"Asynchronous mode may not support read following four sequential
invalid read condition within 200ns." is added
1
Revision 1.7
September, 2006
K8D3x16UTC / K8D3x16UBC
NOR FLASH MEMORY
32M Bit (4M x8/2M x16) Dual Bank NOR Flash Memory
FEATURES
• Single Voltage, 2.7V to 3.6V for Read and Write operations
• Organization
4,194,304 x 8 bit (Byte mode) / 2,097,152 x 16 bit (Word mode)
• Fast Read Access Time : 70ns
• Read While Program/Erase Operation
• Dual Bank architectures
GENERAL DESCRIPTION
The K8D3216U featuring single 3.0V power supply, is a 32Mbit
NOR-type Flash Memory organized as 4Mx8 or 2M x16. The
memory architecture of the device is designed to divide its
memory arrays into 71 blocks to be protected by the block
group. This block architecture provides highly flexible erase and
program capability. The K8D3216U NOR Flash consists of two
banks. This device is capable of reading data from one bank
while programming or erasing in the other bank. Access times
of 70ns, 80ns and 90ns are available for the device. The
device′s fast access times allow high speed microprocessors to
operate without wait states. The device performs a program
operation in units of 8 bits (Byte) or 16 bits (Word) and erases in
units of a block. Single or multiple blocks can be erased. The
block erase operation is completed within typically 0.7 sec. The
device requires 15mA as program/erase current in the standard
and industrial temperature ranges.
Bank 1 / Bank 2 : 8Mb / 24Mb
• Secode(Security Code) Block : Extra 64K Byte block
• Power Consumption (typical value @5MHz)
- Read Current : 14mA
- Program/Erase Current : 15mA
- Read While Program or Read While Erase Current : 25mA
- Standby Mode/Auto Sleep Mode : 5µA
• WP/ACC input pin
- Allows special protection of two outermost boot blocks at VIL,
regardless of block protect status
- Removes special protection of two outermost boot block at VIH,
the two blocks return to normal block protect status
- Program time at VHH : 9µs/word
• Erase Suspend/Resume
• Unlock Bypass Program
The K8D3216U NOR Flash Memory is created by using Sam-
sung's advanced CMOS process technology. This device is
available in 48 pin TSOP1 and 48 ball TBGA, FBGA packages.
The device is compatible with EPROM applications to require
high-density and cost-effective nonvolatile read/write storage
solutions.
• Hardware RESET Pin
• Command Register Operation
• Block Group Protection / Unprotection
• Supports Common Flash Memory Interface
• Industrial Temperature : -40°C to 85°C
• Endurance : 100,000 Program/Erase Cycles Minimum
• Data Retention : 10 years
• Package : 48 Pin TSOP1 : 12 x 20 mm / 0.5 mm Pin pitch
48 Ball TBGA : 6 x 8.5 mm / 0.8 mm Ball pitch
48 Ball FBGA : 6 x 8.5 mm / 0.8 mm Ball pitch
PIN DESCRIPTION
Pin Name
A0 - A20
Pin Function
Address Inputs
PIN CONFIGURATION
DQ0 - DQ14
Data Inputs / Outputs
DQ15 Data Input / Output
A-1 LSB Address
1
2
3
4
5
6
7
8
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
A16
BYTE
Vss
A15
A14
A13
A12
A11
A10
A9
DQ15/A-1
DQ15/A-1
DQ7
DQ14
DQ6
DQ13
DQ5
DQ12
DQ4
Vcc
DQ11
DQ3
DQ10
DQ2
DQ9
DQ1
DQ8
DQ0
OE
BYTE
CE
Word / Byte Selection
Chip Enable
A8
A19
A20
WE
RESET
N.C
WP/ACC
RY/BY
A18
A17
A7
9
48-pin TSOP1
Standard Type
12mm x 20mm
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
OE
Output Enable
RESET
RY/BY
WE
Hardware Reset Pin
Ready/Busy Output
Write Enable
A6
A5
A4
A3
A2
A1
Vss
CE
A0
Hardware Write Protection/Program
Acceleration
WP/ACC
Note :
Please refer to the package dimension.
Vcc
VSS
N.C
Power Supply
Ground
No Connection
SAMSUNG ELECTRONICS CO., LTD. reserves the right to change products and specifications without notice.
2
Revision 1.7
September, 2006
K8D3x16UTC / K8D3x16UBC
NOR FLASH MEMORY
48 Ball TBGA/FBGA TOP VIEW (BALL DOWN)
2
3
4
5
6
1
RY/BY
A
B
C
D
E
F
A3
A4
A2
A1
A7
A17
A6
WE
RESET
N.C
A9
A8
A13
A12
WP/
ACC
A18
A20
A10
A14
A5
A19
A11
A15
A0
CE
OE
VSS
DQ0
DQ8
DQ9
DQ1
DQ2
DQ10
DQ11
DQ3
DQ5
DQ12
VCC
DQ7
DQ14
DQ13
DQ6
A16
BYTE
DQ15/
A-1
G
H
DQ4
VSS
FUNCTIONAL BLOCK DIAGRAM
Bank1
Address
Bank1
Cell Array
X
Vcc
Dec
Vss
Latch &
Control
Y Dec
CE
Bank1 Data-In/Out
OE
WE
I/O
Interface
&
Bank2 Data-In/Out
Latch &
Control
BYTE
Y Dec
Bank
RESET
RY/BY
WP/ACC
Control
Bank2
Address
Bank2
Cell Array
X
Dec
A0~A20
DQ15/A-1
Erase
Control
DQ0~DQ14
High
Voltage
Gen.
Program
Control
3
Revision 1.7
September, 2006
K8D3x16UTC / K8D3x16UBC
NOR FLASH MEMORY
ORDERING INFORMATION
K 8 D 3x 1 6 U T C - T I 0 7
Access Time
07 = 70 ns
08 = 80 ns
09 = 90 ns
Samsung
NOR Flash Memory
Device Type
Dual Bank Boot Block
Operating Temperature Range
C = Commercial Temp. (0 °C to 70 °C)
I = Industrial Temp. (-40 °C to 85 °C)
Package
P=48TSOP1(Lead-Free) Y=48TSOP1
Bank Division
32 = 8Mbits + 24Mbits
D : FBGA(Lead Free)
L : TBGA(Lead Free)
F : FBGA
T : TBGA
Organization
x8/x16 Selectable
Version
C = 4th Generation
Block Architecture
T = Top Boot Block
B = Bottom Boot Block
Operating Voltage Range
2.7V to 3.6V
Table 1. PRODUCT LINE-UP
Part No.
- 7
-8
-9
Vcc
2.7V~3.6V
80ns
Max. Address Access Time (ns)
Max. CE Access Time (ns)
Max. OE Access Time (ns)
70ns
70ns
25ns
90ns
80ns
90ns
35ns
25ns
Table 2. K8D3216U DEVICE BANK DIVISIONS
Device
Part Number
Bank 1
Block Sizes
Bank 2
Mbit
Mbit
Block Sizes
Forty-eight
64 Kbyte/32 Kword
Eight 8 Kbyte/4 Kword,
fifteen 64 Kbyte/32 Kword
K8D3216U
8 Mbit
24 Mbit
4
Revision 1.7
September, 2006
K8D3x16UTC / K8D3x16UBC
NOR FLASH MEMORY
Table 3. Top Boot Block Address (K8D3216UT)
Block Address
Address Range
Block Size
(KB/KW)
K8D3216UT
Block
A20 A19 A18 A17 A16 A15 A14 A13 A12
Byte Mode
Word Mode
BA70
BA69
BA68
BA67
BA66
BA65
BA64
BA63
BA62
BA61
BA60
BA59
BA58
BA57
BA56
BA55
BA54
BA53
BA52
BA51
BA50
BA49
BA48
BA47
BA46
BA45
BA44
BA43
BA42
BA41
BA40
BA39
BA38
BA37
BA36
BA35
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
1
1
1
1
1
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
1
1
1
1
1
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
1
1
1
1
1
0
8/4
3FE000H-3FFFFFH
3FC000H-3FDFFFH
3FA000H-3FBFFFH
3F8000H-3F9FFFH
3F6000H-3F7FFFH
3F4000H-3F5FFFH
3F2000H-3F3FFFH
3F0000H-3F1FFFH
3E0000H-3EFFFFH
3D0000H-3DFFFFH
3C0000H-3CFFFFH
3B0000H-3BFFFFH
3A0000H-3AFFFFH
390000H-39FFFFH
380000H-38FFFFH
370000H-37FFFFH
360000H-36FFFFH
350000H-35FFFFH
340000H-34FFFFH
330000H-33FFFFH
320000H-32FFFFH
310000H-31FFFFH
300000H-30FFFFH
2F0000H-2FFFFFH
2E0000H-2EFFFFH
2D0000H-2DFFFFH
2C0000H-2CFFFFH
2B0000H-2BFFFFH
2A0000H-2AFFFFH
290000H-29FFFFH
280000H-28FFFFH
270000H-27FFFFH
260000H-26FFFFH
250000H-25FFFFH
240000H-24FFFFH
230000H-23FFFFH
1FF000H-1FFFFFH
1FE000H-1FEFFFH
1FD000H-1FDFFFH
1FC000H-1FCFFFH
1FB000H-1FBFFFH
1FA000H-1FAFFFH
1F9000H-1F9FFFH
1F8000H-1F8FFFH
1F0000H-1F7FFFH
1E8000H-1EFFFFH
1E0000H-1E7FFFH
1D8000H-1DFFFFH
1D0000H-1D7FFFH
1C8000H-1CFFFFH
1C0000H-1C7FFFH
1B8000H-1BFFFFH
1B0000H-1B7FFFH
1A8000H-1AFFFFH
1A0000H-1A7FFFH
198000H-19FFFFH
190000H-197FFFH
188000H-18FFFFH
180000H-187FFFH
178000H-17FFFFH
170000H-177FFFH
168000H-16FFFFH
160000H-167FFFH
158000H-15FFFFH
150000H-157FFFH
148000H-14FFFFH
140000H-147FFFH
138000H-13FFFFH
130000H-137FFFH
128000H-12FFFFH
120000H-127FFFH
118000H-11FFFFH
8/4
1
0
1
8/4
1
0
0
8/4
0
1
1
8/4
0
1
0
8/4
0
0
1
8/4
0
0
0
8/4
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
Bank1
Bank2
5
Revision 1.7
September, 2006
K8D3x16UTC / K8D3x16UBC
NOR FLASH MEMORY
Table 3. Top Boot Block Address (K8D3216UT)
Block Address
Address Range
Block Size
(KB/KW)
K8D3216UT
Block
A20 A19 A18 A17 A16 A15 A14 A13 A12
Byte Mode
Word Mode
BA34
BA33
BA32
BA31
BA30
BA29
BA28
BA27
BA26
BA25
BA24
BA23
BA22
BA21
BA20
BA19
BA18
BA17
BA16
BA15
BA14
BA13
BA12
BA11
BA10
BA9
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
220000H-22FFFFH
210000H-21FFFFH
200000H-20FFFFH
1F0000H-1FFFFFH
1E0000H-1EFFFFH
1D0000H-1DFFFFH
1C0000H-1CFFFFH
1B0000H-1BFFFFH
1A0000H-1AFFFFH
190000H-19FFFFH
180000H-18FFFFH
170000H-17FFFFH
160000H-16FFFFH
150000H-15FFFFH
140000H-14FFFFH
130000H-13FFFFH
120000H-12FFFFH
110000H-11FFFFH
100000H-10FFFFH
0F0000H-0FFFFFH
0E0000H-0EFFFFH
0D0000H-0DFFFFH
0C0000H-0CFFFFH
0B0000H-0BFFFFH
0A0000H-0AFFFFH
090000H-09FFFFH
080000H-08FFFFH
070000H-07FFFFH
060000H-06FFFFH
050000H-05FFFFH
040000H-04FFFFH
030000H-03FFFFH
020000H-02FFFFH
010000H-01FFFFH
000000H-00FFFFH
110000H-117FFFH
108000H-10FFFFH
100000H-107FFFH
0F8000H-0FFFFFH
0F0000H-0F7FFFH
0E8000H-0EFFFFH
0E0000H-0E7FFFH
0D8000H-0DFFFFH
0D0000H-0D7FFFH
0C8000H-0CFFFFH
0C0000H-0C7FFFH
0B8000H-0BFFFFH
0B0000H-0B7FFFH
0A8000H-0AFFFFH
0A0000H-0A7FFFH
098000H-09FFFFH
090000H-097FFFH
088000H-08FFFFH
080000H-087FFFH
078000H-07FFFFH
070000H-077FFFH
068000H-06FFFFH
060000H-067FFFH
058000H-05FFFFH
050000H-057FFFH
048000H-04FFFFH
040000H-047FFFH
038000H-03FFFFH
030000H-037FFFH
028000H-02FFFFH
020000H-027FFFH
018000H-01FFFFH
010000H-017FFFH
008000H-00FFFFH
000000H-007FFFH
Bank2
BA8
BA7
BA6
BA5
BA4
BA3
BA2
BA1
BA0
Note : The address range is A20 ∼ A-1 in the byte mode ( BYTE = VIL ) or A20 ∼ A0 in the word mode ( BYTE = VIH ).
The bank address bits is A20 ∼ A19 for K8D3216UT.
Table 4. Secode Block Addresses for Top Boot Devices
Block Address
A20-A12
Block
Size
(X8)
Address Range
(X16)
Address Range
Device
K8D3216UT
111111xxx
64/32
3F0000H-3FFFFFH
1F8000H-1FFFFFH
6
Revision 1.7
September, 2006
K8D3x16UTC / K8D3x16UBC
NOR FLASH MEMORY
Table 5. Bottom Boot Block Address (K8D3216UB)
Block Address
Address Range
Block Size
(KB/KW)
K8D3216UB
Block
A20 A19 A18 A17 A16 A15 A14 A13 A12
Byte Mode
Word Mode
BA70
BA69
BA68
BA67
BA66
BA65
BA64
BA63
BA62
BA61
BA60
BA59
BA58
BA57
BA56
BA55
BA54
BA53
BA52
BA51
BA50
BA49
BA48
BA47
BA46
BA45
BA44
BA43
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
3F0000H-3FFFFFH
3E0000H-3EFFFFH
3D0000H-3DFFFFH
3C0000H-3CFFFFH
3B0000H-3BFFFFH
3A0000H-3AFFFFH
390000H-39FFFFH
380000H-38FFFFH
370000H-37FFFFH
360000H-36FFFFH
350000H-35FFFFH
340000H-34FFFFH
330000H-33FFFFH
320000H-32FFFFH
310000H-31FFFFH
300000H-30FFFFH
2F0000H-2F1FFFH
2E0000H-2EFFFFH
2D0000H-2DFFFFH
2C0000H-2CFFFFH
2B0000H-2BFFFFH
2A0000H-2AFFFFH
290000H-29FFFFH
280000H-28FFFFH
270000H-27FFFFH
260000H-26FFFFH
250000H-25FFFFH
240000H-24FFFFH
1F8000H-1FFFFFH
1F0000H-1F7FFFH
1E8000H-1EFFFFH
1E0000H-1E7FFFH
1D8000H-1DFFFFH
1D0000H-1D7FFFH
1C8000H-1CFFFFH
1C0000H-1C7FFFH
1B8000H-1BFFFFH
1B0000H-1B7FFFH
1A8000H-1AFFFFH
1A0000H-1A7FFFH
198000H-19FFFFH
190000H-197FFFH
188000H-18FFFFH
180000H-187FFFH
178000H-17FFFFH
170000H-177FFFH
168000H-16FFFFH
160000H-167FFFH
158000H-15FFFFH
150000H-157FFFH
148000H-14FFFFH
140000H-147FFFH
138000H-13FFFFH
130000H-137FFFH
128000H-12FFFFH
120000H-127FFFH
Bank2
BA42
BA41
BA40
BA39
BA38
BA37
1
1
1
1
0
0
0
0
0
0
1
1
0
0
0
0
1
1
0
0
0
0
1
1
1
1
0
0
1
1
1
0
1
0
1
0
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
230000H-23FFFFH
220000H-22FFFFH
210000H-21FFFFH
200000H-20FFFFH
1F0000H-1FFFFFH
1E0000H-1EFFFFH
118000H-11FFFFH
110000H-117FFFH
108000H-10FFFFH
100000H-107FFFH
0F8000H-0FFFFFH
0F0000H-0F7FFFH
64/32
64/32
64/32
64/32
64/32
64/32
64/32
BA36
BA35
0
0
1
1
1
1
1
1
0
0
1
0
X
X
X
X
X
X
1D0000H-1DFFFFH
1C0000H-1CFFFFH
0E8000H-0EFFFFH
0E0000H-0E7FFFH
7
Revision 1.7
September, 2006
K8D3x16UTC / K8D3x16UBC
NOR FLASH MEMORY
Table 5. Bottom Block Address (K8D3216UB)
Block Address
Address Range
Block Size
(KB/KW)
K8D3216UB
Block
A20 A19 A18 A17 A16 A15 A14 A13 A12
Byte Mode
Word Mode
BA34
BA33
BA32
BA31
BA30
BA29
BA28
BA27
BA26
BA25
BA24
BA23
BA22
BA21
BA20
BA19
BA18
BA17
BA16
BA15
BA14
BA13
BA12
BA11
BA10
BA9
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
0
0
0
0
0
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
0
0
0
0
0
0
0
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
1
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
1
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
1
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
8/4
1B0000H-1BFFFFH
1A0000H-1AFFFFH
190000H-19FFFFH
180000H-18FFFFH
170000H-17FFFFH
160000H-16FFFFH
150000H-15FFFFH
140000H-14FFFFH
130000H-13FFFFH
120000H-12FFFFH
110000H-11FFFFH
100000H-10FFFFH
0F0000H-0FFFFFH
0E0000H-0EFFFFH
0D0000H-0DFFFFH
0C0000H-0CFFFFH
0B0000H-0BFFFFH
0A0000H-0AFFFFH
090000H-09FFFFH
080000H-08FFFFH
070000H-07FFFFH
060000H-06FFFFH
050000H-05FFFFH
040000H-04FFFFH
030000H-03FFFFH
020000H-02FFFFH
010000H-01FFFFH
00E000H-00FFFFH
00C000H-00DFFFH
00A000H-00BFFFH
008000H-009FFFH
006000H-007FFFH
004000H-005FFFH
002000H-003FFFH
000000H-001FFFH
0D8000H-0DFFFFH
0D0000H-0D7FFFH
0C8000H-0CFFFFH
0C0000H-0C7FFFH
0B8000H-0BFFFFH
0B0000H-0B7FFFH
0A8000H-0AFFFFH
0A0000H-0A7FFFH
098000H-09FFFFH
090000H-097FFFH
088000H-08FFFFH
080000H-087FFFH
078000H-07FFFFH
070000H-077FFFH
068000H-06FFFFH
060000H-067FFFH
058000H-05FFFFH
050000H-057FFFH
048000H-04FFFFH
040000H-047FFFH
038000H-03FFFFH
030000H-037FFFH
028000H-02FFFFH
020000H-027FFFH
018000H-01FFFFH
010000H-017FFFH
008000H-00FFFFH
007000H-007FFFH
006000H-006FFFH
005000H-005FFFH
004000H-004FFFH
003000H-003FFFH
002000H-002FFFH
001000H-001FFFH
000000H-000FFFH
Bank2
Bank1
BA8
BA7
BA6
1
1
0
8/4
BA5
1
0
1
8/4
BA4
1
0
0
8/4
BA3
0
1
1
8/4
BA2
0
1
0
8/4
BA1
0
0
1
8/4
BA0
0
0
0
8/4
Note : The address range is A20 ∼ A-1 in the byte mode ( BYTE = VIL ) or A20 ∼ A0 in the word mode ( BYTE = VIH ).
The bank address bits is A20 ∼ A19 for K8D3216UB.
Table 6. Secode Block Addresses for Bottom Boot Devices
Block Address
A20-A12
Block
Size
(X8)
Address Range
(X16)
Address Range
Device
K8D3216UB
000000xxx
64/32
000000H-00FFFFH
000000H-007FFFH
8
Revision 1.7
September, 2006
K8D3x16UTC / K8D3x16UBC
NOR FLASH MEMORY
PRODUCT INTRODUCTION
The K8D3216U is a 32Mbit (33,554,432 bits) NOR-type Flash memory. The device features single voltage power supply operating
within the range of 2.7V to 3.6V. The device is programmed by using the Channel Hot Electron (CHE) injection mechanism which is
used to program EPROMs. The device is erased electrically by using Fowler-Nordheim tunneling mechanism. To provide highly flex-
ible erase and program capability, the device adapts a block memory architecture that divides its memory array into 71 blocks (64-
Kbyte x 63 , 8-Kbyte x 8). Programming is done in units of 8 bits (Byte) or 16 bits (Word). All bits of data in one or multiple blocks can
be erased simultaneously when the device executes the erase operation. To prevent the device from accidental erasing or over-writ-
ing the programmed data, 71 memory blocks can be hardware protected by the block group. Byte/Word modes are available for read
operation. These modes can be selected via BYTE pin. The device provides read access times of 70ns, 80ns and 90ns supporting
high speed microprocessors to operate without any wait states.
The command set of K8D3216U is fully compatible with standard Flash devices. The device is controlled by chip enable (CE), output
enable (OE) and write enable (WE). Device operations are executed by selective command codes. The command codes to be com-
bined wih addresses and data are sequentially written to the command registers using microprocessor write timing. The command
codes serve as inputs to an internal state machine which controls the program/erase circuitry. Register contents also internally latch
addresses and data necessary to execute the program and erase operations. The K8D3216U is implemented with Internal Program/
Erase Algorithms to execute the program/erase operations. The Internal Program/Erase Algorithms are invoked by program/erase
command sequences. The Internal Program Algorithm automatically programs and verifies data at specified addresses. The Internal
Erase Algorithm automatically pre-programs the memory cell which is not programmed and then executes the erase operation. The
K8D3216U has means to indicate the status of completion of program/erase operations. The status can be indicated via the RY/BY
pin, Data polling of DQ7, or the Toggle bit (DQ6). Once the operations have been completed, the device automatically resets itself to
the read mode. The device requires only 14 mA as active read current and 15 mA for program/erase operations.
Table 7. Operations Table
WP/
ACC
DQ15/
A-1
DQ8/
DQ14
DQ0/
DQ7
Operation
CE
OE
WE
BYTE
A9
A6
A1
A0
RESET
word
byte
L
L
L
L
H
H
H
L
A9
A9
A6
A6
A1
A1
A0
A0
DQ15
A-1
DOUT
DOUT
DOUT
H
H
Read
L/H
(2)
High-Z
Vcc ±
0.3V
Stand-by
X
X
X
X
X
X
X
High-Z
High-Z
High-Z
(2)
Output Disable
Reset
L
X
L
L
H
X
H
H
H
X
L
X
X
H
L
L/H
L/H
X
X
X
X
X
X
X
X
High-Z
High-Z
DIN
High-Z
High-Z
DIN
High-Z
High-Z
DIN
H
L
word
byte
A9
A9
A6
A6
A1
A1
A0
A0
H
H
Write
(4)
L
A-1
High-Z
DIN
Enable Block Group
Protect (3)
L
L
H
H
X
L
L
X
X
X
X
L/H
(4)
(4)
X
X
X
L
H
X
H
H
X
L
L
X
X
X
X
X
X
X
DIN
DIN
X
VID
VID
VID
Enable Block Group
Unprotect (3)
Temporary Block
Group
X
Auto Select
Manufacturer ID (5)
Code(See
Table 9)
L
L
L
L
H
H
X
X
L/H
L/H
VID
VID
L
L
L
L
L
X
X
X
X
H
H
Auto Select
Device Code (5)
Code(See
Table 9)
H
Notes :
1. L = VIL (Low), H = VIH (High), VID = 8.5V~12.5V, DIN = Data in, DOUT = Data out, X = Don't care.
2. WP/ACC and RESET pin are asserted at Vcc±0.3 V or Vss±0.3 V in the Stand-by mode.
3. Addresses must be composed of the Block address (A12 - A20).
The Block Protect and Unprotect operations may be implemented via programming equipment too.
Refer to the "Block Group Protection and Unprotection".
4. If WP/ACC=VIL, the two outermost boot blocks is protected. If WP/ACC=VIH, the two outermost boot block protection depends on whether those
blocks were last protected or unprotected using the method described in "Block Group Protection and Unprotection". If WP/ACC=VHH, all blocks
will be temporarily unprotected.
5. Manufacturer and device codes may also be accessed via a command register write sequence. Refer to Table 9.
9
Revision 1.7
September, 2006
K8D3x16UTC / K8D3x16UBC
NOR FLASH MEMORY
COMMAND DEFINITIONS
The K8D3216U operates by selecting and executing its operational modes. Each operational mode has its own command set. In
order to select a certain mode, a proper command with specific address and data sequences must be written into the command reg-
ister. Writing incorrect information which include address and data or writing an improper command will reset the device to the read
mode. The defined valid register command sequences are stated in Table 8. Note that Erase Suspend (B0H) and Erase Resume
(30H) commands are valid only while the Block Erase Operation is in progress.
Table 8. Command Sequences
1st Cycle
Word Byte
2nd Cycle
3rd Cycle
4th Cycle
5th Cycle
6th Cycle
Command Sequence
Cycle
Word
Byte
Word
Byte
Word
Byte
Word
Byte
Word
Byte
Addr
RA
RD
Read
Data
1
1
Addr
XXXH
F0H
Reset
Data
DA/
555H
DA/
AAAH
DA/
X00H
DA/
X00H
Autoselect
Manufacturer
ID (2,3)
Addr
Data
Addr
Data
Addr
Data
Addr
555H
AAH
AAAH
AAH
AAAH
AAH
AAAH
AAAH
2AAH
55H
2AAH
55H
2AAH
55H
2AAH
555H
555H
555H
4
4
4
90H
ECH
DA/
555H
DA/
AAAH
DA/
X01H
DA/
X02H
Autoselect
Device Code
(2,3)
555H
555H
90H
(See Table 9)
Autoselect
Block Group
Protect Verify
(2,3)
DA/
555H
DA/
AAAH
BA /
X02H
BA/
X04H
(See Table 9)
90H
Auto Select
DA/
555H
DA/
AAAH
DA /
X03H
DA/
X06H
555H
555H
Secode Block
Factory Protect
Verify (2,3)
4
(See Table 9)
Data
Addr
Data
Addr
Data
Addr
Data
Addr
Data
Addr
Data
Addr
Data
Addr
Data
Addr
Data
Addr
Data
Addr
Data
Addr
Data
AAH
AAAH
AAH
AAAH
AAH
AAAH
AAH
AAAH
AAH
55H
2AAH
55H
2AAH
55H
2AAH
55H
2AAH
55H
90H
AAAH
88H
AAAH
90H
AAAH
A0H
AAAH
20H
555H
555H
555H
555H
555H
555H
555H
555H
555H
555H
555H
555H
Enter Secode
Block Region
3
4
4
3
2
XXXH
00H
PA
Exit Secode
Block Region
Program
PD
Unlock Bypass
XXXH
PA
Unlock Bypass
Program
A0H
PD
XXXH
XXXH
00H
Unlock Bypass
Reset
2
6
6
1
90H
555H
AAH
555H AAAH
AAH
AAAH
2AAH
55H
2AAH 555H
55H
555H
555H
555H
AAAH
80H
AAAH
80H
555H
AAAH
AAH
AAAH
AAH
2AAH
55H
2AAH
55H
555H
555H
555H
AAAH
Chip Erase
Block Erase
10H
555H
BA
30H
XXXH
Block Erase
Suspend (4, 5)
B0H
XXXH
Block Erase
Resume
1
1
30H
55H
AAH
CFI Query (6)
98H
10
Revision 1.7
September, 2006
K8D3x16UTC / K8D3x16UBC
NOR FLASH MEMORY
Notes : 1. RA : Read Address, PA : Program Address, RD : Read Data, PD : Program Data
DA : Dual Bank Address (A19 - A20), BA : Block Address (A12 - A20), X = Don’t care .
2. To terminate the Autoselect Mode, it is necessary to write Reset command to the register.
3. The 4th cycle data of Autoselect mode is output data.
The 3rd and 4th cycle bank addresses of Autoselect mode must be same.
4. The Read / Program operations at non-erasing blocks and the autoselect mode are allowed in the Erase Suspend mode.
5. The Erase Suspend command is applicable only to the Block Erase operation.
6. Command is valid when the device is in read mode or Autoselect mode.
7. DQ8 - DQ15 are don’t care in command sequence, but RD and PD is excluded.
8. A11 - A20 are also don’t care, except for the case of special notice.
Table 9. K8D3216U Autoselect Codes, (High Voltage Method)
DQ8 to DQ15
A20 A11
to to
A12 A10
A8
to
A7
A5
to
A2
DQ7
to
DQ0
Description
CE
OE
WE
A9
A6
A1 A0
BYTE
=VIH
BYTE
=VIL
Manufacturer ID
L
L
L
L
H
H
DA
DA
X
X
VID
VID
X
X
L
L
X
X
L
L
L
X
X
X
ECH
A0H
Device Code K8D3216UT
(Top Boot Block)
H
22H
Device Code K8D3216UB
(Bottom Boot Block)
L
L
L
L
L
L
H
H
H
DA
BA
DA
X
X
X
VID
VID
VID
X
X
X
L
L
L
X
X
X
L
H
H
H
L
22H
X
X
X
X
A2H
Block Protection
Verification
01H (Protected),
00H (Unprotected)
80H (Factory locked),
00H (Not factory locked)
Secode Block (2)
Indicator Bit (DQ7)
H
X
Notes : 1. L=Logic Low=VIL, H=Logic High=VIH, DA=Dual Bank Address, BA=Block Address, X=Don’t care.
2. Secode Block : Security Code Block.
11
Revision 1.7
September, 2006
K8D3x16UTC / K8D3x16UBC
NOR FLASH MEMORY
DEVICE OPERATION
Byte/Word Mode
If the BYTE pin is set at logical "1" , the device is in word mode, DQ0-DQ15 are active. Otherwise the BYTE pin is set at logical "0" ,
the device is in byte mode, DQ0-DQ7 are active. DQ8-DQ14 are in the High-Z state and DQ15 pin is used as an input for the LSB
(A-1) address pin.
Read Mode
The K8D3216U is controlled by Chip Enable (CE), Output Enable (OE) and Write Enable (WE). When CE and OE are low and WE
is high, the data stored at the specified address location,will be the output of the device. The outputs are in high impedance state
whenever CE or OE is high.
Standby Mode
The K8D3216U features Stand-by Mode to reduce power consumption. This mode puts the device on hold when the device is dese-
lected by making CE high (CE = VIH). Refer to the DC characteristics for more details on stand-by modes.
Output Disable
The device outputs are disabled when OE is High (OE = VIH). The output pins are in high impedance state.
Automatic Sleep Mode
K8D3216U features Automatic Sleep Mode to minimize the device power consumption. Since the device typically draws 5µA of the
current in Automatic Sleep Mode, this feature plays an extremely important role in battery-powered applications. When addresses
remain steady for tAA+50ns, the device automatically activates the Automatic Sleep Mode. In the sleep mode, output data is latched
and always available to the system. When addresses are changed, the device provides new data without wait time.
tAA + 50ns
Address
Outputs
Data
Data
Data
Data
Data
Data
Auto Sleep Mode
Figure 1. Auto Sleep Mode Operation
Autoselect Mode
The K8D3216U offers the Autoselect Mode to identify manufacturer and device type by reading a binary code. The Autoselect Mode
allows programming equipment to automatically match the device to be programmed with its corresponding programming algorithm.
In addition, this mode allows the verification of the status of write protected blocks. This mode is used by two method. The one is high
voltage method to be required VID (8.5V~12.5V) on address pin A9. When A9 is held at VID and the bank address or block address is
asserted, the device outputs the valid data via DQ pins(see Table 9 and Figure 2). The rest of addresses except A0, A1 and A6 are
Don′t Care. The other is autoselect command method that the autoselect code is accessible by the commamd sequence without VID.
The manufacturer and device code may also be read via the command register. The Command Sequence is shown in Table 8 and
Figure 3. The autoselect operation of block protect verification is initiated by first writing two unlock cycle. The third cycle must con-
tain the bank address and autoselect command (90H). If Block address while (A6, A1, A0) = (0,1,0) is finally asserted on the address
pin, it will produce a logical "1" at the device output DQ0 to indicate a write protected block or a logical "0" at the device output DQ0
to indicate a write unprotected block. To terminate the autoselect operation, write Reset command (F0H) into the command register.
12
Revision 1.7
September, 2006
K8D3x16UTC / K8D3x16UBC
NOR FLASH MEMORY
VID
V = VIH or VIL
A9
01H
00H
A6,A1,A0*
DQ15-DQ0
22A0H
ECH
or
22A2H
Manufacturer
Code
Device Code
(K8D3216U)
Return to
Read Mode
Note : The addresses other than A0 , A1 and A6 are Don′t care. Please refer to Table 9 for device code.
Figure 2. Autoselect Operation ( by high voltage method )
WE
A20∼A0(x16)/*
A20∼A-1(x8)
2AAH/
555H
00H/
00H
01H/
02H
555H/
AAAH
555H/
AAAH
22A0H
or
ECH
DQ15∼DQ0
55H
90H
AAH
F0H
22A2H
Manufacturer
Code
Device Code
(K8D3216U)
Return to
Read Mode
Note : The 3rd Cycle and 4th Cycle address must include the same bank address. Please refer to Table 9 for device code.
Figure 3. Autoselect Operation ( by command sequence method )
Write (Program/Erase) Mode
The K8D3216U executes its program/erase operations by writing commands into the command register. In order to write the com-
mands to the register, CE and WE must be low and OE must be high. Addresses are latched on the falling edge of CE or WE (which-
ever occurs last) and the data are latched on the rising edge of CE or WE (whichever occurs first). The device uses standard
microprocessor write timing.
Program
The K8D3216U can be programmed in units of a word or a byte. Programming is writing 0's into the memory array by executing the
Internal Program Routine. In order to perform the Internal Program Routine, a four-cycle command sequence is necessary. The first
two cycles are unlock cycles. The third cycle is assigned for the program setup command. In the last cycle, the address of the mem-
ory location and the data to be programmed at that location are written. The device automatically generates adequate program
pulses and verifies the programmed cell margin by the Internal Program Routine. During the execution of the Routine, the system is
not required to provide further controls or timings.
During the Internal Program Routine, commands written to the device will be ignored. Note that a hardware reset during a program
operation will cause data corruption at the corresponding location.
WE
A20∼A0(x16)/
555H/
AAAH
2AAH/
555H
555H/
AAAH
Program
Address
A20∼A-1(x8)
DQ15-DQ0
RY/BY
Program
Data
A0H
55H
AAH
Program
Start
Figure 4. Program Command Sequence
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Unlock Bypass
The K8D3216U provides the unlock bypass mode to save its program time for program operation. The mode is invoked by the unlock
bypass command sequence. Then, the unlock bypass program command sequence is required to program the device.
Unlike the standard program command sequence that contains four bus cycles, the unlock bypass program command sequence
comprises only two bus cycles.
The unlock bypass mode is engaged by issuing the unlock bypass command sequence which is comprised of three bus cycles. Writ-
ing first two unlock cycles is followed by a third cycle containing the unlock bypass command (20H). Once the device is in the unlock
bypass mode, the unlock bypass program command sequence is necessary to program in this mode. The unlock bypass program
command sequence is comprised of only two bus cycles; writing the unlock bypass program command (A0H) is followed by the pro-
gram address and data. This command sequence is the only valid one for programming the device in the unlock bypass mode.
The unlock bypass reset command sequence is the only valid command sequence to exit the unlock bypass mode. The unlock
bypass reset command sequence consists of two bus cycles. The first cycle must contain the data (90H). The second cycle contains
only the data (00H). Then, the device returns to the read mode.
Chip Erase
To erase a chip is to write 1′s into the entire memory array by executing the Internal Erase Routine. The Chip Erase requires six bus
cycles to write the command sequence. The erase set-up command is written after first two "unlock" cycles. Then, there are two
more write cycles prior to writing the chip erase command. The Internal Erase Routine automatically pre-programs and verifies the
entire memory for an all zero data pattern prior to erasing. The automatic erase begins on the rising edge of the last WE or CE pulse
in the command sequence and terminates when DQ7 is "1". After that the device returns to the read mode.
WE
A20∼A0(x16)/
A20∼A-1(x8)
555H/
AAAH
2AAH/
555H
555H/
AAAH
555H
AAAH
2AAH/
555H
555H/
AAAH
80H
55H
AAH
AAH
10H
55H
DQ15-DQ0
Chip Erase
Start
RY/BY
Figure 5. Chip Erase Command Sequence
Block Erase
To erase a block is to write 1′s into the desired memory block by executing the Internal Erase Routine. The Block Erase requires six
bus cycles to write the command sequence shown in Table 8. After the first two "unlock" cycles, the erase setup command (80H) is
written at the third cycle. Then there are two more "unlock" cycles followed by the Block Erase command. The Internal Erase Routine
automatically pre-programs and verifies the entire memory prior to erasing it. The block address is latched on the falling edge of WE
or CE, while the Block Erase command is latched on the rising edge of WE or CE.
Multiple blocks can be erased sequentially by writing the six bus-cycle operation in Figure 6. Upon completion of the last cycle for the
Block Erase, additional block address and the Block Erase command (30H) can be written to perform the Multi-Block Erase. An 50µs
(typical) "time window" is required between the Block Erase command writes. The Block Erase command must be written within the
50µs "time window", otherwise the Block Erase command will be ignored. The 50µs "time window" is reset when the falling edge of
the WE occurs within the 50µs of "time window" to latch the Block Erase command. During the 50µs of "time window", any command
other than the Block Erase or the Erase Suspend command written to the device will reset the device to read mode. After the 50µs of
"time window", the Block Erase command will initiate the Internal Erase Routine to erase the selected blocks. Any Block Erase
address and command following the exceeded "time window" may or may not be accepted. No other commands will be recognized
except the Erase Suspend command during Block Erase operation.
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NOR FLASH MEMORY
WE
A20∼A0(x16)/
A20∼A-1(x8)
555H/
AAAH
2AAH/
555H
555H/
AAAH
555H/
AAAH
2AAH/
555H
Block
Address
80H
DQ15-DQ0
55H
AAH
AAH
30H
55H
Block Erase
Start
RY/BY
Figure 6. Block Erase Command Sequence
Erase Suspend / Resume
The Erase Suspend command interrupts the Block Erase to read or program data in a block that is not being erased. The Erase Sus-
pend command is only valid during the Block Erase operation including the time window of 50µs. The Erase Suspend command is
not valid while the Chip Erase or the Internal Program Routine sequence is running.
When the Erase Suspend command is written during a Block Erase operation, the device requires a maximum of 20µs to suspend
the erase operation. But, when the Erase Suspend command is written during the block erase time window (50µs) , the device imme-
diately terminates the block erase time window and suspends the erase operation.
After the erase operation has been suspended, the device is availble for reading or programming data in a block that is not being
erased. The system may also write the autoselect command sequence when the device is in the Erase Suspend mode.
When the Erase Resume command is executed, the Block Erase operation will resume. When the Erase Suspend or Erase Resume
command is executed, the addresses are in Don't Care state.
WE
A20∼A0(x16)/
A20∼A-1(x8)
555H/
AAAH
Block
Address
XXXH
XXXH
30H
AAH
B0H
30H
DQ15-DQ0
Block Erase
Command Sequence
Erase
Resume
Block Erase
Start
Erase
Suspend
Figure 7. Erase Suspend/Resume Command Sequence
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K8D3x16UTC / K8D3x16UBC
NOR FLASH MEMORY
Read While Write
The K8D3216U provides dual bank memory architecture that divides the memory array into two banks. The device is capable of
reading data from one bank and writing data to the other bank simultaneously. This is so called the Read While Write operation with
dual bank architecture; this feature provides the capability of executing the read operation during Program/Erase or Erase-Suspend-
Program operation.
The Read While Write operation is prohibited during the chip erase operation. It is also allowed during erase operation when either
single block or multiple blocks from same bank are loaded to be erased. It means that the Read While Write operation is prohibited
when blocks from Bank1 and another blocks from Bank2 are loaded all together for the multi-block erase operation.
Block Group Protection & Unprotection
The K8D3216U feature hardware block group protection. This feature will disable both program and erase operations in any combi-
nation of twenty five block groups of memory. Please refer to Tables 10 and 11. The block group protection feature is enabled using
programming equipment at the user’s site. The device is shipped with all block groups unprotected.
This feature can be hardware protected or unprotected. If a block is protected, program or erase command in the protected block will
be ignored by the device. The protected block can only be read. This is useful method to preserve an important program data. The
block group unprotection allows the protected blocks to be erased or programed. All blocks must be protected before unprotect oper-
ation is executing. The block group protection and unprotection can be implemented by two methods.
The first method needs the following conditions.
DQ15/
A-1
DQ8/
DQ14
DQ0/
DQ7
Operation
CE
OE
WE
BYTE
A9
A6
A1
A0
RESET
Block Group Protect
L
L
H
H
L
L
X
X
X
X
L
H
H
L
L
X
X
X
X
DIN
DIN
VID
VID
Block Group Unprotect
H
Address must be inputted to the block group address (A12~A20) during block group protection operation. Please refer to Figure 9
(Algorithm) and Switching Waveforms of Block Group Protect & Unprotect Operations.
The second method needs the following conditions in order to keep backward compatibility. Please refer to Figure 8.
DQ15/
A-1
DQ8/
DQ14
DQ0/
DQ7
Operation
CE
OE
WE
BYTE
A9
A6
A1
A0
RESET
Block Group Protect
L
L
VID
VID
X
X
VID
VID
L
H
H
L
L
X
X
X
X
X
X
H
H
Block Group Unprotect
H
The K8D3216U needs the recovery time (20µs) from the rising edge of WE in order to execute its program, erase and read opera-
tions.
Block Group Protect:150µs
Block Group Unprotect:500ms
500ns
500ns
VID
A9
VID
Don't Care
Don't Care
OE
Low
WE
Address
Block Group Address*
Notes : * Block Group Address is Don't Care during Block Group Unprotection.
Figure 8. Block Group Protect Sequence (The second method)
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K8D3x16UTC / K8D3x16UBC
NOR FLASH MEMORY
START
COUNT = 1
RESET=VID
Wait 1µs
No
First Write
Cycle=60h?
Temporary Block Group
Unprotect Mode
Yes
Yes
Block Group
Protection ?
No
Block Unprotect
Algorithm
Block Protect
Algorithm
No
Yes
All Block Groups
Protected ?
Set up Block Group
Block Group <i>, i= 0
address
Block Group Unprotect
Write 60H
with
Block Group Protect:
Write 60H to Block
Group address with
A6=0,A1=1
A6=1,A1=1
A0=0
A0=0
Wait 15ms
Wait 150µs
Reset
COUNT=1
Verify Block Group
Unprotect:Write 40H to
Block Group address
with A6=1,
Verify Block Group
Protect:Write 40H to
Block Group address
with A6=0,
Increment
COUNT
A1=1,A0=0
Increment
COUNT
A1=1,A0=0
Read from
Block Group address
with A6=1,
Read from
Block Group address
with A6=0,
A1=1,A0=0
Set up next Block
Group address
A1=1,A0=0
No
No
No
COUNT
=1000?
Data=00h?
Yes
No
COUNT
=25?
Data=01h?
Yes
Yes
Yes
No
Last Block Group
verified ?
Device failed
Protect another
Block Group?
Device failed
Yes
Yes
Remove VID
from RESET
No
Remove VID
from RESET
Write RESET
command
Write RESET
command
END
END
Note : All blocks must be protected before unprotect operation is executing.
Figure 9. Block Group Protection & Unprotection Algorithms
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NOR FLASH MEMORY
Table 10. Flash Memory Block Group Address (Top Boot Block)
Block Address
Block Group
Block
A20
A19
A18
A17
A16
A15
0
A14
A13
A12
BGA0
BGA1
0
0
0
0
0
X
X
X
BA0
0
1
0
0
0
0
1
0
X
X
X
BA1 to BA3
1
1
BGA2
BGA3
BGA4
BGA5
BGA6
BGA7
BGA8
BGA9
BGA10
BGA11
BGA12
BGA13
BGA14
BGA15
0
0
0
0
0
0
0
1
1
1
1
1
1
1
0
0
0
1
1
1
1
0
0
0
0
1
1
1
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
BA4 to BA7
BA8 to BA11
BA12 to BA15
BA16 to BA19
BA20 to BA23
BA24 to BA27
BA28 to BA31
BA32 to BA35
BA36 to BA39
BA40 to BA43
BA44 to BA47
BA48 to BA51
BA52 to BA55
BA56 to BA59
BGA16
1
1
1
1
0
1
X
X
X
BA60 to BA62
1
0
BGA17
BGA18
BGA19
BGA20
BGA21
BGA22
BGA23
BGA24
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
BA63
BA64
BA65
BA66
BA67
BA68
BA69
BA70
1
1
1
1
1
1
1
1
1
1
1
1
1
1
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K8D3x16UTC / K8D3x16UBC
NOR FLASH MEMORY
Table 11. Flash Memory Block Group Address (Bottom Boot Block)
Block Address
Block Group
Block
A20
A19
A18
A17
A16
A15
0
A14
0
A13
0
A12
0
BGA0
BGA1
BGA2
BGA3
BGA4
BGA5
BGA6
BGA7
0
0
0
0
0
BA0
BA1
BA2
BA3
BA4
BA5
BA6
BA7
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
1
1
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
1
0
1
0
0
0
0
0
0
1
1
0
0
0
0
0
0
0
1
1
1
0
1
BGA8
0
0
0
0
1
0
X
X
X
BA8 to BA10
1
1
BGA9
0
0
0
0
0
0
0
1
1
1
1
1
1
1
0
0
0
1
1
1
1
0
0
0
0
1
1
1
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
BA11 to BA14
BA15 to BA18
BA19 to BA22
BA23 to BA26
BA27 to BA30
BA31 to BA34
BA35 to BA38
BA39 to BA42
BA43 to BA46
BA47 to BA50
BA51 to BA54
BA55 to BA58
BA59 to BA62
BA63 to BA66
BGA10
BGA11
BGA12
BGA13
BGA14
BGA15
BGA16
BGA17
BGA18
BGA19
BGA20
BGA21
BGA22
BGA23
BGA24
1
1
1
1
1
1
1
1
0
1
X
X
X
X
X
X
BA67 to BA69
BA70
1
0
1
1
19
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September, 2006
K8D3x16UTC / K8D3x16UBC
NOR FLASH MEMORY
Temporary Block Group Unprotect
The protected blocks of the K8D3216U can be temporarily unprotected by applying high voltage (VID = 8.5V~12.5V) to the RESET
pin. In this mode, previously protected blocks can be programmed or erased with the program or erase command routines. When the
RESET pin goes high (RESET = VIH), all the previously protected blocks will be protected again. If the WP/ACC pin is asserted at VIL
, the two outermost boot blocks remain protected.
VID
V = VIH or VIL
RESET
CE
Program & Erase Operation
at Protected Block
WE
Figure 10. Temporary Block Group Unprotect Sequence
Write Protect (WP)
The WP/ACC pin has two useful functions. The one is that certain boot block is protected by the hardware method not to use VID.
The other is that program operation is accelerated to reduce the program time (Refer to Accelerated program Operation Paragraph).
When the WP/ACC pin is asserted at VIL, the device can not perform program and erase operation in the two "outermost" 8K byte
boot blocks independently of whether those blocks were protected or unprotected using the method described in "Block Group pro-
tection/Unprotection".
The write protected blocks can only be read. This is useful method to preserve an important program data.
The two outermost 8K byte boot blocks are the two blocks containing the lowest addresses in a bottom-boot-configured device, or
the two blocks containing the highest addresses in a top-boot-congfigured device.
(K8D3216UT : BA69 and BA70, K8D3216UB : BA0 and BA1)
When the WP/ACC pin is asserted at VIH, the device reverts to whether the two outermost 8K byte boot blocks were last set to be
protected or unprotected. That is, block protection or unprotection for these two blocks depends on whether they were last protected
or unprotected using the method described in "Block Group protection/unprotection".
Recommend that the WP/ACC pin must not be in the state of floating or unconnected, or the device may be led to malfunction.
Secode(Security Code) Block Region
The Secode Block feature provides a Flash memory region to be stored unique and permanent identification code, that is, Electronic
Serial Number (ESN), customer code and so on. This is primarily intended for customers who wish to use an Electronic Serial Num-
ber (ESN) in the device with the ESN protected against modification. Once the Secode Block region is protected, any further modifi-
cation of that region is impossible. This ensures the security of the ESN once the product is shipped to the field.
The Secode Block is factory locked or customer lockable. Before the device is shipped, the factory locked Secode Block is written on
the special code and it is protected. The Secode Indicator bit (DQ7) is permanently fixed at "1" and it is not changed. The customer
lockable Secode Block is unprotected, therefore it is programmed and erased. The Secode Indicator bit (DQ7) of it is permanently
fixed at "0" and it is not changed. But once it is protected, there is no procedure to unprotect and modify the Secode Block.
The Secode Block region is 64K bytes in length and is accessed through a new command sequence (see Table 8). After the system
has written the Enter Secode Block command sequence, the system may read the Secode Block region by using the same
addresses of the boot blocks (8KBx8). The K8D3216UT occupies the address of the byte mode 3F0000H to 3FFFFFH (word mode
1F8000H to 1FFFFFH) and the K8D3216UB type occupies the address of the byte mode 000000H to 00FFFFH (word mode
000000H to 007FFFH). This mode of operation continues until the system issues the Exit Secode Block command sequence, or until
power is removed from the device. On power-up, or following a hardware reset, the device reverts to read mode.
20
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K8D3x16UTC / K8D3x16UBC
NOR FLASH MEMORY
Accelerated Program Operation
Accelerated program operation reduces the program time. This is one of two functions provided by the WP/ACC pin. When the WP/
ACC pin is asserted as VHH, the device automatically enters the aforementioned Unlock Bypass mode, temporarily unprotecting any
protected blocks, and reduces the program operation time. The system would use a two-cycle program command sequence as
required by the Unlock Bypass mode. Removing VHH from the WP/ACC pin returns the device to normal operation. Recommend
that the WP/ACC pin must not be asserted at VHH except accelerated program operation, or the device may be damaged. In
addition, the WP/ACC pin must not be in the state of floating or unconnected, otherwise the device may be led to malfunc-
tion.
Software Reset
The reset command provides that the bank is reseted to read mode or erase-suspend-read mode. The addresses are in Don't Care
state. The reset command is vaild between the sequence cycles in an erase command sequence before erasing begins, or in a pro-
gram command sequence before programming begins. This resets the bank in which was operating to read mode. if the device is be
erasing or programming, the reset command is invalid until the operation is completed. Also, the reset command is valid between the
sequence cycles in an autoselect command sequence. In the autoselect mode, the reset command returns the bank to read mode.
If a bank entered the autoselect mode in the Erase Suspend mode, the reset command returns the bank to erase-suspend-read
mode. If DQ5 is high on erase or program operation, the reset command return the bank to read mode or erase-suspend-read mode
if the bank was in the Erase Suspend state.
Hardware Reset
The K8D3216U offers a reset feature by driving the RESET pin to VIL. The RESET pin must be kept low (VIL) for at least 500ns.
When the RESET pin is driven low, any operation in progress will be terminated and the internal state machine will be reset to the
standby mode after 20µs. If a hardware reset occurs during a program operation, the data at that particular location will be lost.
Once the RESET pin is taken high, the device requires 200ns of wake-up time until outputs are valid for read access. Also, note that
all the data output pins are tri-stated for the duration of the RESET pulse.
The RESET pin may be tied to the system reset pin. If a system reset occurs during the Internal Program and Erase Routine, the
device will be automatically reset to the read mode ; this will enable the systems microprocessor to read the boot-up firmware from
the Flash memory.
Power-up Protection
To avoid initiation of a write cycle during Vcc Power-up, RESET low must be asserted during power-up. After RESET goes high, the
device is reset to the read mode.
Low Vcc Write Inhibit
To avoid initiation of a write cycle during Vcc power-up and power-down, a write cycle is locked out for Vcc less than 1.8V. If Vcc <
VLKO (Lock-Out Voltage), the command register and all internal program/erase circuits are disabled. Under this condition the device
will reset itself to the read mode. Subsequent writes will be ignored until the Vcc level is greater than VLKO. It is the user′s responsi-
bility to ensure that the control pins are logically correct to prevent unintentional writes when Vcc is above 1.8V.
Write Pulse Glitch Protection
Noise pulses of less than 5ns(typical) on CE, OE, or WE will not initiate a write cycle.
Logical Inhibit
Writing is inhibited under any one of the following conditions : OE = VIL, CE = VIH or WE = VIH. To initiate a write, CE and WE must
be "0", while OE is "1".
Commom Flash Memory Interface
Common Flash Momory Interface is contrived to increase the compatibility of host system software. It provides the specific informa-
tion of the device, such as memory size, byte/word configuration, and electrical features. Once this information has been obtained,
the system software will know which command sets to use to enable flash writes, block erases, and control the flash component.
When the system writes the CFI command(98H) to address 55H in word mode(or address AAH in byte mode), the device enters the
CFI mode. And then if the system writes the address shown in Table 12, the system can read the CFI data. Query data are always
presented on the lowest-order data outputs(DQ0-7) only. In word(x16) mode, the upper data outputs(DQ8-15) is 00h. To terminate
this operation, the system must write the reset command.
21
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K8D3x16UTC / K8D3x16UBC
NOR FLASH MEMORY
Table 12. Common Flash Memory Interface Code
Description
Addresses
(Word Mode)
Addresses
(Byte Mode)
Data
10H
11H
12H
20H
22H
24H
0051H
0052H
0059H
Query Unique ASCII string "QRY"
13H
14H
26H
28H
0002H
0000H
Primary OEM Command Set
15H
16H
2AH
2CH
0040H
0000H
Address for Primary Extended Table
17H
18H
2EH
30H
0000H
0000H
Alternate OEM Command Set (00h = none exists)
Address for Alternate OEM Extended Table (00h = none exists)
19H
1AH
32H
34H
0000H
0000H
Vcc Min. (write/erase)
D7-D4: volt, D3-D0: 100 millivolt
1BH
1CH
36H
38H
0027H
0036H
Vcc Max. (write/erase)
D7-D4: volt, D3-D0: 100 millivolt
Vpp Min. voltage(00H = no Vpp pin present)
1DH
1EH
1FH
20H
21H
22H
23H
24H
25H
26H
27H
3AH
3CH
3EH
40H
42H
44H
46H
48H
4AH
4CH
4EH
0000H
0000H
0004H
0000H
000AH
0000H
0005H
0000H
0004H
0000H
0016H
Vpp Max. voltage(00H = no Vpp pin present)
Typical timeout per single byte/word write 2N us
Typical timeout for Min. size buffer write 2N us(00H = not supported)
Typical timeout per individual block erase 2N ms
Typical timeout for full chip erase 2N ms(00H = not supported)
Max. timeout for byte/word write 2N times typical
Max. timeout for buffer write 2N times typical
Max. timeout per individual block erase 2N times typical
Max. timeout for full chip erase 2N times typical(00H = not supported)
Device Size = 2N byte
28H
29H
50H
52H
0002H
0000H
Flash Device Interface description
2AH
2BH
54H
56H
0000H
0000H
Max. number of byte in multi-byte write = 2N
Number of Erase Block Regions within device
2CH
58H
0002H
2DH
2EH
2FH
30H
5AH
5CH
5EH
60H
0007H
0000H
0020H
0000H
Erase Block Region 1 Information
Erase Block Region 2 Information
Erase Block Region 3 Information
Erase Block Region 4 Information
31H
32H
33H
34H
62H
64H
66H
68H
003EH
0000H
0000H
0001H
35H
36H
37H
38H
6AH
6CH
6EH
70H
0000H
0000H
0000H
0000H
39H
3AH
3BH
3CH
72H
74H
76H
78H
0000H
0000H
0000H
0000H
22
Revision 1.7
September, 2006
K8D3x16UTC / K8D3x16UBC
NOR FLASH MEMORY
Table 12. Common Flash Memory Interface Code
Description
Addresses
(Word Mode)
Addresses
(Byte Mode)
Data
40H
41H
42H
80H
82H
84H
0050H
0052H
0049H
Query-unique ASCII string "PRI"
Major version number, ASCII
Minor version number, ASCII
43H
44H
86H
88H
0033H
0033H
Address Sensitive Unlock(Bits 1-0)
0 = Required, 1= Not Required
Silcon Revision Number(Bits 7-2)
45H
8AH
0000H
Erase Suspend
0 = Not Supported, 1 = To Read Only, 2 = To Read & Write
46H
47H
8CH
8EH
0002H
0001H
Block Protect
0 = Not Supported, 1 = Number of blocks in per group
Block Temporary Unprotect 00 = Not Supported, 01 = Supported
Block Protect/Unprotect scheme 04=K8D1x16U mode
48H
49H
90H
92H
0001H
0004H
Simultaneous Operation (1)
00 = Not Supported, XX = Number of Blocks in Bank2
4AH
4BH
4CH
94H
96H
98H
00XXH
0000H
0000H
Burst Mode Type 00 = Not Supported, 01 = Supported
Page Mode Type
00 = Not Supported, 01 = 4 Word Page 02 = 8 Word Page
ACC(Acceleration) Supply Minimum
00 = Not Supported, D7 - D4 : Volt, D3 - D0 : 100mV
4DH
4EH
4FH
9AH
9CH
9EH
0085H
00C5H
000XH
ACC(Acceleration) Supply Maximum
00 = Not Supported, D7 - D4 : Volt, D3 - D0 : 100mV
Top/Bottom Boot Block Flag
02H = Bottom Boot Device, 03H = Top Boot Device
Note :
1. The number of blocks in Bank2 is device dependent.
K8D3216U(8Mb/24Mb) = 30h (48blocks)
23
Revision 1.7
September, 2006
K8D3x16UTC / K8D3x16UBC
NOR FLASH MEMORY
DEVICE STATUS FLAGS
The K8D3216U has means to indicate its status of operation in the bank where a program or erase operation is in processes.
Address must include bank address being excuted internal routine operation. The status is indicated by raising the device status flag
via corresponding DQ pins or the RY/ BY pin. The corresponding DQ pins are DQ7, DQ6, DQ5, DQ3 and DQ2. The statuses are as
follows :
Table 13. Hardware Sequence Flags
Status
DQ7
DQ7
0
DQ6
Toggle
Toggle
DQ5
DQ3
DQ2
1
RY/BY
Programming
0
0
0
1
0
0
Block Erase or Chip Erase
Erase Suspend Read
Toggle
Erase Suspended
Block
Toggle
(Note 1)
1
1
0
Data
0
0
Data
0
1
1
0
In Progress
Non-Erase Sus-
pended Block
Erase Suspend Read
Data
DQ7
Data
Toggle
Data
1
Erase Suspend
Program
Non-Erase Sus-
pended Block
No
Toggle
Programming
DQ7
0
Toggle
Toggle
Toggle
1
1
1
0
1
0
0
0
0
Exceeded
Time Limits
Block Erase or Chip Erase
Erase Suspend Program
(Note 2)
No
Toggle
DQ7
Notes :
1. DQ2 will toggle when the device performs successive read operations from the erase suspended block.
2. If DQ5 is High (exceeded timing limits), successive reads from a problem block will cause DQ2 to toggle.
DQ7 : Data Polling
When an attempt to read the device is made while executing the Internal Program, the complement of the data is written to DQ7 as
an indication of the Routine in progress. When the Routine is completed an attempt to access to the device will produce the true data
written to DQ7. When a user attempts to read the device during the Erase operation, DQ7 will be low. If the device is placed in the
Erase Suspend Mode, the status can be detected via the DQ7 pin. If the system tries to read an address which belongs to a block
that is being erased, DQ7 will be high. If a non-erased block address is read, the device will produce the true data to DQ7. If an
attempt is made to program a protected block, DQ7 outputs complements the data for approximately 1µs and the device then returns
to the Read Mode without changing data in the block. If an attempt is made to erase a protected block, DQ7 outputs complement
data in approximately 100us and the device then returns to the Read Mode without erasing the data in the block.
DQ6 : Toggle Bit
Toggle bit is another option to detect whether an Internal Routine is in progress or completed. Once the device is at a busy state,
DQ6 will toggle. Toggling DQ6 will stop after the device completes its Internal Routine. If the device is in the Erase Suspend Mode,
an attempt to read an address that belongs to a block that is being erased will produce a high output of DQ6. If an address belongs
to a block that is not being erased, toggling is halted and valid data is produced at DQ6.
If an attempt is made to program a protected block, DQ6 toggles for approximately 1us and the device then returns to the Read
Mode without changing the data in the block. If an attempt is made to erase a protected block, DQ6 toggles for approximately 100µs
and the device then returns to the Read Mode without erasing the data in the block.
DQ5 : Exceed Timing Limits
If the Internal Program/Erase Routine extends beyond the timing limits, DQ5 will go High, indicating program/erase failure.
24
Revision 1.7
September, 2006
K8D3x16UTC / K8D3x16UBC
NOR FLASH MEMORY
DQ3 : Block Erase Timer
The status of the multi-block erase operation can be detected via the DQ3 pin. DQ3 will go High if 50µs of the block erase time win-
dow expires. In this case, the Internal Erase Routine will initiate the erase operation.Therefore, the device will not accept further write
commands until the erase operation is completed. DQ3 is Low if the block erase time window is not expired. Within the block erase
time window, an additional block erase command (30H) can be accepted. To confirm that the block erase command has been
accepted, the software may check the status of DQ3 following each block erase command.
DQ2 : Toggle Bit 2
The device generates a toggling pulse in DQ2 only if an Internal Erase Routine or an Erase Suspend is in progress. When the device
executes the Internal Erase Routine, DQ2 toggles only if an erasing block is read. Although the Internal Erase Routine is in the
Exceeded Time Limits, DQ2 toggles only if an erasing block in the Exceeded Time Limits is read. When the device is in the Erase
Suspend mode, DQ2 toggles only if an address in the erasing block is read. If a non-erasing block address is read during the Erase
Suspend mode, then DQ2 will produce valid data. DQ2 will go High if the user tries to program a non-erase suspend block while the
device is in the Erase Suspend mode. Combination of the status in DQ6 and DQ2 can be used to distinguish the erase operation
from the program operation.
RY/BY : Ready/Busy
The K8D3216U has a Ready / Busy output that indicates either the completion of an operation or the status of Internal Algorithms. If
the output is Low, the device is busy with either a program or an erase operation. If the output is High, the device is ready to accept
any read/write or erase operation. When the RY/ BY pin is low, the device will not accept any additional program or erase commands
with the exception of the Erase Suspend command. If the K8D3216U is placed in an Erase Suspend mode, the RY/ BY output will be
High. For programming, the RY/ BY is valid (RY/ BY = 0) after the rising edge of the fourth WE pulse in the four write pulse
sequence. For Chip Erase, RY/ BY is also valid after the rising edge of WE pulse in the six write pulse sequence. For Block Erase,
RY/ BY is also valid after the rising edge of the sixth WE pulse.
The pin is an open drain output, allowing two or more Ready/ Busy outputs to be OR-tied. An appropriate pull-up resistor is required
for proper operation.
Rp
Vcc
F
VccF (Max.) - VOL (Max.)
3.2V
Rp =
=
IOL + Σ IL
2.1mA + Σ IL
Ready / Busy
open drain output
where Σ IL is the sum of the input currents of all devices tied to the
Ready / Busy ball.
Vss
Device
25
Revision 1.7
September, 2006
K8D3x16UTC / K8D3x16UBC
NOR FLASH MEMORY
Start
Read(DQ0~DQ7)
Valid Address
Start
Read(DQ0~DQ7)
Valid Address
Read(DQ0~DQ7)
Valid Address
DQ6 = Toggle ?
Yes
DQ7 = Data ?
Yes
No
No
No
No
DQ5 = 1 ?
Yes
DQ5 = 1 ?
Yes
Read twice(DQ0~DQ7)
Valid Address
Read(DQ0~DQ7)
Valid Address
No
Yes
DQ6 = Toggle ?
DQ7 = Data ?
Yes
Fail
No
Fail
Pass
Pass
Figure 12. Toggle Bit Algorithms
Figure 11. Data Polling Algorithms
Start
RESET=VID
(Note 1)
Perform Erase or
Program Operations
RESET=VIH
Temporary Block
Unprotect Completed
(Note 2)
Notes :
1. All protected block groups are unprotected.
( If WP/ACC = VIL , the two outermost boot blocks remain protected )
2. All previously protected block groups are protected once again.
Figure 13. Temporary Block Group Unprotect Routine
26
Revision 1.7
September, 2006
K8D3x16UTC / K8D3x16UBC
NOR FLASH MEMORY
ABSOLUTE MAXIMUM RATINGS
Parameter
Symbol
Rating
-0.5 to +4.0
-0.5 to +12.5
-0.5 to +12.5
-0.5 to +4.0
-10 to +125
-40 to +125
-65 to +150
5
Unit
Vcc
Vcc
A9, OE , RESET
Voltage on any pin relative to VSS
WP/ACC
V
VIN
All Other Pins
Commercial
Temperature Under Bias
Tbias
°C
Industrial
Storage Temperature
Tstg
°C
mA
°C
Short Circuit Output Current
IOS
TA (Commercial Temp.)
TA (Industrial Temp.)
0 to +70
Operating Temperature
-40 to + 85
°C
Notes :
1. Minimum DC voltage is -0.5V on Input/ Output pins. During transitions, this level may fall to -2.0V for periods <20ns. Maximum DC voltage on
input / output pins is Vcc+0.5V which, during transitions, may overshoot to Vcc+2.0V for periods <20ns.
2. Minimum DC voltage is -0.5V on A9, OE, RESET and WP/ACC pins. During transitions, this level may fall to -2.0V for periods <20ns. Maximum DC
voltage on A9, OE, RESET pins is 12.5V which, during transitions, may overshoot to 14.0V for periods <20ns.
3. Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to the conditions
detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
RECOMMENDED OPERATING CONDITIONS ( Voltage reference to Vss )
Parameter
Symbol
Min
2.7
0
Typ.
3.0
0
Max
3.6
0
Unit
V
Supply Voltage
VCC
Supply Voltage
VSS
V
DC CHARACTERISTICS
Parameter
Symbol
Test Conditions
Min
Typ
Max
Unit
Input Leakage Current
ILI
VIN=VSS to VCC, VCC=VCCmax
− 1.0
-
-
+ 1.0
µA
A9,OE,RESET Input Leakage
Current
ILIT
VCC=VCCmax, A9,OE,RESET=12.5V
-
35
µA
WP/ACC Input Leakage Current
Output Leakage Current
ILIW
ILO
VCC=VCCmax, WP/ACC=12.5V
-
-
35
+ 1.0
20
µA
µA
VOUT=VSS to VCC,VCC=VCCmax,OE=VIH
− 1.0
-
5MHz
-
-
-
-
-
14
3
Active Read Current (1)
ICC1
CE=VIL, OE=VIH
1MHz
mA
6
Active Write Current (2)
ICC2
ICC3
ICC4
CE=VIL, OE=VIH, WE=VIL
CE=VIL, OE=VIH
15
25
25
30
mA
mA
mA
Read While Program Current (3)
Read While Erase Current (3)
50
CE=VIL, OE=VIH
50
Program While Erase Suspend
Current
ICC5
IACC
CE=VIL, OE=VIH
-
15
35
mA
mA
ACC Pin
CE=VIL, OE=VIH
-
-
5
10
30
ACC Accelerated Program
Current
Vcc Pin
15
VCC=VCCmax,CE, RESET=VCC±0.3V
WP/ACC= VCC± 0.3V or Vss±0.3V
Standby Current
ISB1
ISB2
ISB3
-
-
-
5
5
5
18
18
18
µA
µA
µA
VCC=VCCmax, RESET=Vss± 0.3V,
WP/ACC=VCC± 0.3V or Vss±0.3V
Standby Current During Reset
Automatic Sleep Mode
VIH=VCC±0.3V, VIL=VSS±0.3V,
OE=VIL, IOL=IOH=0
Input Low Level
Input High Level
VIL
-0.5
-
-
0.8
V
V
VIH
0.7xVcc
VCC+0.3
Voltage for WP/ACC Block Tempo-
rarily Unprotect and Program Accel-
eration (4)
8.5
VHH
VCC = 3.0V ± 0.3V
-
12.5
V
27
Revision 1.7
September, 2006
K8D3x16UTC / K8D3x16UBC
NOR FLASH MEMORY
Parameter
Symbol
Test Conditions
VCC = 3.0V ± 0.3V
Min
Typ
Max
Unit
Voltage for Autoselect and
Block Protect (4)
VID
8.5
-
12.5
V
Output Low Level
VOL
VOH
VLKO
IOL=100µA, VCC=VCCmin
IOH=-100µA, Vcc = VCCmin
-
-
-
-
0.4
-
V
V
V
Output High Level
VCC-0.4
1.8
Low Vcc Lock-out Voltage (5)
2.5
Notes :
1. The ICC current listed includes both the DC operating current and the frequency dependent component(at 5 MHz).
The read current is typically 14 mA (@ VCC=3.0V , OE at VIH.)
2. ICC active during Internal Routine(program or erase) is in progress.
3. ICC active during Read while Write is in progress.
4. The high voltage ( VHH or VID ) must be used in the range of Vcc = 3.0V ± 0.3V
5. Not 100% tested.
6. Typical value are measured at Vcc = 3.0V,TA=25°C , Not 100% tested.
CAPACITANCE(TA = 25 °C, VCC = 3.3V, f = 1.0MHz)
Item
Symbol
Test Condition
Min
Max
Unit
pF
Input Capacitance
CIN
VIN=0V
-
-
-
10
10
10
Output Capacitance
Control Pin Capacitance
COUT
CIN2
VOUT=0V
VIN=0V
pF
pF
Note : Capacitance is periodically sampled and not 100% tested.
AC TEST CONDITION
Parameter
Value
0V to Vcc
5ns
Input Pulse Levels
Input Rise and Fall Times
Input and Output Timing Levels
Output Load
Vcc/2
CL = 30pF
Device
Vcc
Input & Output
Vcc/2
Vcc/2
* CL= 30pF including Scope
and Jig Capacitance
Test Point
CL
0V
Input Pulse and Test Point
Output Load
AC CHARACTERISTICS
Read Operations
VCC=2.7V~3.6V
-8
Parameter
Symbol
-7
-9
Unit
Min
Max
-
Min
Max
-
Min
Max
-
Read Cycle Time (1)
tRC
tAA
tCE
tOE
tDF
tOH
70
-
80
-
90
-
ns
ns
ns
ns
ns
ns
Address Access Time
70
70
25
16
-
80
80
25
16
-
90
90
35
16
-
Chip Enable Access Time
Output Enable Time
-
-
-
-
-
-
CE & OE Disable Time (1)
Output Hold Time from Address, CE or OE (1)
-
-
-
0
0
0
Note : 1. Not 100% tested.
28
Revision 1.7
September, 2006
K8D3x16UTC / K8D3x16UBC
NOR FLASH MEMORY
AC CHARACTERISTICS
Write(Erase/Program)Operations
Alternate WE Controlled Write
VCC=2.7V~3.6V
Parameter
Symbol
-7
-8
-9
Unit
Min
70
0
Max
Min
80
0
Max
Min
90
0
Max
Write Cycle Time (1)
tWC
tAS
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
Address Setup Time
Address Hold Time
tASO
tAH
55
45
0
55
45
0
55
45
0
tAHT
tDS
Data Setup Time
35
0
35
0
45
0
Data Hold Time
tDH
Output Enable Setup Time (1)
tOES
tOEH1
0
0
0
Output
Read (1)
0
0
0
Enable
Hold Time
Toggle and Data Polling (1)
tOEH2
10
-
10
-
10
-
ns
CE Setup Time
tCS
tCH
0
0
-
-
-
-
0
0
-
-
-
-
0
0
-
-
-
-
ns
ns
ns
ns
µs
µs
µs
µs
sec
µs
ns
ns
µs
ns
ns
ns
µs
µs
ns
ns
ns
ns
ns
CE Hold Time
Write Pulse Width
Write Pulse Width High
tWP
35
25
35
25
45
30
tWPH
Word
Byte
Word
Byte
14(typ.)
9(typ.)
14(typ.)
9(typ.)
14(typ.)
9(typ.)
Programming Operation
tPGM
9(typ.)
9(typ.)
9(typ.)
Accelerated Programming
Operation
tACCPGM
7(typ.)
7(typ.)
7(typ.)
Block Erase Operation (2)
VCC Set Up Time
tBERS
tVCS
tRB
0.7(typ.)
0.7(typ.)
0.7(typ.)
50
0
-
-
50
-
-
50
-
-
Write Recovery Time from RY/BY
RESET High Time Before Read
RESET to Power Down Time
Program/Erase Valid to RY/BY Delay
VID Rising and Falling Time
0
50
20
90
500
500
-
0
50
20
90
500
500
-
tRH
50
20
90
-
-
-
tRPD
tBUSY
tVID
-
-
-
-
-
-
500
500
-
-
-
-
RESET Pulse Width
tRP
-
-
-
RESET Low to RY/BY High
tRRB
tRSP
tRSTS
tRSTW
tGHWL
tCEPH
tOEPH
20
-
20
-
20
-
RESET Setup Time for Temporary Unprotect
RESET Low Setup Time
1
1
1
500
200
0
-
500
200
0
-
500
200
0
-
RESET High to Address Valid
Read Recovery Time Before Write
CE High during toggling bit polling
OE High during toggling bit polling
-
-
-
-
-
-
20
20
-
20
20
-
20
20
-
-
-
-
Notes : 1. Not 100% tested.
2. The duration of the Program or Erase operation varies and is calculated in the internal algorithms.
29
Revision 1.7
September, 2006
K8D3x16UTC / K8D3x16UBC
NOR FLASH MEMORY
AC CHARACTERISTICS
Write(Erase/Program)Operations
Alternate CE Controlled Writes
VCC=2.7V~3.6V
Parameter
Symbol
-7
-8
-9
Unit
Min
70
0
Max
Min
80
0
Max
Min
90
0
Max
Write Cycle Time (1)
tWC
tAS
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
ns
ns
ns
ns
ns
ns
ns
Address Setup Time
Address Hold Time
Data Setup Time
tAH
45
35
0
45
35
0
45
45
0
tDS
Data Hold Time
tDH
Output Enable Setup Time (1)
tOES
tOEH1
0
0
0
Output
Read (1)
0
0
0
Enable
Hold Time
Toggle and Data Polling (1)
tOEH2
10
-
10
-
10
-
ns
WE Setup Time
WE Hold Time
tWS
tWH
tCP
0
0
-
-
-
-
0
0
-
-
-
-
0
0
-
-
-
-
ns
ns
ns
ns
µs
µs
µs
µs
sec
ns
CE Pulse Width
CE Pulse Width High
35
25
35
25
45
30
tCPH
Word
Byte
Word
Byte
14(typ.)
9(typ.)
14(typ.)
9(typ.)
14(typ.)
9(typ.)
Programming Operation
tPGM
9(typ.)
9(typ.)
9(typ.)
Accelerated Programming
Operation
tACCPGM
7(typ.)
7(typ.)
7(typ.)
Block Erase Operation (2)
tBERS
tFLQZ
0.7(typ.)
0.7(typ.)
0.7(typ.)
BYTE Switching Low to Output HIGH-Z
25
-
25
-
30
-
Notes : 1. Not 100% tested.
2.This does not include the preprogramming time.
ERASE AND PROGRAM PERFORMANCE
Limits
Parameter
Unit
Comments
Min
Typ
Max
Excludes 00H programming
prior to erasure
Block Erase Time
-
0.7
15
sec
Chip Erase Time
-
-
-
-
-
-
-
49
14
9
-
sec
µs
Word Programming Time
Byte Programming Time
330
210
210
150
84
Excludes system-level overhead
Excludes system-level overhead
Excludes system-level overhead
Excludes system-level overhead
µs
Word Mode
Byte Mode
Word Mode
Byte Mode
9
µs
Accelerated Byte/Word
Program Time
7
µs
28
36
sec
sec
Chip Programming Time
Erase/Program Endurance
Excludes system-level overhead
108
Minimum 100,000 cycles guaran-
teed
100,000
-
-
cycles
Notes : 1. 25 °C, VCC = 3.0V 100,000 cycles, typical pattern.
2. System-level overhead is defined as the time required to execute the four bus cycle command necessary to program each byte.
In the preprogramming step of the Internal Erase Routine, all bytes are programmed to 00H before erasure.
30
Revision 1.7
September, 2006
K8D3x16UTC / K8D3x16UBC
NOR FLASH MEMORY
SWITCHING WAVEFORMS
Read Operations
tRC
Address Stable
Address
tAA
CE
tOE
tDF
OE
tOEH1
WE
tCE
tOH
HIGH-Z
HIGH-Z
Outputs
Output Valid
HIGH
RY/BY
NOTE
Asynchronous mode may not support read following four sequential invalid read condition within 200ns.
-7
-8
-9
Parameter
Symbol
Unit
Min
Max
-
Min
Max
-
Min
Max
-
Read Cycle Time
tRC
tAA
70
-
80
-
90
-
ns
ns
ns
ns
ns
ns
ns
Address Access Time
70
70
25
16
-
80
80
25
16
-
90
90
35
16
-
Chip Enable Access Time
Output Enable Time
tCE
-
-
-
tOE
-
-
-
CE & OE Disable Time (1)
Output Hold Time from Address, CE or OE
OE Hold Time
tDF
-
-
-
tOH
0
0
0
0
0
0
tOEH1
-
-
-
Note : 1. Not 100% tested.
31
Revision 1.7
September, 2006
K8D3x16UTC / K8D3x16UBC
NOR FLASH MEMORY
SWITCHING WAVEFORMS
Hardware Reset/Read Operations
tRC
Address Stable
Address
tAA
CE
tRH
tRP
tRH
tCE
RESET
tOH
High-Z
Output Valid
Outputs
-7
-8
-9
Parameter
Symbol
Unit
Min
70
-
Max
Min
80
-
Max
Min
90
-
Max
Read Cycle Time
tRC
tAA
tCE
tOH
tRP
tRH
-
70
70
-
-
80
80
-
-
90
90
-
ns
ns
ns
ns
ns
ns
Address Access Time
Chip Enable Access Time
-
-
-
Output Hold Time from Address, CE or OE
RESET Pulse Width
0
0
0
500
50
-
500
50
-
500
50
-
RESET High Time Before Read
-
-
-
32
Revision 1.7
September, 2006
K8D3x16UTC / K8D3x16UBC
NOR FLASH MEMORY
SWITCHING WAVEFORMS
Alternate WE Controlled Program Operations
tAS
Data Polling
PA
555H
PA
Address
CE
tRC
tAH
tOES
OE
tWC
tCH
tPGM
tWP
WE
tWPH
tDH
tOE
tDF
tCS
A0H
PD
Status
DOUT
DATA
tCE
tBUSY
tRB
tDS
tOH
RY/BY
Notes : 1. DQ7 is the output of the complement of the data written to the device.
2. DOUT is the output of the data written to the device.
3. PA : Program Address, PD : Program Data
4. The illustration shows the last two cycles of the program command sequence.
-7
-8
-9
Parameter
Symbol
Unit
Min
70
0
Max
Min
80
0
Max
Min
90
0
Max
Write Cycle Time
tWC
tAS
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
us
us
µs
µs
ns
ns
ns
ns
ns
ns
ns
Address Setup Time
Address Hold Time
Data Setup Time
Data Hold Time
tAH
45
35
0
45
35
0
45
45
0
tDS
tDH
CE Setup Time
tCS
0
0
0
CE Hold Time
tCH
0
0
0
OE Setup Time
tOES
tWP
tWPH
0
0
0
Write Pulse Width
Write Pulse Width High
35
25
35
25
45
30
Word
Byte
Word
Byte
14(typ.)
9(typ.)
9(typ.)
7(typ.)
14(typ.)
9(typ.)
9(typ.)
7(typ.)
14(typ.)
9(typ.)
9(typ.)
7(typ.)
Programming Operation
tPGM
Accelerated Programming
Operation
tACCPGM
Read Cycle Time
tRC
tCE
70
-
-
70
25
16
-
80
-
-
80
25
16
-
90
-
-
90
35
16
-
Chip Enable Access Time
Output Enable Time
CE & OE Disable Time
tOE
-
-
-
tDF
-
-
-
Output Hold Time from Address, CE or OE
Program/Erase Valide to RY/BY Delay
Recovery Time from RY/BY
tOH
0
0
0
tBUSY
tRB
90
0
-
90
0
-
90
0
-
-
-
-
33
Revision 1.7
September, 2006
K8D3x16UTC / K8D3x16UBC
NOR FLASH MEMORY
SWITCHING WAVEFORMS
Alternate CE Controlled Program Operations
tAS
Data Polling
555H
PA
PA
Address
WE
tAH
tOES
OE
CE
tWC
tPGM
tCP
tCPH
tWS
tDH
PD
DOUT
Status
A0H
DATA
tDS
tBUSY
tRB
RY/BY
Notes :
1. DQ7 is the output of the complement of the data written to the device.
2. DOUT is the output of the data written to the device.
3. PA : Program Address, PD : Program Data
4. The illustration shows the last two cycles of the program command sequence.
-7
-8
-9
Parameter
Symbol
Unit
Min
70
0
Max
Min
80
0
Max
Min
Max
Write Cycle Time
tWC
tAS
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
90
0
-
-
-
-
-
-
-
-
-
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
µs
µs
µs
ns
ns
Address Setup Time
Address Hold Time
Data Setup Time
Data Hold Time
tAH
45
35
0
45
35
0
45
45
0
tDS
tDH
OE Setup Time
tOES
tWS
tWH
tCP
0
0
0
WE Setup Time
WE Hold Time
0
0
0
0
0
0
CE Pulse Width
CE Pulse Width High
35
25
35
25
45
30
tCPH
Word
Byte
Word
Byte
14(typ.)
14(typ.)
9(typ.)
9(typ.)
7(typ.)
14(typ.)
Programming Operation
tPGM
9(typ.)
9(typ.)
7(typ.)
9(typ.)
9(typ.)
7(typ.)
Accelerated Programming
Operation
tACCPGM
Program/Erase Valide to RY/BY Delay
Recovery Time from RY/BY
tBUSY
tRB
90
0
-
-
90
0
-
-
90
0
-
-
34
Revision 1.7
September, 2006
K8D3x16UTC / K8D3x16UBC
NOR FLASH MEMORY
SWITCHING WAVEFORMS
Word to Byte Timing Diagram for Read Operation
tCE
CE
OE
BYTE
tELFL
Data Output
(DQ0-DQ7)
DQ0-DQ7
Data Output
DQ8-DQ14
DQ15/A-1
(DQ8-DQ14)
Data Output
(DQ15)
Address Input (A-1)
tFLQZ
Byte to Word Timing Diagram for Read Operation
tCE
CE
OE
BYTE
tELFH
Data Output
(DQ0-DQ7)
DQ0-DQ7
Data Output
(DQ8-DQ14)
DQ8-DQ14
Address Input
(A-1)
Data Output
(DQ15)
DQ15/A-1
tFHQV
BYTE Timing Diagram for Write Operation
CE
The falling edge of the last WE signal
WE
BYTE
tSET
(tAS)
tHOLD(tAH)
-7
-8
-9
Parameter
Chip Enable Access Time
Symbol
Unit
Min
Max
70
5
Min
Max
80
5
Min
Max
90
5
tCE
tELFL/tELFH
tFLQZ
-
-
-
-
-
-
-
-
-
-
-
-
ns
ns
ns
ns
CE to BYTE Switching Low or High
BYTE Switching Low to Output HIGH-Z
BYTE Switching High to Output Active
25
25
25
25
30
35
tFHQV
35
Revision 1.7
September, 2006
K8D3x16UTC / K8D3x16UBC
NOR FLASH MEMORY
SWITCHING WAVEFORMS
Chip/Block Erase Operations
tAS
555H for Chip Erase
555H
2AAH
555H
555H
2AAH
BA
Address
CE
tAH
tRC
tOES
OE
tWC
tWP
WE
tWPH
tDH
tCS
10H for Chip Erase
30H
AAH
55H
80H
AAH
55H
DATA
RY/BY
tDS
Vcc
tVCS
Note : BA : Block Address
-7
-8
-9
Parameter
Symbol
Unit
Min
Max
Min
80
0
Max
Min
Max
Write Cycle Time
tWC
tAS
70
0
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
90
0
-
-
-
-
-
-
-
-
-
-
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
Address Setup Time
Address Hold Time
Data Setup Time
Data Hold Time
tAH
45
35
0
45
35
0
45
45
0
tDS
tDH
OE Setup Time
tOES
tCS
0
0
0
CE Setup Time
0
0
0
Write Pulse Width
Write Pulse Width High
Read Cycle Time
VCC Set Up Time
tWP
tWPH
tRC
35
25
70
50
35
25
80
50
45
30
90
50
tVCS
36
Revision 1.7
September, 2006
K8D3x16UTC / K8D3x16UBC
NOR FLASH MEMORY
SWITCHING WAVEFORMS
Read While Write Operations
Read
tRC
Command
tWC
Read
tRC
Command
tWC
Read
tRC
Read
tRC
DA2
(555H)
DA2
(PA)
DA2
(PA)
Address
DA1
DA1
DA1
tAS
tAS
tAH
tAA
tCE
tAHT
CE
OE
tOE
t
CEPH
tDF
tOES
tOEH2
tWP
WE
DQ
t
DF
t
DH
tDS
Valid
Output
Valid
Input
Valid
Output
Valid
Input
Valid
Output
Status
(A0H)
(PD)
Note : This is an example in the program-case of the Read While Write function.
DA1 : Address of Bank1, DA2 : Address of Bank 2
PA = Program Address at one bank , RA = Read Address at the other bank, PD = Program Data In , RD = Read Data Out
-7
-8
-9
Parameter
Symbol
Unit
Min
70
35
25
0
Max
Min
80
35
25
0
Max
Min
90
45
30
0
Max
Write Cycle Time
tWC
tWP
tWPH
tAS
-
-
-
-
-
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Write Pulse Width
Write Pulse Width High
Address Setup Time
Address Hold Time
Data Setup Time
-
-
-
-
-
-
tAH
45
35
0
-
45
35
0
-
45
45
0
-
tDS
-
-
-
Data Hold Time
tDH
-
-
-
Read Cycle Time
tRC
70
-
-
80
-
-
90
-
-
Chip Enable Access Time
Address Access Time
Output Enable Access Time
OE Setup Time
tCE
70
70
25
-
80
80
25
-
90
90
35
-
tAA
-
-
-
tOE
-
-
-
tOES
tOEH2
tDF
0
0
0
OE Hold Time
10
-
-
10
-
-
10
-
-
CE & OE Disable Time
Address Hold Time
CE High during toggle bit polling
16
-
16
-
16
-
tAHT
tCEPH
0
0
0
20
-
20
-
20
-
37
Revision 1.7
September, 2006
K8D3x16UTC / K8D3x16UBC
NOR FLASH MEMORY
SWITCHING WAVEFORMS
Data Polling During Internal Routine Operation
CE
tDF
tOE
OE
tOEH2
WE
tCE
tOH
HIGH-Z
Data In
Data In
DQ7
*DQ7 = Valid Data
DQ7
tPGM or tBERS
HIGH-Z
DQ0-DQ6
Valid Data
Status Data
Note : *DQ7=Vaild Data (The device has completed the internal operation).
RY/BY Timing Diagram During Program/Erase Operation
CE
The rising edge of the last WE signal
WE
Entire progrming
or erase operation
RY/BY
tBUSY
-7
-8
-9
Parameter
Symbol
Unit
Min
90
-
Max
-
Min
90
-
Max
-
Min
90
-
Max
-
Program/Erase Valid to RY/BY Delay
Chip Enable Access Time
Output Enable Time
tBUSY
tCE
ns
ns
ns
ns
ns
ns
70
25
16
-
80
25
16
-
90
35
16
-
tOE
-
-
-
CE & OE Disable Time
tDF
-
-
-
Output Hold Time from Address, CE or OE
OE Hold Time
tOH
0
0
0
tOEH2
10
-
10
-
10
-
38
Revision 1.7
September, 2006
K8D3x16UTC / K8D3x16UBC
NOR FLASH MEMORY
SWITCHING WAVEFORMS
Toggle Bit During Internal Routine Operation
tAS
tAHT
Address*
tAHT
tASO
CE
tOEH2
tCEPH
WE
OE
tOEPH
tDH
tOE
Status
Status
Data
Status
Data
Data In
DQ6/DQ2
RY/BY
Array Data Out
Data
Note : Address for the write operation must include a bank address (A19~A20) where the data is written.
Enter
Embedded
Erasing
Erase
Suspend
Enter Erase
Suspend Program
Erase
Resume
Erase
Erase Suspend
Read
Erase Suspend
Read
Erase
Erase
Complete
WE
DQ6
DQ2
Erase
Suspend
Program
Toggle
DQ2 and DQ6
with OE or CE
Note : DQ2 is read from the erase-suspended block.
-7
-8
-9
Parameter
Symbol
Unit
Min
-
Max
Min
-
Max
Min
Max
Output Enable Access Time
OE Hold Time
tOE
tOEH2
tAHT
tASO
tAS
25
-
25
-
-
35
-
ns
ns
ns
ns
ns
ns
ns
ns
10
0
10
0
10
0
Address Hold Time
-
-
-
Address Setup
55
0
-
55
0
-
55
0
-
Address Setup Time
Data Hold Time
-
-
-
tDH
0
-
0
-
0
-
CE High during toggle bit polling
OE High during toggle bit polling
tCEPH
tOEPH
20
20
-
20
20
-
20
20
-
-
-
-
39
Revision 1.7
September, 2006
K8D3x16UTC / K8D3x16UBC
NOR FLASH MEMORY
SWITCHING WAVEFORMS
RESET Timing Diagram
High
RY/BY
CE or OE
RESET
t
RH
tRP
tREADY
Reset Timings NOT during Internal Routine
tREADY
RY/BY
tRB
CE or OE
tRP
RESET
Reset Timings during Internal Routine
Power-up and RESET Timing Diagram
tRSTS
RESET
Vcc
Address
DATA
tAA
-7
-8
-9
Parameter
RESET Pulse Width
Symbol
Unit
Min
Max
Min
Max
Min
Max
tRP
500
-
-
500
-
500
-
ns
RESET Low to Valid Data
(During Internal Routine)
tREADY
20
-
-
20
-
-
20
µs
RESET Low to Valid Data
(Not during Internal Routine)
tREADY
-
500
500
500
ns
RESET High Time Before Read
RY/BY Recovery Time
tRH
tRB
50
0
-
-
-
-
50
0
-
-
-
-
50
0
-
-
-
-
ns
ns
ns
ns
RESET High to Address Valid
RESET Low Set-up Time
tRSTW
tRSTS
200
500
200
500
200
500
40
Revision 1.7
September, 2006
K8D3x16UTC / K8D3x16UBC
NOR FLASH MEMORY
SWITCHING WAVEFORMS
Block Group Protect & Unprotect Operations
VID
RESET
Vss,VIL,
or VIH
Vss,VIL,
or VIH
BGA,A6
A1,A0
Valid
Valid
Valid
Verify
Block Group Protect / Unprotect
DATA
40H
Status*
60H
60H
Block Group Protect:150µs
Block Group UnProtect:15ms
1µs
CE
WE
tRB
OE
tBUSY
RY/BY
Notes : Block Group Protect (A6=VIL , A1=VIH , A0=VIL) , Status=01H
Block Group Unprotect (A6=VIH , A1=VIH, A0=VIL) , Status=00H
BGA = Block Group Address (A12 ~ A20)
Temporary Block Group Unprotect
VID
RESET
CE
Vss,VIL,
or VIH
Vss,VIL,
or VIH
WE
Program or Erase Command Sequence
tVID
tRSP
tRRB
tVID
RY/BY
41
Revision 1.7
September, 2006
K8D3x16UTC / K8D3x16UBC
NOR FLASH MEMORY
PACKAGE DIMENSIONS
48-PIN LEAD PLASTIC THIN SMALL OUT-LINE PACKAGE TYPE(I)
48 - TSOP1 - 1220F
Unit :mm/Inch
20.00±0.20
0.787±0.008
#1
#48
#24
#25
1.00±0.05
0.039±0.002
0.05
0.002
MIN
1.20
0.047
MAX
18.40±0.10
0.724±0.004
0~8’C
0.45~0.75
0.018~0.030
0.50
0.020
(
)
42
Revision 1.7
September, 2006
K8D3x16UTC / K8D3x16UBC
NOR FLASH MEMORY
PACKAGE DIMENSIONS
48-Ball Tape Ball Grid Array Package (measured in millimeters)
Top View
Bottom View
6.00±0.10
A
6.00±0.10
0.80 x 5=4.00
B
6
5
4
3
2
1
(Datum A)
(Datum B)
0.80
A
B
C
D
E
F
#A1
G
H
48-∅ 0.45±0.05
∅
0.20
M A B
2.00
Side View
0.45±0.05
0.08MAX
8.50±0.10
43
Revision 1.7
September, 2006
K8D3x16UTC / K8D3x16UBC
NOR FLASH MEMORY
PACKAGE DIMENSIONS
48-Ball Fine Ball Grid Array Package (measured in millimeters)
Top View
Bottom View
6.00±0.10
A
6.00±0.10
0.80 x 5=4.00
B
6
5
4
3
2
1
(Datum A)
(Datum B)
0.80
A
B
C
D
E
F
#A1
G
H
48-∅ 0.45±0.05
∅
0.20
M A B
2.00
Side View
0.45±0.05
0.08MAX
8.50±0.10
44
Revision 1.7
September, 2006
相关型号:
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