K9D1G08V0A-SSB00 [SAMSUNG]
Flash Card, 128MX8, 35ns, CARD-22;
| 型号： | K9D1G08V0A-SSB00 |
| 厂家： | 
SAMSUNG |
| 描述： | Flash Card, 128MX8, 35ns, CARD-22 内存集成电路 |
| 文件： | 总37页 (文件大小：657K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
K9D1G08V0M/A-SSB0
K9S1208V0M/A-SSB0
TM
SmartMedia
Document Title
64MB & 128MB SmartMediaTM Card
Revision History
Revision No History
Draft Date
Remark
0.0
0.1
Initial issue
Mar. 30th 2001
Apr. 7th 2001
Preliminary
1. Changed DC characteristics
Parameter
Min
Typ
10
Max
Unit
Sequential Read
Operating
-
-
-
20->30
20->30
20->30
Current
Program
10
mA
Erase
10
2. Added tDBSY parameter
3. Removed Copy-Back program command
4. Changed AC characteristics
Parameter
Symbol
Min
Max
Unit
ALE to RE Delay
( ID read )
tAR1
100->10
-
ns
0.2
Sep. 7th 2001
1.Powerup sequence is added
Recovery time of minimum 1ms is required before internal circuit gets
ready for any command sequences
~ 2.5V
~ 2.5V
V
CC
Hgh
WP
WE
1ms
2. AC parameter tCLR(CLE to RE Delay, min 50ns) is added.
3. Changed AC characteristics
(Before)
Parameter
Symbol
tAR1
Min
Max
-
Unit
ALE to RE Delay (ID read)
ALE to RE Delay (Read
RE Low to Status Output
CE Low to Status Output
RE access time(Read ID)
100
tAR2
100
-
ns
tRSTO
tCSTO
tREADID
-
-
-
35
45
35
Note : For more detailed features and specifications including FAQ, please refer to Samsung’s Flash web site.
http://www.samsung.com/Products/Semiconductor/Flash/TechnicalInfo/datasheets.
The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the
right to change the specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions about device. If you
have any questions, please contact the SAMSUNG branch office near your office.
1
K9D1G08V0M/A-SSB0
K9S1208V0M/A-SSB0
TM
SmartMedia
Revision History
Revision No History
- AC characteristics (After)
Draft Date
Remark
Sep. 7th 2001
Final
. Deleted tRSTO, tCSTO and tREADID / Added tCLR, tCEA
Parameter
ALE to RE Delay (ID read)
ALE to RE Delay (Read cycle)
CLE to RE Delay
Symbol
tAR1
Min
50
50
10
-
Max
Unit
-
-
tAR2
ns
tCLR
CE Access Time
tCEA
45
CLE
CE
tCR
WE
ALE
RE
tAR
tREA
90h
I/O0~7
00h
ECh
Maker code
Address. 1cycle
CLE
CE
tCEA
WE
tAR
ALE
RE
tWHR
tREA
90h
I/O0~7
00h
ECh
Maker code
Address. 1cycle
Note : For more detailed features and specifications including FAQ, please refer to Samsung Flash web site.
http://www.samsung.com/Products/Semiconductor/Flash/TechnicalInfo/datasheets.htm
The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the
right to change the specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions about device. If you
have any questions, please contact the SAMSUNG branch office near your office.
2
K9D1G08V0M/A-SSB0
K9S1208V0M/A-SSB0
TM
SmartMedia
Revision History
Revision No History
Draft Date
Remark
tCLS
CLE
tCLS
tCS
tCLH
tCH
CE
tWP
WE
tCSTO
tCHZ
tWHR
RE
tDH
tDS
tRSTO
tIR
tRHZ
I/O0~7
Status Output
70h
tCLS
CLE
CE
tCLS
tCS
tCLH
tCH
tWP
WE
tCEA
tCHZ
tWHR
RE
tDH
tREA
tDS
70h
tIR
tRHZ
I/O0~7
Status Output
1. Eliminated the duplicated AC parameter.
- AC characteristics (Before)
0.3
Feb. 9th 2002
Final
. Replaced tAR1,tAR2 with tAR
Parameter
ALE to RE Delay (ID read)
ALE to RE Delay (Read cycle)
CLE to RE Delay
Symbol
tAR1
Min
Max
Unit
50
50
10
-
-
-
tAR2
ns
tCLR
CE Access Time
tCEA
45
- AC characteristics (After)
Parameter
Symbol
tAR
Min
10
10
-
Max
Unit
ALE to RE Delay
CLE to RE Delay
CE Access Time
-
tCLR
ns
tCEA
45
The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the
right to change the specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions about device. If you
have any questions, please contact the SAMSUNG branch office near your office.
3
K9D1G08V0M/A-SSB0
K9S1208V0M/A-SSB0
TM
SmartMedia
64MB & 128MB SmartMediaTM Card
FEATURES
GENERAL DESCRIPTION
•Single 2.7V~3.6V Supply
•Organization
- Memory Cell Array :
Using Nand flash memory, SmartMedia provides the most cost-
effective solution for the solid state mass storage market. A pro-
gram operation is implemented by the single page of 528 bytes
in typical 200ms and an erase operation is done by the single
block of 16K bytes in typical 2ms. Data in the page can be read
out at 50ns cycle time per byte. The I/O pins serve as the ports
for address and data input/output as well as command inputs.
The on-chip write controller automates all program and erase
functions including pulse repetition, where required, and inter-
nal verification and margining of data. Even the write-intensive
systems can take advantage of the K9D1G08V0X,
K9S1208V0X¢s extended reliability of 100K program/erase
cycles by providing ECC(Error Correcting Code) with real time
mapping-out algorithm. SmartMedia is an optimum solution for
large nonvolatile storage applications such as solid state file
storage, digital voice recorder, digital still camera and other por-
table applications requiring non-volatility.
- K9S1208V0X: (64M + 2,048K)bit x 8bit
- K9D1G08V0X: (128M + 4,096K)bit x 8bit
- Data Register : (512 + 16)bit x8bit
•Automatic Program and Erase
- Page Program : (512 + 16)Byte
* Multi Page Program : 2K Bytes
- Block Erase : (16K + 512)Byte
•528-Byte Page Read Operation
- Random Access : 12ms(Max.)
- Serial Page Access : 50ns(Min.)
•Fast Write Cycle Time
- Program Time : 200ms(Typ.)
- Block Erase Time : 2ms(Typ.)
•Command/Address/Data Multiplexed I/O Port
•Hardware Data Protection
- Program/Erase Lockout During Power Transitions
•Reliable CMOS Floating-Gate Technology
- Endurance : 100K Program/Erase Cycles
- Data Retention : 10 Years
•Command Register Operation
TM
•22pad SmartMedia (SSFDC)
•Unique ID for Copyright Protection
TM
SmartMedia CARD(SSFDC)
PIN DESCRIPTION
Pin Name
I/O0 ~ I/O7
CLE
Pin Function
Data Input/Outputs
12
22
22 VCC
21 CE
20 RE
19 R/B
18 GND
17 LVD
16 I/O7
15 I/O6
14 I/O5
13 I/O4
12 VCC
1
2
3
4
5
6
7
8
9
VSS
Command Latch Enable
Address Latch Enable
Chip Enable
CLE
ALE
WE
WP
I/O0
I/O1
I/O2
I/O3
ALE
CE
RE
Read Enable
11
1
WE
Write Enable
WP
Write Protect
ID 128MB
LVD
Low Voltage Detect
Ground
GND
R/B
10 VSS
11 VSS
Ready/Busy output
Power
VCC
22 PAD SmartMediaTM
VSS
Ground
N.C
No Connection
NOTE : Connect all VCC and VSS pins of each device to common power supply outputs and do not leave VCC or VSS disconnected.
The pin 17(LVD) is used to detect 5V or 3.3V product electrically. Please, refer to the SmartMedia Application note for detail.
4
K9D1G08V0M/A-SSB0
K9S1208V0M/A-SSB0
TM
SmartMedia
Figure 1. FUNCTIONAL BLOCK DIAGRAM
A25: K9S1208V0X
A26: K9D1G08V0X
VCC
VSS
K9S1208V0X : 512M + 16M Bit
K9D1G08V0X : 1,024M + 32M Bit
X-Buffers
A9 - A26
Latches
NAND Flash
ARRAY
& Decoders
Y-Buffers
A0 - A7
K9S1208V0X : (512+16)Byte x 131,072
K9D1G08V0X : (512+16)Byte x 262,144
Latches
& Decoders
Page Register & S/A
Y-Gating
A8
Command
Command
Register
VCC
VSS
I/O Buffers & Latches
CE
RE
WE
Control Logic
& High Voltage
Generator
I/0 0
I/0 7
Output
Driver
Global Buffers
CLE ALE
WP
5
K9D1G08V0M/A-SSB0
K9S1208V0M/A-SSB0
TM
SmartMedia
Figure 2. ARRAY ORGANIZATION
Pages
K9D1G08V0X : 256K Pages(=8,192 Blocks)
K9S1208V0X : 128K Pages(=4,096 Blocks)
1st half Page Register
(=256 Bytes)
2nd half Page Register
(=256 Bytes)
8 bit
512B Byte
16 Byte
16 Byte
I/O 0 ~ I/O 7
Page Register
512 Byte
ARRAY ORGANIZATION
1 Page
1 Block
1 Device
K9D1G08V0X
K9S1208V0X
528 Byte
528 Byte
528 Byte x 32 Pages
528 Byte x 32 Pages
528Byte x 32Pages x 8,192 Blocks
528Byte x 32Pages x 4,096 Blocks
NOTE : Column Address : Starting Address of the Register.
I/O 0
A0
I/O 1
A1
I/O 2
A2
I/O 3
I/O 4
A4
I/O 5
A5
I/O 6
I/O 7
A7
1st Cycle
2nd Cycle
3rd Cycle
4th Cycle
A3
A12
A20
*L
A6
A15
A23
*L
Column Address
A9
A10
A18
A26
A11
A19
*L
A13
A21
*L
A14
A22
*L
A16
A24
*L
Row Address
(Page Address)
A17
A25
00h Command (Read) : Defines the starting address of the 1st half of the register.
01h Command (Read) : Defines the starting address of the 2nd half of the register.
A25: K9S1208V0X should be designated up to A25, address A26 must be set to "Low".
A26: K9D1G08V0X should be designated up to A26.
* A8 is set to "Low" or "High" by the 00h or 01h Command.
* "L" must be set to "Low".
* The device ignores any additional input of address cycles than required.
6
K9D1G08V0M/A-SSB0
K9S1208V0M/A-SSB0
TM
SmartMedia
Product Introduction
The SmartMeida has the memory organization as following Table1. Spare sixteen columns are located from column address of 512 to
527. A 528-byte data register is connected to memory cell arrays and is accommodating data-transfer between the I/O buffers and
memory cell arrays during page read and page program operations. The memory array is made up of 16 cells that are serially con-
nected to form a NAND structure. Each of the 16 cells resides in a different page. A block consists of the 32 pages formed by two 16
cell memory array. The array organization is shown in Figure 2. The program and the read operations are executed on a page basis,
while the erase operation is executed on a block basis.
The SmartMedia has addresses multiplexed into 8 I/O's. This scheme dramatically reduces pin counts and allows system upgrade to
future densities by maintaining consistency in system board design. Command, address and data are all written through I/O's by
bringing WE to low while CE is low. Data is latched on the rising edge of WE. Command Latch Enable(CLE) and Address Latch
Enable(ALE) are used to multiplex command and address respectively, via the I/O pins. The 128M byte and 64M byte physical space
requires 26 and 25 addresses, thereby requiring four cycles for byte-level addressing; column address, row address, in that order.
Page Read and Page Program need the same four address cycles following the required command input. In Block Erase operation,
however, only the three row address cycles are used. Device operations are selected by writing specific commands into the command
register. Table 2 defines the specific commands of the SmarMedia.
The device provides simultaneous program/erase capability up to four pages/blocks. By dividing the memory array into eight 128Mbit
separate planes, simultaneous multi-plane operation dramatically increases program/erase performance by 4X while still maintaining
the conventional 512 byte structure.
The extended pass/fail status for multi-plane program/erase allows system software to quickly identify the failing page/block out of
selected multiple pages/blocks. Usage of multi-plane operations will be described further throughout this document.
Table 1. MEMORY ORGANIZATION
Memory Organization
Number of rows(Pages)
Number of columns
528Mbit
(553,648,218 bit)
K9S1208V0X
K9D1G08V0X
131,072 rows
528 columns
1,056M bit
(1,107,296,436 bit)
262,144 rows
528 columns
Table2. Command Sets
Function
1st. Cycle
00h/01h(1)
50h
2nd. Cycle
3rd. Cycle
Acceptable Command during
Read 1
-
-
-
-
-
-
-
-
-
-
-
-
-
Read 2
Read ID
90h
-
Reset
FFh
-
O
Page Program (True)
Page Program (Dummy)
Page Program (Multi Block Program)
Block Erase
80h
10h
11h
15h
D0h
D0h
-
80h
80h
60h
Multi-Plane Block Erase
Read Status
60h---60h
70h
O
O
71h(2)
Read Multi-Plane Status
-
NOTE : 1. The 00h command defines starting address of the 1st half of registers.The 01h command defines starting address of the 2nd half of registers.
After data access on the 2nd half of register by the 01h command, the address pointer is automatically moved to the 1st half register(00h) on
the next cycle.
2. Any undefind commands are prohibited, which are not mentioned above command set table.
7
K9D1G08V0M/A-SSB0
K9S1208V0M/A-SSB0
TM
SmartMedia
Figure 3. Memory Array Map
K9D1G08V0X-SSBO
The device is arranged in eight 128Mbit memory planes. Each plane contains 1,024 blocks and 528 byte page registers. This allows
it to perform simultaneous page program and block erase by selecting one page or block from each plane. The block address map is
configured so that multi-plane program/erase operations can be executed for every four sequential blocks by dividing the memory
array into plane 0~3 or plane 4~7 separately. For example, multi-plane program/erase operations into plane 2,3,4 and 5 are prohib-
ited.
Plane 3
(1024 Block)
Plane 2
(1024 Block)
Plane 1
Plane 0
(1024 Block)
(1024 Block)
Block 0
Block 2
Block 3
Block 1
Page 0
Page 1
Page 0
Page 1
Page 0
Page 1
Page 0
Page 1
Page 30
Page 31
Page 30
Page 31
Page 30
Page 31
Page 30
Page 31
Block 4092
Block 4094
Block 4095
Block 4093
Page 0
Page 1
Page 0
Page 1
Page 0
Page 1
Page 0
Page 1
Page 30
Page 31
Page 30
Page 31
Page 30
Page 31
Page 30
Page 31
528byte Page Registers
528byte Page Registers
528byte Page Registers
528byte Page Registers
Plane 3
Plane 2
Plane 1
Plane 0
(1024 Block)
(1024 Block)
(1024 Block)
(1024 Block)
Block 0
Block 2
Block 3
Block 1
Page 0
Page 1
Page 0
Page 1
Page 0
Page 1
Page 0
Page 1
Page 30
Page 31
Page 30
Page 31
Page 30
Page 31
Page 30
Page 31
Block 4092
Block 4094
Block 4095
Block 4093
Page 0
Page 1
Page 0
Page 1
Page 0
Page 1
Page 0
Page 1
Page 30
Page 31
Page 30
Page 31
Page 30
Page 31
Page 30
Page 31
528byte Page Registers
528byte Page Registers
528byte Page Registers
528byte Page Registers
* K9S1208V0X-SSBO
The device is arranged in four 128Mbit memory planes. Each plane contains 1,024 blocks and 528 byte page registers. This allows it
to perform simultaneous page program and block erase by selecting one page or block from each plane. The block address map is
configured so that multi-plane program/erase operations can be executed for every four sequential blocks.
Plane 3
(1024 Block)
Plane 2
(1024 Block)
Plane 1
(1024 Block)
Plane 0
(1024 Block)
Block 0
Block 2
Block 3
Block 1
Page 0
Page 1
Page 0
Page 1
Page 0
Page 1
Page 0
Page 1
Page 30
Page 31
Page 30
Page 31
Page 30
Page 31
Page 30
Page 31
Block 4092
Block 4094
Block 4095
Block 4093
Page 0
Page 1
Page 0
Page 1
Page 0
Page 1
Page 0
Page 1
Page 30
Page 31
Page 30
Page 31
Page 30
Page 31
Page 30
Page 31
528byte Page Registers
528byte Page Registers
528byte Page Registers
528byte Page Registers
8
K9D1G08V0M/A-SSB0
K9S1208V0M/A-SSB0
TM
SmartMedia
PIN DESCRIPTION
Command Latch Enable(CLE)
The CLE input controls the path activation for commands sent to the command register. When active high, commands are latched
into the command register through the I/O ports on the rising edge of the WE signal.
Address Latch Enable(ALE)
The ALE input controls the activating path for address to the internal address registers. Addresses are latched on the rising edge of
WE with ALE high.
Chip Enable(CE)
The CE input is the device selection control. When CE goes high during a read operation the device is returned to standby mode.
However, when the device is in the busy state during program or erase, CE high is ignored and does not return the device to standby
mode.
Write Enable(WE)
The WE input controls writing to the I/O port. Commands, address and data are latched on the rising edge of the WE pulse.
Read Enable(RE)
The RE input is the serial data-out control, and when active drives the data onto the I/O bus.
I/O Port : I/O 0 ~ I/O 7
The I/O pins are used to input command, address and data, and to output data during read operations. The I/O pins float to high-z
when the chip is deselected or when the outputs are disabled.
Write Protect(WP)
The WP pin provides inadvertent write/erase protection during power transitions. The internal high voltage generator is reset when
the WP pin is active low.
Ready/Busy(R/B)
The R/B output indicates the status of the device operation. When low, it indicates that a program, erase or random read operation is
in process and returns to high state upon completion. It is an open drain output and does not float to high-z condition when the chip
is deselected or when outputs are disabled.
Low Voltage Detect(LVD)
The LVD is used to detect the proper supply voltage electrically. By connecting this pin to Vss through a pull-down resister, it is pos-
sible to distinguish 3.3V product from 5V product. When 3.3V is applied as Vcc to pins 12 and 22, a ’High’ level can be detected on
the system side if the device is a 3.3V product, and ’Low’ level for 5V product.
9
K9D1G08V0M/A-SSB0
K9S1208V0M/A-SSB0
TM
SmartMedia
ABSOLUTE MAXIMUM RATINGS
Parameter
Symbol
VIN
Rating
Unit
-0.6 to + 4.6
-0.6 to + 4.6
-10 to +65
-20 to +65
Voltage on any pin relative to VSS
V
VCC
Temperature Under Bias
Storage Temperature
TBIAS
TSTG
°C
°C
NOTE :
1. Minimum DC voltage is -0.3V on input/output pins. During transitions, this level may undershoot to -2.0V for periods <30ns.
Maximum DC voltage on input/output pins is VCC+0.3V which, during transitions, may overshoot to VCC+2.0V for periods <20ns.
2. Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to the conditions
as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
RECOMMENDED OPERATING CONDITIONS
(Voltage reference to GND, TA=0 to 55°C)
Parameter
Supply Voltage
Supply Voltage
Symbol
VCC
Min
2.7
0
Typ.
3.3
0
Max
3.6
0
Unit
V
VSS
V
DC AND OPERATING CHARACTERISTICS(Recommended operating conditions otherwise noted.)
Parameter
Sequential Read
Program
Symbol
ICC1
ICC2
ICC3
ISB1
ISB2
ILI
Test Conditions
Min
Typ
10
10
10
-
Max
30
Unit
tRC=50ns, CE=VIL, IOUT=0mA
-
-
-
-
-
-
Operating
Current
-
-
30
mA
Erase
30
Stand-by Current(TTL)
Stand-by Current(CMOS)
Input Leakage Current
Output Leakage Current
CE=VIH, WP=0V/VCC
CE=VCC-0.2, WP=0V/VCC
VIN=0 to 3.6V
1
10
-
50
±10
mA
ILO
VOUT=0 to 3.6V
-
-
±10
Input High Voltage, All inputs
Input Low Voltage, All inputs
Output High Voltage Level
Output Low Voltage Level
Output Low Current(R/B)
VIH
VIL
-
-
2.0
-0.3
2.4
-
-
-
VCC+0.3
0.8
-
V
VOH
VOL
IOH=-400mA
IOL=2.1mA
-
-
0.4
-
IOL(R/B) VOL=0.4V
8
10
mA
10
K9D1G08V0M/A-SSB0
K9S1208V0M/A-SSB0
TM
SmartMedia
VALID BLOCK
Parameter
Symbol
NVB
Min
Typ.
Max
8,192
4,096
Unit
K9D1G08V0X
8,052
4,026
-
-
Blocks
Blocks
Valid Block Number
K9S1208V0X
NVB
1. The K9D1G08V0X, K9S1208V0X may include invalid blocks when first shipped. Additional invalid blocks may develop while being used. The num-
ber of valid blocks is presented with both cases of invalid blocks considered. Invalid blocks are defined as blocks that contain one or more bad bits. Do
not erase or program factory-market bad blocks. Refer to the attached technical notes for an appropriate management of invalid blocks.
2. Per the specification of the physical format version 1.2 by SSFDC forum, minimum 1,000 vaild blocks are guaranteed for each 16MB memory space.
AC TEST CONDITION
(TA=0 to 55°C, VCC=2.7V~3.6V unless otherwise noted)
Parameter
Value
0.4V to 2.4V
Input Pulse Levels
Input Rise and Fall Times
Input and Output Timing Levels
Output Load (3.0V +/-10%)
Output Load (3.3V +/-10%)
5ns
1.5V
1 TTL GATE and CL=50pF
1 TTL GATE and CL=100pF
CAPACITANCE(TA=25°C, VCC=3.3V, f=1.0MHz)
Max
Item
Symbol
Test Condition
Min
Unit
K9D1G08V0X
K9S1208V0X
Input/Output Capacitance
Input Capacitance
CI/O
CIN
VIL=0V
VIN=0V
-
-
20
20
10
10
pF
pF
NOTE : Capacitance is periodically sampled and not 100% tested.
MODE SELECTION
CLE
H
L
ALE
L
CE
L
WE
RE
H
WP
Mode
X
Command Input
Read Mode
Write Mode
H
L
H
X
Address Input(4clock)
Command Input
H
L
L
L
H
H
H
L
H
H
Address Input(4clock)
L
L
L
H
H
Data Input
L
L
L
H
X
X
X
X
X
X
sequential Read & Data Output
During Read(Busy)
During Program(Busy)
During Erase(Busy)
Write Protect
X
X
L
X
X
X
X
X
X
X
X
X
X
X
H
H
X
X
H
L
X(1)
X
X
(2)
X
Stand-by
0V/VCC
NOTE : 1. X can be VIL or VIH.
2. WP should be biased to CMOS high or CMOS low for standby.
11
K9D1G08V0M/A-SSB0
K9S1208V0M/A-SSB0
TM
SmartMedia
Program / Erase Characteristics
Parameter
Program Time
Symbol
tPROG
Min
Typ
Max
500
10
1
Unit
-
200
ms
ms
Dummy Busy Time for Multi Plane Program
tDBSY
1
-
Main Array
Spare Array
-
-
-
cycle
cycles
ms
Number of Partial Program Cycles
in the Same Page
Nop
-
2
Block Erase Time
tBERS
2
3
AC Timing Characteristics for Command / Address / Data Input
Parameter
Symbol
tCLS
tCLH
tCS
Min
Max
Unit
CLE setup Time
CLE Hold Time
CE setup Time
CE Hold Time
0
-
-
-
-
-
-
-
-
-
-
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
10
0
tCH
10
25(1)
0
WE Pulse Width
ALE setup Time
ALE Hold Time
Data setup Time
Data Hold Time
Write Cycle Time
tWP
tALS
tALH
tDS
10
20
10
50
15
tDH
tWC
WE High Hold Time
tWH
NOTE : 1. If tCS is set less than 10ns, tWP must be minimum 35ns, otherwise, tWP may be minimum 25ns.
AC Characteristics for Operation
Parameter
Data Transfer from Cell to Register
CLE to RE Delay
Symbol
tR
Min
-
Max
Unit
10
ms
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
tCLR
tAR
10
10
20
30
-
-
-
ALE to RE Delay
Ready to RE Low
tRR
-
RE Pulse Width
tRP
-
WE High to Busy
tWB
100
-
Read Cycle Time
tRC
50
-
RE Access Time
tREA
tRHZ
tCHZ
tREH
tIR
35
30
20
-
RE High to Output Hi-Z
15
-
CE High to Output Hi-Z
RE High Hold Time
15
0
Output Hi-Z to RE Low
-
Last RE High to Busy(at sequential read)
CE High to Ready(in case of interception by CE at read)
CE High Hold Time(at the last serial read)(2)
WE High to RE Low
tRB
-
100
50 +tr(R/B)(1)
tCRY
tCEH
tWHR
tRST
-
100
60
-
-
-
5/10/500(3)
Device Resetting Time(Read/Program/Erase)
NOTE : 1. The time to Ready depends on the value of the pull-up resistor tied R/B pin.
2. To break the sequential read cycle, CE must be held high for longer time than tCEH.
3. If reset command(FFh) is written at Ready state, the device goes into Busy for maximum 5us.
12
K9D1G08V0M/A-SSB0
K9S1208V0M/A-SSB0
TM
SmartMedia
SmartMedia Technical Notes
Invalid Block(s)
Invalid blocks are defined as blocks that contain one or more invalid bits whose reliability is not guaranteed by Samsung. The informa-
tion regarding the invalid block(s) is so called as the invalid block information. An invalid block(s) does not affect the performance of
valid block(s) because it is isolated from the bit line and the common source line by a select transistor. The system design must be
able to mask out the invalid block(s) via address mapping.
Identifying Invalid Block(s)
SSFDC Forum specifies the logical format and physical format to ensure compatibility of SmartMedia. Samsung pre-formats Smart-
Media in the Forum-compliant format prior to shipping. The physical format standard by SSFDC Forum specifies that invalid block
information is written at the 6th byte of spare area in invalid blocks with two or more "0" bits, while valid blocks are erased(FFh).
Since the invalid block information is also erasable in most cases, it is impossible to recover the information once it has been erased.
Therefore, the system must be able to recognize the invalid block(s) based on the original invalid block information and create the
invalid block table via the following suggested flow chart(Figure 4). Any intentional erasure of the original invalid block information is
prohibited.
Start
Set Block Address = 0
Increment Block Address
Check "FFh" at the column address 517
*
of the first page in the block
No
Create (or update)
Invalid Block(s) Table
Check "FFh" ?
Yes
No
Last Block ?
Yes
End
Figure 4. Flow chart to create invalid block table.
13
K9D1G08V0M/A-SSB0
K9S1208V0M/A-SSB0
TM
SmartMedia
SmartMedia Technical Notes (Continued)
Error in write or read operation
Over its life time, the additional invalid blocks may develop with NAND Flash memory. Refer to the qualification report for the actual
data.The following possible failure modes should be considered to implement a highly reliable system. In the case of status read fail-
ure after erase or program, block replacement should be done. Because program status fail during a page program does not affect the
data of the other pages in the same block, block replacement can be executed with a page-sized buffer by finding an erased empty
block and reprogramming the current target data and copying the rest of the replaced block. To improve the efficiency of memory
space, it is recommended that the read or verification failure due to single bit error be reclaimed by ECC without any block replace-
ment. The said additional block failure rate does not include those reclaimed blocks.
Failure Mode
Detection and Countermeasure sequence
Erase Failure
Status Read after Erase --> Block Replacement
Status Read after Program --> Block Replacement
Read back ( Verify after Program) --> Block Replacement
or ECC Correction
Write
Read
Program Failure
Single Bit Failure
Verify ECC -> ECC Correction
: Error Correcting Code --> Hamming Code etc.
Example) 1bit correction & 2bit detection
ECC
Program Flow Chart
If ECC is used, this verification
operation is not needed.
Start
Write 80h
Write 00h
Write Address
Wait for tR Time
Write Address
Write Data
Write 10h
*
No
Program Error
Verify Data
Read Status Register
Yes
Program Completed
No
I/O 6 = 1 ?
or R/B = 1 ?
: If program operation results in an error, map out
the block including the page in error and copy the
target data to another block.
*
Yes
*
No
Program Error
I/O 0 = 0 ?
Yes
14
K9D1G08V0M/A-SSB0
K9S1208V0M/A-SSB0
TM
SmartMedia
SmartMedia Technical Notes (Continued)
Erase Flow Chart
Read Flow Chart
Start
Start
Write 60h
Write 00h
Write Block Address
Write Address
Read Data
Write D0h
Read Status Register
ECC Generation
No
No
I/O 6 = 1 ?
or R/B = 1 ?
Reclaim the Error
Verify ECC
Yes
Yes
*
Page Read Completed
No
Erase Error
I/O 0 = 0 ?
Yes
Erase Completed
: If erase operation results in an error, map out
the failing block and replace it with another block.
*
Block Replacement
Block A
1st
2
{
(n-1)th
nth
(page)
Buffer memory of the controller.
Block B
1st
1
{
(n-1)th
nth
(page)
* Step1
When an error happens in the nth page of the Block ’A’ during the program operation.
* Step2
Copy the nth page data of the Block ’A’ in the buffer memory to the nth page of another free block. (Block ’B’)
* Step3
Then, copy the data in the 1st ~ (n-1)th page of the Block ’A’ to the same location of the Block ’B’.
* Step4
Do not erase or program to Block ’A’ by creating an ’invalid Block’ table or using other appropriate scheme.
15
K9D1G08V0M/A-SSB0
K9S1208V0M/A-SSB0
TM
SmartMedia
Pointer Operation of K9D1G08V0X, K9S1208V0X
Samsung NAND Flash has three address pointer commands as a substitute for the two most significant column addresses. ’00h’
command sets the pointer to ’A’ area(0~255byte), ’01h’ command sets the pointer to ’B’ area(256~511byte), and ’50h’ command sets
the pointer to ’C’ area(512~527byte). With these commands, the starting column address can be set to any of a whole
page(0~527byte). ’00h’ or ’50h’ is sustained until another address pointer command is inputted. ’01h’ command, however, is effective
only for one operation. After any operation of Read, Program, Erase, Reset, Power_Up is executed once with ’01h’ command, the
address pointer returns to ’A’ area by itself. To program data starting from ’A’ or ’C’ area, ’00h’ or ’50h’ command must be inputted
before ’80h’ command is written. A complete read operation prior to ’80h’ command is not necessary. To program data starting from
’B’ area, ’01h’ command must be inputted right before ’80h’ command is written.
Destination of the pointer
"A" area
(00h plane)
"B" area
(01h plane)
"C" area
(50h plane)
Command
Pointer position
Area
00h
01h
50h
0 ~ 255 byte
256 ~ 511 byte
512 ~ 527 byte
1st half array(A)
2nd half array(B)
spare array(C)
256 Byte
256 Byte
16 Byte
"A"
"B"
"C"
Internal
Page Register
Pointer select
commnad
(00h, 01h, 50h)
Pointer
Figure 5. Block Diagram of Pointer Operation
(1) Command input sequence for programming ’A’ area
The address pointer is set to ’A’ area(0~255), and sustained
Address / Data input
Address / Data input
80h 10h
00h
80h
10h
00h
’A’,’B’,’C’ area can be programmed.
’00h’ command can be omitted.
It depends on how many data are inputted.
(2) Command input sequence for programming ’B’ area
The address pointer is set to ’B’ area(256~512), and will be reset to
’A’ area after every program operation is executed.
Address / Data input
Address / Data input
80h 10h
01h
80h
10h
01h
’B’, ’C’ area can be programmed.
It depends on how many data are inputted.
’01h’ command must be rewritten before
every program operation
(3) Command input sequence for programming ’C’ area
The address pointer is set to ’C’ area(512~527), and sustained
Address / Data input
Address / Data input
80h 10h
50h
80h
10h
50h
Only ’C’ area can be programmed.
’50h’ command can be omitted.
16
K9D1G08V0M/A-SSB0
K9S1208V0M/A-SSB0
TM
SmartMedia
System Interface Using CE don’t-care.
For an easier system interface, CE may be inactive during the data-loading or sequential read as shown below. The internal 528byte
page registers are utilized as separate buffers for this operation and the system design gets more flexible. In addition, for voice or
audio applications which use slow cycle time on the order of u-seconds, de-activating CE during the data-loading and reading would
provide significant savings in power consumption.
Figure 6. Program Operation with CE don’t-care.
CLE
CE don’t-care
CE
WE
ALE
80h
Start Add.(4Cycle)
Data Input
Data Input
10h
I/O0~7
tCS
tCH
tCEA
CE
RE
CE
tREA
tWP
WE
I/O0~7
out
Figure 7. Read Operation with CE don’t-care.
CLE
CE don’t-care
Must be held
low during tR.
CE
RE
ALE
tR
R/B
WE
Data output (Sequential)
I/O0~7
00h
Start Add.(4Cycle)
17
K9D1G08V0M/A-SSB0
K9S1208V0M/A-SSB0
TM
SmartMedia
Command Latch Cycle
CLE
tCLH
tCH
tCLS
tCS
CE
tWP
WE
tALS
tALH
ALE
tDH
tDS
Command
I/O0~7
Address Latch Cycle
tCLS
CLE
tCS
tWC
tWC
tWC
CE
tWP
tWP
tWP
tWP
WE
tWH
tALH tALS
tWH
tALH tALS
tWH
tALH tALS
tALH
tDH
tALS
ALE
tDH
tDH
tDH
tDS
tDS
tDS
tDS
A0~A7
A9~A16
I/O0~7
A17~A24
A25,A26
A25: K9S1208V0X
A26: K9D1G08V0X
18
K9D1G08V0M/A-SSB0
K9S1208V0M/A-SSB0
TM
SmartMedia
Input Data Latch Cycle
tCLH
CLE
tCH
CE
tWC
tALS
ALE
tWP
tWP
tWP
WE
tWH
tDH
tDH
tDH
tDS
tDS
tDS
I/O0~7
DIN 1
DIN 511
DIN 0
Serial Access Cycle after Read (CLE=L, WE=H, ALE=L)
tRC
CE
tREH
tCHZ
tRHZ
tREA
tREA
tRP
tREA
RE
tRHZ
I/O0~7
R/B
Dout
Dout
Dout
tRR
NOTES : Transition is measured ±200mV from steady state voltage with load.
This parameter is sampled and not 100% tested.
19
K9D1G08V0M/A-SSB0
K9S1208V0M/A-SSB0
TM
SmartMedia
Status Read Cycle
tCLR
CLE
CE
tCLS
tCS
tCLH
tCH
tWP
WE
tCEA
tCHZ
tWHR
RE
tDH
tREA
tDS
tIR
tRHZ
Status Output
I/O0~7
70h
READ1 OPERATION(READ ONE PAGE)
CLE
tCEH
CE
tCHZ
tWC
WE
ALE
RE
tWB
tCRY
tAR
tRHZ
tR
tRC
tRR
A9 ~ A16
A17 ~ A24
Dout N+2
00h or 01h A0 ~ A7
Dout N
N+1
Dout 527
tRB
A25,A26
I/O0~7
R/B
Column
Address
Page(Row)
Address
Busy
A25: K9S1208V0X
A26: K9D1G08V0X
20
K9D1G08V0M/A-SSB0
K9S1208V0M/A-SSB0
TM
SmartMedia
READ1 OPERATION (INTERCEPTED BY CE)
CLE
CE
WE
ALE
RE
tWB
tCHZ
tAR
tR
tRC
tRR
A9 ~ A16 A17 ~ A24
Dout N+2
00h or 01h A0 ~ A7
Dout N
Dout N+1
A25,A26
I/O0~7
R/B
Column
Address
Page(Row)
Address
Busy
A25: K9S1208V0X
A26: K9D1G08V0X
READ2 OPERATION(READ ONE PAGE)
CLE
CE
WE
ALE
RE
tR
tWB
tAR
tRR
Dout
50h
A9 ~ A16 A17 ~ A24
Dout 527
511+M
A0 ~ A7
A25,A26
I/O0~7
R/B
A25: K9S1208V0X
A26: K9D1G08V0X
Selected
Row
M Address
A0~A3 : Valid Address
A4~A7 : Don¢t care
16
512
Start
address M
21
K9D1G08V0M/A-SSB0
K9S1208V0M/A-SSB0
TM
SmartMedia
SEQUENTIAL ROW READ OPERATION (WITHIN A BLOCK)
CLE
CE
WE
ALE
RE
A25: K9S1208V0X
A26: K9D1G08V0X
Dout
N
Dout
N+1
Dout
527
Dout
0
Dout
1
Dout
527
00h
A0 ~ A7 A9 ~ A16
A17 ~ A24
A25,A26
I/O0~7
R/B
Ready
Busy
Busy
M
M+1
Output
N
Output
PAGE PROGRAM OPERATION
CLE
CE
tWC
tWC
tWC
WE
ALE
RE
tPROG
tWB
Din
N
Din
527
A25,A26
10h
80h
A0 ~ A7 A9 ~ A16 A17 ~ A24
70h
I/O0
I/O0~7
R/B
Sequential Data Column
Input Command Address
Program
Command
1 up to 528 Byte Data
Serial Input
Read Status
Command
Page(Row)
Address
A25: K9S1208V0X
A26: K9D1G08V0X
I/O0=0 Successful Program
I/O0=1 Error in Program
22
K9D1G08V0M/A-SSB0
K9S1208V0M/A-SSB0
TM
SmartMedia
BLOCK ERASE OPERATION (ERASE ONE BLOCK)
CLE
CE
tWC
WE
tBERS
tWB
ALE
RE
60h
A9 ~ A16 A17 ~ A24
DOh
70h
I/O 0
A25,A26
I/O0~7
R/B
Page(Row)
Address
Busy
A25: K9S1208V0X
A26: K9D1G08V0X
I/O0=0 Successful Erase
Auto Block Erase Setup Command
Erase Command
Read Status I/O0=1 Error in Erase
Command
23
K9D1G08V0M/A-SSB0
K9S1208V0M/A-SSB0
TM
SmartMedia
»
» »
»
»
» »
»
24
K9D1G08V0M/A-SSB0
K9S1208V0M/A-SSB0
TM
SmartMedia
Multi-Plane Block Erase Operation
CLE
CE
tWC
WE
tBERS
tWB
ALE
RE
A25: K9S1208V0X
A26: K9D1G08V0X
60h
A9 ~ A16 A17 ~ A24
DOh
71h
I/O 0
A25,A26
I/O0~7
R/B
Page(Row)
Address
Busy
Erase Confirm Command
Block Erase Setup Command
Read Multi-Plane
Status Command
Max. 4 times repeatable
* For Multi-Plane Erase operation, Block address to be erased should be repeated before "D0H" command.
Ex.) Four-Plane Block Erase Operation
R/B
tBERS
Address
D0h
60h
Address
Address
71h
60h
60h
Address
A9 ~ A26
60h
I/O0~7
A25: K9S1208V0X
A26: K9D1G08V0X
25
K9D1G08V0M/A-SSB0
K9S1208V0M/A-SSB0
TM
SmartMedia
Figure 8. Read ID Operation
tCLR
CLE
CE
tCEA
WE
ALE
RE
tAR
tREA
I/O0~7
90h
00h
Address. 1cycle
ECh
Maker code
79h
A5h
C0h
Multi Plane code
UniqueID code
Device code
K9S1208V0X : 76h
K9D1G08V0X : 79h
90 ID : Access command = 90H
READ ID (1)
Value
Description
1st Byte
2nd Byte
3rd Byte
4th Byte
ECh
Maker Code
76h/79h Device Code
A5h
C0h
Unique1D code
Multiplane Support
NOTE :
Device Code : K9S1208VOX(76h), KD1G08VOX(79h)
26
K9D1G08V0M/A-SSB0
K9S1208V0M/A-SSB0
TM
SmartMedia
Device Operation
PAGE READ
Upon initial device power up, the device defaults to Read1 mode. This operation is also initiated by writing 00h to the command regis-
ter along with four address cycles. Once the command is latched, it does not need to be written for the following page read operation.
Three types of operations are available : random read, sequential read and sequential row read.
The random read mode is enabled when the page address is changed. The 528 bytes of data within the selected page are transferred
to the data registers in less than 12ms(tR). The system controller can detect the completion of this data transfer(tR) by analyzing the
output of R/B pin. Once the data in a page is loaded into the registers, they may be read out in 50ns cycle time by pulsing RE sequen-
tially. High to low transitions of the RE clock output the data starting from the selected column address up to the last column address.
After the data of last column address is clocked out, the next page is automatically selected for sequential row read.
Waiting 12ms again allows reading the selected page. The sequential row read operation is terminated by bringing CE high. The way
the Read1 and Read2 commands work is like a pointer set to either the main area or the spare area. The spare area of bytes 512 to
527 may be selectively accessed by writing the Read2 command. Addresses A0 to A3 set the starting address of the spare area while
addresses A4 to A7 are ignored. Unless the operation is aborted, the page address is automatically incremented for sequential row
read as in Read1 operation and spare sixteen bytes of each page may be sequentially read. The Read1 command(00h/01h) is
needed to move the pointer back to the main area. Figures 9 to 12 show typical sequence and timings for each read operation.
Figure 9. Read1 Operation
CLE
CE
WE
ALE
tR
R/B
RE
00h
Start Add.(4Cycle)
A0 ~ A7 & A9 ~ A26
Data Output(Serial Access)
I/O0~7
A25: K9S1208V0X
A26: K9D1G08V0X
(00h Command)
(01h Command)*
1st half array 2st half array
1st half array 2st half array
Data Field
Spare Field
Data Field
Spare Field
* After data access on 2nd half array by 01h command, the start pointer is automatically moved to 1st half
array (00h) at next cycle.
27
K9D1G08V0M/A-SSB0
K9S1208V0M/A-SSB0
TM
SmartMedia
Figure 10. Read2 Operation
CLE
CE
WE
ALE
R/B
RE
tR
50h
Data Output(Serial Access)
Spare Field
Start Add.(4Cycle)
A0 ~ A3 & A9 ~ A26
I/O0~7
A25: K9S1208V0X
A26: K9D1G08V0X
(A4 ~ A7 :
Don¢t Care)
1st half array
2nd half array
Data Field
Spare Field
Figure 11. Sequential Row Read1 Operation
tR
tR
tR
R/B
Data Output
1st
Data Output
Data Output
I/O0 ~ 7
00h
01h
Start Add.(4Cycle)
A0 ~ A7 & A9 ~ A26
2nd
(528 Byte)
Nth
(528 Byte)
A25: K9S1208V0X
A26: K9D1G08V0X
(00h Command)
(01h Command)
1st half array
2nd half array
1st half array
2nd half array
1st
1st
2nd
Nth
2nd
Nth
Block
Data Field
Spare Field
Data Field
Spare Field
The Sequential Read 1 and Read 2 operations are allowed only within a block and after the last page of a block
is readout, the sequential read operation must be terminated by bringing CE high. When the page address
moves onto the next block, read command and address must be given.
28
K9D1G08V0M/A-SSB0
K9S1208V0M/A-SSB0
TM
SmartMedia
Figure 12. Sequential Row Read2 Operation
tR
tR
tR
R/B
Start Add.(4Cycle)
A0 ~ A3 & A9 ~ A26
Data Output
1st
A25: K9S1208V0X
A26: K9D1G08V0X
I/O0~7
50h
Data Output
Data Output
2nd
(16Byte)
Nth
(16Byte)
(A4 ~ A7 :
Don¢t Care)
1st
Block
Nth
Data Field
Spare Field
PAGE PROGRAM
The device is programmed basically on a page basis, but it does allow multiple partial page programing of a byte or consecutive bytes
up to 528, in a single page program cycle. The number of consecutive partial page programming operation within the same page with-
out an intervening erase operation must not exceed 1 for main array and 2 for spare array. However, it is advisable not to program
more often than recommend. It might cause failures due to disturbance when it exceeds its limits. The failure mode could be that the
data "1" of the erased cell might be changed into data"0"of the programmed cell.
The addressing may be done in any random order in a block. A page program cycle consists of a serial data loading period in which
up to 528 bytes of data may be loaded into the page register, followed by a non-volatile programming period where the loaded data is
programmed into the appropriate cell. Serial data loading can be started from 2nd half array by moving pointer. About the pointer
operation, please refer to the attached technical notes.
The serial data loading period begins by inputting the Serial Data Input command(80h), followed by the four cycle address input and
then serial data loading. The bytes other than those to be programmed do not need to be loaded.The Page Program confirm com-
mand(10h) initiates the programming process. Writing 10h alone without previously entering the serial data will not initiate the pro-
gramming process. The internal write-state controller automatically executes the algorithms and timings necessary for program and
verify, thereby freeing the system controller for other tasks. Once the program process starts, the Read Status Register command
may be entered, with RE and CE low, to read the status register. The system controller can detect the completion of a program cycle
by monitoring the R/B output, or the Status bit(I/O 6) of the Status Register. Only the Read Status command and Reset command are
valid while programming is in progress. When the Page Program is complete, the Write Status Bit(I/O 0) may be checked(Figure 13).
The internal write verify detects only errors for "1"s that are not successfully programmed to "0"s. The command register remains in
Read Status command mode until another valid command is written to the command register.
Figure 13. Program & Read Status Operation
tPROG
R/B
Pass
I/O0~7
80h
Address & Data Input
I/O0
Fail
10h
70h
A0 ~ A7 & A9 ~ A26
528 Byte Data
A25: K9S1208V0X
A26: K9D1G08V0X
29
K9D1G08V0M/A-SSB0
K9S1208V0M/A-SSB0
TM
SmartMedia
BLOCK ERASE
The Erase operation is done on a block(16K Byte) basis. Block address loading is accomplished in three cycles initiated by an Erase
Setup command(60h). Only address A14 to (A25: K9S1208V0X, A26: K9D1G08V0X), is valid while A9 to A13 is ignored. The Erase
Confirm command(D0h) following the block address loading initiates the internal erasing process. This two-step sequence of setup
followed by execution command ensures that memory contents are not accidentally erased due to external noise conditions.
At the rising edge of WE after the erase confirm command input, the internal write controller handles erase and erase-verify. When
the erase operation is completed, the Write Status Bit(I/O 0) may be checked. Figure 14 details the sequence.
Figure 14. Block Erase Operation
tBERS
R/B
Pass
I/O0~7
60h
I/O0
Fail
70h
Address Input(3Cycle)
Block Add. : A9 ~ A26
D0h
A25: K9S1208V0X
A26: K9D1G08V0X
MULTI-PLANE PAGE PROGRAM INTO PLANE 0~3 OR PLANE 4~7
Multi-Plane Page Program is an extension of Page Program which is executed for a single plane with 528 byte page registers. Since
the device is equipped with eight memory planes, activating the four sets of 528 byte page registers into plane 0~3 or plane 4~7
enables a simultaneous programming of four pages. Partial activation of four planes is also permitted.
After writing the first set of data up to 528 byte into the selected page register, Dummy Page Program command (11h) instead of
actual Page Program (10h) is inputted to finish data-loading of the current plane and move to the next plane. Since no programming
process is involved, R/B remains in Busy state for a short period of time(tDBSY). Read Status command (standard 70h or alternate
71h) may be issued to find out when the device returns to Ready state by polling the Ready/Busy status bit(I/O 6). Then the next set
of data for one of the other planes is inputted with the same command and address sequences. After inputting data for the last plane,
actual True Page Program (10h) instead of dummy Page Program command (11h) must be followed to start the programming pro-
cess. The operation of R/B and Read Status is the same as that of Page Program. Since maximum four pages are programmed
simultaneously, pass/fail status is available for each page when the program operation completes. The extended status bits (I/O1
through I/O 4) are checked by inputting the Read Multi-Plane Status Register. Status bit of I/O 0 is set to "1" when any of the pages
fails. Multi-Plane page Program with "01h" pointer is not supported, thus prohibited.
Figure 15. Four-Plane Page Program
tDBSY
tPROG
tDBSY
tDBSY
R/B
Address &
Data Input
Address &
Data Input
Address &
Data Input
A0 ~ A7 & A9 ~ A26
Address &
Data Input
10h
71h
80h
80h
11h
11h
80h
80h
11h
I/O0~7
80h
11h
11h
A25: K9S1208V0X
A26: K9D1G08V0X
528 Byte Data
10h
80h
80h
11h
80h
Data
input
Plane 3
(1024 Block)
Plane 0
(1024 Block)
Plane 2
(1024 Block)
Plane 1
(1024 Block)
Block 3
Block 7
Block 2
Block 6
Block 1
Block 5
Block 0
Block 4
Block 4091
Block 4095
Block 4090
Block 4094
Block 4089
Block 4093
Block 4088
Block 4092
30
K9D1G08V0M/A-SSB0
K9S1208V0M/A-SSB0
TM
SmartMedia
RESTRICTION IN ADDRESSING WITH PLANE-PLANE PAGE PROGRAM
While any block in each plane may be addressable for Multi-Plane Page Program, the four least significant addresses(A9-A13) for the
selected pages at one operation must be the same. Figure 15 shows an example where 2nd page of each addressed block is selected
for four planes. However, any arbitrary sequence is allowed in addressing multiple planes as shown in Figure16.
Figure 16. Multi-Plane Program & Read Status Operation
Plane 3
(1024 Block)
Plane 2
(1024 Block)
Plane 1
(1024 Block)
Plane 0
(1024 Block)
Block 0
Block 2
Block 3
Block 1
Page 0
Page 1
Page 0
Page 1
Page 0
Page 1
Page 0
Page 1
Page 30
Page 31
Page 30
Page 31
Page 30
Page 31
Page 30
Page 31
Figure 17. Addressing Multiple Planes
Plane 1
Plane3
80h
10h
Plane 2
Plane 0
80h
11h
80h
11h
80h
11h
Figure 18. Multi-Plane Page Program & Read Status Operation
tPROG
R/B
Last Plane input
Pass
I/O0~7
80h
Address & Data Input
I/O
10h
71h
A0 ~ A7 & A9 ~ A26
528 Byte Data
A25: K9S1208V0X
A26: K9D1G08V0X
Fail
The 15h command may be used as actual Page Program with 10h command. The pass/fail status data with 15h command are accu-
mulated until the programming with 10h command as shown in Figure 18. Note that program with 10h command should be executed
for the last pages of each four multi-plane blocks. Figure 18 shows an example when the 2nd page of plane 1 fails during multi-plane
page program and fail status("1") sets.
Figure 19. Multi-Plane Page Program Using 15h Command
Read Status Register Data by 71h Command
Plane 3
15h
I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7
Plane 0
11h
Plane 2
11h
Plane 1
11h
1st Page
80h
0
1
0
0
1
0
0
0
0
X
X
1
1
0
0
80h
80h
80h
80h
80h
80h
11h
2nd Page 80h
11h
11h
15h
0
"Fail"
Block N
31th Page
80h
11h
11h
11h
1
1
0
0
1
1
0
0
0
0
X
X
1
1
0
0
11h
11h
11h
11h
11h
11h
80h
80h
80h
15h
10h
15h
80h
80h
80h
80h
80h
80h
32nd Page
80h
1st Page
Block N+1
80h
0
0
0
0
0
X
1
0
- Please refer to "Read Status Register Definition"
of Table 2 on page 29.
- X means "don’t cared".
31
K9D1G08V0M/A-SSB0
K9S1208V0M/A-SSB0
TM
SmartMedia
MULTI-PLANE BLOCK ERASE INTO PLANE 0~3 OR PLANE 4~7
Basic concept of Multi-Plane Block Erase operation is identical to that of Multi-Plane Page Program. Up to four blocks, one from each
plane can be simultaneously erased. Standard Block Erase command sequences (Block Erase Setup command followed by three
address cycles) may be repeated up to four times for erasing up to four blocks. Only one block should be selected from each plane.
The Erase Confirm command initiates the actual erasing process. The completion is detected by analyzing R/B pin or Ready/Busy
status (I/O 6). Upon the erase completion, pass/fail status of each block is examined by reading extended pass/fail status (I/O 1
through I/O 4).
Figure 20. Four Block Erase Operation
R/B
tBERS
Address
(3 Cycle)
Address
(3 Cycle)
Address
(3 Cycle)
Address
(3 Cycle)
Pass
60h
60h
60h
D0h
71h
I/O
60h
I/O0~7
A0 ~ A7 & A9 ~ A26
A25: K9S1208V0X
A26: K9D1G08V0X
Fail
READ STATUS
The device contains a Status Register which may be read to find out whether program or erase operation is completed, and whether
the program or erase operation is completed successfully. After writing 70h command to the command register, a read cycle outputs
the content of the Status Register to the I/O pins on the falling edge of CE or RE, whichever occurs last. This two line control allows
the system to poll the progress of each device in multiple memory connections even when R/B pins are common-wired. RE or CE
does not need to be toggled for updated status. Refer to Table 3 for specific Status Register definitions. The command register
remains in Status Read mode until further commands are issued to it. Therefore, if the status register is read during a random read
mode, a read command(00h or 50h) should be given before the sequential read cycle.
For Read Status of Multi Plane Program/Erase, the Read Multi-Plane Status command(71h) should be used to find out whether multi-
plane program or erase operation is completed, and whether the program or erase operation is completed successfully. The pass/fail
status data must be checked only in the Ready condition after the completion of Multi-Plane program or erase operation.
Table3. Read Status Register Definition
I/O No.
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
Status
Definition by 70h Command
Definition by 71h Command
Pass : "0"(1)
Fail : "1"
Fail : "1"
Fail : "1"
Fail : "1"
Fail : "1"
Total Pass/Fail
Plane 0 Pass/Fail
Plane 1 Pass/Fail
Plane 2 Pass/Fail
Plane 3 Pass/Fail
Reserved
Pass : "0"
Fail : "1"
Pass : "0"(2)
Must be don’t -cared
Must be don’t -cared
Must be don’t -cared
Must be don’t -cared
Must be don’t -cared
Busy : "0"
Pass : "0"(2)
Pass : "0"(2)
Pass : "0"(2)
Must be don’t-cared
Busy : "0"
Device Operation
Write Protect
Ready : "1"
Ready : "1"
Protected : "0"
Not Protected : "1"
Protected : "0"
Not Protected : "1"
NOTE : 1. I/O 0 describes combined Pass/Fail condition for all planes. If any of the selected multiple pages/blocks fails in Program/
Erase operation, it sets "Fail" flag.
2. The pass/fail status applies only to the corresponding plane.
32
K9D1G08V0M/A-SSB0
K9S1208V0M/A-SSB0
TM
SmartMedia
READ ID
The device contains a product identification mode, initiated by writing 90h and 91h to the command register, followed by an address
input of 00h. Two read cycles with 90h sequentially output the manufacture code(ECh), the device code (K9S1208V0X:76h,
K9D1G08V0X:79h), the UniqueID code(A5h) and the multi plane code(C0h) respectively. The command register remains in Read ID
mode until further commands are issued to it. Figure 21 shows the operation sequence.
Figure 21. Read ID Operation
tCLR
CLE
tCEA
CE
WE
tAR
ALE
tWHR
RE
tREA
I/O0~7
90h
00h
ECh
79h
A5h
C0h
Maker code
UniqueID code
Address. 1cycle
Device code
Multi Plane code
K9S1208V0X : 76h
K9D1G08V0X : 79h
33
K9D1G08V0M/A-SSB0
K9S1208V0M/A-SSB0
TM
SmartMedia
RESET
The device offers a reset feature, executed by writing FFh to the command register. When the device is in Busy state during random
read, program or erase mode, the reset operation will abort these operations. The contents of memory cells being altered are no
longer valid, as the data will be partially programmed or erased. The command register is cleared to wait for the next command, and
the Status Register is cleared to value C0h when WP is high. Refer to Table 4 for device status after reset operation. If the device is
already in reset state a new reset command will not be accepted by the command register. The R/B pin transitions to low for tRST
after the Reset command is written. Reset command is not necessary for normal operation. Refer to Figure 23 below.
Figure 23. RESET Operation
tRST
R/B
I/O0~7
FFh
Table4. Device Status
After Power-up
After Reset
Operation Mode
Read 1
Waiting for next command
34
K9D1G08V0M/A-SSB0
K9S1208V0M/A-SSB0
TM
SmartMedia
READY/BUSY
The device has a R/B output that provides a hardware method of indicating the completion of a page program, erase and random
read operations. The R/B pin is normally high but transitions to low after program or erase command is written to the command regis-
ter or random read is started after address loading. It returns to high when the internal controller has finished the operation. The pin is
an open-drain driver thereby allowing two or more R/B outputs to be Or-tied. Because pull-up resistor value is related to tr(R/B) and
current drain during busy(ibusy) , an appropriate value can be obtained with the following reference chart(Fig 24). Its value can be
determined by the following guidance.
Rp
ibusy
VCC
Ready Vcc
R/B
2.0V
open drain output
0.8V
Busy
tf
tr
GND
Device
Figure 24. Rp vs tr ,tf & Rp vs ibusy
@ Vcc = 3.3V, Ta = 25°C , CL = 100pF
381
3.3
Ibusy
300n
3m
290
1.1
1.65
189
200n
100n
2m
1m
tr
tf
96
0.825
4.2
4.2
2K
4.2
3K
4.2
4K
1K
Rp(ohm)
Rp value guidance
3.2V
VCC(Max.) - VOL(Max.)
Rp(min) =
=
IOL + SIL
8mA + SIL
where IL is the sum of the input currents of all devices tied to the R/B pin.
Rp(max) is determined by maximum permissible limit of tr
35
K9D1G08V0M/A-SSB0
K9S1208V0M/A-SSB0
TM
SmartMedia
DATA PROTECTION
The device is designed to offer protection from any involuntary program/erase during power-transitions. An internal voltage detector
disables all functions whenever Vcc is below about 2V. WP pin provides hardware protection and is recommended to be kept at VIL
during power-up and power-down as shown in Figure 25. The two step command sequence for program/erase provides additional
software protection.
Figure 25. AC Waveforms for Power Transition
~ 2.5V
~ 2.5V
VCC
High
WP
WE
1ms
36
TM
SmartMedia
SmartMedia Dimensions
DIMENSIONS
Unit:mm
22 PAD SOLID STATE FLOPPY DISK CARD (3.3V)
SOLID STATE PRODUCT OUTLINE
37.0±0.1
0.15±0.05
5.0±0.2
Index Label Area
10.0±0.2
Write Protect Area
40.0±0.1
45.0±0.1
0.76±0.08
0.5mm Chamfer 4.2(Min)
1.5±0.1
(3.3V Card)
27.0
2.140 TYP
0.400 TYP
22
12
8.650
7.900
6.500
0.000
6.500
7.900
8.650
1
11
37
相关型号：
K9E2G08B0M-FCB00
Flash, 256MX8, 30ns, PDSO48, 12 X 17 MM, 0.70 MM HEIGHT, LEAD FREE, PLASTIC, WSOP1-48
SAMSUNG
K9E2G08B0M-FIB00
Flash, 256MX8, 30ns, PDSO48, 12 X 17 MM, 0.70 MM HEIGHT, LEAD FREE, PLASTIC, WSOP1-48
SAMSUNG
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