K9F1208U0M-YCB0T [SAMSUNG]
Flash, 64MX8, 35ns, PDSO48,;
| 型号： | K9F1208U0M-YCB0T |
| 厂家： | 
SAMSUNG |
| 描述： | Flash, 64MX8, 35ns, PDSO48, 光电二极管 内存集成电路 存储 闪存 |
| 文件： | 总41页 (文件大小：1077K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
K9F1208U0M
FLASH MEMORY
Document Title
64M x 8 Bit NAND Flash Memory
Revision History
Revision No History
Draft Date
Remark
0.0
0.1
1. Initial issue
Oct. 27th 2000 Advanced
Information
1. Renamed GND input (pin # 6) on behalf of SE (pin # 6)
- The SE input controls the access of the spare area. When SE is high,
the spare area is not accessible for reading or programming. SE is rec
ommended to be coupled to GND or Vcc and should not be toggled
during reading or programming.
Dec. 5th 2000
=> Connect this input pin to GND or set to static low state unless the
sequential read mode excluding spare area is used.
2. Updated operation for tRST timing
- If reset command(FFh) is written at Ready state, the device goes into
Busy for maximum 5us.
0.2
0.3
Dec. 15th 2000
Jan. 8th 2001
1. Changed GND input (pin # 6) pin to N.C ( No Connection).
- The pin # 6 is don’t-cared regardless of external logic input level
and is fixed as low internally.
1. Changed plane address in Copy-Back Program
- A24 and A25 must be the same between source and target page
=> A14 and A15 must be the same between source and target page
1. Changed DC characteristics
0.4
Apr. 7th 2001
Parameter
Sequential Read
Min
Typ
10
Max
Unit
-
-
-
20->30
20->30
20->30
Operating
Current
Program
Erase
10
mA
10
2. Unified access timing parameter definition for multiple operating modes
- Changed AC characteristics (Before)
Parameter
Symbol
tAR1
Min
Max
-
Unit
ALE to RE Delay( ID read )
CE to RE Delay( ID read)
RE Low to Status Output
CE Low to Status Output
RE access time(Read ID)
100
tCR
100
-
tRSTO
tCSTO
tREADID
-
-
-
35
45
35
ns
- AC characteristics (After)
. Deleted tCR,tRSTO, tCSTO and tREADID / Added tCEA
Parameter
ALE to RE Delay( ID read )
CE Access Time
Symbol
tAR1
Min
10
-
Max
-
Unit
ns
tCEA
45
1
K9F1208U0M
FLASH MEMORY
Revision History
Revision No History
Draft Date
Remark
CLE
CE
tCR
WE
tAR1
ALE
RE
tREA
90h
I/O0~7
00h
ECh
Maker code
Address. 1cycle
CLE
CE
tCEA
WE
tAR1
ALE
RE
tWHR
tREA
90h
I/O0~7
00h
ECh
Maker code
Address. 1cycle
tCLS
CLE
CE
tCLS
tCS
tCLH
tCH
tWP
WE
tCSTO
tCHZ*
tWHR
RE
tDH
tDS
tRSTO
tIR
tRHZ*
I/O0~7
Status Output
70h
tCLS
CLE
CE
tCLS
tCS
tCLH
tCH
tWP
WE
tCEA
tCHZ*
tWHR
RE
tDH
tDS
tREA
tIR
tRHZ*
I/O0~7
Status Output
70h
The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right
to change the specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions about device. If you have
any questions, please contact the SAMSUNG branch office near your office.
2
K9F1208U0M
FLASH MEMORY
Revision No History
Draft Date
Remark
0.5
1. Addition of new operation : Multi-Plane Copy-Back Program.
May. 30th 2001 Preliminary
- Multi-Plane Copy-Back Program is extended operation of one-page
Copy-Back program.
=> After successive reading of multiple 528 byte data set at the source
planes, the above data are moved to internal page registers and same
procedure as Multi-Plane Page Programming is executed.
1.Powerup sequence is added
Jul. 23th 2001
0.6
: Recovery time of minimum 1ms is required before internal circuit gets
ready for any command sequences
~ 2.5V
~ 2.5V
V
CC
High
WP
WE
1µs
2. AC parameter tCLR(CLE to RE Delay, min 50ns) is added.
1. Copy-Back Program(Dummy) is added in Command sets table.
0.7
Aug. 23th 2001
(before revision)
1st.
Cycle
2nd.
Cycle
3rd.
Cycle
Function
Page Program (True)
80h
80h
00h
10h
11h
8Ah
-
-
Page Program (Dummy)
Copy-Back Program(True)
10h
(after revision)
1st.
Cycle
2nd.
Cycle
3rd.
Cycle
Function
Page Program (True)(2)
80h
80h
00h
03h
10h
11h
8Ah
8Ah
-
-
Page Program (Dummy)(2)
Copy-Back Program(True)(2)
Copy-Back Program(Dummy)(2)
10h
11h/10h
Note 2. Page Program(True) and Copy-Back Program(True) are available on 1 plane
operation.
Page Program(Dummy) and Copy-Back Program(Dummy) are available on
the 2nd,3rd,4th plane of multi plane operation.
3
K9F1208U0M
FLASH MEMORY
Revision No History
Draft Date
Remark
0.8
1. In Read ID & Status Read timing diagram, tCLS is changed to tCLR.
Oct. 7th 2001
tCLS
CLE
CE
tCEA
WE
tAR1
ALE
RE
tWHR
tREA
90h
I/O0~7
00h
Address. 1cycle
ECh
Maker code
tCLR
CLE
CE
tCEA
WE
ALE
RE
tAR1
tWHR
tREA
90h
I/O0~7
00h
ECh
Maker code
Address. 1cycle
tCLS
CLE
CE
tCLS
tCS
tCLH
tCH
tWP
WE
tCEA
tCHZ*
tWHR
RE
tDH
tREA
tDS
70h
tIR
tRHZ*
I/O0~7
Status Output
tCLR
CLE
CE
tCLS
tCS
tCLH
tCH
tWP
WE
tCEA
tCHZ*
tWHR
RE
tDH
tREA
tDS
70h
tIR
tRHZ*
I/O0~7
Status Output
4
K9F1208U0M
FLASH MEMORY
Revision No History
Draft Date
Remark
0.9
To clarify the meaning of parameter,
Apr. 20th 2002
1. tRHZ is devide into tRHZ and tOH.(page 12)
- tRHZ : RE High to Output Hi-Z
- tOH : RE High to Output Hold
2. tCHZ is devide into tCHZ and tOH.(page 12)
- tCHZ : CE High to Output Hi-Z
- tOH : CE High to Output Hold
Jul. 4th 2003
1. Pb-free Package is added.
K9F1208U0M-PCB0,PIB0
1.0
2. New definition of the number of invalid blocks is added.
(Minimum 1004 valid blocks are guaranteed for each contiguous 128Mb
memory space.)
3. Note is added.
(VIL can undershoot to -0.4V and VIH can overshoot to VCC +0.4V for
durations of 20 ns or less.)
Minimum valid block number is changed.
4026(Before) --> 4036(After)
1.1
1.2
Oct. 24th 2003
Oct. 25th. 2004
1. NAND Flash Technical Notes is changed.
-Invalid block -> initial invalid block ( page 14)
-Error in write or read operation ( page 15 )
-Program Flow Chart ( page 15 )
May 6th. 2005
1. The flow chart to creat the initial invalid block table is changed.
1.3
5
K9F1208U0M
FLASH MEMORY
64M x 8 Bit NAND Flash Memory
FEATURES
GENERAL DESCRIPTION
• Voltage Supply : 2.7V~3.6V
The K9F1208U0M is a 64M(67,108,864)x8bit NAND Flash
Memory with a spare 2,048K(2,097,152)x8bit. Its NAND cell
provides the most cost-effective solution for the solid state
mass storage market. A program operation can be performed in
typical 200µs on the 528-byte page and an erase operation can
be performed in typical 2ms on a 16K-byte block. Data in the
page can be read out at 50ns cycle time per byte. The I/O pins
serve as the ports for address and data input/output as well as
command inputs. The on-chip write controller automates all pro-
gram and erase functions including pulse repetition, where
required, and internal verification and margining of data. Even
the write-intensive systems can take advantage of the
K9F1208U0M’s extended reliability of 100K program/erase
cycles by providing ECC(Error Correcting Code) with real time
mapping-out algorithm. The K9F1208U0M-YCB0,PCB0/
YIB0,PIB0 is an optimum solution for large nonvolatile storage
applications such as solid state file storage and other portable
applications requiring non-volatility.
• Organization
- Memory Cell Array : (64M + 2,048K)bit x 8bit
- Data Register : (512 + 16)bit x8bit multipled by four planes
• Automatic Program and Erase
- Page Program : (512 + 16)Byte
- Block Erase : (16K + 512)Byte
• 528-Byte Page Read Operation
- Random Access : 12µs(Max.)
- Serial Page Access : 50ns(Min.)
• Fast Write Cycle Time
- Program time : 200µs(Typ.)
- Block Erase Time : 2ms(Typ.)
• Command/Address/Data Multiplexed I/O Port
• Hardware Data Protection
- Program/Erase Lockout During Power Transitions
• Reliable CMOS Floating-Gate Technology
- Endurance : 100K Program/Erase Cycles
- Data Retention : 10 Years
• Command Register Operation
• Intelligent Copy-Back Operation
• Package :
- K9F1208U0M-YCB0, K9F1208U0M-YIB0 :
48 - Pin TSOP I (12 x 20 / 0.5 mm pitch)
- K9F1208U0M-PCB0, K9F1208U0M-PIB0 :
48 - Pin TSOP I (12 x 20 / 0.5 mm pitch) - LEAD FREE
• Simultaneous Four Page/Block Program/Erase
PIN CONFIGURATION
PIN DESCRIPTION
Pin Name
I/O0 ~ I/O7
CLE
Pin Function
Data Input/Outputs
N.C
N.C
N.C
N.C
I/O7
I/O6
I/O5
I/O4
N.C
N.C
N.C
Vcc
Vss
N.C
N.C
N.C
I/O3
I/O2
I/O1
I/O0
N.C
N.C
N.C
N.C
N.C
N.C
N.C
N.C
N.C
N.C
R/B
RE
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
1
2
3
4
Command Latch Enable
Address Latch Enable
Chip Enable
5
6
7
ALE
8
CE
9
N.C
N.C
Vcc
Vss
N.C
N.C
CLE
ALE
WE
WP
N.C
N.C
N.C
N.C
N.C
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
CE
48-pin TSOP1
Standard Type
12mm x 20mm
RE
Read Enable
WE
Write Enable
WP
Write Protect
R/B
Ready/Busy output
Power(+2.7V~3.6V)
Ground
VCC
VSS
N.C
No Connection
NOTE : Connect all VCC and VSS pins of each device to common power supply outputs.
Do not leave VCC or VSS disconnected.
6
K9F1208U0M
FLASH MEMORY
Figure 1. Functional Block Diagram
VCC
VSS
X-Buffers
A9 - A25
512M + 16M Bit
NAND Flash
ARRAY
Latches
& Decoders
Y-Buffers
A0 - A7
Latches
& Decoders
(512 + 16)Byte x 131072
Page Register & S/A
Y-Gating
A8
Command
Command
Register
VCC
VSS
I/O Buffers & Latches
Global Buffers
CE
RE
WE
Control Logic
& High Voltage
Generator
I/0 0
Output
Driver
I/0 7
CLE ALE
WP
Figure 2. Array Organization
1 Block = 32 Pages
(16K + 512) Byte
1 Page = 528 Bytes
1 Block = 528 B x 32 Pages
= (16K + 512) Bytes
1 Device = 528B x 32Pages x 4,096 Blocks
= 528 Mbits
128K Pages
1st half Page Register
(=4,096 Blocks)
2nd half Page Register
(=256 Bytes)
(=256 Bytes)
8 bit
512B Bytes
16 Bytes
16 Bytes
I/O 0 ~ I/O 7
Page Register
512 Bytes
I/O 0
A0
I/O 1
A1
I/O 2
A2
I/O 3
A3
I/O 4
A4
I/O 5
A5
I/O 6
A6
I/O 7
A7
1st Cycle
2nd Cycle
3rd Cycle
4th Cycle
Column Address
Row Address
(Page Address)
A9
A10
A18
*L
A11
A19
*L
A12
A20
*L
A13
A21
*L
A14
A22
*L
A15
A23
*L
A16
A24
*L
A17
A25
NOTE : Column Address : Starting Address of the Register.
00h Command(Read) : Defines the starting address of the 1st half of the register.
01h Command(Read) : Defines the starting address of the 2nd half of the register.
* A8 is set to "Low" or "High" by the 00h or 01h Command.
* L must be set to "Low".
* The device ignores any additional input of address cycles than reguired.
7
K9F1208U0M
FLASH MEMORY
Product Introduction
The K9F1208U0M is a 528Mbit(553,648,218 bit) memory organized as 131,072 rows(pages) by 528 columns. Spare sixteen columns
are located from column address of 512 to 527. A 528-byte data register is connected to memory cell arrays accommodating data
transfer between the I/O buffers and memory during page read and page program operations. The memory array is made up of 16
cells that are serially connected to form a NAND structure. Each of the 16 cells resides in a different page. A block consists of two
NAND structured strings. A NAND structure consists of 16 cells. Total 135168 NAND cells reside in a block. The array organization is
shown in Figure 2. The program and read operations are executed on a page basis, while the erase operation is executed on a block
basis. The memory array consists of 4,096 separately erasable 16K-byte blocks. It indicates that the bit by bit erase operation is pro-
hibited on the K9F1208U0M.
The K9F1208U0M has addresses multiplexed into 8 I/O's. This scheme dramatically reduces pin counts and allows systems
upgrades to future densities by maintaining consistency in system board design. Command, address and data are all written through
I/O's by bringing WE to low while CE is low. Data is latched on the rising edge of WE. Command Latch Enable(CLE) and Address
Latch Enable(ALE) are used to multiplex command and address respectively, via the I/O pins. The 64M byte physical space requires
26 addresses, thereby requiring four cycles for byte-level addressing: column address, low row address and high row address, in that
order. Page Read and Page Program need the same four address cycles following the required command input. In Block Erase oper-
ation, however, only the three row address cycles are used. Device operations are selected by writing specific commands into the
command register. Table 1 defines the specific commands of the K9F1208U0M.
The device provides simultaneous program/erase capability up to four pages/blocks. By dividing the memory array into four 128Mbit
separate planes, simultaneous multi-plane operation dramatically increases program/erase performance by 4X while still maintaining
the conventional 512 byte structure.
The extended pass/fail status for multi-plane program/erase allows system software to quickly identify the failing page/block out of
selected multiple pages/blocks. Usage of multi-plane operations will be described further throughout this document.
In addition to the enhanced architecture and interface, the device incorporates copy-back program feature from one page to another
of the same plane without the need for transporting the data to and from the external buffer memory. Since the time-consuming burst-
reading and data-input cycles are removed, system performance for solid-state disk application is significantly increased.
Table 1. Command Sets
Acceptable Command
Function
1st. Cycle
2nd. Cycle
3rd. Cycle
during Busy
00h/01h(1)
50h
Read 1
Read 2
Read ID
Reset
-
-
-
-
90h
-
-
FFh
-
-
O
Page Program (True)(2)
Page Program (Dummy)(2)
Copy-Back Program(True)(2)
Copy-Back Program(Dummy)(2)
Block Erase
80h
10h
11h
8Ah
8Ah
D0h
D0h
-
-
80h
-
00h
10h
03h
11h
60h
-
-
-
-
Multi-Plane Block Erase
Read Status
60h----60h
70h
O
O
71h(3)
Read Multi-Plane Status
-
NOTE : 1. The 00h command defines starting address of the 1st half of registers.
The 01h command defines starting address of the 2nd half of registers.
After data access on the 2nd half of register by the 01h command, the status pointer is
automatically moved to the 1st half register(00h) on the next cycle.
2. Page Program(True) and Copy-Back Program(True) are available on 1 plane operation.
Page Program(Dummy) and Copy-Back Program(Dummy) are available on the 2nd,3rd,4th plane of multi plane operation.
3. The 71h command should be used for read status of Multi Plane operation.
Caution : Any undefined command inputs are prohibited except for above command set of Table 1.
8
K9F1208U0M
FLASH MEMORY
Memory Map
The device is arranged in four 128Mbit memory planes. Each plane contains 1,024 blocks and 528 byte page registers. This allows it
to perform simultaneous page program and block erase by selecting one page or block from each plane. The block address map is
configured so that multi-plane program/erase operations can be executed for every four sequential blocks.
Figure 3. Memory Array Map
Plane 3
(1024 Block)
Plane 2
(1024 Block)
Plane 1
(1024 Block)
Plane 0
(1024 Block)
Block 0
Block 2
Block 3
Block 1
Page 0
Page 1
Page 0
Page 0
Page 1
Page 0
Page 1
Page 1
Page 30
Page 31
Page 30
Page 31
Page 30
Page 31
Page 30
Page 31
Block 4
Block 6
Block 7
Block 5
Page 0
Page 1
Page 0
Page 1
Page 0
Page 1
Page 0
Page 1
Page 30
Page 31
Page 30
Page 31
Page 30
Page 31
Page 30
Page 31
Block 4088
Block 4090
Block 4091
Block 4089
Page 0
Page 1
Page 0
Page 1
Page 0
Page 1
Page 0
Page 1
Page 30
Page 31
Page 30
Page 31
Page 30
Page 31
Page 30
Page 31
Block 4092
Block 4094
Block 4095
Block 4093
Page 0
Page 1
Page 0
Page 1
Page 0
Page 1
Page 0
Page 1
Page 30
Page 31
Page 30
Page 31
Page 30
Page 31
Page 30
Page 31
528byte Page Registers
528byte Page Registers
528byte Page Registers
528byte Page Registers
9
K9F1208U0M
FLASH MEMORY
Pin Description
Command Latch Enable(CLE)
The CLE input controls the path activation for commands sent to the command register. When active high, commands are latched into
the command register through the I/O ports on the rising edge of the WE signal.
Address Latch Enable(ALE)
The ALE input controls the activating path for address to the internal address registers. Addresses are latched on the rising edge of
WE with ALE high.
Chip Enable(CE)
The CE input is the device selection control. When the device is in the Busy state, CE high is ignored, and the device does not return
to standby mode in program or erase operation. Regarding CE control during read operation, refer to ’Page read’ section of Device
operation .
Write Enable(WE)
The WE input controls writes to the I/O port. Commands, address and data are latched on the rising edge of the WE pulse.
The WE must be held high when outputs are activated.
Read Enable(RE)
The RE input is the serial data-out control, and when active drives the data onto the I/O bus. Data is valid tREA after the falling edge of
RE which also increments the internal column address counter by one.
I/O Port : I/O 0 ~ I/O 7
The I/O pins are used to input command, address and data, and to output data during read operations. The I/O pins float to high-z
when the chip is deselected or when the outputs are disabled.
Write Protect(WP)
The WP pin provides inadvertent write/erase protection during power transitions. The internal high voltage generator is reset when the
WP pin is active low.
Ready/Busy(R/B)
The R/B output indicates the status of the device operation. When low, it indicates that a program, erase or random read operation is
in process and returns to high state upon completion. It is an open drain output and does not float to high-z condition when the chip is
deselected or when outputs are disabled.
10
K9F1208U0M
FLASH MEMORY
Absolute Maximum Ratings
Parameter
Symbol
VIN
Rating
Unit
-0.6 to + 4.6
-0.6 to + 4.6
-10 to +125
-40 to +125
-65 to +150
Voltage on any pin relative to VSS
V
VCC
K9F1208U0M-XCB0
K9F1208U0M-XIB0
Temperature Under Bias
TBIAS
TSTG
°C
°C
Storage Temperature
NOTE :
1. Minimum DC voltage is -0.6V on input/output pins. During transitions, this level may undershoot to -2.0V for periods <30ns.
Maximum DC voltage on input/output pins is VCC,+0.3V which, during transitions, may overshoot to VCC+2.0V for periods <20ns.
2. Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to the conditions
as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
Recommended Operating Conditions
(Voltage reference to GND, K9F1208U0M-XCB0 :TA=0 to 70°C, K9F1208U0M-XIB0:TA=-40 to 85°C)
Parameter
Supply Voltage
Supply Voltage
Symbol
VCC
Min
2.7
0
Typ.
3.3
0
Max
3.6
0
Unit
V
VSS
V
Dc and Operating Characteristics(Recommended operating conditions otherwise noted.)
Parameter
Sequential Read
Program
Symbol
ICC1
ICC2
ICC3
ISB1
ISB2
ILI
Test Conditions
Min
Typ
10
10
10
-
Max
30
Unit
tRC=50ns, CE=VIL, IOUT=0mA
-
Operating
Current
-
-
30
mA
Erase
-
CE=VIH, WP= 0V/VCC
CE=VCC-0.2, WP = 0V/VCC
VIN=0 to 3.6V
VOUT=0 to 3.6V
-
-
30
Stand-by Current(TTL)
Stand-by Current(CMOS)
Input Leakage Current
Output Leakage Current
Input High Voltage
-
-
1
10
-
50
-
±10
±10
µA
ILO
-
-
VIH*
VIL*
2.0
-0.3
2.4
-
-
VCC+0.3
Input Low Voltage, All inputs
Output High Voltage Level
Output Low Voltage Level
Output Low Current(R/B)
-
-
0.8
-
V
VOH
VOL
IOH=-400µA
-
IOL=2.1mA
-
0.4
-
IOL(R/B) VOL=0.4V
8
10
mA
NOTE : VIL can undershoot to -0.4V and VIH can overshoot to VCC +0.4V for durations of 20 ns or less.
11
K9F1208U0M
FLASH MEMORY
Valid Block
Parameter
Symbol
Min
Typ.
Max
Unit
Valid Block Number
NVB
4,036
-
4,096
Blocks
NOTE :
1. The device may include invalid blocks when first shipped. Additional invalid blocks may develop while being used. The number of valid blocks is pre-
sented with both cases of invalid blocks considered. Invalid blocks are defined as blocks that contain one or more bad bits. Do not erase or program
factory-marked bad blocks. Refer to the attached technical notes for an appropriate management of invalid blocks.
2. The 1st block, which is placed on 00h block address, is guaranteed to be a valid block, does not require Error Correction up to 1K program/erase
cycles.
3. Minimum 1004 valid blocks are guaranteed for each contiguous 128Mb memory space.
AC Test Condition
(K9F1208U0M-XCB0 :TA=0 to 70°C, K9F1208U0M-XIB0:TA=-40 to 85°C, VCC=2.7V~3.6V unless otherwise)
Parameter
Input Pulse Levels
Value
0.4V to 2.4V
Input Rise and Fall Times
Input and Output Timing Levels
Output Load (3.0V +/-10%)
Output Load (3.3V +/-10%)
5ns
1.5V
1 TTL GATE and CL=50pF
1 TTL GATE and CL=100pF
Capacitance(TA=25°C, VCC=3.3V, f=1.0MHz)
Item
Symbol
Test Condition
VIL=0V
Min
Max
10
Unit
pF
Input/Output Capacitance
Input Capacitance
CI/O
-
-
CIN
VIN=0V
10
pF
NOTE : Capacitance is periodically sampled and not 100% tested.
MODE SELECTION
CLE
H
L
ALE
L
CE
L
WE
RE
H
WP
Mode
X
Command Input
Read Mode
H
L
H
X
Address Input(4clock)
Command Input
H
L
L
L
H
H
Write Mode
Data Input
H
L
H
H
Address Input(4clock)
L
L
L
H
H
L
L
L
H
H
X
X
X
X
X
Sequential Read & Data Output
During Read(Busy)
During Program(Busy)
During Erase(Busy)
Write Protect
L
L
L
H
X
X
X
X
X
X
X
X
X
X
H
H
X
X
H
L
X(1)
X
X
(2)
X
Stand-by
0V/VCC
NOTE : 1. X can be VIL or VIH.
2. WP should be biased to CMOS high or CMOS low for standby.
Program / Erase Characteristics
Parameter
Symbol
Min
Typ
Max
500
10
1
Unit
Program Time
tPROG
-
200
µs
µs
Dummy Busy Time for Multi Plane Program
tDBSY
1
-
Main Array
Spare Array
-
-
-
cycle
cycles
ms
Number of Partial Program Cycles
Nop
in the Same Page
Block Erase Time
-
2
tBERS
2
3
12
K9F1208U0M
FLASH MEMORY
AC Timing Characteristics for Command / Address / Data Input
Parameter
Symbol
tCLS
tCLH
tCS
Min
Max
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
CLE setup Time
CLE Hold Time
CE setup Time
CE Hold Time
0
-
-
-
-
-
-
-
-
-
-
-
10
0
tCH
10
25(1)
0
WE Pulse Width
ALE setup Time
ALE Hold Time
Data setup Time
Data Hold Time
Write Cycle Time
tWP
tALS
tALH
tDS
10
20
10
50
15
tDH
tWC
WE High Hold Time
tWH
NOTE : 1. If tCS is set less than 10ns, tWP must be minimum 35ns, otherwise, tWP may be minimum 25ns.
AC Characteristics for Operation
Parameter
Data Transfer from Cell to Register
ALE to RE Delay( ID read )
ALE to RE Delay(Read cycle)
CLE to RE Delay
Symbol
tR
Min
-
Max
Unit
12
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
tAR1
tAR2
tCLR
tRR
10
50
50
20
30
-
-
-
-
Ready to RE Low
-
RE Pulse Width
tRP
-
WE High to Busy
tWB
100
Read Cycle Time
tRC
50
-
-
RE Access Time
tREA
tRHZ
tCHZ
tOH
35
RE High to Output Hi-Z
-
30
CE High to Output Hi-Z
-
20
RE or CE High to Output hold
RE High Hold Time
15
15
0
-
tREH
tIR
-
Output Hi-Z to RE Low
-
Last RE High to Busy(at sequential read)
CE High to Ready(in case of interception by CE at read)
CE High Hold Time(at the last serial read)(2)
CE Access Time
tRB
-
100
50 +tr(R/B)(1)
tCRY
tCEH
tCEA
tWHR
tRST
-
100
-
-
45
WE High to RE Low
60
-
-
5/10/500(3)
Device Resetting Time(Read/Program/Erase)
NOTE : 1. The time to Ready depends on the value of the pull-up resistor tied R/B pin.
2. To break the sequential read cycle, CE must be held high for longer time than tCEH.
3. If reset command(FFh) is written at Ready state, the device goes into Busy for maximum 5us.
13
K9F1208U0M
FLASH MEMORY
NAND Flash Technical Notes
Initial Invalid Block(s)
Initial invalid blocks are defined as blocks that contain one or more initial invalid bits whose reliability is not guaranteed by Samsung.
The information regarding the initial invalid block(s) is so called as the initial invalid block information. Devices with initial invalid
block(s) have the same quality level or as devices with all valid blocks and have the same AC and DC characteristics. An initial
invalid block(s) does not affect the performance of valid block(s) because it is isolated from the bit line and the common source line by
a select transistor. The system design must be able to mask out the initial invalid block(s) via address mapping. The 1st block, which
is placed on 00h block address, is guaranteed to be a valid block, does not require Error Correction up to 1K Program/ Erase cycles.
Identifying Initial Invalid Block(s)
All device locations are erased(FFh) except locations where the initial invalid block(s) information is written prior to shipping. The
initial invalid block(s) status is defined by the 6th byte in the spare area. Samsung makes sure that either the 1st or 2nd page of every
initial invalid block has non-FFh data at the column address of 517. Since the initial invalid block information is also erasable in most
cases, it is impossible to recover the information once it has been erased. Therefore, the system must be able to recognize the initial
invalid block(s) based on the initial invalid block information and create the initial invalid block table via the following suggested flow
chart(Figure 4). Any intentional erasure of the initial invalid block information is prohibited.
Start
Set Block Address = 0
Increment Block Address
Check "FFh" at the column address 517
*
of the 1st and 2nd page in the block
No
Create (or update)
Check "FFh" ?
Initial
Invalid Block(s) Table
Yes
No
Last Block ?
Yes
End
Figure 4. Flow chart to create initial invalid block table.
14
K9F1208U0M
FLASH MEMORY
NAND Flash Technical Notes (Continued)
Error in write or read operation
Within its life time, additional invalid blocks may develop with NAND Flash memory. Refer to the qualification report for the actual
data.The following possible failure modes should be considered to implement a highly reliable system. In the case of status read fail-
ure after erase or program, block replacement should be done. Because program status fail during a page program does not affect
the data of the other pages in the same block, block replacement can be executed with a page-sized buffer by finding an erased
empty block and reprogramming the current target data and copying the rest of the replaced block. In case of Read, ECC must be
employed. To improve the efficiency of memory space, it is recommended that the read or verification failure due to single bit error be
reclaimed by ECC without any block replacement. The said additional block failure rate does not include those reclaimed blocks.
Failure Mode
Erase Failure
Detection and Countermeasure sequence
Status Read after Erase --> Block Replacement
Status Read after Program --> Block Replacement
Verify ECC -> ECC Correction
Write
Read
Program Failure
Single Bit Failure
: Error Correcting Code --> Hamming Code etc.
Example) 1bit correction & 2bit detection
ECC
Program Flow Chart
Start
Write 80h
Write Address
Write Data
Write 10h
Read Status Register
No
I/O 6 = 1 ?
or R/B = 1 ?
Yes
*
No
Program Error
I/O 0 = 0 ?
Yes
Program Completed
15
K9F1208U0M
FLASH MEMORY
NAND Flash Technical Notes (Continued)
Erase Flow Chart
Read Flow Chart
Start
Start
Write 60h
Write 00h
Write Block Address
Write Address
Read Data
Write D0h
Read Status Register
ECC Generation
No
No
I/O 6 = 1 ?
or R/B = 1 ?
Reclaim the Error
Verify ECC
Yes
Yes
*
No
Page Read Completed
Erase Error
I/O 0 = 0 ?
Yes
Erase Completed
: If erase operation results in an error, map out
the failing block and replace it with another block.
*
Block Replacement
Block A
1st
2
{
(n-1)th
nth
an error occurs.
(page)
Buffer memory of the controller.
Block B
1st
1
{
(n-1)th
nth
(page)
* Step1
When an error happens in the nth page of the Block ’A’ during erase or program operation.
* Step2
Copy the nth page data of the Block ’A’ in the buffer memory to the nth page of another free block. (Block ’B’)
* Step3
Then, copy the data in the 1st ~ (n-1)th page to the same location of the Block ’B’.
* Step4
Do not erase or program to Block ’A’ by creating an ’invalid Block’ table or other appropriate scheme.
16
K9F1208U0M
FLASH MEMORY
Pointer Operation of K9F1208U0M
Samsung NAND Flash has three address pointer commands as a substitute for the two most significant column addresses. ’00h’
command sets the pointer to ’A’ area(0~255byte), ’01h’ command sets the pointer to ’B’ area(256~511byte), and ’50h’ command sets
the pointer to ’C’ area(512~527byte). With these commands, the starting column address can be set to any of a whole
page(0~527byte). ’00h’ or ’50h’ is sustained until another address pointer command is inputted. ’01h’ command, however, is effective
only for one operation. After any operation of Read, Program, Erase, Reset, Power_Up is executed once with ’01h’ command, the
address pointer returns to ’A’ area by itself. To program data starting from ’A’ or ’C’ area, ’00h’ or ’50h’ command must be inputted
before ’80h’ command is written. A complete read operation prior to ’80h’ command is not necessary. To program data starting from
’B’ area, ’01h’ command must be inputted right before ’80h’ command is written.
Table 2. Destination of the pointer
"A" area
(00h plane)
"B" area
(01h plane)
"C" area
(50h plane)
Command
Pointer position
Area
00h
01h
50h
0 ~ 255 byte
256 ~ 511 byte
512 ~ 527 byte
1st half array(A)
2nd half array(B)
spare array(C)
256 Byte
256 Byte
16 Byte
"A"
"B"
"C"
Internal
Page Register
Pointer select
commnad
(00h, 01h, 50h)
Pointer
Figure 5. Block Diagram of Pointer Operation
(1) Command input sequence for programming ’A’ area
The address pointer is set to ’A’ area(0~255), and sustained
Address / Data input
Address / Data input
80h 10h
00h
80h
10h
00h
’A’,’B’,’C’ area can be programmed.
’00h’ command can be omitted.
It depends on how many data are inputted.
(2) Command input sequence for programming ’B’ area
The address pointer is set to ’B’ area(256~511), and will be reset to
’A’ area after every program operation is executed.
Address / Data input
Address / Data input
80h 10h
01h
80h
10h
01h
’B’, ’C’ area can be programmed.
It depends on how many data are inputted.
’01h’ command must be rewritten before
every program operation
(3) Command input sequence for programming ’C’ area
The address pointer is set to ’C’ area(512~527), and sustained
Address / Data input
Address / Data input
80h 10h
50h
80h
10h
50h
Only ’C’ area can be programmed.
’50h’ command can be omitted.
17
K9F1208U0M
FLASH MEMORY
System Interface Using CE don’t-care.
For an easier system interface, CE may be inactive during the data-loading or sequential data-reading as shown below. The internal
528byte page registers are utilized as separate buffers for this operation and the system design gets more flexible. In addition, for
voice or audio applications which use slow cycle time on the order of u-seconds, de-activating CE during the data-loading and read-
ing would provide significant savings in power consumption.
Figure 6. Program Operation with CE don’t-care.
CLE
CE don’t-care
CE
WE
ALE
80h
Start Add.(4Cycle)
Data Input
Data Input
10h
I/O0~7
tCS
tCH
tCEA
CE
RE
CE
tREA
tWP
WE
I/O0~7
out
Figure 7. Read Operation with CE don’t-care.
CLE
CE don’t-care
Must be held
low during tR.
CE
RE
ALE
tR
R/B
WE
Data Output(sequential)
I/O0~7
00h
Start Add.(4Cycle)
18
K9F1208U0M
FLASH MEMORY
Command Latch Cycle
CLE
CE
tCLH
tCH
tCLS
tCS
tWP
WE
tALS
tALH
ALE
tDH
tDS
Command
I/O0~7
Address Latch Cycle
tCLS
CLE
tCS
tWC
tWC
tWC
CE
tWP
tWP
tWP
tWP
WE
tWH
tALH
tALS
tWH
tALH
tALS
tWH
tALH
tALS
tALH
tDH
tALS
ALE
tDH
tDH
tDH
tDS
tDS
tDS
tDS
A9~A16
A0~A7
I/O0~7
A17~A24
A25
19
K9F1208U0M
FLASH MEMORY
Input Data Latch Cycle
tCLH
CLE
CE
tCH
tWC
tALS
ALE
tWP
tWP
tWP
WE
tWH
tDH
tDH
tDH
tDS
tDS
tDS
I/O0~7
DIN 1
DIN 511
DIN 0
Serial access Out Cycle after Read(CLE=L, WE=H, ALE=L)
tRC
CE
tCHZ*
tOH
tREH
tREA
tREA
tREA
RE
tRHZ*
tRHZ*
tOH
Dout
I/O0~7
R/B
Dout
Dout
tRR
NOTES : Transition is measured ±200mV from steady state voltage with load.
This parameter is sampled and not 100% tested.
20
K9F1208U0M
FLASH MEMORY
Status Read Cycle
tCLR
CLE
CE
tCLS
tCS
tCLH
tCH
tWP
WE
tCEA
tCHZ*
tOH
tWHR
RE
tRHZ*
tOH
tDH
tREA
tDS
tIR
Status Output
I/O0~7
70h
Read1 Operation(Read One Page)
CLE
tCEH
CE
tCHZ
tOH
tWC
WE
ALE
RE
tWB
tCRY
tAR2
tRHZ
tOH
tR
tRC
tRR
A9 ~ A16
A17 ~ A24
Dout N+2
Dout N+1
00h or 01h A0 ~ A7
Dout N
Dout 527
tRB
A25
I/O0~7
R/B
Column
Address
Page(Row)
Address
Busy
21
K9F1208U0M
FLASH MEMORY
Read1 Operation(Intercepted by CE)
CLE
CE
WE
ALE
RE
tWB
tCHZ
tOH
tAR2
tR
tRC
tRR
A9 ~ A16 A17 ~ A24
Dout N+2
00h or 01h A0 ~ A7
Dout N+1
Dout N
A25
I/O0~7
R/B
Page(Row)
Address
Column
Address
Busy
Read2 Operation(Read One Page)
CLE
CE
WE
ALE
RE
tR
tWB
tAR2
tRR
Dout
511+M
50h
A9 ~ A16 A17 ~ A24
Dout 527
A0 ~ A7
A25
I/O0~7
R/B
Selected
Row
M Address
A0~A3 : Valid Address
A4~A7 : Don′t care
16
512
Start
address M
22
K9F1208U0M
FLASH MEMORY
Sequential Row Read Operation ( Within a Block )
CLE
CE
WE
ALE
RE
Dout
N
Dout
N+1
Dout
527
Dout
0
Dout
1
Dout
527
00h
A0 ~ A7 A9 ~ A16 A17 ~ A24
A25
I/O0~7
R/B
Ready
Busy
Busy
M
M+1
Output
N
Output
Page Program Operation
CLE
CE
tWC
tWC
tWC
WE
ALE
RE
tPROG
tWB
Din
N
Din
80h
A0 ~ A7 A9 ~ A16 A17 ~ A24
Column
A25
10h
70h
I/O0
I/O0~7
R/B
527
Sequential Data
Input Command Address
Program
Command
1 up to 528 Byte Data
Serial Input
Read Status
Command
Page(Row)
Address
I/O0=0 Successful Program
I/O0=1 Error in Program
23
K9F1208U0M
FLASH MEMORY
BLOCK ERASE OPERATION (ERASE ONE BLOCK)
CLE
CE
tWC
WE
tBERS
tWB
ALE
RE
60h
A9 ~ A16 A17 ~ A24
DOh
70h
I/O 0
A25
I/O0~7
R/B
Page(Row)
Address
Busy
I/O0=0 Successful Erase
Read Status I/O0=1 Error in Erase
Command
Auto Block Erase Setup Command
Erase Command
24
K9F1208U0M
FLASH MEMORY
≈
≈ ≈
≈
≈
≈ ≈
≈
25
K9F1208U0M
FLASH MEMORY
Multi-Plane Block Erase Operation
CLE
CE
tWC
WE
ALE
RE
tBERS
tWB
60h
A9 ~ A16 A17 ~ A24
DOh
71h
I/O 0
A25
I/O0~7
R/B
Page(Row)
Address
Busy
Block Erase Setup Command
Erase Confirm Command
Read Multi-Plane
Status Command
Max. 4 times repeatable
* For Multi-Plane Erase operation, Block address to be erased should be repeated before "D0H" command.
Ex.) Four-Plane Block Erase Operation
R/B
tBERS
Address
D0h
60h
Address
Address
71h
60h
60h
Address
A9 ~ A25
60h
I/O0~7
26
K9F1208U0M
FLASH MEMORY
Read ID Operation
CLE
CE
WE
ALE
RE
tREA
76h
Maker Code Device Code
90h
00h
ECh
A5h
C0h
I/O 0 ~ 7
Read ID Command
Address. 1cycle
Multi Plane Code
ID Defintition Table
90 ID : Access command = 90H
Value
Description
1st Byte
2nd Byte
3rd Byte
4th Byte
ECh
76h
A5h
C0h
Maker Code
Device Code
Must be don’t -cared
Supports Multi Plane Operation
27
K9F1208U0M
FLASH MEMORY
Copy-Back Program Operation
CLE
CE
tWC
WE
ALE
RE
tWB
tPROG
tWB
tR
8Ah
00h
A0~A7 A9~A16 A17~A24
A25
10h
70h
I/O0
A0~A7 A9~A16 A17~A24 A25
I/O0~7
R/B
Column
Column
Read Status
Command
Page(Row)
Page(Row)
Address
Address
Address
Address
Busy
Busy
I/O0=0 Successful Program
I/O0=1 Error in Program
Copy-Back Data
Input Command
28
K9F1208U0M
FLASH MEMORY
Device Operation
PAGE READ
Upon initial device power up, the device defaults to Read1 mode. This operation is also initiated by writing 00h to the command regis-
ter along with four address cycles. Once the command is latched, it does not need to be written for the following page read operation.
Three types of operations are available : random read, serial page read and sequential row read.
The random read mode is enabled when the page address is changed. The 528 bytes of data within the selected page are transferred
to the data registers in less than 12µs(tR). The system controller can detect the completion of this data transfer(tR) by analyzing the
output of R/B pin. Once the data in a page is loaded into the registers, they may be read out in 50ns cycle time by sequentially pulsing
RE. High to low transitions of the RE clock output the data stating from the selected column address up to the last column address.
After the data of last column address is clocked out, the next page is automatically selected for sequential row read.
Waiting 12µs again allows reading the selected page. The sequential row read operation is terminated by bringing CE high. The way
the Read1 and Read2 commands work is like a pointer set to either the main area or the spare area. The spare area of bytes 512 to
527 may be selectively accessed by writing the Read2 command. Addresses A0 to A3 set the starting address of the spare area while
addresses A4 to A7 are ignored. Unless the operation is aborted, the page address is automatically incremented for sequential row
read as in Read1 operation and spare sixteen bytes of each page may be sequentially read. The Read1 command(00h/01h) is
needed to move the pointer back to the main area. Figures 8 to 11 show typical sequence and timings for each read operation.
Figure 8. Read1 Operation
CLE
CE
WE
ALE
tR
R/B
RE
00h
Start Add.(4Cycle)
A0 ~ A7 & A9 ~ A25
Data Output(Sequential)
I/O0~7
(00h Command)
(01h Command)*
1st half array 2st half array
1st half array 2st half array
Data Field
Spare Field
Data Field
Spare Field
* After data access on 2nd half array by 01h command, the start pointer is automatically moved to 1st half
array (00h) at next cycle.
29
K9F1208U0M
FLASH MEMORY
Figure 9. Read2 Operation
CLE
CE
WE
ALE
R/B
RE
tR
50h
Data Output(Sequential)
Spare Field
Start Add.(4Cycle)
A0 ~ A3 & A9 ~ A25
I/O0~7
(A4 ~ A7 :
Don′t Care)
1st half array
2nd half array
Data Field
Spare Field
Figure 10. Sequential Row Read1 Operation
tR
tR
tR
R/B
Data Output
1st
Data Output
Data Output
I/O0 ~ 7
00h
01h
Start Add.(4Cycle)
A0 ~ A7 & A9 ~ A25
2nd
(528 Byte)
Nth
(528 Byte)
( 00h Command)
( 01h Command)
1st half array
2nd half array
1st half array
2nd half array
1st
1st
2nd
Nth
Block
2nd
Nth
Data Field
Spare Field
Data Field
Spare Field
The Sequential Read 1 and 2 operation is allowed only within a block and after the last page of a block is read-
out, the sequential read operation must be terminated by bringing CE high. When the page address moves onto
the next block, read command and address must be given.
30
K9F1208U0M
FLASH MEMORY
Figure 11. Sequential Row Read2 Operation
tR
tR
tR
R/B
Start Add.(4Cycle)
A0 ~ A3 & A9 ~ A25
Data Output
1st
I/O0~7
50h
Data Output
Data Output
2nd
(16Byte)
Nth
(16Byte)
(A4 ~ A7 :
Don’t Care)
1st
Block
Nth
Data Field
Spare Field
PAGE PROGRAM
The device is programmed basically on a page basis, but it does allow multiple partial page programing of a byte or consecutive bytes
up to 528, in a single page program cycle. The number of consecutive partial page programming operation within the same page with-
out an intervening erase operation must not exceed 1 for main array and 2 for spare array. The addressing may be done in any ran-
dom order in a block. A page program cycle consists of a serial data loading period in which up to 528 bytes of data may be loaded
into the page register, followed by a non-volatile programming period where the loaded data is programmed into the appropriate cell.
Serial data loading can be started from 2nd half array by moving pointer. About the pointer operation, please refer to the attached
technical notes.
The serial data loading period begins by inputting the Serial Data Input command(80h), followed by the four cycle address input and
then serial data loading. The bytes other than those to be programmed do not need to be loaded.The Page Program confirm com-
mand(10h) initiates the programming process. Writing 10h alone without previously entering the serial data will not initiate the pro-
gramming process. The internal write state control automatically executes the algorithms and timings necessary for program and
verify, thereby freeing the system controller for other tasks. Once the program process starts, the Read Status Register command
may be entered, with RE and CE low, to read the status register. The system controller can detect the completion of a program cycle
by monitoring the R/B output, or the Status bit(I/O 6) of the Status Register. Only the Read Status command and Reset command are
valid while programming is in progress. When the Page Program is complete, the Write Status Bit(I/O 0) may be checked(Figure 12).
The internal write verify detects only errors for "1"s that are not successfully programmed to "0"s. The command register remains in
Read Status command mode until another valid command is written to the command register.
Figure 12. Program & Read Status Operation
tPROG
R/B
Pass
I/O0~7
80h
Address & Data Input
I/O0
Fail
10h
70h
A0 ~ A7 & A9 ~ A25
528 Byte Data
31
K9F1208U0M
FLASH MEMORY
BLOCK ERASE
The Erase operation is done on a block(16K Byte) basis. Block address loading is accomplished in three cycles initiated by an Erase
Setup command(60h). Only address A14 to A25 is valid while A9 to A13 is ignored. The Erase Confirm command(D0h) following the
block address loading initiates the internal erasing process. This two-step sequence of setup followed by execution command
ensures that memory contents are not accidentally erased due to external noise conditions.
At the rising edge of WE after the erase confirm command input, the internal write controller handles erase and erase-verify. When
the erase operation is completed, the Write Status Bit(I/O 0) may be checked. Figure 13 details the sequence.
Figure 13. Block Erase Operation
tBERS
R/B
Pass
I/O0~7
60h
I/O0
Fail
70h
Address Input(3Cycle)
Block Add. : A14 ~ A25
D0h
Multi-Plane Page Program
Multi-Plane Page Program is an extension of Page Program, which is executed for a single plane with 528 byte page registers. Since
the device is equipped with four memory planes, activating the four sets of 528 byte page registers enables a simultaneous program-
ming of four pages. Partial activation of four planes is also permitted.
After writing the first set of data up to 528 byte into the selected page register, Dummy Page Program command (11h) instead of
actual Page Program (10h) is inputted to finish data-loading of the current plane and move to the next plane. Since no programming
process is involved, R/B remains in Busy state for a short period of time(tDBSY). Read Status command (standard 70h or alternate
71h) may be issued to find out when the device returns to Ready state by polling the Ready/Busy status bit(I/O 6). Then the next set
of data for one of the other planes is inputted with the same command and address sequences. After inputting data for the last plane,
actual True Page Program (10h) instead of dummy Page Program command (11h) must be followed to start the programming pro-
cess. The operation of R/B and Read Status is the same as that of Page Program. Since maximum four pages are programmed simul-
taneously, pass/fail status is available for each page when the program operation completes. The extended status bits (I/O1 through I/
O 4) are checked by inputting the Read Multi-Plane Status Register. Status bit of I/O 0 is set to "1" when any of the pages fails. Multi-
Plane page Program with "01h" pointer is not supported, thus prohibited.
Figure 14. Four-Plane Page Program
tDBSY
tPROG
10h
tDBSY
11h
tDBSY
11h
R/B
Address &
Data Input
Address &
Data Input
Address &
Data Input
A0 ~ A7 & A9 ~ A25
528 Byte Data
Address &
Data Input
71h
80h
80h
80h
80h
80h
80h
11h
I/O0~7
80h
80h
11h
11h
11h
10h
Data
input
Plane 3
(1024 Block)
Plane 0
(1024 Block)
Plane 2
(1024 Block)
Plane 1
(1024 Block)
Block 3
Block 7
Block 2
Block 6
Block 1
Block 5
Block 0
Block 4
Block 4091
Block 4095
Block 4090
Block 4094
Block 4089
Block 4093
Block 4088
Block 4092
32
K9F1208U0M
FLASH MEMORY
Restriction in addressing with Multi Plane Page Program
While any block in each plane may be addressable for Multi-Plane Page Program, the five least significant addresses(A9-A13) for
the selected pages at one operation must be the same. Figure 15 shows an example where 2nd page of each addressed block is
selected for four planes. However, any arbitrary sequence is allowed in addressing multiple planes as shown in Figure16.
Figure 15. Multi-Plane Program & Read Status Operation
Plane 3
(1024 Block)
Plane 2
(1024 Block)
Plane 1
(1024 Block)
Plane 0
(1024 Block)
Block 0
Block 2
Block 3
Block 1
Page 0
Page 1
Page 0
Page 0
Page 1
Page 0
Page 1
Page 1
Page 30
Page 31
Page 30
Page 31
Page 30
Page 31
Page 30
Page 31
Figure 16. Addressing Multiple Planes
Plane 1
Plane3
80h
10h
Plane 2
Plane 0
80h
11h
80h
11h
80h
11h
Figure 17. Multi-Plane Page Program & Read Status Operation
tPROG
R/B
Last Plane input
Pass
I/O0~7
80h
Address & Data Input
I/O
10h
71h
A0 ~ A7 & A9 ~ A25
528 Byte Data
Fail
Multi-Plane Block Erase
Basic concept of Multi-Plane Block Erase operation is identical to that of Multi-Plane Page Program. Up to four blocks, one from each
plane can be simultaneously erased. Standard Block Erase command sequences (Block Erase Setup command followed by three
address cycles) may be repeated up to four times for erasing up to four blocks. Only one block should be selected from each plane.
The Erase Confirm command initiates the actual erasing process. The completion is detected by analyzing R/B pin or Ready/Busy
status (I/O 6). Upon the erase completion, pass/fail status of each block is examined by reading extended pass/fail status(I/O 1
through I/O 4).
Figure 18. Four Block Erase Operation
R/B
tBERS
Address
(3 Cycle)
Address
(3 Cycle)
Address
(3 Cycle)
Address
(3 Cycle)
60h
D0h
71h
Pass
60h
60h
60h
I/O
I/O0~7
A0 ~ A7 & A9 ~ A25
Fail
33
K9F1208U0M
FLASH MEMORY
Copy-Back Program
The copy-back program is configured to quickly and efficiently rewrite data stored in one page within the plane to another page within
the same plane without utilizing an external memory. Since the time-consuming sequently-reading and its re-loading cycles are
removed, the system performance is improved. The benefit is especially obvious when a portion of a block is updated and the rest of
the block also need to be copied to the newly assigned free block. The operation for performing a copy-back program is a sequential
execution of page-read without burst-reading cycle and copying-program with the address of destination page. A normal read opera-
tion with "00h" command and the address of the source page moves the whole 528byte data into the internal page registers. As soon
as the device returns to Ready state, Page-Copy Data-input command (8Ah) with the address cycles of destination page followed
may be written. The Program Confirm command (10h) is required to actually begin the programming operation. Copy-Back Program
operation is allowed only within the same memory plane. Once the Copy-Back Program is finished, any additional partial page pro-
gramming into the copied pages is prohibited before erase. A14 and A15 must be the same between source and target page.
Figure19 shows the command sequence for single plane operation. "When there is a program-failure at Copy-Back operation,
error is reported by pass/fail status. But if the soure page has a bit error for charge loss, accumulated copy-back operations
could also accumulate bit errors. For this reason, two bit ECC is recommended for copy-back operation."
Figure 19. One Page Copy-Back program Operation
tR
tPROG
R/B
Add.(4Cycles)
Pass
I/O0~7
00h
Add.(4Cycles)
10h
I/O0
Fail
8Ah
70h
A0 ~ A7 & A9 ~ A25
Source Address
A0 ~ A7 & A9 ~ A25
Destination Address
34
K9F1208U0M
FLASH MEMORY
Multi-Plane Copy-Back Program
Multi-Plane Copy-Back Program is an extension of one page Copy-Back Program into four plane operation. Since the device is
equipped with four memory planes, activating the four sets of 528 byte page registers enables a simultaneous Multi-Plane Copy-Back
programming of four pages. Partial activation of four planes is also permitted.
First, normal read operation with the "00h"command and address of the source page moves the whole 528 byte data into internal
page buffers. Any further read operation for transferring the addressed pages to the corresponding page register must be executed
with "03h" command instead of "00h" command. Any plane may be selected without regard to "00h" or "03h". Up to four planes may
be addressed. Data moved into the internal page registers are loaded into the destination plane addresses. After the input of com-
mand sequences for reading the source pages, the same procedure as Multi-Plane Page programming except for a replacement
address command with "8Ah" is executed. Since no programming process is involved during data loading at the destination plane
address , R/B remains in Busy state for a short period of time(tDBSY). Read Status command (standard 70h or alternate 71h) may be
issued to find out when the device returns to Ready state by polling the Ready/Busy status bit(I/O 6). After inputting data for the last
plane, actual True Page Program (10h) instead of dummy Page Program command (11h) must be followed to start the programming
process. The operation of R/B and Read Status is the same as that of Page Program. Since maximum four pages are programmed
simultaneously, pass/fail status is available for each page when the program operation completes. No pointer operation is supported
with Multi-Plane Copy-Back Program. Once the Multi-Plane Copy-Back Program is finished, any additional partial page pro-
gramming into the copied pages is prohibited before erase once the Multi-Plane Copy-Back Program is finished.
Figure 20. Four-Plane Copy-Back Program
Max Three Times Repeatable
03h
03h
00h
03h
Source
Address
Input
Plane 3
(1024 Block)
Plane 0
(1024 Block)
Plane 2
(1024 Block)
Plane 1
(1024 Block)
Block 3
Block 7
Block 1
Block 5
Block 2
Block 6
Block 0
Block 4
Block 4091
Block 4095
Block 4089
Block 4093
Block 4090
Block 4094
Block 4088
Block 4092
Max Three Times Repeatable
8Ah
10h
8Ah
11h
8Ah
11h
8Ah
11h
Destination
Address
Input
Plane 3
(1024 Block)
Plane 0
(1024 Block)
Plane 2
(1024 Block)
Plane 1
(1024 Block)
Block 3
Block 7
Block 2
Block 6
Block 1
Block 5
Block 0
Block 4
Block 4091
Block 4095
Block 4090
Block 4094
Block 4089
Block 4093
Block 4088
Block 4092
35
K9F1208U0M
FLASH MEMORY
≈
≈
≈
≈
≈
≈
36
K9F1208U0M
FLASH MEMORY
READ STATUS
The device contains a Status Register which may be read to find out whether program or erase operation is completed, and whether
the program or erase operation is completed successfully. After writing 70h command to the command register, a read cycle outputs
the content of the Status Register to the I/O pins on the falling edge of CE or RE, whichever occurs last. This two line control allows
the system to poll the progress of each device in multiple memory connections even when R/B pins are common-wired. RE or CE
does not need to be toggled for updated status. Refer to table 2 for specific Status Register definitions. The command register
remains in Status Read mode until further commands are issued to it. Therefore, if the status register is read during a random read
cycle, a read command(00h or 50h) should be given before sequential page read cycle.
For Read Status of Multi Plane Program/Erase, the Read Multi-Plane Status command(71h) should be used to find out whether multi-
plane program or erase operation is completed, and whether the program or erase operation is completed successfully. The pass/fail
status data must be checked only in the Ready condition after the completion of Multi-Plane program or erase operation.
Table3. Read Staus Register Definition
I/O No.
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
Status
Definition by 70h Command
Definition by 71h Command
Pass : "0"(1)
Fail : "1"
Fail : "1"
Total Pass/Fail
Plane 0 Pass/Fail
Plane 1 Pass/Fail
Plane 2 Pass/Fail
Plane 3 Pass/Fail
Reserved
Pass : "0"
Fail : "1"
Pass : "0"(2)
Must be don’t -cared
Must be don’t -cared
Must be don’t -cared
Must be don’t -cared
Must be don’t -cared
Busy : "0"
Pass : "0"(2)
Fail : "1"
Fail : "1"
Fail : "1"
Pass : "0"(2)
Pass : "0"(2)
Must be don’t-cared
Busy : "0"
Device Operation
Write Protect
Ready : "1"
Ready : "1"
Protected : "0"
Not Protected : "1"
Protected : "0"
Not Protected : "1"
NOTE : 1. I/O 0 describes combined Pass/Fail condition for all planes. If any of the selected multiple pages/blocks fails in Program/
Erase operation, it sets "Fail" flag.
2. The pass/fail status applies only to the corresponding plane.
Read ID
The device contains a product identification mode, initiated by writing 90h to the command register, followed by an address input of
00h. Four read cycles sequentially output the manufacture code(ECh), and the device code (76h), Reserved(A5h), Multi plane opera-
tion code(C0h) respectively. A5h must be don’t-cared. C0h means that device supports Multi Plane operation. The command register
remains in Read ID mode until further commands are issued to it. Figure 22 shows the operation sequence.
Figure 22. Read ID Operation
tCLR
CLE
CE
tCEA
WE
tAR1
ALE
RE
tWHR
tREA
I/O0~7
90h
76h
00h
Address. 1cycle
ECh
A5h
C0h
Maker code
Device code
Multi-Plane code
37
K9F1208U0M
FLASH MEMORY
RESET
The device offers a reset feature, executed by writing FFh to the command register. When the device is in Busy state during random
read, program or erase mode, the reset operation will abort these operations. The contents of memory cells being altered are no
longer valid, as the data will be partially programmed or erased. The command register is cleared to wait for the next command, and
the Status Register is cleared to value C0h when WP is high. Refer to table 4 for device status after reset operation. If the device is
already in reset state a new reset command will not be accepted by the command register. The R/B pin transitions to low for tRST
after the Reset command is written. Refer to Figure 23 below.
Figure 23. RESET Operation
tRST
R/B
I/O0~7
FFh
Table4. Device Status
After Power-up
After Reset
Operation Mode
Read
Waiting for next command
38
K9F1208U0M
FLASH MEMORY
READY/BUSY
The device has a R/B output that provides a hardware method of indicating the completion of a page program, erase and random
read completion. The R/B pin is normally high but transitions to low after program or erase command is written to the command regis-
ter or random read is started after address loading. It returns to high when the internal controller has finished the operation. The pin is
an open-drain driver thereby allowing two or more R/B outputs to be Or-tied. Because pull-up resistor value is related to tr(R/B) and
current drain during busy(ibusy) , an appropriate value can be obtained with the following reference chart(Fig 24). Its value can be
determined by the following guidance.
Rp
ibusy
VCC
Ready Vcc
R/B
2.0V
open drain output
0.8V
Busy
tf
tr
GND
Device
Figure 24. Rp vs tr ,tf & Rp vs ibusy
@ Vcc = 3.3V, Ta = 25°C , CL = 100pF
381
3.3
Ibusy
300n
3m
290
1.1
1.65
189
200n
100n
2m
1m
tr
tf
96
0.825
4.2
4.2
2K
4.2
3K
4.2
4K
1K
Rp(ohm)
Rp value guidance
VCC(Max.) - VOL(Max.)
3.2V
Rp(min) =
=
IOL + ΣIL
8mA + ΣIL
where IL is the sum of the input currents of all devices tied to the R/B pin.
Rp(max) is determined by maximum permissible limit of tr
39
K9F1208U0M
FLASH MEMORY
Data Protection & Power-up sequence
The device is designed to offer protection from any involuntary program/erase during power-transitions. An internal voltage detector
disables all functions whenever Vcc is below about 2V. WP pin provides hardware protection and is recommended to be kept at VIL
during power-up and power-down. A recovery time of minimum 10µs is required before internal circuit gets ready for any command
sequences as shown in Figure 25. The two step command sequence for program/erase provides additional software protection.
Figure 25. AC Waveforms for Power Transition
~ 2.5V
~ 2.5V
VCC
High
WP
WE
10µs
40
FLASH MEMORY
Package Dimensions
Package Dimensions
48-Pin Lead / Lead Free Plastic Thin Small Out-Line Package Type(I)
48 - TSOP1 - 1220F
Unit :mm/Inch
20.00±0.20
0.787±0.008
#1
#48
#24
#25
1.00±0.05
0.039±0.002
0.05
0.002
MIN
1.20
0.047
MAX
18.40±0.10
0.724±0.004
0~8°
0.45~0.75
0.018~0.030
0.50
0.020
(
)
41
相关型号：
K9F1216D0A-PCB00
Flash, 32MX16, 30ns, PDSO48, 12 X 20 MM, 0.50 MM PITCH, LEAD FREE, PLASTIC, TSOP1-48
SAMSUNG
K9F1216D0A-PIB00
Flash, 32MX16, 30ns, PDSO48, 12 X 20 MM, 0.50 MM PITCH, LEAD FREE, PLASTIC, TSOP1-48
SAMSUNG
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