K9F5608X0D-FIB0 [SAMSUNG]
32M x 8 Bit NAND Flash Memory; 32M ×8位NAND闪存
| 型号： | K9F5608X0D-FIB0 |
| 厂家： | 
SAMSUNG |
| 描述： | 32M x 8 Bit NAND Flash Memory |
| 文件： | 总35页 (文件大小：861K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
K9F5608R0D
K9F5608U0D
FLASH MEMORY
K9F5608D0D
K9F5608X0D
INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS,
AND IS SUBJECT TO CHANGE WITHOUT NOTICE.
NOTHING IN THIS DOCUMENT SHALL BE CONSTRUED AS GRANTING ANY LICENSE,
EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE,
TO ANY INTELLECTUAL PROPERTY RIGHTS IN SAMSUNG PRODUCTS OR TECHNOLOGY. ALL
INFORMATION IN THIS DOCUMENT IS PROVIDED
ON AS "AS IS" BASIS WITHOUT GUARANTEE OR WARRANTY OF ANY KIND.
1. For updates or additional information about Samsung products, contact your nearest Samsung office.
2. Samsung products are not intended for use in life support, critical care, medical, safety equipment, or similar
applications where Product failure could result in loss of life or personal or physical harm, or any military or
defense application, or any governmental procurement to which special terms or provisions may apply.
* Samsung Electronics reserves the right to change products or specification without notice.
1
K9F5608R0D
K9F5608U0D
FLASH MEMORY
K9F5608D0D
Document Title
32M x 8 Bit NAND Flash Memory
Revision History
Revision No. History
Draft Date
Remark
0.0
0.1
0.2
1.0
1.1
Initial issue
May 16th. 2005
Aug. 11th. 2005
Oct. 17th. 2005
Oct. 30th. 2005
Dec. 30th 2005
Advance
1. Leaded package devices are eliminated
Advance
Preliminary
Final
1. LOCKPRE pin mode is eliminated
Note : For more detailed features and specifications including FAQ, please refer to Samsung’s Flash web site.
http://www.samsung.com/Products/Semiconductor/Flash/TechnicalInfo/datasheets.htm
The attached datasheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right
to change the specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions about device. If you have
any questions, please contact the SAMSUNG branch office near you.
2
K9F5608R0D
K9F5608U0D
FLASH MEMORY
K9F5608D0D
32M x 8 Bit NAND Flash Memory
PRODUCT LIST
Part Number
K9F5608R0D-J
K9F5608D0D-P
K9F5608D0D-J
K9F5608U0D-P
K9F5608U0D-J
K9F5608U0D-F
Vcc Range
Organization
PKG Type
FBGA
1.65 ~ 1.95V
TSOP1
FBGA
2.4 ~ 2.9V
2.7 ~ 3.6V
X8
TSOP1
FBGA
WSOP1
FEATURES
• Voltage Supply
- 1.8V device(K9F5608R0D) : 1.65~1.95V
- 2.65V device(K9F5608D0D) : 2.4~2.9V
- 3.3V device(K9F5608U0D) : 2.7 ~ 3.6 V
• Organization
• Command/Address/Data Multiplexed I/O Port
• Hardware Data Protection
- Program/Erase Lockout During Power Transitions
• Reliable CMOS Floating-Gate Technology
- Memory Cell Array
- Endurance
: 100K Program/Erase Cycles
-(32M + 1024K)bit x 8 bit
- Data Register
- Data Retention : 10 Years
• Command Register Operation
- (512 + 16)bit x 8bit
• Intelligent Copy-Back
• Automatic Program and Erase
- Page Program
• Unique ID for Copyright Protection
• Package
-(512 + 16)Byte
- K9F5608D(U)0D-PCB0/PIB0
- Block Erase :
- (16K + 512)Byte
48 - Pin TSOP I (12 x 20 / 0.5 mm pitch)- Pb-free Package
- K9F5608X0D-JCB0/JIB0
• Page Read Operation
- Page Size
63- Ball FBGA ( 9 x 11 /0.8mm pitch , Width 1.0 mm)
- Pb-free Package
- (512 + 16)Byte
- K9F5608U0D-FCB0/FIB0
- Random Access
- Serial Page Access : 50ns(Min.)
• Fast Write Cycle Time
: 15µs(Max.)
48 - Pin WSOP I (12X17X0.7mm)- Pb-free Package
* K9F5608U0D-F(WSOPI ) is the same device as
K9F5608U0D-P(TSOP1) except package type.
- Program time : 200µs(Typ.)
- Block Erase Time : 2ms(Typ.)
GENERAL DESCRIPTION
Offered in 32Mx8bit , the K9F5608X0D is 256M bit with spare 8M bit capacity. The device is offered in 1.8V, 2.65V, 3.3V Vcc. Its
NAND cell provides the most cost-effective solutIon for the solid state mass storage market. A program operation can be performed
in typical 200µs on a 528-byte page and an erase operation can be performed in typical 2ms on a 16K-byte block. Data in the page
can be read out at 50ns cycle time per byte. The I/O pins serve as the ports for address and data input/output as well as command
input. The on-chip write control automates all program and erase functions including pulse repetition, where required, and internal
verification and margining of data. Even the write-intensive systems can take advantage of the K9F5608X0D′s extended reliability of
100K program/erase cycles by providing ECC(Error Correcting Code) with real time mapping-out algorithm.
The K9F5608X0D is an optimum solution for large nonvolatile storage applications such as solid state file storage and other portable
applications requiring non-volatility.
3
K9F5608R0D
K9F5608U0D
FLASH MEMORY
K9F5608D0D
PIN CONFIGURATION (TSOP1)
K9F5608D(U)0D-PCB0/PIB0
N.C
N.C
N.C
N.C
I/O7
I/O6
I/O5
I/O4
N.C
N.C
N.C
Vcc
Vss
N.C
N.C
N.C
I/O3
I/O2
I/O1
I/O0
N.C
N.C
N.C
N.C
N.C
1
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
N.C
2
N.C
3
N.C
4
N.C
5
N.C
6
R/B
7
RE
8
CE
9
N.C
10
N.C
11
Vcc
Vss
N.C
N.C
CLE
ALE
WE
WP
N.C
N.C
N.C
N.C
N.C
12
13
14
15
16
17
18
19
20
21
22
23
24
PACKAGE DIMENSIONS
48-PIN LEAD/LEAD FREE PLASTIC THIN SMALL OUT-LINE PACKAGE TYPE(I)
48 - TSOP1 - 1220F
Unit :mm/Inch
20.00±0.20
0.787±0.008
#1
#48
#24
#25
1.00±0.05
0.039±0.002
0.05
0.002
MIN
1.20
0.047
MAX
18.40±0.10
0.724±0.004
0~8°
0.45~0.75
0.018~0.030
0.50
0.020
(
)
4
K9F5608R0D
K9F5608U0D
FLASH MEMORY
K9F5608D0D
PIN CONFIGURATION (FBGA)
K9F5608X0D-JCB0/JIB0
Top View
1
2
3
4
5
6
N.C N.C
N.C
N.C N.C
N.C N.C
A
/WP ALE Vss /CE /WE R/B
B
C
D
E
NC
NC
NC
NC
/RE CLE NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC NC
NC NC
NC NC
NC NC
NC
F
NC I/O0 NC
NC
Vcc
G
H
NC I/O1 NC VccQ I/O5 I/O7
Vss I/O2 I/O3 I/O4 I/O6 Vss
N.C N.C
N.C N.C
N.C N.C
N.C N.C
PACKAGE DIMENSIONS
63-Ball FBGA (measured in millimeters)
Top View
Bottom View
9.00±0.10
A
0.80 x 9= 7.20
0.80 x 5= 4.00
0.80
4
9.00±0.10
B
6
5
3
2
1
(Datum A)
#A1
A
B
(Datum B)
C
D
E
F
G
H
63-∅0.45±0.05
2.00
∅
0.20 M A B
Side View
9.00±0.10
0.10MAX
0.45±0.05
5
K9F5608R0D
K9F5608U0D
FLASH MEMORY
K9F5608D0D
PIN CONFIGURATION (WSOP1)
K9F5608U0D-FCB0/FIB0
N.C
N.C
DNU
N.C
I/O7
I/O6
I/O5
I/O4
N.C
DNU
N.C
Vcc
N.C
N.C
DNU
N.C
N.C
N.C
R/B
RE
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
1
2
3
4
5
6
7
8
CE
9
DNU
N.C
Vcc
Vss
N.C
DNU
CLE
ALE
WE
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
Vss
N.C
DNU
N.C
I/O3
I/O2
I/O1
I/O0
N.C
DNU
N.C
N.C
WP
N.C
N.C
DNU
N.C
N.C
PACKAGE DIMENSIONS
48-PIN LEAD PLASTIC VERY VERY THIN SMALL OUT-LINE PACKAGE TYPE (I)
Unit :mm
48 - WSOP1 - 1217F
0.70 MAX
0.58±0.04
15.40±0.10
#1
#48
#24
#25
(0.01Min)
0.45~0.75
17.00±0.20
6
K9F5608R0D
K9F5608U0D
FLASH MEMORY
K9F5608D0D
PIN DESCRIPTION
Pin NAME
Pin Function
DATA INPUTS/OUTPUTS
I/O0 ~ I/O7
CLE
The I/O pins are used to input command, address and data, and to output data during read operations. The I/
O pins float to high-z when the chip is deselected or when the outputs are disabled.
COMMAND LATCH ENABLE
The CLE input controls the activating path for commands sent to the command register. When active high,
commands are latched into the command register through the I/O ports on the rising edge of the WE signal.
ADDRESS LATCH ENABLE
ALE
The ALE input controls the activating path for address to the internal address registers. Addresses are
latched on the rising edge of WE with ALE high.
CHIP ENABLE
The CE input is the device selection control. When the device is in the Busy state, CE high is ignored, and
the device does not return to standby mode in program or erase operation. Regarding CE control during
read operation, refer to ’Page read’ section of Device operation.
CE
READ ENABLE
RE
WE
WP
The RE input is the serial data-out control, and when active drives the data onto the I/O bus. Data is valid
tREA after the falling edge of RE which also increments the internal column address counter by one.
WRITE ENABLE
The WE input controls writes to the I/O port. Commands, address and data are latched on the rising edge of
the WE pulse.
WRITE PROTECT
The WP pin provides inadvertent write/erase protection during power tra nsitions. The internal high voltage
generator is reset when the WP pin is active low.
READY/BUSY OUTPUT
The R/B output indicates the status of the device operation. When low, it indicates that a program, erase or
random read operation is in process and returns to high state upon completion. It is an open drain output and
does not float to high-z condition when the chip is deselected or when outputs are disabled.
R/B
OUTPUT BUFFER POWER
VccQ
VccQ is the power supply for Output Buffer.
VccQ is internally connected to Vcc, thus should be biased to Vcc.
POWER
Vcc
Vss
N.C
VCC is the power supply for device.
GROUND
NO CONNECTION
Lead is not internally connected.
DO NOT USE
Leave it disconnected
DNU
NOTE : Connect all VCC and VSS pins of each device to common power supply outputs.
Do not leave VCC or VSS disconnected.
7
K9F5608R0D
K9F5608U0D
FLASH MEMORY
K9F5608D0D
Figure 1-1. K9F5608X0D FUNCTIONAL BLOCK DIAGRAM
VCC
VSS
X-Buffers
A9 - A24
Latches
256M + 8M Bit
& Decoders
NAND Flash
ARRAY
Y-Buffers
Latches
A0 - A7
& Decoders
(512 + 16)Byte x 65536
Page Register & S/A
Y-Gating
A8
Command
Command
Register
VCC/VCCQ
VSS
I/O Buffers & Latches
Global Buffers
CE
RE
WE
Control Logic
& High Voltage
Generator
I/0 0
Output
Driver
I/0 7
CLE ALE
WP
Figure 2-1. K9F5608X0D ARRAY ORGANIZATION
1 Block =32 Pages
= (16K + 512) Byte
1 Page = 528 Byte
1 Block = 528 Byte x 32 Pages
= (16K + 512) Byte
1 Device = 528Bytes x 32Pages x 2048 Blocks
= 264 Mbits
64K Pages
(=2,048 Blocks)
1st half Page Register
(=256 Bytes)
2nd half Page Register
(=256 Bytes)
8 bit
512Byte
16 Byte
16 Byte
I/O 0 ~ I/O 7
Page Register
512 Byte
I/O 0
A0
I/O 1
A1
I/O 2
I/O 3
A3
I/O 4
A4
I/O 5
A5
I/O 6
A6
I/O 7
A7
1st Cycle
A2
A11
A19
Column Address
Row Address
(Page Address)
2nd Cycle
3rd Cycle
A9
A10
A18
A12
A20
A13
A21
A14
A22
A15
A23
A16
A24
A17
NOTE : Column Address : Starting Address of the Register.
00h Command(Read) : Defines the starting address of the 1st half of the register.
01h Command(Read) : Defines the starting address of the 2nd half of the register.
* A8 is set to "Low" or "High" by the 00h or 01h Command.
* The device ignores any additional input of address cycles than required.
8
K9F5608R0D
K9F5608U0D
FLASH MEMORY
K9F5608D0D
PRODUCT INTRODUCTION
The K9F5608X0D is a 264Mbit(276,824,064 bit) memory organized as 65,536 rows(pages) by 528 columns. Spare eight columns are
located from column address of 512~527. A 528-byte data register is connected to memory cell arrays accommodating data transfer
between the I/O buffers and memory during page read and page program operations.The memory array is made up of 16 cells that
are serially connected to form a NAND structure. Each of the 16 cells resides in a different page. A block consists of two NAND struc-
tured strings. A NAND structure consists of 16 cells. Total 135168 NAND cells reside in a block. The array organization is shown in
Figure 2-1. The program and read operations are executed on a page basis, while the erase operation is executed on a block basis.
The memory array consists of 2048 separately erasable 16K-Byte blocks. It indicates that the bit by bit erase operation is prohibited
on the K9F5608X0D.
The K9F5608X0D has addresses multiplexed into 8 I/Os. This scheme dramatically reduces pin counts while providing high perfor-
mance and allows systems upgrades to future densities by maintaining consistency in system board design. Command, address and
data are all written through I/O′s by bringing WE to low while CE is low. Data is latched on the rising edge of WE. Command Latch
Enable(CLE) and Address Latch Enable(ALE) are used to multiplex command and address respectively, via the I/O pins. Some com-
mands require one bus cycle. For example, Reset command, Read command, Status Read command, etc require just one cycle bus.
Some other commands like Page Program and Copy-back Program and Block Erase, require two cycles: one cycle for setup and the
other cycle for execution. The 32M-byte physical space requires 24 addresses, thereby requiring three cycles for word-level address-
ing: column address, low row address and high row address, in that order. Page Read and Page Program need the same three
address cycles following the required command input. In Block Erase operation, however, only the two row address cycles are used.
Device operations are selected by writing specific commands into the command register. Table 1 defines the specific commands of
the K9F5608X0D.
The device includes one block sized OTP(One Time Programmable), which can be used to increase system security or to provide
identification capabilities. Detailed information can be obtained by contact with Samsung.
Table 1. COMMAND SETS
Function
1st. Cycle
2nd. Cycle
Acceptable Command during Busy
Read 1
Read 2
Read ID
Reset
-
00h/01h
50h
-
-
90h
FFh
80h
-
O
O
Page Program
Copy-Back Program
Block Erase
10h
8Ah
D0h
-
00h
60h
Read Status
70h
Caution : Any undefined command inputs are prohibited except for above command set of Table 1.
9
K9F5608R0D
K9F5608U0D
FLASH MEMORY
K9F5608D0D
ABSOLUTE MAXIMUM RATINGS
Parameter
Symbol
VIN/OUT
VCC
Rating
Unit
-0.6 to + 4.6
-0.6 to + 4.6
-0.6 to + 4.6
-10 to +125
-40 to +125
Voltage on any pin relative to VSS
V
VCCQ
K9F5608X0D-XCB0
Temperature Under Bias
TBIAS
°C
K9F5608X0D-XIB0
K9F5608X0D-XCB0
Storage Temperature
TSTG
Ios
-65 to +150
5
°C
K9F5608X0D-XIB0
Short Circuit Current
mA
NOTE :
1. Minimum DC voltage is -0.6V on input/output pins. During transitions, this level may undershoot to -2.0V for periods <30ns.
Maximum DC voltage on input/output pins is VCC,+0.3V which, during transitions, may overshoot to VCC+2.0V for periods <20ns.
2. Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to the conditions
as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
RECOMMENDED OPERATING CONDITIONS
(Voltage reference to GND, K9F5608X0D-XCB0 :TA=0 to 70°C, K9F5608X0D-XIB0:TA=-40 to 85°C)
K9F5608R0D(1.8V)
K9F5608D0D(2.65V)
K9F5608U0D(3.3V)
Parameter
Symbol
Unit
Min
Typ.
1.8
1.8
0
Max
Min
Typ.
2.65
2.65
0
Max
Min
Typ.
3.3
3.3
0
Max
Supply Voltage
Supply Voltage
Supply Voltage
VCC
VCCQ
VSS
1.65
1.65
0
1.95
1.95
0
2.4
2.4
0
2.9
2.9
0
2.7
2.7
0
3.6
3.6
0
V
V
V
10
K9F5608R0D
K9F5608U0D
FLASH MEMORY
K9F5608D0D
DC AND OPERATING CHARACTERISTICS(Recommended operating conditions otherwise noted.)
K9F5608X0D
Parameter
Symbol
Test Conditions
1.8V
2.65V
3.3V
Unit
Min Typ Max Min Typ Max Min Typ Max
Sequential
Read
tRC=50ns, CE=VIL
IOUT=0mA
Operat-
ing
ICC1
-
8
20
-
10
20
-
10 20
Current Program
ICC2
ICC3
-
-
-
-
-
8
8
-
20
20
1
-
-
-
10
10
-
20
20
1
-
-
-
10 25
10 25
mA
Erase
Stand-by Current(TTL)
ISB1 CE=VIH, WP=0V/VCC
-
1
Stand-by Cur-
rent(CMOS)
ISB2 CE=VCC-0.2, WP=0V/VCC
-
10
50
-
10
50
-
10 50
µA
Input Leakage Current
Output Leakage Current
ILI
VIN=0 to Vcc(max)
-
-
-
-
±10
±10
-
-
-
-
±10
±10
-
-
-
-
±10
±10
ILO
VOUT=0 to Vcc(max)
VccQ
-0.4
VCCQ VCCQ
+0.3 -0.4
VCCQ
+0.3
VCCQ
+0.3
I/O pins
-
-
-
-
-
-
2.0
2.0
-
-
-
Input High Voltage
VIH*
VIL*
VCC
-0.4
VCC VCC
+0.3 -0.4
VCC
VCC
Except I/O pins
+0.3
+0.3
Input Low Voltage, All
inputs
-
-0.3
0.4 -0.3
0.5 -0.3
0.8
V
K9F5608R0D :IOH=-100µA
Output High Voltage
Level
VCCQ
-0.1
VCCQ
VOH K9F5608D0D :IOH=-100µA
K9F5608U0D :IOH=-400µA
-
-
-
-
-
-
0.4
-
2.4
-
-
-
-
-0.4
K9F5608R0D :IOL=100uA
VOL K9F5608D0D :IOL=100µA
K9F5608U0D :IOL=2.1mA
Output Low Voltage
Level
-
0.1
-
-
0.4
-
K9F5608R0D :VOL=0.1V
Output Low Current(R/B) IOL(R/B) K9F5608D0D :VOL=0.1V
K9F5608U0D :VOL=0.4V
3
4
3
4
8
10
mA
NOTE : VIL can undershoot to -0.4V and VIH can overshoot to VCC +0.4V for durations of 20 ns or less.
11
K9F5608R0D
K9F5608U0D
FLASH MEMORY
K9F5608D0D
VALID BLOCK
Parameter
Symbol
Min
Typ.
Max
Unit
Valid Block Number
NVB
2013
-
2048
Blocks
NOTE :
1. The device may include invalid blocks when first shipped. Additional invalid blocks may develop while being used. The number of valid blocks is pre-
sented with both cases of invalid blocks considered. Invalid blocks are defined as blocks that contain one or more bad bits. Do not erase or program
factory-marked bad blocks. Refer to the attached technical notes for a appropriate management of invalid blocks.
2. The 1st block, which is placed on 00h block address, is guaranteed to be a valid block, does not require Error Correction up to 1K Program/Erase
cycles.
3. Minimum 1004 valid blocks are guaranteed for each contiguous 128Mb memory space.
AC TEST CONDITION
(K9F5608X0D-XCB0 :TA=0 to 70°C, K9F5608X0D-XIB0:TA=-40 to 85°C
K9F5608R0D : Vcc=1.65V~1.95V , K9F5608D0D : Vcc=2.4V~2.9V , K9F5608U0D : Vcc=2.7V~3.6V unless otherwise noted)
Parameter
K9F5608R0D
0V to VccQ
5ns
K9F5608D0D
0V to VccQ
5ns
K9F5608U0D
0.4V to 2.4V
5ns
Input Pulse Levels
Input Rise and Fall Times
Input and Output Timing Levels
VccQ/2
VccQ/2
1.5V
K9F5608R0D:Output Load (VccQ:1.8V +/-10%)
K9F5608D0D:Output Load (VccQ:2.65V +/-10%) 1 TTL GATE and CL=30pF 1 TTL GATE and CL=30pF 1 TTL GATE and CL=50pF
K9F5608U0D:Output Load (VccQ:3.0V +/-10%)
K9F5608U0D:Output Load (VccQ:3.3V +/-10%)
-
-
1 TTL GATE and CL=100pF
CAPACITANCE(TA=25°C, VCC=1.8V/2.65V/3.3V, f=1.0MHz)
Item
Symbol
Test Condition
Min
Max
Unit
pF
Input/Output Capacitance
Input Capacitance
CI/O
VIL=0V
-
-
10
10
CIN
VIN=0V
pF
NOTE : Capacitance is periodically sampled and not 100% tested.
MODE SELECTION
CLE
H
L
ALE
L
CE
L
WE
RE
H
WP
X
Mode
Command Input
Read Mode
Write Mode
H
L
L
H
X
Address Input(3clock)
Command Input
H
L
L
H
H
H
L
L
H
H
Address Input(3clock)
L
L
H
H
Data Input
Data Output
L
L
L
H
H
X
L
L
L
H
H
X
During Read(Busy) On K9F5608U0D_Y,P,V,F or K9F5608D0D_Y,P
During Read(Busy) on the devices except On K9F5608U0D_Y,P,V,F or
K9F5608D0D_Y,P
X
X
X
X
X
X
X
X
X
X
X
X
X
X
H
X
X
X
X
X
X
X
X
H
During Program(Busy)
During Erase(Busy)
Write Protect
H
L
X(1)
X
(2)
Stand-by
0V/VCC
NOTE : 1. X can be VIL or VIH.
2. WP should be biased to CMOS high or CMOS low for standby.
12
K9F5608R0D
K9F5608U0D
FLASH MEMORY
K9F5608D0D
PROGRAM/ERASE CHARACTERISTICS
Parameter
Symbol
Min
Typ
Max
500
2
Unit
µs
Program Time
tPROG
-
-
-
-
200
Main Array
Spare Array
-
-
cycles
cycles
ms
Number of Partial Program Cycles
in the Same Page
Nop
3
Block Erase Time
tBERS
2
3
AC TIMING CHARACTERISTICS FOR COMMAND / ADDRESS / DATA INPUT
Parameter
CLE setup Time
Symbol
tCLS
tCLH
tCS
Min
0
Max
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
-
-
-
-
-
-
-
-
-
-
-
-
CLE Hold Time
10
0
CE setup Time
CE Hold Time
tCH
10
25(1)
0
WE Pulse Width
ALE setup Time
ALE Hold Time
tWP
tALS
tALH
tDS
10
20
10
50
15
100
Data setup Time
Data Hold Time
tDH
Write Cycle Time
WE High Hold Time
Address to Data Loading Time
tWC
tWH
tADL
NOTE: 1. If tCS is set less than 10ns, tWP must be minimum 35ns, otherwise, tWP may be minimum 25ns.
13
K9F5608R0D
K9F5608U0D
FLASH MEMORY
K9F5608D0D
AC CHARACTERISTICS FOR OPERATION
Parameter
Data Transfer from Cell to Register
ALE to RE Delay
Symbol
Min
-
Max
Unit
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
tR
tAR
15
10
10
20
25
-
-
CLE to RE Delay
tCLR
tRR
-
Ready to RE Low
-
RE Pulse Width
tRP
-
WE High to Busy
tWB
tRC
100
Read Cycle Time
50
-
-
30/35(1)
RE Access Time
tREA
tCEA
tRHZ
tCHZ
tOH
CE Access Time
-
45
RE High to Output Hi-Z
CE High to Output Hi-Z
RE or CE High to Output hold
RE High Hold Time
-
30
-
20
15
15
0
-
tREH
tIR
-
Output Hi-Z to RE Low
WE High to RE Low
-
tWHR
tRST
60
-
-
5/10/500(2)
Device Resetting Time(Read/Program/Erase)
Symbol
tRB
Min
Max
Uni
ns
K9F5608U0D-
P,F or
K9F5608D0D--
Last RE High to Busy(at sequential read)
-
-
100
50 +tr(R/B)(3)
-
CE High to Ready(in case of interception by CE at
CE High Hold Time(at the last serial read)(4)
tCRY
ns
tCEH
100
ns
P
only
NOTE: 1. K9F5608R0D tREA = 35ns.
2. If reset command(FFh) is written at Ready state, the device goes into Busy for maximum 5us.
3. The time to Ready depends on the value of the pull-up resistor tied R/B pin.
4. To break the sequential read cycle, CE must be held high for longer time than tCEH.
14
K9F5608R0D
K9F5608U0D
FLASH MEMORY
K9F5608D0D
NAND Flash Technical Notes
Initial Invalid Block(s)
Initial invalid blocks are defined as blocks that contain one or more initial invalid bits whose reliability is not guaranteed by Samsung.
The information regarding the initial invalid block(s) is so called as the initial invalid block information. Devices with initial invalid
block(s) have the same quality level as devices with all valid blocks and have the same AC and DC characteristics. An initial invalid
block(s) does not affect the performance of valid block(s) because it is isolated from the bit line and the common source line by a
select transistor. The system design must be able to mask out the invalid block(s) via address mapping. The 1st block, which is
placed on 00h block address, is guaranteed to be a valid block, does not require Error Correction up to 1K Program/Erase cycles.
Identifying Initial Invalid Block(s)
All device locations are erased(FFh) except locations where the initial invalid block(s) information is written prior to shipping. The
initial invalid block(s) status is defined by the 6th byte in the spare area. Samsung makes sure that either the 1st or 2nd page of every
initial invalid block has non-FFh data at the column address of 517. Since the initial invalid block information is also erasable in most
cases, it is impossible to recover the information once it has been erased. Therefore, the system must be able to recognize the initial
invalid block(s) based on the initial invalid block information and create the initial invalid block table via the following suggested flow
chart(Figure 3). Any intentional erasure of the initial invalid block information is prohibited.
Start
Set Block Address = 0
Increment Block Address
Check "FFh" at the column address
517of the 1st and 2nd page in the block
*
No
Create (or update)
Check "FFh" ?
Initial
Invalid Block(s) Table
Yes
No
Last Block ?
Yes
End
Figure 3. Flow chart to create initial invalid block table.
15
K9F5608R0D
K9F5608U0D
FLASH MEMORY
K9F5608D0D
NAND Flash Technical Notes (Continued)
Error in write or read operation
Within its life time, the additional invalid blocks may develop with NAND Flash memory. Refer to the qualification report for the actual
data.The following possible failure modes should be considered to implement a highly reliable system. In the case of status read fail-
ure after erase or program, block replacement should be done. Because program status fail during a page program does not affect
the data of the other pages in the same block, block replacement can be executed with a page-sized buffer by finding an erased
empty block and reprogramming the current target data and copying the rest of the replaced block. In case of Read, ECC must be
employed. To improve the efficiency of memory space, it is recommended that the read or verification failure due to single bit error be
reclaimed by ECC without any block replacement. The said additional block failure rate does not include those reclaimed blocks.
Failure Mode
Erase Failure
Detection and Countermeasure sequence
Status Read after Erase --> Block Replacement
Status Read after Program --> Block Replacement
Verify ECC -> ECC Correction
Write
Read
Program Failure
Single Bit Failure
: Error Correcting Code --> Hamming Code etc.
Example) 1bit correction & 2bit detection
ECC
Program Flow Chart
Start
Write 80h
Write Address
Write Data
Write 10h
Read Status Register
No
I/O 6 = 1 ?
or R/B = 1 ?
Yes
*
No
Program Error
I/O 0 = 0 ?
Yes
Program Completed
: If program operation results in an error, map out
the block including the page in error and copy the
target data to another block.
*
16
K9F5608R0D
K9F5608U0D
FLASH MEMORY
K9F5608D0D
NAND Flash Technical Notes (Continued)
Erase Flow Chart
Read Flow Chart
Start
Start
Write 60h
Write 00h
Write Block Address
Write Address
Read Data
Write D0h
Read Status Register
ECC Generation
No
No
I/O 6 = 1 ?
or R/B = 1 ?
Reclaim the Error
Verify ECC
Yes
Yes
*
No
Page Read Completed
Erase Error
I/O 0 = 0 ?
Yes
Erase Completed
: If erase operation results in an error, map out
the failing block and replace it with another block.
*
Block Replacement
Block A
1st
2
{
(n-1)th
nth
an error occurs.
(page)
Buffer memory of the controller.
Block B
1st
1
{
(n-1)th
nth
(page)
* Step1
When an error happens in the nth page of the Block ’A’ during erase or program operation.
* Step2
Copy the nth page data of the Block ’A’ in the buffer memory to the nth page of another free block. (Block ’B’)
* Step3
Then, copy the data in the 1st ~ (n-1)th page to the same location of the Block ’B’.
* Step4
Do not further erase Block ’A’ by creating an ’invalid Block’ table or other appropriate scheme.
17
K9F5608R0D
K9F5608U0D
FLASH MEMORY
K9F5608D0D
Pointer Operation of K9F5608X0D(X8)
Samsung NAND Flash has three address pointer commands as a substitute for the two most significant column addresses. ’00h’
command sets the pointer to ’A’ area(0~255byte), ’01h’ command sets the pointer to ’B’ area(256~511byte), and ’50h’ command sets
the pointer to ’C’ area(512~527byte). With these commands, the starting column address can be set to any of a whole
page(0~527byte). ’00h’ or ’50h’ is sustained until another address pointer command is inputted. ’01h’ command, however, is effective
only for one operation. After any operation of Read, Program, Erase, Reset, Power_Up is executed once with ’01h’ command, the
address pointer returns to ’A’ area by itself. To program data starting from ’A’ or ’C’ area, ’00h’ or ’50h’ command must be inputted
before ’80h’ command is written. A complete read operation prior to ’80h’ command is not necessary. To program data starting from
’B’ area, ’01h’ command must be inputted right before ’80h’ command is written.
Table 2. Destination of the pointer
Command
Pointer position
Area
"A" area
"B" area
"C" area
(00h plane)
(01h plane)
(50h plane)
00h
01h
50h
0 ~ 255 byte
256 ~ 511 byte
512 ~ 527 byte
1st half array(A)
2nd half array(B)
spare array(C)
256 Byte
256 Byte
16 Byte
"A"
"B"
"C"
Internal
Page Register
Pointer select
commnad
(00h, 01h, 50h)
Pointer
Figure 4. Block Diagram of Pointer Operation
(1) Command input sequence for programming ’A’ area
The address pointer is set to ’A’ area(0~255), and sustained
Address / Data input
Address / Data input
80h 10h
00h
80h
10h
00h
’A’,’B’,’C’ area can be programmed.
’00h’ command can be omitted.
It depends on how many data are inputted.
(2) Command input sequence for programming ’B’ area
The address pointer is set to ’B’ area(256~512), and will be reset to
’A’ area after every program operation is executed.
Address / Data input
Address / Data input
80h 10h
01h
80h
10h
01h
’B’, ’C’ area can be programmed.
It depends on how many data are inputted.
’01h’ command must be rewritten before
every program operation
(3) Command input sequence for programming ’C’ area
The address pointer is set to ’C’ area(512~527), and sustained
Address / Data input
Address / Data input
80h 10h
50h
80h
10h
50h
Only ’C’ area can be programmed.
’50h’ command can be omitted.
18
K9F5608R0D
K9F5608U0D
FLASH MEMORY
K9F5608D0D
System Interface Using CE don’t-care.
For an easier system interface, CE may be inactive during the data-loading or sequential data-reading as shown below. The internal
528byte page registers are utilized as seperate buffers for this operation and the system design gets more flexible. In addition, for
voice or audio applications which use slow cycle time on the order of u-seconds, de-activating CE during the data-loading and read-
ing would provide significant savings in power consumption.
Figure 6. Program Operation with CE don’t-care.
CLE
CE don’t-care
CE
WE
ALE
I/Ox
80h
Start Add.(3Cycle)
Data Input
Data Input
10h
tCS
tCH
tCEA
CE
RE
CE
tREA
tWP
tOH
WE
I/O0~7
out
Figure 7. Read Operation with CE don’t-care.
CLE
On K9F5608U0D_Y,P,V,F or K9F5608D0D_Y,P
CE must be held
CE don’t-care
low during tR
CE
RE
ALE
tR
R/B
WE
I/Ox
Data Output(sequential)
00h
Start Add.(3Cycle)
19
K9F5608R0D
K9F5608U0D
FLASH MEMORY
K9F5608D0D
I/O
I/Ox
DATA
Device
K9F5608X0D(X8 device)
Data In/Out
~528byte
I/O 0 ~ I/O 7
NOTE: 1. I/O8~15 must be set to "0" during command or address input.
I/O8~15 are used only for data bus.
Command Latch Cycle
CLE
tCLH
tCH
tCLS
tCS
CE
tWP
WE
tALS
tALH
ALE
tDH
tDS
Command
I/Ox
Address Latch Cycle
tCLS
CLE
tCS
tWC
tWC
CE
tCH
tWP
tWP
tWP
WE
tWH
tALH
tALS
tWH
tALH
tALS
tALH
tALS
ALE
I/Ox
tDH
tDH
tDH
tDS
tDS
tDS
AO~A7
A9~A16
A17~A24
20
K9F5608R0D
K9F5608U0D
FLASH MEMORY
K9F5608D0D
Input Data Latch Cycle
tCLH
CLE
tCH
CE
tWC
tALS
ALE
tWP
tWP
tWP
WE
tWH
tDH
tDH
tDH
tDS
tDS
tDS
I/Ox
DIN n
DIN 0
DIN 1
Sequential Out Cycle after Read(CLE=L, WE=H, ALE=L)
tRC
CE
tCHZ*
tOH
tREH
tREA
tREA
tREA
tRP
RE
tRHZ*
tRHZ*
tOH
I/Ox
Dout
Dout
Dout
tRR
R/B
NOTES : Transition is measured ±200mV from steady state voltage with load.
This parameter is sampled and not 100% tested.
21
K9F5608R0D
K9F5608U0D
FLASH MEMORY
K9F5608D0D
Status Read Cycle
tCLR
CLE
CE
tCLS
tCS
tCLH
tCH
tWP
WE
tCEA
tCHZ
tOH
tWHR1
RE
tRHZ
tOH
tDH
tREA
tDS
tIR
Status Output
I/Ox
70h
Read1 Operation (Read One Page)
CLE
1)
tCEH
On K9F5608U0D_Y,P,V,F or K9F5608D0D_Y,P
CE must be held
low during tR
CE
tCHZ
tOH
tWC
WE
tWB
tCRY
tAR
ALE
tRHZ
tOH
tR
tRC
RE
N Address
tRR
Read
CMD
A9~A16
A17~A24
Dout N+3
A0~A7
Dout N
Dout N+1 Dout N+2
Dout m
tRB
I/Ox
R/B
Column
Address
Page(Row)
Address
Busy
1)
m = 528 , Read CMD = 00h or 01h
NOTES : 1) is only valid On K9F5608U0D_Y,P,V,F or K9F5608D0D_Y,P
22
K9F5608R0D
K9F5608U0D
FLASH MEMORY
K9F5608D0D
Read1 Operation (Intercepted by CE)
CLE
On K9F5608U0D_Y,P,V,F or K9F5608D0D_Y,P
CE must be held
low during tR
CE
WE
ALE
tWB
tCHZ
tOH
tAR
tR
tRC
RE
N Address
tRR
Read
CMD
Dout N+2
Dout N+3
Dout N
Dout N+1
Row Add1 Row Add2
Col. Add
I/Ox
R/B
Page(Row)
Address
Column
Address
Busy
Read2 Operation (Read One Page)
CLE
CE
On K9F5608U0D_Y,P,V,F or K9F5608D0D_Y,P
CE must be held
low during tR
WE
ALE
RE
tR
tWB
tAR
tRR
Dout
n+M+1
Dout
n+M
I/Ox
R/B
50h
Row Add1 Row Add2
Dout n+m
Col. Add
Selected
Row
M Address
A0~A3 are Valid Address & A4~A7 are Don′t care
m
n
n = 512, m = 16
Start
address M
23
K9F5608R0D
K9F5608U0D
FLASH MEMORY
K9F5608D0D
Sequential Row Read Operation (only for On K9F5608U0D_Y,P,V,F or K9F5608D0D_Y,P)
CLE
CE
WE
ALE
RE
Dout
N
Dout
N+1
Dout
N+2
Dout
527
Dout
0
Dout
1
Dout
2
Dout
527
Row Add2
Col. Add Row Add1
00h
I/Ox
R/B
Ready
Busy
Busy
M
M+1
Output
N
Output
Page Program Operation
CLE
CE
tWC
tWC
tWC
WE
tADL
tPROG
tWB
ALE
RE
N Address
Din
m
Din
N
Din
N+1
10h
Program
80h
Row Add1 Row Add2
70h
I/O0
Col. Add
I/Ox
R/B
Sequential Data
Input Command
Column
Address
1 up to m Data
Serial Input
Read Status
Command
Page(Row)
Address
Command
I/O0=0 Successful Program
I/O0=1 Error in Program
m = 528 byte
24
K9F5608R0D
K9F5608U0D
FLASH MEMORY
K9F5608D0D
Copy-Back Program Operation
CLE
CE
tWC
WE
ALE
RE
tWB
tWB
tPROG
tR
I/Ox
R/B
Row Add1 Row Add2
8Ah
00h
Col. Add
70h
I/O0
A0~A7 A9~A16 A17~A24
Program
Command
Column
Address
Column
Address
Read Status
Command
Page(Row)
Address
Page(Row)
Address
I/O0=0 Successful Program
I/O0=1 Error in Program
Busy
Busy
Block Erase Operation (Erase One Block)
CLE
CE
tWC
WE
tBERS
tWB
ALE
RE
I/Ox
A9~A16
A17~A24
60h
D0h
70h
I/O 0
Page(Row)
Address
Busy
R/B
I/O0=0 Successful Erase
Read Status I/O0=1 Error in Erase
Command
Auto Block Erase
Setup Command
Erase Command
25
K9F5608R0D
K9F5608U0D
FLASH MEMORY
K9F5608D0D
Manufacture & Device ID Read Operation
CLE
CE
WE
ALE
RE
tAR
tREA
Device
Code*
I/Ox
90h
00h
ECh
Read ID Command
Address. 1cycle
Maker Code
Device Code
Device
Device Code*
K9F5608R0D
35h
75h
75h
K9F5608D0D
K9F5608U0D
26
K9F5608R0D
K9F5608U0D
FLASH MEMORY
K9F5608D0D
DEVICE OPERATION
PAGE READ
Upon initial device power up, the device defaults to Read1 mode. This operation is also initiated by writing 00h to the command regis-
ter along with three address cycles. Once the command is latched, it does not need to be written for the following page read opera-
tion. Two types of operations are available : random read, serial page read.
The random read mode is enabled when the page address is changed. The 528 byte of data within the selected page are transferred
to the data registers in less than 15µs(tR). The system controller can detect the completion of this data transfer(tR) by analyzing the
output of R/B pin. Once the data in a page is loaded into the registers, they may be read out in 50ns cycle time by sequentially pulsing
RE. High to low transitions of the RE clock output the data starting from the selected column address up to the last column address.
The way the Read1 and Read2 commands work is like a pointer set to either the main area or the spare area. Addresses A0~A3 set
the starting address of the spare area while addresses A4~A7 are ignored . The Read1 command is needed to move the pointer back
to the main area. Figures 8,9 show typical sequence and timings for each read operation.
Sequential Row Read is available only on K9F5608U0D_Y,P,V,F or K9F5608D0D_Y,P :
After the data of last column address is clocked out, the next page is automatically selected for sequential row read. Waiting 15µs
again allows reading the selected page. The sequential row read operation is terminated by bringing CE high. Unless the operation
is aborted, the page address is automatically incremented for sequential row read as in Read1 operation and spare sixteen bytes of
each page may be sequentially read. The Sequential Read 1 and 2 operations are allowed only within a block and after the last page
of a block being readout, the sequential read operation must be terminated by bringing CE high. When the page address moves onto
the next block, read command and address must be given. Figures 8-1, 9-1 show typical sequence and timings for sequential row
read operation.
Figure8. Read1 Operation
CLE
On K9F5608U0D_Y,P,V,F or K9F5608D0D_Y,P
CE must be held
CE
low during tR
WE
ALE
R/B
tR
RE
I/Ox
Start Add.(3Cycle)
A0 ~ A7 & A9 ~ A24
00h
Data Output(Sequential)
(00h Command)
(01h Command)
1)
1st half array 2st half array
Main array
Data Field
Spare Field
Data Field
Spare Field
NOTE: 1) After data access on 2nd half array by 01h command, the start pointer is automatically moved to 1st half
array (00h) at next cycle.
27
K9F5608R0D
K9F5608U0D
FLASH MEMORY
K9F5608D0D
Figure 9. Read2 Operation
CLE
On K9F5608U0D_Y,P,V,F or K9F5608D0D_Y,P
CE must be held
low during tR
CE
WE
ALE
R/B
tR
RE
Start Add.(3Cycle)
I/Ox
50h
Data Output(Sequential)
Spare Field
A4 ~ A7 Don’t care
Main array
Data Field
Spare Field
Figure 8-1. Sequential Row Read1 Operation (only for K9F5608U0D_Y,P,V,F or K9F5608D0D_Y,P)
tR
tR
tR
R/B
I/Ox
Data Output
1st
Data Output
Data Output
00h
01h
Start Add.(3Cycle)
A0 ~ A7 & A9 ~ A24
2nd
(528 Byte)
Nth
(528 Byte)
(00h Command)
(01h Command)
1st half array
2nd half array
1st half array
2nd half array
1st
1st
2nd
Nth
Block
2nd
Nth
Data Field
Spare Field
Data Field
Spare Field
28
K9F5608R0D
K9F5608U0D
FLASH MEMORY
K9F5608D0D
Figure 9-1. Sequential Row Read2 Operation (only for K9F5608U0D_Y,P,V,F or K9F5608D0D_Y,P)
tR
tR
tR
R/B
I/Ox
Start Add.(3Cycle)
Data Output
1st
Data Output
50h
Data Output
2nd
(16Byte)
Nth
(16Byte)
A0 ~ A3 & A9 ~ A24
(A4 ~ A7 :
Don′t Care)
1st
Block
Nth
Data Field
Spare Field
29
K9F5608R0D
K9F5608U0D
FLASH MEMORY
K9F5608D0D
PAGE PROGRAM
The device is programmed basically on a page basis, but it does allow multiple partial page programing of a byte/word or consecutive
bytes/words up to 528, in a single page program cycle. The number of consecutive partial page programming operation within the
same page without an intervening erase operation should not exceed 2 for main array and 3 for spare array. The addressing may be
done in any random order in a block. A page program cycle consists of a serial data loading period in which up to 528 bytes of data
may be loaded into the page register, followed by a non-volatile programming period where the loaded data is programmed into the
appropriate cell. About the pointer operation, please refer to the attached technical notes.
The serial data loading period begins by inputting the Serial Data Input command(80h), followed by the three cycle address input and
then serial data loading. The words other than those to be programmed do not need to be loaded.The Page Program confirm com-
mand(10h) initiates the programming process. Writing 10h alone without previously entering the serial data will not initiate the pro-
gramming process. The internal write controller automatically executes the algorithms and timings necessary for program and verify,
thereby freeing the system controller for other tasks. Once the program process starts, the Read Status Register command may be
entered, with RE and CE low, to read the status register. The system controller can detect the completion of a program cycle by mon-
itoring the R/B output, or the Status bit(I/O 6) of the Status Register. Only the Read Status command and Reset command are valid
while programming is in progress. When the Page Program is complete, the Write Status Bit(I/O 0) may be checked(Figure 10). The
internal write verify detects only errors for "1"s that are not successfully programmed to "0"s. The command register remains in Read
Status command mode until another valid command is written to the command register.
Figure 10. Program Operation
tPROG
R/B
I/Ox
Pass
80h
Address & Data Input
I/O0
Fail
10h
70h
COPY-BACK PROGRAM
The copy-back program is configured to quickly and efficiently rewrite data stored in one page within the array to another page within
the same array without utilizing an external memory. Since the time-consuming sequently-reading and its re-loading cycles are
removed, the system performance is improved. The benefit is especially obvious when a portion of a block is updated and the rest of
the block also need to be copied to the newly assigned free block. The operation for performing a copy-back is a sequential execution
of page-read without burst-reading cycle and copying-program with the address of destination page. A normal read operation with
"00h" command with the address of the source page moves the whole 528bytes data into the internal buffer. As soon as the Flash
returns to Ready state, copy-back programming command "8Ah" may be given with three address cycles of target page followed. The
data stored in the internal buffer is then programmed directly into the memory cells of the destination page. Once the Copy-Back Pro-
gram is finished, any additional partial page programming into the copied pages is prohibited before erase. Since the memory array is
internally partitioned into two different planes, copy-back program is allowed only within the same memory plane. Thus, A14, the
plane address, of source and destination page address must be the same."When there is a program-failure at Copy-Back opera-
tion, error is reported by pass/fail status. But if the soure page has a bit error for charge loss, accumulated copy-back
operations could also accumulate bit errors. For this reason, two bit ECC is recommended for copy-back operation."
Figure 11. Copy-Back Program Operation
tR
tPROG
R/B
I/Ox
Add.(3Cycles)
Pass
Add.(3Cycles)
00h
I/O0
Fail
8Ah
70h
Source Address
Destination Address
30
K9F5608R0D
K9F5608U0D
FLASH MEMORY
K9F5608D0D
BLOCK ERASE
The Erase operation is done on a block basis. Block address loading is accomplished in two cycles initiated by an Erase Setup com-
mand(60h). Only address A14 to A24 is valid while A9 to A13 is ignored. The Erase Confirm command(D0h) following the block address
loading initiates the internal erasing process. This two-step sequence of setup followed by execution command ensures that memory
contents are not accidentally erased due to external noise conditions.
At the rising edge of WE after the erase confirm command input, the internal write controller handles erase and erase-verify. When the
erase operation is completed, the Write Status Bit(I/O 0) may be checked. Figure 12 details the sequence.
Figure 12. Block Erase Operation
tBERS
R/B
Pass
I/Ox
60h
I/O0
Fail
70h
Address Input(2Cycle)
Block Add. : A9 ~ A24
D0h
READ STATUS
The device contains a Status Register which may be read to find out whether program or erase operation is completed, and whether
the program or erase operation is completed successfully. After writing 70h command to the command register, a read cycle outputs
the content of the Status Register to the I/O pins on the falling edge of CE or RE, whichever occurs last. This two line control allows
the system to poll the progress of each device in multiple memory connections even when R/B pins are common-wired. RE or CE
does not need to be toggled for updated status. Refer to table 4 for specific Status Register definitions. The command register
remains in Status Read mode until further commands are issued to it. Therefore, if the status register is read during a random read
cycle, a read command(00h or 50h) should be given before sequential page read cycle.
Table4. Read Status Register Definition
I/O #
Status
Definition
"0" : Successful Program / Erase
I/O 0
Program / Erase
"1" : Error in Program / Erase
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
"0"
"0"
"0"
"0"
"0"
Reserved for Future
Use
Device Operation
Write Protect
"0" : Busy
"1" : Ready
"1" : Not Protected
"0" : Protected
31
K9F5608R0D
K9F5608U0D
FLASH MEMORY
K9F5608D0D
READ ID
The device contains a product identification mode, initiated by writing 90h to the command register, followed by an address input of
00h. Two read cycles sequentially output the manufacture code(ECh), and the device code respectively. The command register
remains in Read ID mode until further commands are issued to it. Figure 13 shows the operation sequence.
Figure 13. Read ID Operation
CLE
tCEA
CE
WE
tAR
ALE
RE
tWHR1
tREA
Device
Code*
I/Ox
ECh
00h
90h
Address. 1cycle
Maker code
Device code
Device
Device Code*
K9F5608R0D
35h
75h
75h
K9F5608D0D
K9F5608U0D
RESET
The device offers a reset feature, executed by writing FFh to the command register. When the device is in Busy state during random
read, program or erase mode, the reset operation will abort these operations. The contents of memory cells being altered are no
longer valid, as the data will be partially programmed or erased. The command register is cleared to wait for the next command, and
the Status Register is cleared to value C0h when WP is high. Refer to table 5 for device status after reset operation. If the device is
already in reset state a new reset command will not be accepted by the command register. The R/B pin transitions to low for tRST
after the Reset command is written. Refer to Figure 14 below.
Figure 14. RESET Operation
tRST
R/B
I/Ox
FFh
Table5. Device Status
After Power-up
After Reset
Operation Mode
Read 1
Waiting for next command
32
K9F5608R0D
K9F5608U0D
FLASH MEMORY
K9F5608D0D
READY/BUSY
The device has a R/B output that provides a hardware method of indicating the completion of a page program, erase and random
read completion. The R/B pin is normally high but transitions to low after program or erase command is written to the command reg-
ister or random read is started after address loading. It returns to high when the internal controller has finished the operation. The pin
is an open-drain driver thereby allowing two or more R/B outputs to be Or-tied. Because pull-up resistor value is related to tr(R/B)
and current drain during busy(ibusy) , an appropriate value can be obtained with the following reference chart(Fig 15). Its value can
be determined by the following guidance.
Rp
ibusy
VCC
1.8V device - VOL : 0.1V, VOH : VccQ-0.1V
2.65V device - VOL : 0.4V, VOH : VccQ-0.4V
3.3V device - VOL : 0.4V, VOH : 2.4V
Ready Vcc
R/B
VOH
open drain output
CL
VOL
Busy
tf
tr
GND
Device
Figure 15. Rp vs tr ,tf & Rp vs ibusy
33
K9F5608R0D
K9F5608U0D
FLASH MEMORY
K9F5608D0D
@ Vcc = 1.8V, Ta = 25°C , CL = 30pF
Ibusy
300n
3m
1.7
200n
100n
2m
1m
120
0.85
60
90
tr
30
0.57
1.7
0.43
1.7
1.7
2K
tf
1.7
4K
1K
3K
Rp(ohm)
@ Vcc = 2.65V, Ta = 25°C , CL = 30pF
300n
3m
2.3
Ibusy
200n
100n
1.1
2m
1m
120
90
tr
60
30
0.75
2.3
2.3
2.3
0.55
tf
2.3
4K
1K
2K
3K
Rp(ohm)
@ Vcc = 3.3V, Ta = 25°C , CL = 100pF
400
2.4
Ibusy
300n
3m
300
0.8
1.2
200n
100n
200
2m
1m
tr
tf
100
0.6
3.6
3.6
2K
3.6
3.6
4K
1K
3K
Rp(ohm)
Rp value guidance
VCC(Max.) - VOL(Max.)
IOL + ΣIL
1.85V
Rp(min, 1.8V part) =
=
=
=
3mA + ΣIL
2.5V
VCC(Max.) - VOL(Max.)
IOL + ΣIL
Rp(min, 2.65V part) =
Rp(min, 3.3V part) =
3mA + ΣIL
3.2V
VCC(Max.) - VOL(Max.)
IOL + ΣIL
8mA + ΣIL
where IL is the sum of the input currents of all devices tied to the R/B pin.
Rp(max) is determined by maximum permissible limit of tr
34
K9F5608R0D
K9F5608U0D
FLASH MEMORY
K9F5608D0D
Data Protection & Power up sequence
The device is designed to offer protection from any involuntary program/erase during power-transitions. An internal voltage detector
disables all functions whenever Vcc is below about 1.1V(1.8V device), 1.8V(2.65V device), 2V(3.3V device). WP pin provides hard-
ware protection and is recommended to be kept at VIL during power-up and power-down and recovery time of minimum 10µs is
required before internal circuit gets ready for any command sequences as shown in Figure 16. The two step command sequence for
program/erase provides additional software protection.
Figure 16. AC Waveforms for Power Transition
1.8V device : ~ 1.5V
2.65V device : ~ 2.0V
3.3V device : ~ 2.5V
1.8V device : ~ 1.5V
2.65V device : ~ 2.0V
3.3V device : ~ 2.5V
VCC
High
WP
WE
10µs
35
相关型号：
K9F5616D0C-DCB00
Flash, 16MX16, 30ns, PBGA63, 9 X 11 MM, 1 MM HEIGHT, 0.80 MM PITCH, TBGA-63
SAMSUNG
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