K9F5616U0B-HCB0 [SAMSUNG]
32M x 8 Bit , 16M x 16 Bit NAND Flash Memory; 32M ×8位， 16M x 16位NAND闪存
| 型号： | K9F5616U0B-HCB0 |
| 厂家： | 
SAMSUNG |
| 描述： | 32M x 8 Bit , 16M x 16 Bit NAND Flash Memory |
| 文件： | 总34页 (文件大小：602K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
K9F5608U0B-VCB0,VIB0,FCB0,FIB0
K9F5608Q0B-DCB0,DIB0,HCB0,HIB0
K9F5608U0B-YCB0,YIB0,PCB0,PIB0
K9F5608U0B-DCB0,DIB0,HCB0,HIB0
K9F5616Q0B-DCB0,DIB0,HCB0,HIB0
K9F5616U0B-YCB0,YIB0,PCB0,PIB0
K9F5616U0B-DCB0,DIB0,HCB0,HIB0
FLASH MEMORY
Document Title
32M x 8 Bit , 16M x 16 Bit NAND Flash Memory
Revision History
Revision No. History
Draft Date
Remark
0.0
Initial issue.
May. 15th 2001
Advance
0.1
At Read2 operation in X16 device
Sep. 20th 2001
: A3 ~ A7 are Don’t care ==> A3 ~ A7 are "L"
0.2
1. IOL(R/B) of 1.8V device is changed.
Nov. 5th 2001
-min. Value: 7mA -->3mA
-typ. Value: 8mA -->4mA
2. AC parameter is changed.
tRP(min.) : 30ns --> 25ns
3. WP pin provides hardware protection and is recommended to be kept
at VIL during power-up and power-down and recovery time of minimum
1ms is required before internal circuit gets ready for any command
sequences as shown in Figure 15.
---> WP pin provides hardware protection and is recommended to be
kept at VIL during power-up and power-down and recovery time of
minimum 10ms is required before internal circuit gets ready for any
command sequences as shown in Figure 15.
0.3
0.4
1. X16 TSOP1 pin is changed.
: #36 pin is changed from VccQ to N.C .
Feb. 15th 2002
Apr. 15th 2002
1. In X16 device, bad block information location is changed from 256th
byte to 256th and 261th byte.
2. tAR1, tAR2 are merged to tAR.(page 12)
(before revision) min. tAR1 = 20ns , min. tAR2 = 50ns
(after revision) min. tAR = 10ns
3. min. tCLR is changed from 50ns to 10ns.(page12)
4. min. tREA is changed from 35ns to 30ns.(page12)
5. min. tWC is changed from 50ns to 45ns.(page12)
6. Unique ID for Copyright Protection is available
-The device includes one block sized OTP(One Time Programmable),
which can be used to increase system security or to provide
identification capabilities. Detailed information can be obtained by
contact with Samsung.
7. tRHZ is divide into tRHZ and tOH.(page 12)
- tRHZ : RE High to Output Hi-Z
- tOH : RE High to Output Hold
8. tCHZ is divide into tCHZ and tOH.(page 12)
- tCHZ : CE High to Output Hi-Z
- tOH : CE High to Output Hold
Note : For more detailed features and specifications including FAQ, please refer to Samsung’s Flash web site.
http://www.intl.samsungsemi.com/Memory/Flash/datasheets.html
The attached datasheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right
to change the specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions about device. If you have
any questions, please contact the SAMSUNG branch office near you.
1
K9F5608U0B-VCB0,VIB0,FCB0,FIB0
K9F5608Q0B-DCB0,DIB0,HCB0,HIB0
K9F5608U0B-YCB0,YIB0,PCB0,PIB0
K9F5608U0B-DCB0,DIB0,HCB0,HIB0
K9F5616Q0B-DCB0,DIB0,HCB0,HIB0
K9F5616U0B-YCB0,YIB0,PCB0,PIB0
K9F5616U0B-DCB0,DIB0,HCB0,HIB0
FLASH MEMORY
Document Title
32M x 8 Bit , 16M x 16 Bit NAND Flash Memory
Revision History
Revision No. History
Draft Date
Remark
0.5
1. Add the Rp vs tr ,tf & Rp vs ibusy graph for 1.8V device (Page 33)
Nov. 22.2002
2. Add the data protection Vcc guidence for 1.8V device - below about
1.1V. (Page 34)
0.6
0.7
The min. Vcc value 1.8V devices is changed.
K9F56XXQ0B : Vcc 1.65V~1.95V --> 1.70V~1.95V
Mar. 6.2003
Pb-free Package is added.
K9F5608U0B-FCB0,FIB0
K9F5608Q0B-HCB0,HIB0
K9F5616U0B-HCB0,HIB0
K9F5616U0B-PCB0,PIB0
K9F5616Q0B-HCB0,HIB0
K9F5608U0B-HCB0,HIB0
K9F5608U0B-PCB0,PIB0
Mar. 13rd 2003
0.8
0.9
New definition of the number of invalid blocks is added.
Apr. 4th 2003
(Minimum 1004 valid blocks are guaranteed for each contiguous 128Mb
memory space.)
Pin assignment of TBGA A3 ball is changed.
(before) N.C --> (after) Vss
May. 24th 2003
Note : For more detailed features and specifications including FAQ, please refer to Samsung’s Flash web site.
http://www.intl.samsungsemi.com/Memory/Flash/datasheets.html
The attached datasheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right
to change the specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions about device. If you have
any questions, please contact the SAMSUNG branch office near you.
2
K9F5608U0B-VCB0,VIB0,FCB0,FIB0
K9F5608Q0B-DCB0,DIB0,HCB0,HIB0
K9F5608U0B-YCB0,YIB0,PCB0,PIB0
K9F5608U0B-DCB0,DIB0,HCB0,HIB0
K9F5616Q0B-DCB0,DIB0,HCB0,HIB0
K9F5616U0B-YCB0,YIB0,PCB0,PIB0
K9F5616U0B-DCB0,DIB0,HCB0,HIB0
FLASH MEMORY
32M x 8 Bit / 16M x 16 Bit NAND Flash Memory
PRODUCT LIST
Part Number
Vcc Range
Organization
PKG Type
K9F5608Q0B-D,H
K9F5616Q0B-D,H
K9F5608U0B-Y,P
K9F5608U0B-D,H
K9F5608U0B-V,F
K9F5616U0B-Y,P
K9F5616U0B-D,H
X8
1.70 ~ 1.95V
TBGA
X16
TSOP1
TBGA
X8
2.7 ~ 3.6V
WSOP1
TSOP1
TBGA
X16
FEATURES
· Voltage Supply
· Fast Write Cycle Time
- 1.8V device(K9F56XXQ0B) : 1.70~1.95V
- 3.3V device(K9F56XXU0B) : 2.7 ~ 3.6 V
· Organization
- Program time : 200ms(Typ.)
- Block Erase Time : 2ms(Typ.)
· Command/Address/Data Multiplexed I/O Port
· Hardware Data Protection
- Memory Cell Array
- X8 device(K9F5608X0B) : (32M + 1024K)bit x 8 bit
- X16 device(K9F5616X0B) : (16M + 512K)bit x 16bit
- Data Register
- Program/Erase Lockout During Power Transitions
· Reliable CMOS Floating-Gate Technology
- Endurance
: 100K Program/Erase Cycles
- X8 device(K9F5608X0B) : (512 + 16)bit x 8bit
- X16 device(K9F5616X0B) : (256 + 8)bit x16bit
· Automatic Program and Erase
- Data Retention : 10 Years
· Command Register Operation
· Intelligent Copy-Back
- Page Program
· Unique ID for Copyright Protection
· Package
- K9F56XXU0B-YCB0/YIB0
48 - Pin TSOP I (12 x 20 / 0.5 mm pitch)
- K9F56XXX0B-DCB0/DIB0
63- Ball TBGA ( 9 x 11 /0.8mm pitch , Width 1.0 mm)
- K9F5608U0B-VCB0/VIB0
- X8 device(K9F5608X0B) : (512 + 16)Byte
- X16 device(K9F5616X0B) : (256 + 8)Word
- Block Erase :
- X8 device(K9F5608X0B) : (16K + 512)Byte
- X16 device(K9F5616X0B) : ( 8K + 256)Word
· Page Read Operation
- Page Size
- X8 device(K9F5608X0B) : (512 + 16)Byte
- X16 device(K9F5616X0B) : (256 + 8)Word
48 - Pin WSOP I (12X17X0.7mm)
- K9F56XXU0B-PCB0/PIB0
48 - Pin TSOP I (12 x 20 / 0.5 mm pitch) - Pb-free Package
- K9F56XXX0B-HCB0/HIB0
- Random Access
: 10ms(Max.)
- Serial Page Access : 50ns(Min.)
63- Ball TBGA ( 9 x 11 /0.8mm pitch , Width 1.0 mm)
- Pb-free Package
- K9F5608U0B-FCB0/FIB0
48 - Pin WSOP I (12X17X0.7mm) - Pb-free Package
* K9F5608U0B-V,F(WSOPI ) is the same device as
K9F5608U0B-Y,P(TSOP1) except package type.
GENERAL DESCRIPTION
Offered in 32Mx8bit or 16Mx16bit, the K9F56XXX0B is 256M bit with spare 8M bit capacity. The device is offered in 1.8V or 3.3V
Vcc. Its NAND cell provides the most cost-effective solutIon for the solid state mass storage market. A program operation can be
performed in typical 200ms on the 528-byte(X8 device) or 264-word(X16 device) page and an erase operation can be performed in
typical 2ms on a 16K-byte(X8 device) or 8K-word(X16 device) block. Data in the page can be read out at 50ns cycle time per word.
The I/O pins serve as the ports for address and data input/output as well as command input. The on-chip write control automates all
program and erase functions including pulse repetition, where required, and internal verification and margining of data. Even the
write-intensive systems can take advantage of the K9F56XXX0B¢s extended reliability of 100K program/erase cycles by providing
ECC(Error Correcting Code) with real time mapping-out algorithm.
The K9F56XXX0B is an optimum solution for large nonvolatile storage applications such as solid state file storage and other portable
applications requiring non-volatility.
3
K9F5608U0B-VCB0,VIB0,FCB0,FIB0
K9F5608Q0B-DCB0,DIB0,HCB0,HIB0
K9F5608U0B-YCB0,YIB0,PCB0,PIB0
K9F5608U0B-DCB0,DIB0,HCB0,HIB0
K9F5616Q0B-DCB0,DIB0,HCB0,HIB0
K9F5616U0B-YCB0,YIB0,PCB0,PIB0
K9F5616U0B-DCB0,DIB0,HCB0,HIB0
FLASH MEMORY
PIN CONFIGURATION (TSOP1)
K9F56XXU0B-YCB0,PCB0/YIB0,PIB0
X16 X8
X8
X16
N.C
N.C
N.C
N.C
I/O7
I/O6
I/O5
I/O4
N.C
N.C
N.C
Vcc
Vss
N.C
N.C
N.C
I/O3
I/O2
I/O1
I/O0
N.C
N.C
N.C
N.C
Vss
N.C
N.C
N.C
N.C
N.C
GND
R/B
RE
N.C
N.C
N.C
N.C
N.C
GND
R/B
RE
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
1
2
I/O15
I/O7
I/O14
I/O6
I/O13
I/O5
I/O12
I/O4
N.C
3
4
5
6
7
8
CE
CE
9
N.C
N.C
Vcc
Vss
N.C
N.C
CLE
ALE
WE
WP
N.C
N.C
N.C
N.C
N.C
N.C
N.C
Vcc
Vss
N.C
N.C
CLE
ALE
WE
WP
N.C
N.C
N.C
N.C
N.C
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
N.C
Vcc
N.C
N.C
N.C
I/O11
I/O3
I/O10
I/O2
I/O9
I/O1
I/O8
I/O0
Vss
PACKAGE DIMENSIONS
48-PIN LEAD/LEAD FREE PLASTIC THIN SMALL OUT-LINE PACKAGE TYPE(I)
48 - TSOP1 - 1220F
Unit :mm/Inch
20.00±0.20
0.787±0.008
#1
#48
#24
#25
1.00±0.05
0.039±0.002
0.05
0.002
MIN
1.20
0.047
MAX
18.40±0.10
0.724±0.004
0~8¡Æ
0.45~0.75
0.018~0.030
0.50
0.020
(
)
4
K9F5608U0B-VCB0,VIB0,FCB0,FIB0
K9F5608Q0B-DCB0,DIB0,HCB0,HIB0
K9F5608U0B-YCB0,YIB0,PCB0,PIB0
K9F5608U0B-DCB0,DIB0,HCB0,HIB0
K9F5616Q0B-DCB0,DIB0,HCB0,HIB0
K9F5616U0B-YCB0,YIB0,PCB0,PIB0
K9F5616U0B-DCB0,DIB0,HCB0,HIB0
FLASH MEMORY
PIN CONFIGURATION (TBGA)
K9F56XXX0B-DCB0,HCB0/DIB0,HIB0
X8
X16
DNU DNU
DNU
DNU DNU
DNU DNU
DNU DNU
DNU
DNU DNU
DNU DNU
/WP ALE Vss /CE /WE R/B
/WP ALE Vss /CE /WE R/B
NC /RE CLE NC
NC NC
NC NC
NC NC
NC /RE CLE NC
NC NC
NC NC
NC NC
NC NC
NC
NC
NC
NC
NC
NC
NC NC
NC NC
NC
NC
NC
NC
NC
NC
NC NC
NC NC
NC NC
NC I/O5 I/O7 NC
Vcc
I/O8 I/O1 I/O10 I/O12 IO14
NC I/O0 NC
NC
NC
Vcc
I/O0 I/O9 I/O3 VccQ I/O6 I/O15
Vss I/O2 I/O11 I/O4 I/O13 Vss
NC I/O1 NC VccQ I/O5 I/O7
Vss I/O2 I/O3 I/O4 I/O6 Vss
DNU DNU
DNU DNU
DNU DNU
DNU DNU
DNU DNU
DNU DNU
DNU DNU
DNU DNU
(Top View)
(Top View)
PACKAGE DIMENSIONS
63-Ball TBGA (measured in millimeters)
Top View
Bottom View
9.00±0.10
A
0.80 x9= 7.20
0.80 x5= 4.00
0.80
4
9.00±0.10
B
6
5
3
2
1
(Datum A)
#A1
A
B
C
D
E
F
(Datum B)
G
H
63-Æ0.45±0.05
2.00
Æ
0.20
M A B
Side View
9.00±0.10
0.08MAX
0.45±0.05
5
K9F5608U0B-VCB0,VIB0,FCB0,FIB0
K9F5608Q0B-DCB0,DIB0,HCB0,HIB0
K9F5608U0B-YCB0,YIB0,PCB0,PIB0
K9F5608U0B-DCB0,DIB0,HCB0,HIB0
K9F5616Q0B-DCB0,DIB0,HCB0,HIB0
K9F5616U0B-YCB0,YIB0,PCB0,PIB0
K9F5616U0B-DCB0,DIB0,HCB0,HIB0
FLASH MEMORY
PIN CONFIGURATION (WSOP1)
K9F5608U0B-VCB0,FCB0/VIB0,FIB0
N.C
N.C
DNU
N.C
I/O7
I/O6
I/O5
I/O4
N.C
DNU
N.C
Vcc
N.C
N.C
DNU
N.C
N.C
N.C
R/B
RE
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
1
2
3
4
5
6
7
8
CE
9
DNU
N.C
Vcc
Vss
N.C
DNU
CLE
ALE
WE
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
Vss
N.C
DNU
N.C
I/O3
I/O2
I/O1
I/O0
N.C
DNU
N.C
N.C
WP
N.C
N.C
DNU
N.C
N.C
PACKAGE DIMENSIONS
48-PIN LEAD/LEAD FREE PLASTIC VERY VERY THIN SMALL OUT-LINE PACKAGE TYPE (I)
Unit :mm
48 - WSOP1 - 1217F
0.70 MAX
0.58±0.04
15.40±0.10
#1
#48
#24
#25
(0.1Min)
0.45~0.75
17.00±0.20
6
K9F5608U0B-VCB0,VIB0,FCB0,FIB0
K9F5608Q0B-DCB0,DIB0,HCB0,HIB0
K9F5608U0B-YCB0,YIB0,PCB0,PIB0
K9F5608U0B-DCB0,DIB0,HCB0,HIB0
K9F5616Q0B-DCB0,DIB0,HCB0,HIB0
K9F5616U0B-YCB0,YIB0,PCB0,PIB0
K9F5616U0B-DCB0,DIB0,HCB0,HIB0
FLASH MEMORY
PIN DESCRIPTION
Pin Name
Pin Function
DATA INPUTS/OUTPUTS
I/O0 ~ I/O7
(K9F5608X0B)
I/O0 ~ I/O15
The I/O pins are used to input command, address and data, and to output data during read operations. The
I/O pins float to high-z when the chip is deselected or when the outputs are disabled.
I/O8 ~ I/O15 are used only in X16 organization device. Since command input and address input are x8 oper-
ation, I/O8 ~ I/O15 are not used to input command & address. I/O8 ~ I/O15 are used only for data input and
output.
(K9F5616X0B)
COMMAND LATCH ENABLE
CLE
ALE
The CLE input controls the activating path for commands sent to the command register. When active high,
commands are latched into the command register through the I/O ports on the rising edge of the WE signal.
ADDRESS LATCH ENABLE
The ALE input controls the activating path for address to the internal address registers. Addresses are
latched on the rising edge of WE with ALE high.
CHIP ENABLE
The CE input is the device selection control. When the device is in the Busy state, CE high is ignored, and
the device does not return to standby mode in program or erase opertion. Regarding CE control during read
operation, refer to ’Page read’ section of Device operation.
CE
READ ENABLE
RE
WE
WP
The RE input is the serial data-out control, and when active drives the data onto the I/O bus. Data is valid
tREA after the falling edge of RE which also increments the internal column address counter by one.
WRITE ENABLE
The WE input controls writes to the I/O port. Commands, address and data are latched on the rising edge of
the WE pulse.
WRITE PROTECT
The WP pin provides inadvertent write/erase protection during power transitions. The internal high voltage
generator is reset when the WP pin is active low.
READY/BUSY OUTPUT
The R/B output indicates the status of the device operation. When low, it indicates that a program, erase or
random read operation is in process and returns to high state upon completion. It is an open drain output and
does not float to high-z condition when the chip is deselected or when outputs are disabled.
R/B
OUTPUT BUFFER POWER
VccQ
VCCQ is the power supply for Output Buffer.
VccQ is internally connected to Vcc, thus should be biased to Vcc.
POWER
Vcc
Vss
N.C
VCC is the power supply for device.
GROUND
NO CONNECTION
Lead is not internally connected.
GND INPUT FOR ENABLING SPARE AREA
GND
DNU
To do sequential read mode including spare area , connect this input pin to Vss or set to static low state
or to do sequential read mode excluding spare area , connect this input pin to Vcc or set to static high state.
DO NOT USE
Leave it disconnected.
NOTE : Connect all VCC and VSS pins of each device to common power supply outputs.
Do not leave VCC or VSS disconnected.
7
K9F5608U0B-VCB0,VIB0,FCB0,FIB0
K9F5608Q0B-DCB0,DIB0,HCB0,HIB0
K9F5608U0B-YCB0,YIB0,PCB0,PIB0
K9F5608U0B-DCB0,DIB0,HCB0,HIB0
K9F5616Q0B-DCB0,DIB0,HCB0,HIB0
K9F5616U0B-YCB0,YIB0,PCB0,PIB0
K9F5616U0B-DCB0,DIB0,HCB0,HIB0
FLASH MEMORY
Figure 1-1. K9F5608X0B (X8) FUNCTIONAL BLOCK DIAGRAM
VCC
VSS
X-Buffers
A9 - A24
Latches
256M + 8M Bit
NAND Flash
ARRAY
& Decoders
Y-Buffers
Latches
A0 - A7
& Decoders
(512 + 16)Byte x 65536
Page Register & S/A
Y-Gating
A8
Command
Command
Register
VCC/VCCQ
VSS
I/O Buffers & Latches
Global Buffers
CE
RE
WE
Control Logic
& High Voltage
Generator
I/0 0
Output
Driver
I/0 7
CLE ALE
WP
Figure 2-1. K9F5608X0B (X8) ARRAY ORGANIZATION
1 Block =32 Pages
= (16K + 512) Byte
1 Page = 528 Byte
1 Block = 528 Byte x 32 Pages
= (16K + 512) Byte
1 Device = 528Bytes x 32Pages x 2048 Blocks
= 264 Mbits
64K Pages
(=2,048 Blocks)
1st half Page Register
(=256 Bytes)
2nd half Page Register
(=256 Bytes)
8 bit
512Byte
16 Byte
16 Byte
I/O 0 ~ I/O 7
Page Register
512 Byte
I/O 0
A0
I/O 1
A1
I/O 2
I/O 3
A3
I/O 4
A4
I/O 5
A5
I/O 6
A6
I/O 7
A7
1st Cycle
A2
A11
A19
Column Address
Row Address
(Page Address)
2nd Cycle
3rd Cycle
A9
A10
A18
A12
A20
A13
A21
A14
A22
A15
A23
A16
A24
A17
NOTE : Column Address : Starting Address of the Register.
00h Command(Read) : Defines the starting address of the 1st half of the register.
01h Command(Read) : Defines the starting address of the 2nd half of the register.
* A8 is set to "Low" or "High" by the 00h or 01h Command.
* The device ignores any additional input of address cycles than reguired.
8
K9F5608U0B-VCB0,VIB0,FCB0,FIB0
K9F5608Q0B-DCB0,DIB0,HCB0,HIB0
K9F5608U0B-YCB0,YIB0,PCB0,PIB0
K9F5608U0B-DCB0,DIB0,HCB0,HIB0
K9F5616Q0B-DCB0,DIB0,HCB0,HIB0
K9F5616U0B-YCB0,YIB0,PCB0,PIB0
K9F5616U0B-DCB0,DIB0,HCB0,HIB0
FLASH MEMORY
Figure 1-2. K9F5616X0B (X16) FUNCTIONAL BLOCK DIAGRAM
VCC
VSS
X-Buffers
A9 - A24
Latches
256M + 8M Bit
NAND Flash
ARRAY
& Decoders
Y-Buffers
Latches
A0 - A7
& Decoders
(256 + 8)Word x 65536
Page Register & S/A
Y-Gating
Command
Command
Register
VCC/VCCQ
VSS
I/O Buffers & Latches
Global Buffers
CE
RE
WE
Control Logic
& High Voltage
Generator
I/0 0
Output
Driver
I/0 15
CLE ALE
WP
Figure 2-2. K9F5616X0B (X16) ARRAY ORGANIZATION
1 Block =32 Pages
= (8K + 256) Word
1 Page = 264 Word
1 Block = 264 Word x 32 Pages
= (8K + 256) Word
1 Device = 264Words x 32Pages x 2048 Blocks
= 264 Mbits
64K Pages
(=2,048 Blocks)
Page Register
(=256 Words)
16 bit
256Word
8 Word
8 Word
I/O 0 ~ I/O 15
Page Register
256 Word
I/O 0
A0
I/O 1
A1
I/O 2
A2
I/O 3
I/O 4
A4
I/O 5
A5
I/O 6
A6
I/O 7
A7
I/O8 to 15
1st Cycle
2nd Cycle
3rd Cycle
A3
L*
L*
L*
Column Address
Row Address
(Page Address)
A9
A10
A18
A11
A19
A12
A20
A13
A21
A14
A22
A15
A23
A16
A24
A17
NOTE : Column Address : Starting Address of the Register.
* L must be set to "Low".
9
K9F5608U0B-VCB0,VIB0,FCB0,FIB0
K9F5608Q0B-DCB0,DIB0,HCB0,HIB0
K9F5608U0B-YCB0,YIB0,PCB0,PIB0
K9F5608U0B-DCB0,DIB0,HCB0,HIB0
K9F5616Q0B-DCB0,DIB0,HCB0,HIB0
K9F5616U0B-YCB0,YIB0,PCB0,PIB0
K9F5616U0B-DCB0,DIB0,HCB0,HIB0
FLASH MEMORY
PRODUCT INTRODUCTION
The K9F56XXX0B is a 264Mbit(276,824,064 bit) memory organized as 65,536 rows(pages) by 528(X8 device) or 264(X16 device)
columns. Spare eight columns are located from column address of 512~527(X8 device) or 256~263(X16 device). A 528-byte(X8
device) or 264-word(X16 device) data register is connected to memory cell arrays accommodating data transfer between the I/O
buffers and memory during page read and page program operations. The memory array is made up of 16 cells that are serially con-
nected to form a NAND structure. Each of the 16 cells resides in a different page. A block consists of two NAND structures. A NAND
structure consists of 16 cells. Total 16896 NAND cells reside in a block. The array organization is shown in Figure 2-1,2-2. The pro-
gram and read operations are executed on a page basis, while the erase operation is executed on a block basis. The memory array
consists of 2048 separately erasable 16K-Byte(X8 device) or 8K-Word(X16 device) blocks. It indicates that the bit by bit erase oper-
ation is prohibited on the K9F56XXX0B.
The K9F56XXX0B has addresses multiplexed into 8 I/Os(X16 device case: lower 8 I/Os). K9F5616X0B allows sixteen bit wide data
transport into and out of page registers. This scheme dramatically reduces pin counts while providing high performance and allows
systems upgrades to future densities by maintaining consistency in system board design. Command, address and data are all written
through I/O¢s by bringing WE to low while CE is low. Data is latched on the rising edge of WE. Command Latch Enable(CLE) and
Address Latch Enable(ALE) are used to multiplex command and address respectively, via the I/O pins. Some commands require one
bus cycle. For example, Reset command, Read command, Status Read command, etc require just one cycle bus. Some other com-
mands like Page Program and Copy-back Program and Block Erase, require two cycles: one cycle for setup and the other cycle for
execution. The 32M-byte(X8 device) or 16M-word(X16 device) physical space requires 24 addresses, thereby requiring three cycles
for word-level addressing: column address, low row address and high row address, in that order. Page Read and Page Program
need the same three address cycles following the required command input. In Block Erase operation, however, only the two row
address cycles are used. Device operations are selected by writing specific commands into the command register. Table 1 defines
the specific commands of the K9F56XXX0B.
The device includes one block sized OTP(One Time Programmable), which can be used to increase system security or to provide
identification capabilities. Detailed information can be obtained by contact with Samsung.
Table 1. COMMAND SETS
Function
1st. Cycle
00h/01h(1)
50h
2nd. Cycle
Acceptable Command during Busy
Read 1
Read 2
Read ID
Reset
-
-
-
90h
FFh
-
O
O
Page Program
Copy-Back Program
Block Erase
80h
10h
8Ah
D0h
-
00h
60h
Read Status
70h
NOTE : 1. The 01h command is available only on X8 device(K9F5608X0B).
Caution : Any undefined command inputs are prohibited except for above command set of Table 1.
10
K9F5608U0B-VCB0,VIB0,FCB0,FIB0
K9F5608Q0B-DCB0,DIB0,HCB0,HIB0
K9F5608U0B-YCB0,YIB0,PCB0,PIB0
K9F5608U0B-DCB0,DIB0,HCB0,HIB0
K9F5616Q0B-DCB0,DIB0,HCB0,HIB0
K9F5616U0B-YCB0,YIB0,PCB0,PIB0
K9F5616U0B-DCB0,DIB0,HCB0,HIB0
FLASH MEMORY
ABSOLUTE MAXIMUM RATINGS
Rating
Parameter
Symbol
Unit
V
K9F56XXQ0B(1.8V)
K9F56XXU0B(3.3V)
-0.6 to + 4.6
VIN/OUT
VCC
-0.6 to + 2.45
-0.2 to + 2.45
-0.2 to + 2.45
Voltage on any pin relative to VSS
-0.6 to + 4.6
VCCQ
-0.6 to + 4.6
K9F56XXX0B-XCB0
Temperature Under Bias
-10 to +125
TBIAS
°C
K9F56XXX0B-XIB0
-40 to +125
-65 to +150
5
K9F56XXX0B-XCB0
Storage Temperature
TSTG
Ios
°C
K9F56XXX0B-XIB0
Short Circuit Current
mA
NOTE:
1. Minimum DC voltage is -0.6V on input/output pins. During transitions, this level may undershoot to -2.0V for periods <30ns.
Maximum DC voltage on input/output pins is VCC,+0.3V which, during transitions, may overshoot to VCC+2.0V for periods <20ns.
2. Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to the conditions
as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
RECOMMENDED OPERATING CONDITIONS
(Voltage reference to GND, K9F56XXX0B-XCB0 :TA=0 to 70°C, K9F56XXX0B-XIB0 :TA=-40 to 85°C)
K9F56XXQ0B(1.8V)
K9F56XXU0B(3.3V)
Parameter
Symbol
Unit
Min
1.70
1.70
0
Typ.
1.8
1.8
0
Max
1.95
1.95
0
Min
2.7
2.7
0
Typ.
3.3
3.3
0
Max
3.6
3.6
0
Supply Voltage
Supply Voltage
Supply Voltage
VCC
VCCQ
VSS
V
V
V
DC AND OPERATING CHARACTERISTICS(Recommended operating conditions otherwise noted.)
K9F56XXQ0B(1.8V)
K9F56XXU0B(3.3V)
Unit
Parameter
Symbol
Test Conditions
Min
Typ
Max
Min Typ
Max
tRC=50ns, CE=VIL
IOUT=0mA
Operat-
ing
Sequential Read
ICC1
-
8
15
-
10
20
Current Program
ICC2
ICC3
ISB1
ISB2
ILI
-
-
-
-
-
-
-
8
8
-
15
15
-
-
-
-
-
-
10
10
-
20
20
mA
Erase
-
Stand-by Current(TTL)
Stand-by Current(CMOS)
Input Leakage Current
Output Leakage Current
CE=VIH, WP=0V/VCC
CE=VCC-0.2, WP=0V/VCC
VIN=0 to Vcc(max)
VOUT=0 to Vcc(max)
1
1
10
-
50
10
-
50
±10
±10
±10
±10
mA
ILO
-
-
VCCQ
I/O pins
VCCQ-0.4
-
2.0
-
VCCQ+0.3
+0.3
Input High Voltage
VIH
VCC
Except I/O pins
-
VCC-0.4
-0.3
-
-
-
2.0
-0.3
2.4
-
-
-
VCC+0.3
+0.3
V
Input Low Voltage, All inputs
Output High Voltage Level
VIL
0.4
0.8
-
K9F56XXQ0B :IOH=-100mA
K9F56XXU0B :IOH=-400mA
VOH
VCCQ-0.1
-
K9F56XXQ0B :IOL=100uA
K9F56XXU0B :IOL=2.1mA
Output Low Voltage Level
Output Low Current(R/B)
VOL
-
-
0.1
-
-
-
0.4
-
K9F56XXQ0B :VOL=0.1V
K9F56XXU0B :VOL=0.4V
IOL(R/B)
3
4
8
10
mA
11
K9F5608U0B-VCB0,VIB0,FCB0,FIB0
K9F5608Q0B-DCB0,DIB0,HCB0,HIB0
K9F5608U0B-YCB0,YIB0,PCB0,PIB0
K9F5608U0B-DCB0,DIB0,HCB0,HIB0
K9F5616Q0B-DCB0,DIB0,HCB0,HIB0
K9F5616U0B-YCB0,YIB0,PCB0,PIB0
K9F5616U0B-DCB0,DIB0,HCB0,HIB0
FLASH MEMORY
VALID BLOCK
Parameter
Symbol
Min
Typ.
Max
Unit
Valid Block Number
NVB
2013
-
2048
Blocks
NOTE :
1. The K9F56XXX0B may include invalid blocks when first shipped. Additional invalid blocks may develop while being used. The number of valid blocks
is presented with both cases of invalid blocks considered. Invalid blocks are defined as blocks that contain one or more bad bits. Do not erase or
program factory-marked bad blocks. Refer to the attached technical notes for a appropriate management of invalid blocks.
2. The 1st block, which is placed on 00h block address, is fully guaranteed to be a valid block, does not require Error Correction.
3. The number of initial bad blocks upon shipping does not exceed 20.
4. Minimum 1004 valid blocks are guaranteed for each contiguous 128Mb memory space.
AC TEST CONDITION
(K9F56XXX0B-XCB0 :TA=0 to 70°C, K9F56XXX0B-XIB0 :TA=-40 to 85°C
K9F56XXQ0B : Vcc=1.70V~1.95V , K9F56XXU0B : Vcc=2.7V~3.6V unless otherwise noted)
Parameter
K9F56XXQ0B
0V to VccQ
5ns
K9F56XXU0B
0.4V to 2.4V
5ns
Input Pulse Levels
Input Rise and Fall Times
Input and Output Timing Levels
VccQ/2
1.5V
K9F56XXQ0B:Output Load (VccQ:1.8V +/-10%)
K9F56XXU0B:Output Load (VccQ:3.0V +/-10%)
1 TTL GATE and CL=30pF
-
1 TTL GATE and CL=50pF
1 TTL GATE and CL=100pF
K9F56XXU0B:Output Load (VccQ:3.3V +/-10%)
CAPACITANCE(TA=25°C, VCC=1.8V/3.3V, f=1.0MHz)
Item
Symbol
Test Condition
Min
Max
10
Unit
pF
Input/Output Capacitance
Input Capacitance
CI/O
VIL=0V
-
-
CIN
VIN=0V
10
pF
NOTE : Capacitance is periodically sampled and not 100% tested.
MODE SELECTION
CLE
H
L
ALE
L
CE
L
WE
RE
H
GND
WP
X
Mode
X
X
X
X
L
Command Input
Read Mode
H
L
L
H
X
Address Input(3clock)
Command Input
H
L
L
H
H
Write Mode
H
L
L
H
H
Address Input(3clock)
L
L
H
H
Data Input
Data Output
L
L
L
H
H
L
X
L
L
L
H
H
L
X
During Read(Busy) on K9F5608U0B_Y,P or K9F5608U0B_V,F
During Read(Busy) on the devices except K9F5608U0B_Y,P and
K9F5608U0B_V,F
X
X
X
X
L
X
X
X
X
X
X
X
X
X
X
H
X
X
X
X
X
X
X
X
L
X
H
During Program(Busy)
During Erase(Busy)
Write Protect
H
L
X(1)
X
X
(2)
0V
Stand-by
0V/VCC
NOTE : 1. X can be VIL or VIH.
2. WP should be biased to CMOS high or CMOS low for standby.
Program/Erase Characteristics
Parameter
Symbol
Min
Typ
Max
500
2
Unit
ms
Program Time
tPROG
-
-
-
-
200
Main Array
-
-
cycles
cycles
ms
Number of Partial Program Cycles
in the Same Page
Nop
Spare Array
3
Block Erase Time
tBERS
2
3
12
K9F5608U0B-VCB0,VIB0,FCB0,FIB0
K9F5608Q0B-DCB0,DIB0,HCB0,HIB0
K9F5608U0B-YCB0,YIB0,PCB0,PIB0
K9F5608U0B-DCB0,DIB0,HCB0,HIB0
K9F5616Q0B-DCB0,DIB0,HCB0,HIB0
K9F5616U0B-YCB0,YIB0,PCB0,PIB0
K9F5616U0B-DCB0,DIB0,HCB0,HIB0
FLASH MEMORY
AC Timing Characteristics for Command / Address / Data Input
Parameter
Symbol
tCLS
tCLH
tCS
Min
Max
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
CLE Set-up Time
CLE Hold Time
CE Setup Time
CE Hold Time
0
-
-
10
0
.-
-
tCH
10
25 (1)
0
WE Pulse Width
ALE Setup Time
ALE Hold Time
Data Setup Time
Data Hold Time
Write Cycle Time
tWP
-
tALS
tALH
tDS
-
10
20
10
45
15
-
-
tDH
-
tWC
-
WE High Hold Time
tWH
-
NOTE :
1. If tCS is set less than 10ns, tWP must be minimum 35ns, otherwise, tWP may be minimum 25ns.
AC Characteristics for Operation
Parameter
Symbol
tR
Min
Max
Unit
ms
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Data Transfer from Cell to Register
-
10
10
20
25
-
10
ALE to RE Delay
tAR
-
-
CLE to RE Delay
tCLR
tRR
Ready to RE Low
-
RE Pulse Width
tRP
-
WE High to Busy
tWB
100
-
Read Cycle Time
tRC
50
-
CE Access Time
tCEA
tREA
tRHZ
tCHZ
tOH
45
30
30
20
-
RE Access Time
-
RE High to Output Hi-Z
CE High to Output Hi-Z
RE or CE High to Output hold
RE High Hold Time
Output Hi-Z to RE Low
WE High to RE Low
Device Resetting Time(Read/Program/Erase)
-
-
15
15
0
tREH
tIR
-
ns
ns
ns
ms
ns
ns
ns
-
tWHR
tRST
tRB
60
-
-
5/10/500(1)
Last RE High to Busy(at sequential read)
-
100
K9F5608U0B-
Y,P,V,F only
CE High to Ready(in case of interception by CE at read)
CE High Hold Time(at the last serial read)(2)
tCRY
tCEH
-
50 +tr(R/B)(3)
-
100
NOTE :
1. If reset command(FFh) is written at Ready state, the device goes into Busy for maximum 5us.
2. To break the sequential read cycle, CE must be held high for longer time than tCEH.
3. The time to Ready depends on the value of the pull-up resistor tied R/B pin.
13
K9F5608U0B-VCB0,VIB0,FCB0,FIB0
K9F5608Q0B-DCB0,DIB0,HCB0,HIB0
K9F5608U0B-YCB0,YIB0,PCB0,PIB0
K9F5608U0B-DCB0,DIB0,HCB0,HIB0
K9F5616Q0B-DCB0,DIB0,HCB0,HIB0
K9F5616U0B-YCB0,YIB0,PCB0,PIB0
K9F5616U0B-DCB0,DIB0,HCB0,HIB0
FLASH MEMORY
NAND Flash Technical Notes
Invalid Block(s)
Invalid blocks are defined as blocks that contain one or more invalid bits whose reliability is not guaranteed by Samsung. The infor-
mation regarding the invalid block(s) is so called as the invalid block information. Devices with invalid block(s) have the same quality
level as devices with all valid blocks and have the same AC and DC characteristics. An invalid block(s) does not affect the perfor-
mance of valid block(s) because it is isolated from the bit line and the common source line by a select transistor. The system design
must be able to mask out the invalid block(s) via address mapping. The 1st block, which is placed on 00h block address, is fully guar-
anteed to be a valid block, does not require Error Correction.
Identifying Invalid Block(s)
All device locations are erased(FFh) except locations where the invalid block(s) information is written prior to shipping. The invalid
block(s) status is defined by the 6th byte(X8 device) or 1st word(X16 device) in the spare area. Samsung makes sure that either the
1st or 2nd page of every invalid block has non-FFh(X8 device) or non-FFFFh(X16 device) data at the column address of 517(X8
device) or 256 and 261(X16 device). Since the invalid block information is also erasable in most cases, it is impossible to recover the
information once it has been erased. Therefore, the system must be able to recognize the invalid block(s) based on the original
invalid block information and create the invalid block table via the following suggested flow chart(Figure 3). Any intentional erasure of
the original invalid block information is prohibited.
Start
Set Block Address = 0
Increment Block Address
Check "FFh" at the column address
517(X8 device) or 256 and 261(X16 device)
of the 1st and 2nd page in the block
*
No
Create (or update)
Invalid Block(s) Table
Check "FFh" ?
Yes
No
Last Block ?
Yes
End
Figure 3. Flow chart to create invalid block table.
14
K9F5608U0B-VCB0,VIB0,FCB0,FIB0
K9F5608Q0B-DCB0,DIB0,HCB0,HIB0
K9F5608U0B-YCB0,YIB0,PCB0,PIB0
K9F5608U0B-DCB0,DIB0,HCB0,HIB0
K9F5616Q0B-DCB0,DIB0,HCB0,HIB0
K9F5616U0B-YCB0,YIB0,PCB0,PIB0
K9F5616U0B-DCB0,DIB0,HCB0,HIB0
FLASH MEMORY
NAND Flash Technical Notes (Continued)
Error in write or read operation
Within its life time, the additional invalid blocks may develop with NAND Flash memory. Refer to the qualification report for the actual
data.The following possible failure modes should be considered to implement a highly reliable system. In the case of status read fail-
ure after erase or program, block replacement should be done. Because program status fail during a page program does not affect
the data of the other pages in the same block, block replacement can be executed with a page-sized buffer by finding an erased
empty block and reprogramming the current target data and copying the rest of the replaced block. To improve the efficiency of
memory space, it is recommended that the read or verification failure due to single bit error be reclaimed by ECC without any block
replacement. The said additional block failure rate does not include those reclaimed blocks.
Failure Mode
Detection and Countermeasure sequence
Erase Failure
Status Read after Erase --> Block Replacement
Status Read after Program --> Block Replacement
Read back ( Verify after Program) --> Block Replacement
or ECC Correction
Write
Read
Program Failure
Single Bit Failure
Verify ECC -> ECC Correction
: Error Correcting Code --> Hamming Code etc.
Example) 1bit correction & 2bit detection
ECC
Program Flow Chart
If ECC is used, this verification
operation is not needed.
Start
Write 80h
Write 00h
Write Address
Wait for tR Time
Write Address
Write Data
Write 10h
*
No
Program Error
Verify Data
Read Status Register
Yes
Program Completed
I/O 6 = 1 ?
No
or R/B = 1 ?
: If program operation results in an error, map out
the block including the page in error and copy the
target data to another block.
*
Yes
*
No
Program Error
I/O 0 = 0 ?
Yes
15
K9F5608U0B-VCB0,VIB0,FCB0,FIB0
K9F5608Q0B-DCB0,DIB0,HCB0,HIB0
K9F5608U0B-YCB0,YIB0,PCB0,PIB0
K9F5608U0B-DCB0,DIB0,HCB0,HIB0
K9F5616Q0B-DCB0,DIB0,HCB0,HIB0
K9F5616U0B-YCB0,YIB0,PCB0,PIB0
K9F5616U0B-DCB0,DIB0,HCB0,HIB0
FLASH MEMORY
NAND Flash Technical Notes (Continued)
Erase Flow Chart
Read Flow Chart
Start
Start
Write 60h
Write 00h
Write Block Address
Write Address
Read Data
Write D0h
Read Status Register
ECC Generation
No
No
I/O 6 = 1 ?
or R/B = 1 ?
Reclaim the Error
Verify ECC
Yes
Yes
*
No
Page Read Completed
Erase Error
I/O 0 = 0 ?
Yes
Erase Completed
: If erase operation results in an error, map out
the failing block and replace it with another block.
*
Block Replacement
Block A
1st
2
{
(n-1)th
nth
an error occurs.
(page)
Buffer memory of the controller.
Block B
1st
1
{
(n-1)th
nth
(page)
* Step1
When an error happens in the nth page of the Block ’A’ during erase or program operation.
* Step2
Copy the nth page data of the Block ’A’ in the buffer memory to the nth page of another free block. (Block ’B’)
* Step3
Then, copy the data in the 1st ~ (n-1)th page to the same location of the Block ’B’.
* Step4
Do not further erase Block ’A’ by creating an ’invalid Block’ table or other appropriate scheme.
16
K9F5608U0B-VCB0,VIB0,FCB0,FIB0
K9F5608Q0B-DCB0,DIB0,HCB0,HIB0
K9F5608U0B-YCB0,YIB0,PCB0,PIB0
K9F5608U0B-DCB0,DIB0,HCB0,HIB0
K9F5616Q0B-DCB0,DIB0,HCB0,HIB0
K9F5616U0B-YCB0,YIB0,PCB0,PIB0
K9F5616U0B-DCB0,DIB0,HCB0,HIB0
FLASH MEMORY
Pointer Operation of K9F5608X0B(X8)
Samsung NAND Flash has three address pointer commands as a substitute for the two most significant column addresses. ’00h’
command sets the pointer to ’A’ area(0~255byte), ’01h’ command sets the pointer to ’B’ area(256~511byte), and ’50h’ command sets
the pointer to ’C’ area(512~527byte). With these commands, the starting column address can be set to any of a whole
page(0~527byte). ’00h’ or ’50h’ is sustained until another address pointer command is inputted. ’01h’ command, however, is effec-
tive only for one operation. After any operation of Read, Program, Erase, Reset, Power_Up is executed once with ’01h’ command,
the address pointer returns to ’A’ area by itself. To program data starting from ’A’ or ’C’ area, ’00h’ or ’50h’ command must be input-
ted before ’80h’ command is written. A complete read operation prior to ’80h’ command is not necessary. To program data starting
from ’B’ area, ’01h’ command must be inputted right before ’80h’ command is written.
"A" area
"B" area
"C" area
(00h plane)
(01h plane)
(50h plane)
256 Byte
256 Byte
16 Byte
Table 2. Destination of the pointer
Command
Pointer position
Area
00h
01h
50h
0 ~ 255 byte
256 ~ 511 byte
512 ~ 527 byte
1st half array(A)
2nd half array(B)
spare array(C)
"A"
"B"
"C"
Internal
Page Register
Pointer select
commnad
(00h, 01h, 50h)
Pointer
Figure 4. Block Diagram of Pointer Operation
(1) Command input sequence for programming ’A’ area
The address pointer is set to ’A’ area(0~255), and sustained
Address / Data input
Address / Data input
00h
80h
10h
00h
80h
10h
’A’,’B’,’C’ area can be programmed.
’00h’ command can be omitted.
It depends on how many data are inputted.
(2) Command input sequence for programming ’B’ area
The address pointer is set to ’B’ area(256~512), and will be reset to
’A’ area after every program operation is executed.
Address / Data input
Address / Data input
80h 10h
01h
80h
10h
01h
’B’, ’C’ area can be programmed.
It depends on how many data are inputted.
’01h’ command must be rewritten before
every program operation
(3) Command input sequence for programming ’C’ area
The address pointer is set to ’C’ area(512~527), and sustained
Address / Data input
Address / Data input
80h 10h
50h
80h
10h
50h
Only ’C’ area can be programmed.
’50h’ command can be omitted.
17
K9F5608U0B-VCB0,VIB0,FCB0,FIB0
K9F5608Q0B-DCB0,DIB0,HCB0,HIB0
K9F5608U0B-YCB0,YIB0,PCB0,PIB0
K9F5608U0B-DCB0,DIB0,HCB0,HIB0
K9F5616Q0B-DCB0,DIB0,HCB0,HIB0
K9F5616U0B-YCB0,YIB0,PCB0,PIB0
K9F5616U0B-DCB0,DIB0,HCB0,HIB0
FLASH MEMORY
Pointer Operation of K9F5616X0B(X16)
Samsung NAND Flash has two address pointer commands as a substitute for the most significant column address. ’00h’ command
sets the pointer to ’A’ area(0~255word), and ’50h’ command sets the pointer to ’B’ area(256~263word). With these commands, the
starting column address can be set to any of a whole page(0~263word). ’00h’ or ’50h’ is sustained until another address pointer com-
mand is inputted. To program data starting from ’A’ or ’B’ area, ’00h’ or ’50h’ command must be inputted before ’80h’ command is
written. A complete read operation prior to ’80h’ command is not necessary.
"A" area
"B" area
(00h plane)
(50h plane)
256 Word
8 Word
Table 3. Destination of the pointer
Command
Pointer position
Area
00h
50h
0 ~ 255 word
256 ~ 263 word
main array(A)
spare array(B)
"A"
"B"
Internal
Page Register
Pointer select
command
(00h, 50h)
Pointer
Figure 5. Block Diagram of Pointer Operation
(1) Command input sequence for programming ’A’ area
The address pointer is set to ’A’ area(0~255), and sustained
Address / Data input
Address / Data input
00h
80h
10h
00h
80h
10h
’A’,’B’ area can be programmed.
’00h’ command can be omitted.
It depends on how many data are inputted.
(2) Command input sequence for programming ’B’ area
The address pointer is set to ’B’ area(256~263), and sustained
Address / Data input
Address / Data input
80h 10h
50h
80h
10h
50h
Only ’B’ area can be programmed.
’50h’ command can be omitted.
18
K9F5608U0B-VCB0,VIB0,FCB0,FIB0
K9F5608Q0B-DCB0,DIB0,HCB0,HIB0
K9F5608U0B-YCB0,YIB0,PCB0,PIB0
K9F5608U0B-DCB0,DIB0,HCB0,HIB0
K9F5616Q0B-DCB0,DIB0,HCB0,HIB0
K9F5616U0B-YCB0,YIB0,PCB0,PIB0
K9F5616U0B-DCB0,DIB0,HCB0,HIB0
FLASH MEMORY
System Interface Using CE don’t-care.
For an easier system interface, CE may be inactive during the data-loading or sequential data-reading as shown below. The internal
528byte/264word page registers are utilized as seperate buffers for this operation and the system design gets more flexible. In addi-
tion, for voice or audio applications which use slow cycle time on the order of u-seconds, de-activating CE during the data-loading
and reading would provide significant savings in power consumption.
Figure 6. Program Operation with CE don’t-care.
CLE
CE don’t-care
CE
WE
ALE
I/Ox
80h
Start Add.(3Cycle)
Data Input
Data Input
10h
tCS
tCH
tCEA
CE
RE
CE
tREA
tWP
WE
I/O0~15
out
Figure 7. Read Operation with CE don’t-care.
CLE
On K9F5608U0B_Y,P or K9F5608U0B_V,F
CE must be held
low during tR
CE don’t-care
CE
RE
ALE
tR
R/B
WE
I/Ox
Data Output(sequential)
00h
Start Add.(3Cycle)
19
K9F5608U0B-VCB0,VIB0,FCB0,FIB0
K9F5608Q0B-DCB0,DIB0,HCB0,HIB0
K9F5608U0B-YCB0,YIB0,PCB0,PIB0
K9F5608U0B-DCB0,DIB0,HCB0,HIB0
K9F5616Q0B-DCB0,DIB0,HCB0,HIB0
K9F5616U0B-YCB0,YIB0,PCB0,PIB0
K9F5616U0B-DCB0,DIB0,HCB0,HIB0
FLASH MEMORY
I/O
DATA
Device
I/Ox
Data In/Out
~528byte
~264word
K9F5608X0B(X8 device)
K9F5616X0B(X16 device)
I/O 0 ~ I/O 7
I/O 0 ~ I/O 151)
NOTE: 1. I/O8~15 must be set to "0" during command or address input.
2. I/O8~15 are used only for data bus.
* Command Latch Cycle
CLE
tCLH
tCH
tCLS
tCS
CE
tWP
WE
tALS
tALH
ALE
tDH
tDS
Command
I/Ox
* Address Latch Cycle
tCLS
CLE
tCS
tWC
tWC
CE
tWP
tWP
tWP
WE
tWH
tALH tALS
tWH
tALH
tALS
tALH
tALS
ALE
I/Ox
tDH
tDH
tDH
tDS
tDS
tDS
AO~A7
A9~A16
A17~A24
20
K9F5608U0B-VCB0,VIB0,FCB0,FIB0
K9F5608Q0B-DCB0,DIB0,HCB0,HIB0
K9F5608U0B-YCB0,YIB0,PCB0,PIB0
K9F5608U0B-DCB0,DIB0,HCB0,HIB0
K9F5616Q0B-DCB0,DIB0,HCB0,HIB0
K9F5616U0B-YCB0,YIB0,PCB0,PIB0
K9F5616U0B-DCB0,DIB0,HCB0,HIB0
FLASH MEMORY
* Input Data Latch Cycle
tCLH
CLE
tCH
CE
tWC
tALS
ALE
tWP
tWP
tWP
WE
tWH
tDH
tDH
tDH
tDS
tDS
tDS
I/Ox
DIN 0
DIN 1
DIN n
* Serial access Cycle after Read(CLE=L, WE=H, ALE=L)
tRC
CE
tCHZ*
tOH
tREH
tREA
tREA
tREA
tRP
RE
tRHZ*
tRHZ*
tOH
I/Ox
Dout
Dout
Dout
tRR
R/B
NOTES : Transition is measured ±200mV from steady state voltage with load.
This parameter is sampled and not 100% tested.
21
K9F5608U0B-VCB0,VIB0,FCB0,FIB0
K9F5608Q0B-DCB0,DIB0,HCB0,HIB0
K9F5608U0B-YCB0,YIB0,PCB0,PIB0
K9F5608U0B-DCB0,DIB0,HCB0,HIB0
K9F5616Q0B-DCB0,DIB0,HCB0,HIB0
K9F5616U0B-YCB0,YIB0,PCB0,PIB0
K9F5616U0B-DCB0,DIB0,HCB0,HIB0
FLASH MEMORY
* Status Read Cycle
tCLR
CLE
tCLS
tCLH
tCS
CE
tCH
tWP
WE
tCEA
tCHZ
tOH
tWHR
RE
tRHZ
tOH
tDH
tREA
tDS
tIR
Status Output
I/Ox
70h
READ1 OPERATION(READ ONE PAGE)
CLE
1)
tCEH
On K9F5608U0B_Y,P or K9F5608U0B_V,F
CE must be held
low during tR
CE
tCHZ
tOH
tWC
WE
tWB
tCRY
tAR
ALE
RE
tRHZ
tOH
tR
tRC
N Address
tRR
Read
CMD
A17~A24
A0~A7 A9~A16
Dout N+1 Dout N+2 Dout N+3
Dout m
tRB
Dout N
I/Ox
Column
Address
Page(Row)
Address
Busy
R/B
1)
X8 device : m = 528 , Read CMD = 00h or 01h
X16 device : m = 264 , Read CMD = 00h
NOTES : 1) is only valid on K9F5608U0B_Y,P or K9F5608U0B_V,F
22
K9F5608U0B-VCB0,VIB0,FCB0,FIB0
K9F5608Q0B-DCB0,DIB0,HCB0,HIB0
K9F5608U0B-YCB0,YIB0,PCB0,PIB0
K9F5608U0B-DCB0,DIB0,HCB0,HIB0
K9F5616Q0B-DCB0,DIB0,HCB0,HIB0
K9F5616U0B-YCB0,YIB0,PCB0,PIB0
K9F5616U0B-DCB0,DIB0,HCB0,HIB0
FLASH MEMORY
READ1 OPERATION (INTERCEPTED BY CE)
CLE
On K9F5608U0B_Y,P or K9F5608U0B_V,F
CE must be held
low during tR
CE
WE
tWB
tCHZ
tOH
tAR
ALE
tR
tRC
RE
N Address
tRR
Read
CMD
Dout N
Dout N+1
Dout N+2
Dout N+3
Col. Add Row Add1 Row Add2
I/Ox
Page(Row)
Address
Column
Address
Busy
R/B
READ2 OPERATION (READ ONE PAGE)
CLE
CE
On K9F5608U0B_Y,P or K9F5608U0B_V,F
CE must be held
low during tR
WE
ALE
RE
tR
tWB
tAR
tRR
Dout
n+M+1
Dout
n+M
I/Ox
R/B
50h
Col. Add Row Add1 Row Add2
Dout n+m
Selected
Row
M Address
X8 device : A0~A3 are Valid Address & A4~A7 are Don¢t care
X16 device : A0~A2 are Valid Address & A3~A7 are "L"
m
n
X8 device : n = 512, m = 16
X16 device : n = 256, m = 8
Start
address M
23
K9F5608U0B-VCB0,VIB0,FCB0,FIB0
K9F5608Q0B-DCB0,DIB0,HCB0,HIB0
K9F5608U0B-YCB0,YIB0,PCB0,PIB0
K9F5608U0B-DCB0,DIB0,HCB0,HIB0
K9F5616Q0B-DCB0,DIB0,HCB0,HIB0
K9F5616U0B-YCB0,YIB0,PCB0,PIB0
K9F5616U0B-DCB0,DIB0,HCB0,HIB0
FLASH MEMORY
SEQUENTIAL ROW READ OPERATION (only for K9F5608U0B-Y,P and K9F5608U0B-V,F, Valid with in a block)
CLE
CE
WE
ALE
RE
Dout
N
Dout
N+1
Dout
N+2
Dout
527
Dout
0
Dout
1
Dout
2
Dout
527
Col. Add Row Add1 Row Add2
00h
I/Ox
R/B
Ready
Busy
Busy
M
M+1
Output
N
Output
PAGE PROGRAM OPERATION
CLE
CE
tWC
tWC
tWC
WE
tPROG
tWB
ALE
RE
N Address
Din
m
Din
N
Din
N+1
10h
Program
80h
Row Add1 Row Add2
70h
I/O0
Col. Add
I/Ox
R/B
Sequential Data Column
Input Command Address
1 up to m Data
Serial Input
Read Status
Command
Page(Row)
Address
Command
I/O0=0 Successful Program
I/O0=1 Error in Program
X8 device : m = 528 byte
X16 device : m = 264 word
24
K9F5608U0B-VCB0,VIB0,FCB0,FIB0
K9F5608Q0B-DCB0,DIB0,HCB0,HIB0
K9F5608U0B-YCB0,YIB0,PCB0,PIB0
K9F5608U0B-DCB0,DIB0,HCB0,HIB0
K9F5616Q0B-DCB0,DIB0,HCB0,HIB0
K9F5616U0B-YCB0,YIB0,PCB0,PIB0
K9F5616U0B-DCB0,DIB0,HCB0,HIB0
FLASH MEMORY
COPY-BACK PROGRAM OPERATION
CLE
CE
tWC
WE
tWB
tWB
tPROG
ALE
tR
RE
I/Ox
8Ah
00h
Col. Add
Row Add1 Row Add2
70h
I/O0
A0~A7 A9~A16 A17~A24
Program
Column
Address
Column
CommandAddress
Read Status
Command
Page(Row)
Address
Page(Row)
Address
R/B
I/O0=0 Successful Program
I/O0=1 Error in Program
Busy
Busy
BLOCK ERASE OPERATION (ERASE ONE BLOCK)
CLE
CE
tWC
WE
tBERS
tWB
ALE
RE
I/Ox
A9~A16
A17~A24
60h
DOh
70h
I/O 0
Page(Row)
Address
Busy
R/B
I/O0=0 Successful Erase
Read Status I/O0=1 Error in Erase
Command
Auto Block Erase
Setup Command
Erase Command
25
K9F5608U0B-VCB0,VIB0,FCB0,FIB0
K9F5608Q0B-DCB0,DIB0,HCB0,HIB0
K9F5608U0B-YCB0,YIB0,PCB0,PIB0
K9F5608U0B-DCB0,DIB0,HCB0,HIB0
K9F5616Q0B-DCB0,DIB0,HCB0,HIB0
K9F5616U0B-YCB0,YIB0,PCB0,PIB0
K9F5616U0B-DCB0,DIB0,HCB0,HIB0
FLASH MEMORY
MANUFACTURE & DEVICE ID READ OPERATION
CLE
CE
WE
ALE
tAR
RE
tREA
Device
Code*
I/Ox
90h
00h
ECh
Read ID Command
Address. 1cycle
Maker Code
Device Code
Device
Device Code*
K9F5608Q0B
35h
75h
K9F5608U0B
K9F5616Q0B
K9F5616U0B
XX45h
XX55h
26
K9F5608U0B-VCB0,VIB0,FCB0,FIB0
K9F5608Q0B-DCB0,DIB0,HCB0,HIB0
K9F5608U0B-YCB0,YIB0,PCB0,PIB0
K9F5608U0B-DCB0,DIB0,HCB0,HIB0
K9F5616Q0B-DCB0,DIB0,HCB0,HIB0
K9F5616U0B-YCB0,YIB0,PCB0,PIB0
K9F5616U0B-DCB0,DIB0,HCB0,HIB0
FLASH MEMORY
DEVICE OPERATION
PAGE READ
Upon initial device power up, the device defaults to Read1 mode. This operation is also initiated by writing 00h to the command regis-
ter along with three address cycles. Once the command is latched, it does not need to be written for the following page read opera-
tion. Two types of operations are available : random read, serial page read.
The random read mode is enabled when the page address is changed. The 528 bytes(X8 device) or 264 words(X16 device) of data
within the selected page are transferred to the data registers in less than 10ms(tR). The system controller can detect the completion of
this data transfer(tR) by analyzing the output of R/B pin. Once the data in a page is loaded into the registers, they may be read out in
50ns cycle time by sequentially pulsing RE. High to low transitions of the RE clock output the data starting from the selected column
address up to the last column address[column 511/ 527(X8 device) 255 /263(X16 device) depending on the state of GND input pin].
The way the Read1 and Read2 commands work is like a pointer set to either the main area or the spare area. The spare area of 512
~527 bytes(X8 device) or 256~263 words(X16 device) may be selectively accessed by writing the Read2 command with GND input
pin low. Addresses A0~A3(X8 device) or A0~A2(X16 device) set the starting address of the spare area while addresses A4~A7 are
ignored in X8 device case or A3~A7 must be "L" in X16 device case. The Read1 command is needed to move the pointer back to the
main area. Figures 8, 9 show typical sequence and timings for each read operation.
Sequential Row Read is available only for K9F5608U0B_Y,P and K9F5608U0B_V,F :
After the data of last column address is clocked out, the next page is automatically selected for sequential row read. Waiting 10ms
again allows reading the selected page. The sequential row read operation is terminated by bringing CE high. Unless the operation
is aborted, the page address is automatically incremented for sequential row read as in Read1 operation and spare sixteen bytes of
each page may be sequentially read. The Sequential Read 1 and 2 operation is allowed only within a block and after the last page of
a block is readout, the sequential read operation must be terminated by bringing CE high. When the page address moves onto the
next block, read command and address must be given. Figures 8-1, 9-1 show typical sequence and timings for sequential row read
operation.
Figure 8. Read1 Operation
CLE
On K9F5608U0B_Y,P or K9F5608U0B_V,F
CE must be held
CE
low during tR
WE
ALE
R/B
tR
RE
I/Ox
Start Add.(3Cycle)
00h
Data Output(Sequential)
X8 device : A0 ~ A7 & A9 ~ A24
X16 device : A0 ~ A7 & A9 ~ A24
(00h Command)
(01h Command)
1)
1st half array 2st half array
Main array
Data Field
Spare Field
Data Field
Spare Field
NOTE: 1) After data access on 2nd half array by 01h command, the start pointer is automatically moved to 1st half
array (00h) at next cycle. 01h command is only available on X8 device(K9F5608X0B).
27
K9F5608U0B-VCB0,VIB0,FCB0,FIB0
K9F5608Q0B-DCB0,DIB0,HCB0,HIB0
K9F5608U0B-YCB0,YIB0,PCB0,PIB0
K9F5608U0B-DCB0,DIB0,HCB0,HIB0
K9F5616Q0B-DCB0,DIB0,HCB0,HIB0
K9F5616U0B-YCB0,YIB0,PCB0,PIB0
K9F5616U0B-DCB0,DIB0,HCB0,HIB0
FLASH MEMORY
Figure 9. Read2 Operation
CLE
CE
On K9F5608U0B_Y,P or K9F5608U0B_V,F
CE must be held
low during tR
WE
ALE
R/B
tR
RE
Start Add.(3Cycle)
I/Ox
50h
Data Output(Sequential)
Spare Field
X8 device : A0 ~ A3 & A9 ~ A24
X16 device : A0 ~ A2 & A9 ~ A24
X8 device : A4 ~ A7 Don’t care
X16 device : A3 ~ A7 are "L"
Main array
Data Field
Spare Field
Figure 8-1. Sequential Row Read1 Operation (only for K9F5608U0B-Y,P and K9F5608U0B-V,F Valid with in a block )
tR
tR
tR
R/B
I/Ox
Data Output
1st
Data Output
Data Output
00h
01h
Start Add.(3Cycle)
A0 ~ A7 & A9 ~ A24
2nd
(528 Byte)
Nth
(528 Byte)
(GND input=L, 00h Command)
(GND input=L, 01h Command)
(GND input=H, 00h Command)
1st half array
2nd half array
1st half array
2nd half array
1st half array
2nd half array
1st
1st
1st
2nd
Nth
Block
2nd
Nth
2nd
Nth
Data Field
Spare Field
Data Field
Spare Field
Data Field
Spare Field
28
K9F5608U0B-VCB0,VIB0,FCB0,FIB0
K9F5608Q0B-DCB0,DIB0,HCB0,HIB0
K9F5608U0B-YCB0,YIB0,PCB0,PIB0
K9F5608U0B-DCB0,DIB0,HCB0,HIB0
K9F5616Q0B-DCB0,DIB0,HCB0,HIB0
K9F5616U0B-YCB0,YIB0,PCB0,PIB0
K9F5616U0B-DCB0,DIB0,HCB0,HIB0
FLASH MEMORY
Figure 9-1. Sequential Row Read2 Operation (GND Input=Fixed Low)
(only for K9F5608U0B-Y,P and K9F5608U0B-V,F Valid with in a block)
tR
tR
tR
R/B
Start Add.(3Cycle)
Data Output
1st
Data Output
I/Ox
50h
Data Output
2nd
(16Byte)
Nth
(16Byte)
A0 ~ A3 & A9 ~ A24
(A4 ~ A7 :
Don¢t Care)
1st
Block
Nth
Data Field
Spare Field
29
K9F5608U0B-VCB0,VIB0,FCB0,FIB0
K9F5608Q0B-DCB0,DIB0,HCB0,HIB0
K9F5608U0B-YCB0,YIB0,PCB0,PIB0
K9F5608U0B-DCB0,DIB0,HCB0,HIB0
K9F5616Q0B-DCB0,DIB0,HCB0,HIB0
K9F5616U0B-YCB0,YIB0,PCB0,PIB0
K9F5616U0B-DCB0,DIB0,HCB0,HIB0
FLASH MEMORY
PAGE PROGRAM
The device is programmed basically on a page basis, but it does allow multiple partial page programing of a byte/word or consecutive
bytes/words up to 528(X8 device) or 264(X16 device), in a single page program cycle. The number of consecutive partial page program-
ming operation within the same page without an intervening erase operation should not exceed 2 for main array and 3 for spare
array. The addressing may be done in any random order in a block. A page program cycle consists of a serial data loading period in
which up to 528 bytes(X8 device) or 264 words(X16 device) of data may be loaded into the page register, followed by a non-volatile pro-
gramming period where the loaded data is programmed into the appropriate cell. About the pointer operation, please refer to the
attached technical notes.
The serial data loading period begins by inputting the Serial Data Input command(80h), followed by the three address cycles input
and then serial data loading. The words other than those to be programmed do not need to be loaded.The Page Program confirm
command(10h) initiates the programming process. Writing 10h alone without previously entering the serial data will not initiate the
programming process. The internal write controller automatically executes the algorithms and timings necessary for program and
verify, thereby freeing the system controller for other tasks. Once the program process starts, the Read Status Register command
may be entered, with RE and CE low, to read the status register. The system controller can detect the completion of a program cycle
by monitoring the R/B output, or the Status bit(I/O 6) of the Status Register. Only the Read Status command and Reset command
are valid while programming is in progress. When the Page Program is complete, the Write Status Bit(I/O 0) may be checked(Figure
10). The internal write verify detects only errors for "1"s that are not successfully programmed to "0"s. The command register remains
in Read Status command mode until another valid command is written to the command register.
Figure 10. Program Operation
tPROG
R/B
I/Ox
Pass
80h
Address & Data Input
I/O0
Fail
10h
70h
COPY-BACK PROGRAM
The copy-back program is configured to quickly and efficiently rewrite data stored in one page within the array to another page within
the same array without utilizing an external memory. Since the time-consuming sequently-reading and its re-loading cycles are
removed, the system performance is improved. The benefit is especially obvious when a portion of a block is updated and the rest of
the block also need to be copied to the newly assigned free block. The operation for performing a copy-back is a sequential execu-
tion of page-read without burst-reading cycle and copying-program with the address of destination page. A normal read operation
with "00h" command with the address of the source page moves the whole 528bytes/264words(X8 device:528bytes, X16
device:264words) data into the internal buffer. As soon as the Flash returns to Ready state, copy-back programming command "8Ah"
may be given with three address cycles of target page followed. The data stored in the internal buffer is then programmed directly
into the memory cells of the destination page. Once the Copy-Back Program is finished, any additional partial page programming into
the copied pages is prohibited before erase. Since the memory array is internally partitioned into two different planes, copy-back pro-
gram is allowed only within the same memory plane. Thus, A14, the plane address, of source and destination page address must be
the same. "When there is a program-failure at Copy-Back operation, error is reported by pass/fail status. But, if Copy-Back
operations are accumulated over time, bit error due to charge loss is not checked by external error detection/correction
scheme. For this reason, two bit error correction is recommended for the use of Copy-Back operation."
Figure 11. Copy-Back Program Operation
tR
tPROG
R/B
I/Ox
Add.(3Cycles)
Pass
Add.(3Cycles)
00h
I/O0
Fail
8Ah
70h
Source Address
Destination Address
30
K9F5608U0B-VCB0,VIB0,FCB0,FIB0
K9F5608Q0B-DCB0,DIB0,HCB0,HIB0
K9F5608U0B-YCB0,YIB0,PCB0,PIB0
K9F5608U0B-DCB0,DIB0,HCB0,HIB0
K9F5616Q0B-DCB0,DIB0,HCB0,HIB0
K9F5616U0B-YCB0,YIB0,PCB0,PIB0
K9F5616U0B-DCB0,DIB0,HCB0,HIB0
FLASH MEMORY
BLOCK ERASE
The Erase operation is done on a block basis. Block address loading is accomplished in two cycles initiated by an Erase Setup com-
mand(60h). Only address A14 to A24 is valid while A9 to A13 is ignored. The Erase Confirm command(D0h) following the block
address loading initiates the internal erasing process. This two-step sequence of setup followed by execution command ensures that
memory contents are not accidentally erased due to external noise conditions.
At the rising edge of WE after the erase confirm command input, the internal write controller handles erase and erase-verify. When
the erase operation is completed, the Write Status Bit(I/O 0) may be checked. Figure 12 details the sequence.
Figure 12. Block Erase Operation
tBERS
R/B
Pass
I/Ox
60h
I/O0
Fail
70h
Address Input(2Cycle)
Block Add. : A9 ~ A24
D0h
READ STATUS
The device contains a Status Register which may be read to find out whether program or erase operation is completed, and whether
the program or erase operation is completed successfully. After writing 70h command to the command register, a read cycle outputs
the content of the Status Register to the I/O pins on the falling edge of CE or RE, whichever occurs last. This two line control allows
the system to poll the progress of each device in multiple memory connections even when R/B pins are common-wired. RE or CE
does not need to be toggled for updated status. Refer to table 4 for specific Status Register definitions. The command register
remains in Status Read mode until further commands are issued to it. Therefore, if the status register is read during a random read
cycle, a read command(00h or 50h) should be given before sequential page read cycle.
Table4. Read Status Register Definition
I/O #
Status
Definition
"0" : Successful Program / Erase
I/O 0
Program / Erase
"1" : Error in Program / Erase
I/O 1
I/O 2
"0"
"0"
"0"
"0"
"0"
Reserved for Future
Use
I/O 3
I/O 4
I/O 5
I/O 6
Device Operation
Write Protect
Not use
"0" : Busy
"1" : Ready
"1" : Not Protected
I/O 7
"0" : Protected
Don’t care
I/O 8~15
31
K9F5608U0B-VCB0,VIB0,FCB0,FIB0
K9F5608Q0B-DCB0,DIB0,HCB0,HIB0
K9F5608U0B-YCB0,YIB0,PCB0,PIB0
K9F5608U0B-DCB0,DIB0,HCB0,HIB0
K9F5616Q0B-DCB0,DIB0,HCB0,HIB0
K9F5616U0B-YCB0,YIB0,PCB0,PIB0
K9F5616U0B-DCB0,DIB0,HCB0,HIB0
FLASH MEMORY
READ ID
The device contains a product identification mode, initiated by writing 90h to the command register, followed by an address input of
00h. Two read cycles sequentially output the manufacture code(ECh), and the device code respectively. The command register
remains in Read ID mode until further commands are issued to it. Figure 13 shows the operation sequence.
Figure 13. Read ID Operation
CLE
tCEA
CE
WE
tAR
ALE
RE
tWHR
tREA
Device
Code*
I/Ox
ECh
00h
90h
Address. 1cycle
Maker code
Device code
Device
Device Code*
K9F5608Q0B
K9F5608U0B
K9F5616Q0B
K9F5616U0B
35h
75h
45h
55h
RESET
The device offers a reset feature, executed by writing FFh to the command register. When the device is in Busy state during random
read, program or erase mode, the reset operation will abort these operations. The contents of memory cells being altered are no
longer valid, as the data will be partially programmed or erased. The command register is cleared to wait for the next command, and
the Status Register is cleared to value C0h when WP is high. Refer to table 5 for device status after reset operation. If the device is
already in reset state a new reset command will not be accepted by the command register. The R/B pin transitions to low for tRST
after the Reset command is written. Refer to Figure 14 below.
Figure 14. RESET Operation
tRST
R/B
I/Ox
FFh
Table5. Device Status
After Power-up
After Reset
Operation Mode
Read 1
Waiting for next command
32
K9F5608U0B-VCB0,VIB0,FCB0,FIB0
K9F5608Q0B-DCB0,DIB0,HCB0,HIB0
K9F5608U0B-YCB0,YIB0,PCB0,PIB0
K9F5608U0B-DCB0,DIB0,HCB0,HIB0
K9F5616Q0B-DCB0,DIB0,HCB0,HIB0
K9F5616U0B-YCB0,YIB0,PCB0,PIB0
K9F5616U0B-DCB0,DIB0,HCB0,HIB0
FLASH MEMORY
READY/BUSY
The device has a R/B output that provides a hardware method of indicating the completion of a page program, erase and random
read completion. The R/B pin is normally high but transitions to low after program or erase command is written to the command reg-
ister or random read is started after address loading. It returns to high when the internal controller has finished the operation. The pin
is an open-drain driver thereby allowing two or more R/B outputs to be Or-tied. Because pull-up resistor value is related to tr(R/B)
and current drain during busy(ibusy) , an appropriate value can be obtained with the following reference chart(Fig 15). Its value can
be determined by the following guidance.
Rp
ibusy
VCC
1.8V device - VOL : 0.1V, VOH : VCCq-0.1V
3.3V device - VOL : 0.4V, VOH : 2.4V
Ready Vcc
R/B
open drain output
VOH
CL
VOL
Busy
tf
tr
GND
Device
Fig 15 Rp vs tr ,tf & Rp vs ibusy
@ Vcc = 1.8V, Ta = 25°C , CL = 30pF
@ Vcc = 3.3V, Ta = 25°C , CL = 100pF
400
2.4
Ibusy
Ibusy
300n
3m
300n
3m
300
1.2
1.7
200n
100n
2m
1m
200n
100n
200
2m
1m
0.8
120
0.85
60
90
tr
tf
tr
30
100
0.6
0.57
1.7
0.43
3.6
2K
3.6
3.6
3.6
tf
1.7
1.7
2K
1.7
4K
1K
3K
Rp(ohm)
4K
1K
3K
Rp(ohm)
Rp value guidance
VCC(Max.) - VOL(Max.)
1.85V
Rp(min, 1.8V part) =
=
=
3mA + SIL
IOL + SIL
VCC(Max.) - VOL(Max.)
3.2V
Rp(min, 3.3V part) =
IOL + SIL
8mA + SIL
where IL is the sum of the input currents of all devices tied to the R/B pin.
Rp(max) is determined by maximum permissible limit of tr
33
K9F5608U0B-VCB0,VIB0,FCB0,FIB0
K9F5608Q0B-DCB0,DIB0,HCB0,HIB0
K9F5608U0B-YCB0,YIB0,PCB0,PIB0
K9F5608U0B-DCB0,DIB0,HCB0,HIB0
K9F5616Q0B-DCB0,DIB0,HCB0,HIB0
K9F5616U0B-YCB0,YIB0,PCB0,PIB0
K9F5616U0B-DCB0,DIB0,HCB0,HIB0
FLASH MEMORY
Data Protection & Powerup sequence
The device is designed to offer protection from any involuntary program/erase during power-transitions. An internal voltage detector
disables all functions whenever Vcc is below about 1.3V. WP pin provides hardware protection and is recommended to be kept at
VIL during power-up and power-down and recovery time of minimum 10ms is required before internal circuit gets ready for any com-
mand sequences as shown in Figure 16. The two step command sequence for program/erase provides additional software protec-
tion.
Figure 16. AC Waveforms for Power Transition
1.8V device : ~ 1.5V
3.3V device : ~ 2.5V
1.8V device : ~ 1.5V
3.3V device : ~ 2.5V
VCC
High
WP
WE
10ms
34
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