K9F6408U0C-FIB0 [SAMSUNG]
Flash, 8MX8, 35ns, PDSO48;
| 型号： | K9F6408U0C-FIB0 |
| 厂家： | 
SAMSUNG |
| 描述： | Flash, 8MX8, 35ns, PDSO48 光电二极管 内存集成电路 |
| 文件： | 总30页 (文件大小：784K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
FLASH MEMORY
K9F6408U0C
Document Title
8M x 8 Bit NAND Flash Memory
Revision History
Revision No. History
Draft Date
Remark
0.0
0.1
Initial issue.
Jul. 24 . 2001
Advance
1. IOL(R/B) of 1.8V device is changed.
-min. Value: 7mA -->3mA
Nov. 5 . 2001
Preliminary
-typ. Value: 8mA -->4mA
2. Package part number is modified.
K9F6408U0C-Y ---> K9F6408U0C_T
3. AC parameter is changed.
tRP(min.) : 30ns --> 25ns
Nov. 12 . 2001
0.2
1. TBGA package is changed.
- 9mmX11mm 63ball TBGA ---> 6mmX8.5mm 48ball TBGA
2. Part number(TBGA package part number) is changed
- K9F6408Q0C-D ----> K9F6408Q0C-B
- K9F6408U0C-D -----> K9F6408U0C-B
3. K9F6408U0C-BCB0,BIB0 products are added
1. WSOP1 package is added.
0.3
0.4
Mar. 13 . 2002
Nov. 21. 2002
- Part number : K9F6408U0C_VCB0,VIBO
1. Add the Rp vs tr ,tf & Rp vs ibusy graph for 1.8V device (Page 28)
2. Add the data protection Vcc guidence for 1.8V device - below about
1.1V. (Page 29)
Mar. 05. 2003
Mar. 13 . 2003
The min. Vcc value 1.8V devices is changed.
K9F64XXQ0C : Vcc 1.65V~1.95V --> 1.70V~1.95V
0.5
0.6
Pb-free Package is added.
K9F6408U0C-QCB0,QIB0
K9F6408U0C-HCB0,HIB0
K9F6408Q0C-HCB0,HIB0
K9F6408U0C-FCB0,FIB0
0.7
Note is added.
Jul. 04. 2003
(VIL can undershoot to -0.4V and VIH can overshoot to VCC +0.4V for
durations of 20 ns or less.)
Apr. 24. 2004
May. 24. 2004
0.8
0.9
1. Add the Protrusion/Burr value in WSOP1 PKG Diagram.
1. PKG(WSOP1) Dimension Change
Note : For more detailed features and specifications including FAQ, please refer to Samsung’s Flash web site.
http://www.samsung.com/Products/Semiconductor/Flash/TechnicalInfo/datasheets.htm
The attached datasheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the
specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions about device. If you have any questions, please contact the
SAMSUNG branch office near you.
1
FLASH MEMORY
K9F6408U0C
Document Title
8M x 8 Bit NAND Flash Memory
Revision History
Revision No. History
Draft Date
Remark
1.0
1. NAND Flash Technical Notes is changed.
Oct. 25th. 2004
-Invalid block -> initial invalid block ( page 13)
-Error in write or read operation ( page 14 )
-Program Flow Chart ( page 14 )
May 6th. 2005
1. The flow chart to creat the initial invalid block table is changed.
1.1
Note : For more detailed features and specifications including FAQ, please refer to Samsung’s Flash web site.
http://www.samsung.com/Products/Semiconductor/Flash/TechnicalInfo/datasheets.htm
The attached datasheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the
specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions about device. If you have any questions, please contact the
SAMSUNG branch office near you.
2
FLASH MEMORY
K9F6408U0C
8M x 8 Bit Bit NAND Flash Memory
PRODUCT LIST
Part Number
K9F6408U0C-B,H
K9F6408U0C-T,Q
K9F6408U0C-V,F
Vcc Range
Organization
PKG Type
TBGA
2.7 ~ 3.6V
X8
TSOP II
WSOP I
FEATURES
• Voltage Supply
- 1.70~1.95V
• Command/Address/Data Multiplexed I/O Port
• Hardware Data Protection
• Organization
- Memory Cell Array : (8M + 256K)bit x 8bit
- Data Register : (512 + 16)bit x8bit
• Automatic Program and Erase
- Page Program : (512 + 16)Byte
- Block Erase : (8K + 256)Byte
• 528-Byte Page Read Operation
- Random Access : 10µs(Max.)
- Serial Page Access
- Program/Erase Lockout During Power Transitions
• Reliable CMOS Floating-Gate Technology
- Endurance : 100K Program/Erase Cycles
- Data Retention : 10 Years
• Command Register Operation
• Package
- K9F6408U0C-TCB0/TIB0
44(40) - Lead TSOP Type II (400mil / 0.8 mm pitch)
- K9F6408U0C-BCB0/BIB0
- 50ns
• Fast Write Cycle Time
48 - Ball TBGA ( 6 x 8.5 /0.8mm pitch , Width 1.0 mm)
- K9F6408U0C-VCB0/VIB0
- Program Time : 200µs(Typ.)
- Block Erase Time : 2ms(Typ.)
48 - Pin WSOP I (12X17X0.7mm)
- K9F6408U0C-QCB0/QIB0 : Pb-free Package
44(40) - Lead TSOP Type II (400mil / 0.8 mm pitch)
- K9F6408U0C-HCB0/HIB0 : Pb-free Package
48 - Ball TBGA ( 6 x 8.5 /0.8mm pitch , Width 1.0 mm)
- K9F6408U0C-FCB0/FIB0 : Pb-free Package
48 - Pin WSOP I (12X17X0.7mm)
* K9F6408U0C-V,F(WSOPI ) is the same device as
K9F6408U0C-T,Q(TSOPII) except package type.
GENERAL DESCRIPTION
The K9F6408U0C is a 8M(8,388,608)x8bit NAND Flash Memory with a spare 256K(262,144)x8bit. The device is offered in 3.3V Vcc.
Its NAND cell provides the most cost-effective solution for the solid state mass storage market. A program operation programs the
528-byte page in typical 200µs and an erase operation can be performed in typical 2ms on an 8K-byte block. Data in the page can be
read out at 50ns cycle time per byte. The I/O pins serve as the ports for address and data input/output as well as command inputs.
The on-chip write controller automates all program and erase functions including pulse repetition, where required, and internal verifi-
cation and margining of data. Even the write-intensive systems can take advantage of the K9F6408U0C′s extended reliability of 100K
program/erase cycles by providing ECC(Error Correcting Code) with real time mapping-out algorithm. These algorithms have been
implemented in many mass storage applications and also the spare 16 bytes of a page combined with the other 512 bytes can be uti-
lized by system-level ECC. The K9F6408U0C is an optimum solution for large nonvolatile storage applications such as solid state file
storage, digital voice recorder, digital still camera and other portable applications requiring non-volatility.
3
FLASH MEMORY
K9F6408U0C
PIN CONFIGURATION (TSOP II )
K9F6408U0C-TCB0,QCB0/TIB0,QIB0
VSS
CLE
ALE
WE
WP
N.C
N.C
N.C
N.C
N.C
1
2
3
4
5
6
7
8
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
VCC
CE
RE
R/B
GND
N.C
N.C
N.C
N.C
N.C
9
10
11
12
13
14
15
16
17
18
19
20
21
22
N.C
N.C
N.C
N.C
N.C
I/O0
I/O1
I/O2
I/O3
VSS
N.C
N.C
N.C
N.C
N.C
I/O7
I/O6
I/O5
I/O4
VCC
PACKAGE DIMENSIONS
44(40) LEAD/LEAD FREE PLASTIC THIN SMALL OUT-LINE PACKAGE TYPE(II)
44(40) - TSOP II - 400F
Unit :mm/Inch
0~8°
0.25
0.010
TYP
#44(40)
#23(21)
0.50
0.020
#1
#22(20)
+0.10
0.15
-0.05
+0.004
-0.002
0.006
18.81
0.741
Max.
18.41±0.10
0.725±0.004
0.10
MAX
0.004
0.805
0.032
0.35±0.10
0.014±0.004
0.80
(
)
0.0315
4
FLASH MEMORY
K9F6408U0C
PIN CONFIGURATION (TBGA)
K9F6408U0C-BCB0,HCB0/BIB0,HIB0
1
2
3
4
5
6
N.C
A
B
C
D
E
F
WP
N.C
N.C
N.C
ALE
RE
CE
WE
N.C
N.C
N.C
N.C
N.C
R/B
N.C
N.C
N.C
N.C
VCC
I/O7
VSS
CLE
N.C
N.C
N.C
N.C
N.C
N.C
N.C
N.C
N.C
N.C
N.C
N.C
I/O0
I/O1
I/O2
N.C
N.C
N.C
VSS
G
H
N.C VCCQ I/O5
I/O3 I/O4 I/O6
(Top View)
PACKAGE DIMENSIONS
48-Ball TBGA (measured in millimeters)
Top View
Bottom View
6.00±0.10
A
0.80 x5= 4.00
0.80
6.00±0.10
(Datum A)
(Datum B)
6
5
4
3
2
1
A
B
C
D
E
F
Ball #A1
G
H
48-∅0.45±0.05
2.00
B
∅
0.20 M A B
Side View
0.45±0.05
0.08MAX
6.00±0.10
5
FLASH MEMORY
K9F6408U0C
PIN CONFIGURATION (WSOP1)
K9F6408U0C-VCB0,FCB0/VIB0,FIB0
N.C
N.C
DNU
N.C
I/O7
I/O6
I/O5
I/O4
N.C
DNU
N.C
Vcc
N.C
N.C
DNU
N.C
N.C
N.C
R/B
RE
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
1
2
3
4
5
6
7
8
CE
9
DNU
N.C
Vcc
Vss
N.C
DNU
CLE
ALE
WE
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
Vss
N.C
DNU
N.C
I/O3
I/O2
I/O1
I/O0
N.C
DNU
N.C
N.C
WP
N.C
N.C
DNU
N.C
N.C
PACKAGE DIMENSIONS
48-PIN LEAD PLASTIC VERY VERY THIN SMALL OUT-LINE PACKAGE TYPE (I)
Unit :mm
48 - WSOP1 - 1217F
0.70 MAX
0.58±0.04
15.40±0.10
#1
#48
#24
#25
(0.01Min)
0.45~0.75
17.00±0.20
6
FLASH MEMORY
K9F6408U0C
PIN DESCRIPTION
Pin Name
Pin Function
DATA INPUTS/OUTPUTS
I/O0 ~ I/O7
CLE
The I/O pins are used to input command, address and data, and to output data during read operations. The I/
O pins float to high-z when the chip is deselected or when the outputs are disabled.
COMMAND LATCH ENABLE
The CLE input controls the activating path for commands sent to the command register. When active high,
commands are latched into the command register through the I/O ports on the rising edge of the WE signal.
ADDRESS LATCH ENABLE
ALE
The ALE input controls the activating path for address to the internal address registers. Addresses are
latched on the rising edge of WE with ALE high.
CHIP ENABLE
The CE input is the device selection control. When the device is in the Busy state, CE high is ignored, and
the device does not return to standby mode in program or erase operation. Regarding CE control during read
operation, refer to ’Page read’ section of Device operation .
CE
READ ENABLE
RE
WE
WP
The RE input is the serial data-out control, and when active drives the data onto the I/O bus. Data is valid
tREA after the falling edge of RE which also increments the internal column address counter by one.
WRITE ENABLE
The WE input controls writes to the I/O port. Commands, address and data are latched on the rising edge of
the WE pulse.
WRITE PROTECT
The WP pin provides inadvertent write/erase protection during power transitions. The internal high voltage
generator is reset when the WP pin is active low.
READY/BUSY OUTPUT
The R/B output indicates the status of the device operation. When low, it indicates that a program, erase or
random read operation is in process and returns to high state upon completion. It is an open drain output and
does not float to high-z condition when the chip is deselected or when outputs are disabled.
R/B
OUTPUT BUFFER POWER
VccQ
VccQ is the power supply for Output Buffer.
VccQ is internally connected to Vcc, thus should be biased to Vcc.
POWER
Vcc
Vss
N.C
VCC is the power supply for device.
GROUND
NO CONNECTION
Lead is not internally connected.
GND INPUT FOR ENABLING SPARE AREA
GND
DNU
To do sequential read mode including spare area , connect this input pin to Vss or set to static low state
or to do sequential read mode excluding spare area , connect this input pin to Vcc or set to static high state .
DO NOT USE
Leave it disconnected.
NOTE : Connect all VCC and VSS pins of each device to common power supply outputs.
Do not leave VCC or VSS disconnected.
7
FLASH MEMORY
K9F6408U0C
Figure 1. FUNCTIONAL BLOCK DIAGRAM
VCC
VSS
Y-Gating
2nd half Page Register & S/A
X-Buffers
A9 - A22
Latches
& Decoders
64M + 2M Bit
NAND Flash
ARRAY
Y-Buffers
A0 - A7
Latches
& Decoders
(512 + 16)Byte x 16384
1st half Page Register & S/A
Y-Gating
A8
Command
Command
Register
Vcc/VccQ
VSS
I/O Buffers & Latches
CE
RE
WE
Control Logic
& High Voltage
Generator
I/0 0
I/0 7
Output
Driver
Global Buffers
CLE ALE WP
Figure 2. ARRAY ORGANIZATION
1 Block =16 Pages
= (8K + 256) Byte
1 Page = 528 Byte
1 Block = 528 Byte x 16 Pages
= (8K + 256) Byte
1 Device = 528 Byte x 16Pages x 1024 Blocks
= 66 Mbits
16K Pages
(=1,024 Blocks)
1st half Page Register
(=256 Bytes)
2nd half Page Register
(=256 Bytes)
8 bit
512Byte
16 Byte
16 Byte
I/O 0 ~ I/O 7
Page Register
512 Byte
I/O 0
A0
I/O 1
A1
I/O 2
I/O 3
A3
I/O 4
A4
I/O 5
A5
I/O 6
A6
I/O 7
A7
1st Cycle
A2
A11
A19
Column Address
Row Address
2nd Cycle
3rd Cycle
A9
A10
A18
A12
A20
A13
A21
A14
A22
A15
*L
A16
*L
A17
(Page Address)
NOTE : Column Address : Starting Address of the Register.
00h Command(Read) : Defines the starting address of the 1st half of the register.
01h Command(Read) : Defines the starting address of the 2nd half of the register.
* A8 is set to "Low" or "High" by the 00h or 01h Command.
* L must be set to "Low".
* The device ignores any additional input of address cycles than reguired.
8
FLASH MEMORY
K9F6408U0C
PRODUCT INTRODUCTION
The K9F6408U0C is a 66Mbit(69,206,016 bit) memory organized as 16,384 rows(pages) by 528 columns. Spare sixteen columns are
located from column address of 512 to 527. A 528-byte data register is connected to memory cell arrays accommodating data trans-
fer between the I/O buffers and memory during page read and page program operations. The memory array is made up of 16 cells
that are serially connected to form a NAND structure. Each of the 16 cells resides in a different page. A block consists of two NAND
structured strings. A NAND structure consists of 16 cells. Total 135168 NAND cells reside in a block. The array organization is shown
in Figure 2. The program and read operations are executed on a page basis, while the erase operation is executed on a block basis.
The memory array consists of 1024 separately erasable 8K-byte blocks. It indicates that the bit by bit erase operation is prohibited on
the K9F6408U0C.
The K9F6408U0C has addresses multiplexed into 8 I/O′s. This scheme dramatically reduces pin counts and allows systems
upgrades to future densities by maintaining consistency in system board design. Command, address and data are all written through
I/O′s by bringing WE to low while CE is low. Data is latched on the rising edge of WE. Command Latch Enable(CLE) and Address
Latch Enable(ALE) are used to multiplex command and address respectively, via the I/O pins. All commands require one bus cycle
except for Block Erase command which requires two cycles: one cycle for erase-setup and another for erase-execution after block
address loading. The 8M byte physical space requires 23 addresses, thereby requiring three cycles for byte-level addressing: column
address, low row address and high row address, in that order. Page Read and Page Program need the same three address cycles
following the required command input. In Block Erase operation, however, only the two row address cycles are used.
Device operations are selected by writing specific commands into the command register. Table 1 defines the specific commands of
the K9F6408U0C.
Table 1. COMMAND SETS
Function
1st. Cycle
00h/01h(1)
50h(2)
90h
2nd. Cycle
Acceptable Command during Busy
Read 1
Read 2
Read ID
Reset
-
-
-
-
FFh
O
O
Page Program
Block Erase
Read Status
80h
10h
D0h
-
60h
70h
NOTE : 1. The 00h command defines starting address of the 1st half of registers.
The 01h command defines starting address of the 2nd half of registers.
After data access on the 2nd half of register by the 01h command, the status pointer is
automatically moved to the 1st half register(00h) on the next cycle.
2. The 50h command is valid only when the GND input(pin #40) is low level.
Caution : Any undefined command inputs are prohibited except for above command set of Table 1.
9
FLASH MEMORY
K9F6408U0C
ABSOLUTE MAXIMUM RATINGS
Parameter
Symbol
VIN/OUT
VCC
Rating
Unit
V
-0.6 to + 4.6
-0.6 to + 4.6
-0.6 to + 4.6
-10 to + 125
-40 to + 125
-65 to + 150
Voltage on any pin relative to VSS
V
VccQ
V
K9F6408U0C-XCB0
K9F6408U0C-XIB0
Temperature
Under Bias
TBIAS
TSTG
°C
°C
Storage Temperature
NOTE :
1. Minimum DC voltage is -0.6V on input/output pins and -0.2V on Vcc and VccQ pins. During transitions, this level may undershoot to -2.0V for periods
<20ns. Maximum DC voltage on input/output pins is VCCQ+0.3V which, during transitions, may overshoot to VCC+2.0V for periods <20ns.
2. Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to the conditions
as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
RECOMMENDED OPERATING CONDITIONS
(Voltage reference to GND, K9F6408U0C-XCB0:TA=0 to 70°C, K9F6408U0C-XIB0:TA=-40 to 85°C)
Parameter
Supply Voltage
Symbol
VCC
Min
2.7
2.7
0
Typ.
3.3
3.3
0
Max
3.6
3.6
0
Unit
V
Supply Voltage
Supply Voltage
VccQ
VSS
V
V
DC AND OPERATING CHARACTERISTICS(Recommended operating conditions otherwise noted.)
Parameter
Symbol
Test Conditions
CE=VIL, IOUT=0mA
tRC=50ns
Min
Typ
Max
Unit
Sequential Read
ICC1
-
10
20
Operating
Current
Program
Erase
ICC2
ICC3
ISB1
ISB2
ILI
-
-
-
10
10
-
20
mA
-
-
20
Stand-by Current(TTL)
Stand-by Current(CMOS)
Input Leakage Current
Output Leakage Current
CE=VIH, WP=0V/VCC
CE=VCC-0.2, WP=0V/VCC
VIN=0 to Vcc(max)
VOUT=0 to Vcc(max)
I/O pins
1
-
10
-
50
-
±10
µA
ILO
-
-
±10
2.0
2.0
-0.3
2.4
-
-
VccQ+0.3
Input High Voltage
VIH*
Except I/O pins
-
-
VCC+0.3
Input Low Voltage, All inputs
Output High Voltage Level
Output Low Voltage Level
Output Low Current(R/B)
VIL*
VOH
-
0.8
-
V
IOH=-400µA
-
VOL
IOL=2.1mA
-
0.4
-
IOL(R/B)
VOL=0.4V
8
10
mA
NOTE : VIL can undershoot to -0.4V and VIH can overshoot to VCC +0.4V for durations of 20 ns or less.
10
FLASH MEMORY
K9F6408U0C
VALID BLOCK
Parameter
Symbol
Min
Typ.
Max
Unit
Valid Block Number
NVB
1014
1020
1024
Blocks
NOTE :
1. The device may include invalid blocks when first shipped. Additional invalid blocks may develop while being used. The number of valid blocks is pre-
sented with both cases of invalid blocks considered. Invalid blocks are defined as blocks that contain one or more bad bits. Do not erase or pro-
gram factory-marked bad blocks. Refer to the attached technical notes for a appropriate management of invalid blocks.
2. The 1st block, which is placed on 00h block address, is guaranteed to be a valid block, does not require Error Correction up to 1K program/erase
cycles.
AC TEST CONDITION
(K9F6408U0C-XCB0:TA=0 to 70°C, K9F6408U0C-XIB0:TA=-40 to 85°C
K9F6408U0C: Vcc=2.7V~3.6V unless otherwise noted)
Parameter
K9F6408U0C
0.4V to 2.4V
Input Pulse Levels
Input Rise and Fall Times
5ns
Input and Output Timing Levels
1.5V
K9F6408U0C:Output Load (VccQ:3.0V +/-10%)
K9F6408U0C:Output Load (VccQ:3.3V +/-10%)
1 TTL GATE and CL=50pF
1 TTL GATE and CL=100pF
CAPACITANCE(TA=25°C, VCC=3.3V, f=1.0MHz)
Item
Symbol
Test Condition
Min
Max
10
Unit
pF
Input/Output Capacitance
Input Capacitance
CI/O
VIL=0V
-
-
CIN
VIN=0V
10
pF
NOTE : Capacitance is periodically sampled and not 100% tested.
MODE SELECTION
CLE
H
L
ALE
L
CE
L
WE
RE
H
WP
X
Mode
Command Input
Read Mode
H
L
L
H
X
Address Input(3clock)
Command Input
H
L
L
H
H
Write Mode
H
L
L
H
H
Address Input(3clock)
L
L
H
H
Data Input
Data Output
L
L
L
H
H
X
L
L
L
H
H
X
During Read(Busy) on K9F6408U0C_T,Q or K9F6408U0C_V,F
During Read(Busy) on the devices except K9F6408U0C_T,Q
and K9F6408U0C_V,F)
X
X
X
X
X
X
X
X
X
X
X
X
X
X
H
X
X
X
X
X
X
X
X
H
During Program(Busy)
During Erase(Busy)
Write Protect
H
L
X(1)
X
(2)
Stand-by
0V/VCC
NOTE : 1. X can be VIL or VIH.
2. WP should be biased to CMOS high or CMOS low for standby.
Program/Erase Characteristics
Parameter
Symbol
Min
Typ
Max
500
2
Unit
µs
Program Time
tPROG
-
-
-
-
200
Main Array
Spare Array
-
-
cycles
cycles
ms
Number of Partial Program Cycles
in the Same Page
Nop
3
Block Erase Time
tBERS
2
3
NOTE : Typical program time is defined as the time within which more than 50% of the whole pages are programmed at Vcc of 3.3V and temperature of
25°C .
11
FLASH MEMORY
K9F6408U0C
AC Timing Characteristics for Command / Address / Data Input
Parameter
Symbol
tCLS
tCLH
tCS
Min
Max
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
CLE Set-up Time
0
-
-
-
-
-
-
-
-
-
-
-
CLE Hold Time
CE Setup Time
CE Hold Time
10
0
tCH
10
25(1)
0
WE Pulse Width
ALE Setup Time
ALE Hold Time
Data Setup Time
Data Hold Time
Write Cycle Time
WE High Hold Time
tWP
tALS
tALH
tDS
10
20
10
50
15
tDH
tWC
tWH
NOTE : 1. If tCS is set less than 10ns, tWP must be minimum 35ns, otherwise, tWP may be minimum 25ns.
AC Characteristics for Operation
Parameter
Symbol
tR
Min
-
Max
Unit
Data Transfer from Cell to Register
10
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
ALE to RE Delay( ID read )
ALE to RE Delay(Read cycle)
CLE to RE Delay
tAR1
tAR2
tCLR
tRR
20
50
50
20
25
-
-
-
-
Ready to RE Low
-
RE Pulse Width
tRP
-
WE High to Busy
tWB
100
Read Cycle Time
tRC
50
-
-
CE Access Time
tCEA
tREA
tRHZ
tCHZ
tOH
45
RE Access Time
-
35
RE High to Output Hi-Z
CE High to Output Hi-Z
RE or CE High to Output hold
RE High Hold Time
-
30
-
20
15
15
0
-
tREH
tIR
-
Output Hi-Z to RE Low
WE High to RE Low
-
tWHR
tRST
60
-
-
5/10/500(1)
Device Resetting Time(Read/Program/Erase)
Last RE High to Busy
(at sequential read)
tRB
-
100
ns
K9F6408U0C-
T,Q,V,F only
CE High to Ready(in case of interception by
CE at read)
tCRY
50 +tr(R/B)(3)
-
-
ns
ns
CE High Hold Time(at the last serial read)(2)
tCEH
100
NOTE : 1. If reset command(FFh) is written at Ready state, the device goes into Busy for maximum 5us.
2. To break the sequential read cycle, CE must be held high for longer time than tCEH.
3. The time to Ready depends on the value of the pull-up resistor tied R/B pin.
12
FLASH MEMORY
K9F6408U0C
NAND Flash Technical Notes
Initial Invalid Block(s)
Initial invalid blocks are defined as blocks that contain one or more initial invalid bits whose reliability is not guaranteed by Samsung.
The information regarding the initial invalid block(s) is so called as the initial invalid block information. Devices with initial invalid
block(s) have the same quality level or as devices with all valid blocks and have the same AC and DC characteristics. An initial
invalid block(s) does not affect the performance of valid block(s) because it is isolated from the bit line and the common source line by
a select transistor. The system design must be able to mask out the initial invalid block(s) via address mapping. The 1st block of the
NAND Flash, however, is guaranteed to be a valid block up to 1K program/erase cycles.
Identifying Initial Invalid Block(s)
All device locations are erased(FFh) except locations where the initial invalid block(s) information is written prior to shipping. The
initial invalid block(s) status is defined by the 6th byte in the spare area. Samsung makes sure that either the 1st or 2nd page of every
initial invalid block has non-FFh data at the column address of 517. Since the invalid block information is also erasable in most cases,
it is impossible to recover the information once it has been erased. Therefore, the system must be able to recognize the initial invalid
block(s) based on the initial invalid block information and create the initial invalid block table via the following suggested flow
chart(Figure 1). Any intentional erasure of the initial invalid block information is prohibited.
Start
Set Block Address = 0
Increment Block Address
Check "FFh" at the column address 517
*
No
of the 1st and 2nd page in the block
Create (or update)
Initial
Invalid Block(s) Table
Check "FFh" ?
Yes
No
Last Block ?
Yes
End
Figure 1. Flow chart to create initial invalid block table.
13
FLASH MEMORY
K9F6408U0C
NAND Flash Technical Notes (Continued)
Error in write or read operation
Within its life time, the additional invalid blocks may develop with NAND Flash memory. Refer to the qualification report for the actual
data.The following possible failure modes should be considered to implement a highly reliable system. In the case of status read fail-
ure after erase or program, block replacement should be done. In case of Read, ECC must be employed. To improve the efficiency of
memory space, it is recommended that the read or verification failure due to single bit error be reclaimed by ECC without any block
replacement. The said additional block failure rate does not include those reclaimed blocks.
Failure Mode
Erase Failure
Detection and Countermeasure sequence
Status Read after Erase --> Block Replacement
Status Read after Program --> Block Replacement
Verify ECC -> ECC Correction
Write
Read
Program Failure
Single Bit Failure
: Error Correcting Code --> Hamming Code etc.
Example) 1bit correction & 2bit detection
ECC
Program Flow Chart
Start
Write 80h
Write Address
Write Data
Write 10h
Read Status Registe
No
I/O 6 = 1 ?
or R/B = 1 ?
Yes
*
No
Program Error
I/O 0 = 0 ?
Yes
Program Completed
: If program operation results in an error, map out
the block including the page in error and copy the
target data to another block.
*
14
FLASH MEMORY
K9F6408U0C
NAND Flash Technical Notes (Continued)
Erase Flow Chart
Read Flow Chart
Start
Start
Write 60h
Write 00h
Write Block Address
Write Address
Read Data
Write D0h
Read Status Register
ECC Generation
No
No
I/O 6 = 1 ?
or R/B = 1 ?
Reclaim the Error
Verify ECC
Yes
Yes
*
No
Page Read Completed
Erase Error
I/O 0 = 0 ?
Yes
Erase Completed
: If erase operation results in an error, map out
the failing block and replace it with another block.
*
Block Replacement
Block A
1st
2
{
(n-1)th
nth
(page)
Buffer memory of the controller.
Block B
1st
1
{
(n-1)th
nth
(page)
* Step1
When an error happens in the nth page of the Block ’A’ during erase or program operation.
* Step2
Copy the nth page data of the Block ’A’ in the buffer memory to the nth page of another free block. (Block ’B’)
* Step3
Then, Copy the 1st ~ (n-1)th data to the same location of the Block ’B’.
* Step4
Do not further erase Block ’A’ by creating a ’invalid Block’ table or other appropriate scheme.
15
FLASH MEMORY
K9F6408U0C
Pointer Operation of K9F6408U0C
Samsung NAND Flash has three address pointer commands as a substitute for the two most significant column addresses. ’00h’
command sets the pointer to ’A’ area(0~255byte), ’01h’ command sets the pointer to ’B’ area(256~511byte), and ’50h’ command sets
the pointer to ’C’ area(512~527byte). With these commands, the starting column address can be set to any of a whole
page(0~527byte). ’00h’ or ’50h’ is sustained until another address pointer command is inputted. ’01h’ command, however, is effective
only for one operation. After any operation of Read, Program, Erase, Reset, Power_Up is executed once with ’01h’ command, the
address pointer returns to ’A’ area by itself. To program data starting from ’A’ or ’C’ area, ’00h’ or ’50h’ command must be inputted
before ’80h’ command is written. A complete read operation prior to ’80h’ command is not necessary. To program data starting from
’B’ area, ’01h’ command must be inputted right before ’80h’ command is written.
Table 1. Destination of the pointer
Command
Pointer position
Area
"A" area
(00h plane)
"B" area
(01h plane)
"C" area
(50h plane)
00h
01h
50h
0 ~ 255 byte
256 ~ 511 byte
512 ~ 527 byte
1st half array(A)
2nd half array(B)
spare array(C)
256 Byte
256 Byte
16 Byte
"A"
"B"
"C"
Internal
Page Register
Pointer select
commnad
(00h, 01h, 50h)
Pointer
Figure 2. Block Diagram of Pointer Operation
(1) Command input sequence for programming ’A’ area
The address pointer is set to ’A’ area(0~255), and sustained
Address / Data input
Address / Data input
80h 10h
00h
80h
10h
00h
’A’,’B’,’C’ area can be programmed.
’00h’ command can be omitted.
It depends on how many data are inputted.
(2) Command input sequence for programming ’B’ area
The address pointer is set to ’B’ area(256~512), and will be reset to
’A’ area after every program operation is executed.
Address / Data input
Address / Data input
80h 10h
01h
80h
10h
01h
’B’, ’C’ area can be programmed.
It depends on how many data are inputted.
’01h’ command must be rewritten before
every program operation
(3) Command input sequence for programming ’C’ area
The address pointer is set to ’C’ area(512~527), and sustained
Address / Data input
Address / Data input
80h 10h
50h
80h
10h
50h
Only ’C’ area can be programmed.
’50h’ command can be omitted.
16
FLASH MEMORY
K9F6408U0C
System Interface Using CE don’t-care.
For an easier system interface, CE may be inactive during the data-loading or sequential data-reading as shown below. The internal
528byte page registers are utilized as seperate buffers for this operation and the system design gets more flexible. In addition, for
voice or audio applications which use slow cycle time on the order of u-seconds, de-activating CE during the data-loading and read-
ing would provide significant savings in power consumption.
Figure 3. Program Operation with CE don’t-care.
CLE
CE don’t-care
CE
WE
ALE
80h
Start Add.(3Cycle)
Data Input
Data Input
10h
I/O0~7
CE
tCS
tCH
tCEA
CE
RE
tREA
tWP
WE
I/O0~7
out
Timing requirements : If CE is exerted high during sequential
data-reading, the falling edge of CE to valid data(tCEA) must
be kept greater than 45ns.
Timing requirements : If CE is is exerted high during data-loading,
tCS must be minimum 10ns and tWC must be increased accordingly.
Figure 4. Read Operation with CE don’t-care.
On K9F6408U0C_T,Q or K9F6408U0C_V,F
CLE
CE
CE must be held
low during tR
CE don’t-care
RE
ALE
tR
R/B
WE
Data Output(sequential)
00h
Start Add.(3Cycle)
I/O0~7
17
FLASH MEMORY
K9F6408U0C
Command Latch Cycle
CLE
CE
tCLH
tCH
tCLS
tCS
tWP
WE
tALH
tALS
ALE
tDH
tDS
Command
I/O0~7
Address Latch Cycle
tCLS
CLE
CE
tCS
tWC
tWC
tWP
tWP
tWP
WE
tWH
tALH
tALS
tWH
tALH
tALS
tALH
tALS
ALE
tDH
tDH
tDH
tDS
tDS
tDS
A9~A16
A0~A7
I/O0~7
A17~A22
18
FLASH MEMORY
K9F6408U0C
Input Data Latch Cycle
tCLH
CLE
CE
tCH
tWC
tALS
ALE
tWP
tWP
tWP
WE
tWH
tDH
tDH
tDH
tDS
tDS
tDS
I/O0~7
DIN 1
DIN 511
DIN 0
Serial access Cycle after Read(CLE=L, WE=H, ALE=L)
tRC
CE
tCHZ*
tOH
tREH
tREA
tREA
tREA
RE
tRHZ*
tRHZ*
tOH
Dout
I/O0~7
R/B
Dout
Dout
tRR
NOTES : Transition is measured ±200mV from steady state voltage with load.
This parameter is sampled and not 100% tested.
19
FLASH MEMORY
K9F6408U0C
Status Read Cycle
tCLR
CLE
CE
tCLS
tCS
tCLH
tCH
tWP
WE
tCHZ*
tOH
tCSTO
tWHR
RE
tRHZ*
tOH
tDH
tRSTO
tDS
tIR
Status Output
I/O0~7
70h
READ1 OPERATION(READ ONE PAGE)
CLE
1)
On K9F6408U0C_T,Q or K9F6408U0C_V,F
CE must be held
tCEH
low during tR
CE
tCHZ
tOH
tWC
WE
tWB
tCRY
tAR2
ALE
RE
tRHZ
tOH
tR
tRC
tRR
A9 ~ A16 A17 ~ A24
Dout N+3
00h or 01h A0 ~ A7
Dout N
Dout N+1 Dout N+2
Dout 527
tRB
I/O0~7
R/B
Column
Address
Page(Row)
Address
Busy
1)
NOTES : 1) is only valid on K9F6408U0C_T,Q or K9F6408U0C_V,F
20
FLASH MEMORY
K9F6408U0C
READ1 OPERATION(INTERCEPTED BY CE)
CLE
On K9F6408U0C_T,Q or K9F6408U0C_V,F
CE must be held
low during tR
CE
WE
tCHZ
tOH
tWB
tAR2
ALE
RE
tR
tRC
tRR
A9 ~ A16 A17 ~ A22
Dout N+2
Dout N+3
00h or 01h A0 ~ A7
Dout N
Dout N+1
I/O0~7
R/B
Page(Row)
Address
Column
Address
Busy
READ2 OPERATION(READ ONE PAGE)
On K9F6408U0C_T,Q or K9F6408U0C_V,F
CE must be held
low during tR
CLE
CE
WE
ALE
RE
tR
tWB
tAR2
tRR
Dout
511+M+1
Dout
50h
A9 ~ A16 A17 ~ A22
Dout 527
A0 ~ A7
I/O0~7
R/B
511+M
Selected
Row
M Address
A0~A3 : Valid Address
A4~A7 : Don′t care
16
512
Start
address M
21
FLASH MEMORY
K9F6408U0C
SEQUENTIAL ROW READ OPERATION
(only for K9F6408U0C-T,Q and K9F6408U0C-V,F valid within a block)
CLE
CE
WE
ALE
RE
Dout
N
Dout
N+1
Dout
N+2
Dout
527
Dout
0
Dout
1
Dout
2
Dout
527
00h
A0 ~ A7 A9 ~ A16 A17 ~ A22
I/O0~7
R/B
Ready
Busy
Busy
M
M+1
Output
N
Output
PAGE PROGRAM OPERATION
CLE
CE
tWC
tWC
tWC
WE
ALE
RE
tPROG
tWB
Din
527
Din
N
Din
N+1
10h
Program
80h
A0 ~ A7 A9 ~ A16 A17 ~ A22
70h
I/O0
I/O0~7
R/B
Sequential Data Column
Input Command
Read Status
Command
1 up to 528 Byte Data
Serial Input
Page(Row)
Address
Address
Command
I/O0=0 Successful Program
I/O0=1 Error in Program
22
FLASH MEMORY
K9F6408U0C
BLOCK ERASE OPERATION (ERASE ONE BLOCK)
CLE
CE
tWC
WE
tBERS
tWB
ALE
RE
A9 ~ A16 A17 ~ A22
60h
DOh
70h
I/O 0
I/O0~7
R/B
Page(Row)
Address
Busy
I/O0=0 Successful Erase
Read Status I/O0=1 Error in Erase
Command
Auto Block Erase
Setup Command
Erase Command
MANUFACTURE & DEVICE ID READ OPERATION
tCLR
CLE
CE
WE
ALE
tAR1
RE
tREA
Device
Code*
90h
00h
ECh
Maker Code
I/O 0 ~ 7
Address. 1cycle
Read ID Command
Device Code
Device
Device Code*
K9F6408U0C
E6h
23
FLASH MEMORY
K9F6408U0C
DEVICE OPERATION
PAGE READ
Upon initial device power up, the device defaults to Read1 mode. This operation is also initiated by writing 00h to the command regis-
ter along with three address cycles. Once the command is latched, it does not need to be written for the following page read opera-
tion. Three types of operations are available : random read, serial page read and sequential row read.
The random read mode is enabled when the page address is changed. The 528 bytes of data within the selected page are transferred
to the data registers in less than 10µs(tR). The CPU can detect the completion of this data transfer(tR) by analyzing the output of R/B
pin. Once the data in a page is loaded into the registers, they may be read out in 50ns cycle time by sequentially pulsing RE. High to
low transitions of the RE clock output the data stating from the selected column address up to the last column address(column 511 or
527 depending on the state of GND input pin).
After the data of last column address is clocked out, the next page is automatically selected for sequential row read.
Waiting 10µs again allows reading the selected page.The sequential row read operation is terminated by bringing CE high. The way
the Read1 and Read2 commands work is like a pointer set to either the main area or the spare area. The spare area of bytes 512 to
527 may be selectively accessed by writing the Read2 command with GND input pin low. Addresses A0 to A3 set the starting address
of the spare area while addresses A4 to A7 are ignored. Unless the operation is aborted, the page address is automatically incre-
mented for sequential row read as in Read1 operation and spare sixteen bytes of each page may be sequentially read. The Read1
command(00h/01h) is needed to move the pointer back to the main area. Figures 3 through 6 show typical sequence and timings for
each read operation.
Sequential Row Read is available only on K9F6408U0C_T,Q or K9F6408U0C_V,F :
After the data of last column address is clocked out, the next page is automatically selected for sequential row read. Waiting 10µs
again allows reading the selected page. The sequential row read operation is terminated by bringing CE high. Unless the operation
is aborted, the page address is automatically incremented for sequential row read as in Read1 operation and spare sixteen bytes of
each page may be sequentially read. The Sequential Read 1 and 2 operation is allowed only within a block and after the last page of
a block is readout, the sequential read operation must be terminated by bringing CE high. When the page address moves onto the
next block, read command and address must be given. Figures 5, 6 show typical sequence and timings for sequential row read oper-
ation.
Figure 3. Read1 Operation
CLE
On K9F6408U0C_T,Q or K9F6408U0C_V,F
CE must be held
low during tR
CE
WE
ALE
tR
R/B
RE
00h
01h
Start Add.(3Cycle)
A0 ~ A7 & A9 ~ A22
Data Output(Sequential)
(01h Command)*
I/O0 ~ 7
(00h Command)
1st half array
2nd half array
1st half array
2nd half array
Data Field
Spare Field
Data Field
Spare Field
* After data access on 2nd half array by 01H command, the start pointer is automatically moved to 1st half array (00h) at next cycle.
24
FLASH MEMORY
K9F6408U0C
Figure 4. Read2 Operation
CLE
CE
WE
ALE
R/B
RE
tR
Start Add.(3Cycle)
A0 ~ A3 & A9 ~ A22
50h
Data Output(Sequential)
Spare Field
I/O0 ~ 7
(A4 ~ A7 :
Don't Care)
1st half array
2nd half array
Data Field
Spare Field
Figure 5. Sequential Row Read1 Operation
(only for K9F6408U0C-T,Q and K9F6408U0C-V,F valid within a block)
tR
tR
tR
R/B
Start Add.(3Cycle)
A0 ~ A7 & A9 ~ A22
I/O0 ~ 7
00h
01h
Data Output
1st
Data Output
Data Output
2nd
(528 Byte)
Nth
(528 Byte)
(GND Input=L, 00h Command)
(GND Input=L, 01h Command)
(GND Input=H, 00h Command)
1st half array
2nd half array
1st half array
2nd half array
1st half array
2nd half array
1st
1st
1st
2nd
2nd
2nd
Nth
Nth
Nth
Data Field
Spare Field
Data Field
Spare Field
Data Field
Spare Field
25
FLASH MEMORY
K9F6408U0C
Figure 6. Sequential Row Read2 Operation (GND Input=Fixed Low)
(only for K9F6408U0C-T,Q and K9F6408U0C-V,F valid within a block)
tR
tR
tR
R/B
50h
Start Add.(3Cycle)
A0 ~ A3 & A9 ~ A22
Data Output
1st
Data Output
Data Output
I/O0 ~ 7
2nd
(16 Byte)
Nth
(16 Byte)
(A4 ~ A7 :
Don′t Care)
1st half array
2nd half array
1st
2nd
Nth
Data Field
Spare Field
PAGE PROGRAM
The device is programmed basically on a page basis, but it does allow multiple partial page programming of a byte or consecutive
bytes up to 528, in a single page program cycle. The number of consecutive partial page programming operation within the same
page without an intervening erase operation should not exceed 2 for main array and 3 for spare array. The addressing may be done
in any random order in a block. A page program cycle consists of a serial data loading period in which up to 528 bytes of data may be
loaded into the page register, followed by a non-volatile programming period where the loaded data is programmed into the appropri-
ate cell. Serial data loading can be started from 2nd half array by moving pointer. About the pointer operation, please refer to the
attached technical notes.
The serial data loading period begins by inputting the Serial Data Input command(80h), followed by the three cycle address input and
then serial data loading. The bytes other than those to be programmed do not need to be loaded.The Page Program confirm com-
mand(10h) initiates the programming process. Writing 10h alone without previously entering the serial data will not initiate the pro-
gramming process. The internal write controller automatically executes the algorithms and timings necessary for program and verify,
thereby freeing the CPU for other tasks. Once the program process starts, the Read Status Register command may be entered, with
RE and CE low, to read the status register. The CPU can detect the completion of a program cycle by monitoring the R/B output, or
the Status bit(I/O 6) of the Status Register. Only the Read Status command and Reset command are valid while programming is in
progress. When the Page Program is complete, the Write Status Bit(I/O 0) may be checked(Figure 7). The internal write verify detects
only errors for "1"s that are not successfully programmed to "0"s. The command register remains in Read Status command mode
until another valid command is written to the command register.
Figure 7. Program & Read Status Operation
tPROG
R/B
Pass
I/O0 ~ 7
80h
Address & Data Input
I/O0
Fail
10h
70h
A0 ~ A7 & A9 ~ A22
528 Byte Data
26
FLASH MEMORY
K9F6408U0C
BLOCK ERASE
The Erase operation is done on a block(8K Byte) basis. Block address loading is accomplished in two cycles initiated by an Erase
Setup command(60h). Only address A13 to A22 is valid while A9 to A12 is ignored. The Erase Confirm command(D0h) following the
block address loading initiates the internal erasing process. This two-step sequence of setup followed by execution command
ensures that memory contents are not accidentally erased due to external noise conditions.
At the rising edge of WE after the erase confirm command input, the internal write controller handles erase and erase-verify. When
the erase operation is completed, the Write Status Bit(I/O 0) may be checked.
Figure 8 details the sequence.
Figure 8. Block Erase Operation
tBERS
R/B
Pass
I/O0 ~ 7
60h
I/O0
Fail
70h
Address Input(2Cycle)
Block Add. : A9 ~ A22
D0h
READ STATUS
The device contains a Status Register which may be read to find out whether program or erase operation is completed, and whether
the program or erase operation is completed successfully. After writing 70h command to the command register, a read cycle outputs
the content of the Status Register to the I/O pins on the falling edge of CE or RE, whichever occurs last. This two line control allows
the system to poll the progress of each device in multiple memory connections even when R/B pins are common-wired. RE or CE
does not need to be toggled for updated status. Refer to table 2 for specific Status Register definitions. The command register
remains in Status Read mode until further commands are issued to it. Therefore, if the status register is read during a random read
cycle, a read command(00h or 50h) should be given before sequential page read cycle.
Table2. Read Status Register Definition
I/O #
Status
Definition
"0" : Successful Program / Erase
I/O0
Program / Erase
"1" : Error in Program / Erase
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
"0"
"0"
"0"
"0"
"0"
Reserved for Future
Use
Device Operation
Write Protect
"0" : Busy
"1" : Ready
"1" : Not Protected
"0" : Protected
27
FLASH MEMORY
K9F6408U0C
READ ID
The device contains a product identification mode, initiated by writing 90h to the command register, followed by an address input of
00h. Two read cycles sequentially output the manufacture code(ECh), and the device code respectively. The command register
remains in Read ID mode until further commands are issued to it. Figure 9 shows the operation sequence.
Figure 9. Read ID Operation
tCLR
CLE
tCEA
CE
WE
tAR1
ALE
RE
tREA
Device
Code*
I/O0 ~ 7
00h
90h
ECh
Address. 1 cycle
Maker code
Device code
Device
Device Code*
K9F6408U0C
E6h
RESET
The device offers a reset feature, executed by writing FFh to the command register. When the device is in Busy state during random
read, program or erase modes, the reset operation will abort these operation. The contents of memory cells being altered are no
longer valid, as the data will be partially programmed or erased. Internal address registers are cleared to "0"s and data registers to
"1"s. The command register is cleared to wait for the next command, and the Status Register is cleared to value C0h when WP is
high. Refer to table 3 for device status after reset operation. If the device is already in reset state a new reset command will not be
accepted to by the command register. The R/B pin transitions to low for tRST after the Reset command is written. Reset command is
not necessary for normal operation. Refer to Figure 10 below.
Figure 10. RESET Operation
tRST
R/B
I/O0 ~ 7
FFh
Table3. Device Status
After Power-up
After Reset
Operation Mode
Read 1
Waiting for next command
28
FLASH MEMORY
K9F6408U0C
READY/BUSY
The device has a R/B output that provides a hardware method of indicating the completion of a page program, erase and random
read completion. The R/B pin is normally high but transitions to low after program or erase command is written to the command regis-
ter or random read is started after address loading. It returns to high when the internal controller has finished the operation. The pin is
an open-drain driver thereby allowing two or more R/B outputs to be Or-tied. Because pull-up resistor value is related to tr(R/B) and
current drain during busy(ibusy) , an appropriate value can be obtained with the following reference chart(Fig 11). Its value can be
determined by the following guidance.
Rp
ibusy
VCC
VOL : 0.1V, VOH : VccQ-0.1V
Ready Vcc
R/B
open drain output
VOH
CL
VOL
Busy
tf
tr
GND
Device
Figure 11. Rp vs tr ,tf & Rp vs ibusy
@ Vcc = 3.3V, Ta = 25°C , CL = 100pF
400
2.4
Ibusy
300n
3m
300
0.8
1.2
200n
100n
200
2m
1m
tr
tf
100
0.6
3.6
3.6
2K
3.6
3.6
4K
1K
3K
Rp(ohm)
Rp value guidance
3.2V
VCC(Max.) - VOL(Max.)
Rp(min) =
=
IOL + ΣIL
8mA + ΣIL
where IL is the sum of the input currents of all devices tied to the R/B pin.
Rp(max) is determined by maximum permissible limit of tr
29
FLASH MEMORY
K9F6408U0C
Data Protection & Powerup sequence
The device is designed to offer protection from any involuntary program/erase during power-transitions. An internal voltage detector
disables all functions whenever Vcc is below about 2V. WP pin provides hardware protection and is recommended to be kept at VIL
during power-up and power-down and recovery time of minimum 10µs is required before internal circuit gets ready for any command
sequences as shown in Figure 12. The two step command sequence for program/erase provides additional software protection.
Figure 12. AC Waveforms for Power Transition
3.3V device : ~ 2.5V
3.3V device : ~ 2.5V
VCC
High
WP
WE
10µs
30
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