K9K2G08U0A-VIB0 [SAMSUNG]
Flash, 256MX8, 30ns, PDSO48,;
| 型号： | K9K2G08U0A-VIB0 |
| 厂家： | 
SAMSUNG |
| 描述： | Flash, 256MX8, 30ns, PDSO48, 光电二极管 内存集成电路 |
| 文件： | 总35页 (文件大小：669K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
K9K2G08U0A
FLASH MEMORY
Document Title
256M x 8 Bit NAND Flash Memory
Revision History
Revision No History
Draft Date
Remark
0.0
1. Initial issue
May. 31. 2004
Advance
The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the
right to change the specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions about device. If you
have any questions, please contact the SAMSUNG branch office near your office.
1
K9K2G08U0A
FLASH MEMORY
256M x 8 Bit NAND Flash Memory
PRODUCT LIST
Part Number
Vcc Range
2.7 ~ 3.6V
2.7 ~ 3.6V
Organization
PKG Type
TSOP1
K9K2G08U0A-Y,P
K9K2G08U0A-V,F
X8
X8
WSOP1
FEATURES
· Voltage Supply
· Fast Write Cycle Time
-3.3V device(K9K2G08U0A): 2.7 V ~3.6 V
· Organization
- Program time : 300ms(Typ.)
- Block Erase Time : 2ms(Typ.)
- Memory Cell Array
-X8 device(K9K2G08U0A) : (256M + 8,192K)bit x 8bit
- Data Register
-X8 device(K9K2G08U0A): (2K + 64)bit x8bit
- Cache Register
-X8 device(K9K2G08U0A) : (2K + 64)bit x8bit
· Automatic Program and Erase
- Page Program
-X8 device(K9K2G08U0A) : (2K + 64)Byte
- Block Erase
-X8 device(K9K2G08U0A) : (128K + 4K)Byte
· Page Read Operation
· Command/Address/Data Multiplexed I/O Port
· Hardware Data Protection
- Program/Erase Lockout During Power Transitions
· Reliable CMOS Floating-Gate Technology
- Endurance : 100K Program/Erase Cycles
- Data Retention : 10 Years
· Command Register Operation
· Cache Program Operation for High Performance Program
· Intelligent Copy-Back Operation
· Unique ID for Copyright Protection
· Package :
- K9K2G08U0A-YCB0/YIB0
- Page Size
48 - Pin TSOP I (12 x 20 / 0.5 mm pitch)
- K9K2G08U0A-VIB0
48 - Pin WSOP I (12X17X0.7mm)
- X8 device(K9K2G08U0A) : 2K-Byte
- Random Read : 25ms(Max.)
- Serial Access : 30ns(Min.)
- K9K2G08U0A-PCB0/PIB0
48 - Pin TSOP I (12 x 20 / 0.5 mm pitch)- Pb-free Package
- K9K2G08U0A-FIB0
48 - Pin WSOP I (12X17X0.7mm)- Pb-free Package
* K9K2G08U0A-V,F(WSOPI ) is the same device as
K9K2G08U0A-Y,P(TSOP1) except package type.
GENERAL DESCRIPTION
Offered in 256Mx8bit the K9K2G08U0A is 2G bit with spare 64M bit capacity. Its NAND cell provides the most cost-effective solution
for the solid state mass storage market. A program operation can be performed in typical 300ms on the 2112byte page and an erase
operation can be performed in typical 2ms on a 128K-byte block. Data in the data page can be read out at 30ns cycle time per byte.
The I/O pins serve as the ports for address and data input/output as well as command input. The on-chip write controller automates
all program and erase functions including pulse repetition, where required, and internal verification and margining of data. Even the
write-intensive systems can take advantage of the K9K2G08U0A¢s extended reliability of 100K program/erase cycles by providing
ECC(Error Correcting Code) with real time mapping-out algorithm. The K9K2G08U0A is an optimum solution for large nonvolatile
storage applications such as solid state file storage and other portable applications requiring non-volatility.
2
K9K2G08U0A
FLASH MEMORY
PIN CONFIGURATION (TSOP1)
K9K2G08U0A-YCB0,PCB0/YIB0,PIB0
X8
X8
N.C
N.C
N.C
N.C
I/O7
I/O6
I/O5
I/O4
N.C
N.C
N.C
Vcc
Vss
N.C
N.C
N.C
I/O3
I/O2
I/O1
I/O0
N.C
N.C
N.C
N.C
N.C
N.C
N.C
N.C
N.C
N.C
R/B
RE
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
1
2
3
4
5
6
7
8
CE
9
N.C
N.C
Vcc
Vss
N.C
N.C
CLE
ALE
WE
WP
N.C
N.C
N.C
N.C
N.C
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48-pin TSOP1
Standard Type
12mm x 20mm
PACKAGE DIMENSIONS
48-PIN LEAD/LEAD FREE PLASTIC THIN SMALL OUT-LINE PACKAGE TYPE(I)
48 - TSOP1 - 1220AF
Unit :mm/Inch
20.00±0.20
0.787±0.008
#1
#48
#24
#25
1.00±0.05
0.039±0.002
0.05
0.002
MIN
1.20
0.047
MAX
18.40±0.10
0.724±0.004
0~8°
0.45~0.75
0.018~0.030
0.50
0.020
(
)
3
K9K2G08U0A
FLASH MEMORY
PIN CONFIGURATION (WSOP1)
K9K2G08U0A-VIB0,FIB0
N.C
N.C
DNU
N.C
I/O7
I/O6
I/O5
I/O4
N.C
DNU
N.C
Vcc
N.C
N.C
DNU
N.C
N.C
N.C
R/B
RE
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
1
2
3
4
5
6
7
8
CE
9
DNU
N.C
Vcc
Vss
N.C
DNU
CLE
ALE
WE
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
Vss
N.C
DNU
N.C
I/O3
I/O2
I/O1
I/O0
N.C
DNU
N.C
N.C
WP
N.C
N.C
DNU
N.C
N.C
PACKAGE DIMENSIONS
48-PIN LEAD PLASTIC VERY VERY THIN SMALL OUT-LINE PACKAGE TYPE (I)
Unit :mm
48 - WSOP1 - 1217F
0.70 MAX
0.58±0.04
15.40±0.10
#1
#48
#24
#25
(0.01Min)
0.45~0.75
17.00±0.20
4
K9K2G08U0A
FLASH MEMORY
PIN DESCRIPTION
Pin Name
Pin Function
DATA INPUTS/OUTPUTS
I/O0 ~ I/O7
The I/O pins are used to input command, address and data, and to output data during read operations. The I/
O pins float to high-z when the chip is deselected or when the outputs are disabled.
(K9K2G08U0A)
COMMAND LATCH ENABLE
CLE
ALE
The CLE input controls the activating path for commands sent to the command register. When active high,
commands are latched into the command register through the I/O ports on the rising edge of the WE signal.
ADDRESS LATCH ENABLE
The ALE input controls the activating path for address to the internal address registers. Addresses are
latched on the rising edge of WE with ALE high.
CHIP ENABLE
The CE input is the device selection control. When the device is in the Busy state, CE high is ignored, and
the device does not return to standby mode in program or erase opertion. Regarding CE control during read
operation, refer to ’Page read’ section of Device operation .
CE
READ ENABLE
RE
WE
WP
The RE input is the serial data-out control, and when active drives the data onto the I/O bus. Data is valid
tREA after the falling edge of RE which also increments the internal column address counter by one.
WRITE ENABLE
The WE input controls writes to the I/O port. Commands, address and data are latched on the rising edge of
the WE pulse.
WRITE PROTECT
The WP pin provides inadvertent write/erase protection during power transitions. The internal high voltage
generator is reset when the WP pin is active low.
READY/BUSY OUTPUT
The R/B output indicates the status of the device operation. When low, it indicates that a program, erase or
random read operation is in process and returns to high state upon completion. It is an open drain output and
does not float to high-z condition when the chip is deselected or when outputs are disabled.
R/B
POWER
Vcc
Vss
N.C
VCC is the power supply for device.
GROUND
NO CONNECTION
Lead is not internally connected.
NOTE: Connect all VCC and VSS pins of each device to common power supply outputs.
Do not leave VCC or VSS disconnected.
5
K9K2G08U0A
FLASH MEMORY
Figure 1-1. K9K2G08U0A (X8) Functional Block Diagram
VCC
VSS
2048M + 64M Bit
NAND Flash
ARRAY
X-Buffers
Latches
& Decoders
A12 - A28
A0 - A11
(2048 + 64)Byte x 131072
Data Register & S/A
Y-Buffers
Latches
& Decoders
Cache Register
Y-Gating
Command
Command
Register
VCC
VSS
I/O Buffers & Latches
Global Buffers
CE
RE
WE
Control Logic
& High Voltage
Generator
I/0 0
Output
Driver
I/0 7
CLE ALE
WP
Figure 2-1. K9K2G08U0A (X8) Array Organization
1 Block = 64 Pages
(128K + 4k) Byte
1 Page = (2K + 64)Bytes
1 Block = (2K + 64)B x 64 Pages
= (128K + 4K) Bytes
1 Device = (2K+64)B x 64Pages x 2048 Blocks
= 2112 Mbits
128K Pages
(=2,048 Blocks)
8 bit
2K Bytes
64 Bytes
64 Bytes
I/O 0 ~ I/O 7
Page Register
2K Bytes
I/O 0
A0
I/O 1
A1
I/O 2
I/O 3
A3
I/O 4
A4
I/O 5
A5
I/O 6
A6
I/O 7
A7
Column Address
Column Address
Row Address
1st Cycle
2nd Cycle
3rd Cycle
4th Cycle
5th Cycle
A2
A10
A14
A22
*L
A8
A9
A11
A15
A23
*L
*L
*L
*L
*L
A12
A20
A28
A13
A21
*L
A16
A24
*L
A17
A25
*L
A18
A26
*L
A19
A27
*L
Row Address
Row Address
NOTE : Column Address : Starting Address of the Register.
* L must be set to "Low".
* The device ignores any additional input of address cycles than reguired.
6
K9K2G08U0A
FLASH MEMORY
Product Introduction
The K9K2G08U0A is a 2112Mbit(2,214,592,512 bit) memory organized as 131,072 rows(pages) by 2112x8 columns. Spare 64 col-
umns are located from column address of 2048~2111. A 2112-byte data register and a 2112-byte cache register are serially con-
nected to each other. Those serially connected registers are connected to memory cell arrays for accommodating data transfer
between the I/O buffers and memory cells during page read and page program operations. The memory array is made up of 32 cells
that are serially connected to form a NAND structure. Each of the 32 cells resides in a different page. A block consists of two NAND
structures. A NAND structure consists of 32 cells. Total 135168 NAND cells reside in a block. The program and read operations are
executed on a page basis, while the erase operation is executed on a block basis. The memory array consists of 2048 separately
erasable 128K-byte blocks. It indicates that the bit by bit erase operation is prohibited on the K9K2G08U0A.
The K9K2G08U0A has addresses multiplexed into 8 I/Os. This scheme dramatically reduces pin counts and allows system upgrades
to future densities by maintaining consistency in system board design. Command, address and data are all written through I/O's by
bringing WE to low while CE is low. Those are latched on the rising edge of WE. Command Latch Enable(CLE) and Address Latch
Enable(ALE) are used to multiplex command and address respectively, via the I/O pins. Some commands require one bus cycle. For
example, Reset Command, Status Read Command, etc require just one cycle bus. Some other commands, like page read and block
erase and page program, require two cycles: one cycle for setup and the other cycle for execution. The 256M byte physical space
requires 29 addresses, thereby requiring five cycles for addressing: 2 cycles of column address, 3 cycles of row address, in that
order. Page Read and Page Program need the same five address cycles following the required command input. In Block Erase oper-
ation, however, only the three row address cycles are used. Device operations are selected by writing specific commands into the
command register. Table 1 defines the specific commands of the K9K2G08U0A.
The device provides cache program in a block. It is possible to write data into the cache registers while data stored in data registers
are being programmed into memory cells in cache program mode. The program performace may be dramatically improved by cache
program when there are lots of pages of data to be programmed.
In addition to the enhanced architecture and interface, the device incorporates copy-back program feature from one page to another
page without need for transporting the data to and from the external buffer memory. Since the time-consuming serial access and
data-input cycles are removed, system performance for solid-state disk application is significantly increased.
Table 1. Command Sets
Function
1st. Cycle
00h
2nd. Cycle
Acceptable Command during Busy
Read
30h
35h
-
Read for Copy Back
Read ID
00h
90h
Reset
FFh
80h
-
O
Page Program
Cache Program
Copy-Back Program
Block Erase
10h
15h
10h
D0h
-
80h
85h
60h
Random Data Input*
Random Data Output*
Read Status
85h
05h
E0h
70h
O
NOTE : 1. Random Data Input/Output can be executed in a page.
Caution : Any undefined command inputs are prohibited except for above command set of Table 1.
7
K9K2G08U0A
FLASH MEMORY
ABSOLUTE MAXIMUM RATINGS
Rating
Unit
K9K2G08U0A(3.3V)
Parameter
Symbol
VIN/OUT
VCC
-0.6 to + 4.6
V
-0.6 to + 4.6
Voltage on any pin relative to VSS
K9K2G08U0A-YCB0
-10 to +125
°C
Temperature Under Bias
Storage Temperature
TBIAS
K9K2G08U0A-XIB0
K9K2G08U0A-YCB0
K9K2G08U0A-XIB0
-40 to +125
-65 to +150
TSTG
Ios
°C
Short Circuit Current
5
mA
NOTE :
1. Minimum DC voltage is -0.6V on input/output pins. During transitions, this level may undershoot to -2.0V for periods <30ns.
Maximum DC voltage on input/output pins is VCC,+0.3V which, during transitions, may overshoot to VCC+2.0V for periods <20ns.
2. Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to the conditions
as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
RECOMMENDED OPERATING CONDITIONS
(Voltage reference to GND, K9K2G08U0A-YCB0 :TA=0 to 70°C, K9K2G08U0A-XIB0:TA=-40 to 85°C)
K9K2G08U0A(3.3V)
Parameter
Symbol
Unit
Min
2.7
0
Typ.
3.3
0
Max
3.6
0
Supply Voltage
Supply Voltage
VCC
VSS
V
V
DC AND OPERATING CHARACTERISTICS(Recommended operating conditions otherwise noted.)
K9K2G08U0A(3.3V)
Unit
Parameter
Symbol
Test Conditions
Min
Typ
Max
Page Read with Serial
Access
tRC=30ns, CE=VIL
IOUT=0mA
ICC1
-
10
30
Operating
Current
Program
Erase
ICC2
ICC3
ISB1
-
-
-
-
-
10
10
-
30
30
1
mA
Stand-by Current(TTL)
CE=VIH, WP=0V/VCC
CE=VCC-0.2,
WP=0V/VCC
Stand-by Current(CMOS)
ISB2
-
20
100
mA
Input Leakage Current
Output Leakage Current
Input High Voltage
ILI
ILO
VIN=0 to Vcc(max)
VOUT=0 to Vcc(max)
-
-
-
-
±10
-
±10
VIH
0.8xVcc
-
Vcc+0.3
Input Low Voltage, All inputs
Output High Voltage Level
Output Low Voltage Level
Output Low Current(R/B)
VIL
-
-0.3
2.4
-
-
0.2xVcc
V
VOH
VOL
K9K2G08U0A :IOH=-400mA
K9K2G08U0A :IOL=2.1mA
K9K2G08U0A :VOL=0.4V
-
-
0.4
-
-
IOL(R/B)
8
10
mA
8
K9K2G08U0A
FLASH MEMORY
VALID BLOCK
Parameter
Symbol
Min
Typ.
Max
Unit
Valid Block Number
NVB
2008
-
2048
Blocks
NOTE :
1. The K9K2G08U0A may include invalid blocks when first shipped. Additional invalid blocks may develop while being used. The number of valid
blocks is presented with both cases of invalid blocks considered. Invalid blocks are defined as blocks that contain one or more bad bits. Do not erase
or program factory-marked bad blocks. Refer to the attached technical notes for appropriate management of invalid blocks.
2. The 1st block, which is placed on 00h block address, is fully guaranteed to be a valid block and does not require Error Correction.
AC TEST CONDITION
(K9K2G08U0A-YCB0 :TA=0 to 70°C, K9K2G08U0A-XIB0:TA=-40 to 85°C
K9K2G08U0A : Vcc=2.7V~3.6V unless otherwise noted)
Parameter
K9K2G08U0A
Input Pulse Levels
0V to Vcc
Input Rise and Fall Times
Input and Output Timing Levels
5ns
Vcc/2
K9K2G08U0A:Output Load (Vcc:3.0V +/-10%)
1 TTL GATE and CL=50pF
CAPACITANCE(TA=25°C, VCC=3.3V, f=1.0MHz)
Item
Symbol
Test Condition
Min
Max
10
Unit
pF
Input/Output Capacitance
Input Capacitance
CI/O
VIL=0V
-
-
CIN
VIN=0V
10
pF
NOTE : Capacitance is periodically sampled and not 100% tested.
MODE SELECTION
CLE
H
L
ALE
L
CE
L
WE
RE
H
WP
Mode
X
Command Input
Read Mode
H
L
H
X
Address Input(5clock)
Command Input
H
L
L
L
H
H
Write Mode
H
L
H
H
Address Input(5clock)
L
L
L
H
H
Data Input
L
L
L
H
X
X
X
X
X
X
Data Output
X
X
X
X
X
X
H
H
X
X
X
X
X
During Read(Busy)
During Program(Busy)
During Erase(Busy)
Write Protect
X
X
H
X
X
H
L
X(1)
X
X
(2)
X
Stand-by
0V/VCC
NOTE : 1. X can be VIL or VIH.
2. WP should be biased to CMOS high or CMOS low for standby.
Program / Erase Characteristics
Parameter
Symbol
Min
Typ
Max
700
700
4
Unit
ms
Program Time
tPROG
tCBSY
-
300
Dummy Busy Time for Cache Program
3
-
ms
Main Array
-
-
-
cycles
cycles
ms
Number of Partial Program Cycles
in the Same Page
Nop
Spare Array
-
4
Block Erase Time
tBERS
2
3
NOTE : 1. Max. time of tCBSY depends on timing between internal program completion and data in
9
K9K2G08U0A
FLASH MEMORY
AC Timing Characteristics for Command / Address / Data Input
Parameter
Symbol
tCLS
tCLH
tCS
Min
10
5
Max
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
-
CLE setup Time
CLE Hold Time
CE setup Time
CE Hold Time
-
-
15
5
-
tCH
-
WE Pulse Width
ALE setup Time
ALE Hold Time
Data setup Time
Data Hold Time
Write Cycle Time
tWP
15
10
5
-
tALS
tALH
tDS
-
-
10
5
-
tDH
-
tWC
30
10
100(1)
-
-
WE High Hold Time
tWH
100(1)
ALE to Data Loading Time
tADL
NOTE : 1. tADL is the time from the WE rising edge of final address cycle to the WE rising edge of first data cycle.
AC Characteristics for Operation
Parameter
Data Transfer from Cell to Register
ALE to RE Delay
Symbol
tR
Min
-
Max
Unit
25
ms
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
tAR
10
10
20
15
-
-
CLE to RE Delay
tCLR
tRR
-
Ready to RE Low
-
RE Pulse Width
tRP
-
WE High to Busy
tWB
100
Read Cycle Time
tRC
30
-
-
RE Access Time
tREA
tCEA
tRHZ
tCHZ
tOH
18
CE Access Time
-
23
RE High to Output Hi-Z
CE High to Output Hi-Z
RE or CE High to Output hold
RE High Hold Time
-
30
-
20
15
10
0
-
tREH
tIR
-
Output Hi-Z to RE Low
WE High to RE Low
-
tWHR
tRST
60
-
-
5/10/500(1)
Device Resetting Time(Read/Program/Erase)
NOTE: 1. If reset command(FFh) is written at Ready state, the device goes into Busy for maximum 5us.
10
K9K2G08U0A
FLASH MEMORY
NAND Flash Technical Notes
Invalid Block(s)
Invalid blocks are defined as blocks that contain one or more invalid bits whose reliability is not guaranteed by Samsung. The infor-
mation regarding the invalid block(s) is so called as the invalid block information. Devices with invalid block(s) have the same quality
level as devices with all valid blocks and have the same AC and DC characteristics. An invalid block(s) does not affect the perfor-
mance of valid block(s) because it is isolated from the bit line and the common source line by a select transistor. The system design
must be able to mask out the invalid block(s) via address mapping. The 1st block, which is placed on 00h block address, is fully guar-
anteed to be a valid block, does not require Error Correction.
Identifying Invalid Block(s)
All device locations are erased(FFh for x8) except locations where the invalid block(s) information is written prior to shipping. The
invalid block(s) status is defined by the 1st byte in the spare area. Samsung makes sure that either the 1st or 2nd page of every
invalid block has non-FFh data at the column address of 2048. Since the invalid block information is also erasable in most cases, it
is impossible to recover the information once it has been erased. Therefore, the system must be able to recognize the invalid
block(s) based on the original invalid block information and create the invalid block table via the following suggested flow chart(Fig-
ure 3). Any intentional erasure of the original invalid block information is prohibited.
Start
Set Block Address = 0
Increment Block Address
Check "FFh" at the column address
2048 of the 1st and 2nd page in the block
*
No
Create (or update)
Invalid Block(s) Table
Check "FFh ?
Yes
No
Last Block ?
Yes
End
Figure 3. Flow chart to create invalid block table.
11
K9K2G08U0A
FLASH MEMORY
NAND Flash Technical Notes (Continued)
Error in write or read operation
Within its life time, additional invalid blocks may develop with NAND Flash memory. Refer to the qualification report for the actual
data.The following possible failure modes should be considered to implement a highly reliable system. In the case of status read fail-
ure after erase or program, block replacement should be done. Because program status fail during a page program does not affect
the data of the other pages in the same block, block replacement can be executed with a page-sized buffer by finding an erased
empty block and reprogramming the current target data and copying the rest of the replaced block.To improve the efficiency of mem-
ory space, it is recommended that the read or verification failure due to single bit error be reclaimed by ECC without any block
replacement. The said additional block failure rate does not include those reclaimed blocks.
Failure Mode
Detection and Countermeasure sequence
Erase Failure
Status Read after Erase --> Block Replacement
Status Read after Program --> Block Replacement
Read back ( Verify after Program) --> Block Replacement
or ECC Correction
Write
Read
Program Failure
Single Bit Failure
Verify ECC -> ECC Correction
: Error Correcting Code --> Hamming Code etc.
Example) 1bit correction & 2bit detection
ECC
Program Flow Chart
If ECC is used, this verification
operation is not needed.
Start
Write 80h
Write 00h
Write Address
Write 30h
Write Address
Write Data
Write 10h
Wait for tR Time
*
Fail
Read Status Register
Program Error
Verify Data
No
Pass
I/O 6 = 1 ?
or R/B = 1 ?
Program Completed
Yes
*
No
: If program operation results in an error, map out
the block including the page in error and copy the
target data to another block.
Program Error
I/O 0 = 0 ?
*
Yes
12
K9K2G08U0A
FLASH MEMORY
NAND Flash Technical Notes (Continued)
Erase Flow Chart
Read Flow Chart
Start
Write 00h
Start
Write 60h
Write Block Address
Write Address
Write 30h
Write D0h
Read Data
Read Status Register
ECC Generation
No
I/O 6 = 1 ?
or R/B = 1 ?
No
Verify ECC
Reclaim the Error
Yes
*
No
Yes
Erase Error
I/O 0 = 0 ?
Page Read Completed
Yes
Erase Completed
: If erase operation results in an error, map out
the failing block and replace it with another block.
*
Block Replacement
Block A
1st
{
(n-1)th
1
nth
an error occurs.
(page)
Buffer memory of the controller.
Block B
1st
2
{
(n-1)th
nth
(page)
* Step1
When an error happens in the nth page of the Block ’A’ during erase or program operation.
* Step2
Copy the data in the 1st ~ (n-1)th page to the same location of another free block. (Block ’B’)
* Step3
Then, copy the nth page data of the Block ’A’ in the buffer memory to the nth page of the Block ’B’.
* Step4
Do not erase or program to Block ’A’ by creating an ’invalid Block’ table or other appropriate scheme.
13
K9K2G08U0A
FLASH MEMORY
NAND Flash Technical Notes (Continued)
Addressing for program operation
Within a block, the pages must be programmed consecutively from the LSB (least significant bit) page of the block to MSB (most sig-
nificant bit) pages of the block. Random page address programming is prohibited.
(64)
(64)
Page 63
Page 31
Page 63
Page 31
:
:
(1)
:
(32)
:
(3)
(2)
(1)
Page 2
Page 1
Page 0
(3)
(32)
(2)
Page 2
Page 1
Page 0
Data register
Data register
From the LSB page to MSB page
DATA IN: Data (1)
Data (64)
Ex.) Random page program (Prohibition)
DATA IN: Data (1)
Data (64)
14
K9K2G08U0A
FLASH MEMORY
System Interface Using CE don’t-care.
For an easier system interface, CE may be inactive during the data-loading or serial access as shown below. The internal 2112byte
data registers are utilized as separate buffers for this operation and the system design gets more flexible. In addition, for voice or
audio applications which use slow cycle time on the order of u-seconds, de-activating CE during the data-loading and serial access
would provide significant savings in power consumption.
Figure 4. Program Operation with CE don’t-care.
CLE
CE don’t-care
CE
WE
ALE
I/Ox
Address(5Cycles)
80h
Data Input
Data Input
10h
tCH
tCEA
tCS
CE
RE
CE
tREA
tWP
WE
out
I/O0~7
Figure 5. Read Operation with CE don’t-care.
CLE
CE
CE don’t-care
RE
ALE
tR
R/B
WE
I/Ox
Data Output(serial access)
00h
Address(5Cycle)
30h
15
K9K2G08U0A
FLASH MEMORY
NOTE
I/O
I/Ox
DATA
ADDRESS
Device
Data In/Out
~2112byte
Col. Add1
Col. Add2
Row Add1
Row Add2
Row Add3
K9K2G08U0A
I/O 0 ~ I/O 7
A0~A7
A8~A11
A12~A19
A20~A27
A28
Command Latch Cycle
CLE
tCLS
tCS
tCLH
tCH
CE
tWP
WE
tALS
tALH
ALE
I/Ox
tDH
tDS
Command
Address Latch Cycle
tCLS
tCS
CLE
tWC
tWC
tWC
CE
tWP
tWP
tWP
tWP
WE
tWH
tWH
tWH
tALH
tDH
tALH
tALS
tALH
tALS
tALH
tALS
tALS
ALE
I/Ox
tDH
tDH
tDH
tDS
tDS
tDS
tDS
Col. Add2
Row Add1
Col. Add1
Row Add2
16
K9K2G08U0A
FLASH MEMORY
Input Data Latch Cycle
tCLH
CLE
CE
tCH
tALS
ALE
tWC
tWP
tWP
tWP
WE
tWH
tDH
tDH
tDH
tDS
tDS
tDS
I/Ox
DIN final*
DIN 0
DIN 1
NOTES : DIN final means 2112
Serial Access Cycle after Read(CLE=L, WE=H, ALE=L)
tCEA
CE
tCHZ*
tOH
tREH
tREA
tREA
tREA
RE
tRHZ*
tRHZ*
tOH
I/Ox
Dout
Dout
Dout
tRC
tRR
R/B
NOTES : Transition is measured ±200mV from steady state voltage with load.
This parameter is sampled and not 100% tested.
17
K9K2G08U0A
FLASH MEMORY
Status Read Cycle
tCLR
CLE
CE
tCLS
tCS
tCLH
tCH
tWP
WE
tCEA
tCHZ*
tOH
tWHR
RE
tRHZ*
tOH
tDH
tREA
tDS
tIR*
I/Ox
Status Output
70h
18
K9K2G08U0A
FLASH MEMORY
Read Operation
tCLR
CLE
CE
tWC
WE
ALE
RE
tWB
tAR
tRHZ
tR
tRC
tRR
Col. Add2 Row Add1 Row Add2
00h
Col. Add1
30h
Dout N
Dout N+1
Dout M
Row Add3
I/Ox
Column Address
Row Address
Busy
R/B
Read Operation(Intercepted by CE)
CLE
CE
WE
ALE
RE
tWB
tCHZ
tOH
tAR
tR
tRC
tRR
Row Add1 Row Add2 Row Add3
Dout N+2
00h
Col. Add1 Col. Add2
30h
Dout N
Dout N+1
I/Ox
R/B
Row Address
Column Address
Busy
19
K9K2G08U0A
FLASH MEMORY
20
K9K2G08U0A
FLASH MEMORY
Page Program Operation
CLE
CE
tWC
tWC
tWC
WE
ALE
RE
tPROG
tWB
tADL
Din
N
Din
M
Co.l Add1 Col. Add2 Row Add1 Row Add2 Row Add3
80h
I/Ox
R/B
10h
70h
I/O0
SerialData
Input Command
Program
Command
1 up to m Byte
Serial Input
Read Status
Command
Column Address
Row Address
I/O
0
=0 Successful Program
I/O0
=1 Error in Program
m = 2112byte
NOTES : tADL is the time from the WE rising edge of final address cycle to the WE rising edge of first data cycle.
21
K9K2G08U0A
FLASH MEMORY
»
» »
»
» »
»
22
K9K2G08U0A
FLASH MEMORY
»
» »
»
23
K9K2G08U0A
FLASH MEMORY
»
» »
» »
24
»
»
»
K9K2G08U0A
FLASH MEMORY
BLOCK ERASE OPERATION
CLE
CE
tWC
WE
tBERS
tWB
ALE
RE
I/Ox
Row Add1 Row Add2 Row Add3
60h
D0h
70h
I/O 0
Row Address
Busy
R/B
Auto Block Erase
Setup Command
Erase Command
I/O
0
=0 Successful Erase
Read Status I/O
Command
0=1 Error in Erase
25
K9K2G08U0A
FLASH MEMORY
Read ID Operation
CLE
CE
WE
ALE
RE
tAR
tREA
Device
Code*
I/Ox
4th cyc.*
00h
ECh
XXh
90h
Read ID Command
Maker Code Device Code
Address. 1cycle
Device
Device Code*(2nd Cycle)
DAh
4th Cycle*
15h
K9K2G08U0A
ID Defintition Table
90 ID : Access command = 90H
Description
1st Byte
2nd Byte
3rd Byte
4th Byte
Maker Code
Device Code
Don’t care
Page Size, Block Size, Spare Size, Organization
26
K9K2G08U0A
4th ID Data
FLASH MEMORY
Description
1KB
2KB
Reserved
Reserved
I/O7
I/O6
I/O5 I/O4
I/O3
I/O2
I/O1 I/O0
0
0
1
1
0
1
0
1
Page Size
(w/o redundant area )
64KB
0
0
1
1
0
1
0
1
Blcok Size
(w/o redundant area )
128KB
256KB
Reserved
Redundant Area Size
( byte/512byte)
8
16
0
1
x8
x16
0
1
Organization
50ns / 30ns
25ns
Reserved
Reserved
0
1
0
1
0
0
1
1
Serial AccessMinimum
27
K9K2G08U0A
FLASH MEMORY
Device Operation
PAGE READ
Page read is initiated by writing 00h-30h to the command register along with five address cycles. After initial power up, 00h command
is latched. Therefore only five address cycles and 30h command initiates that operation after initial power up. The 2112 bytes of data
within the selected page are transferred to the data registers in less than 25ms(tR). The system controller can detect the completion of
this data transfer(tR) by analyzing the output of R/B pin. Once the data in a page is loaded into the data registers, they may be read
out in 30ns cycle time by sequentially pulsing RE. The repetitive high to low transitions of the RE clock make the device output the
data starting from the selected column address up to the last column address.
The device may output random data in a page instead of the consecutive sequential data by writing random data output command.
The column address of next data, which is going to be out, may be changed to the address which follows random data output com-
mand. Random data output can be operated multiple times regardless of how many times it is done in a page.
Figure 6. Read Operation
CLE
CE
WE
ALE
tR
R/B
RE
I/Ox
00h
Address(5Cycle)
30h
Data Output(Serial Access)
Col Add1,2 & Row Add1,2,3
Data Field
Spare Field
28
K9K2G08U0A
FLASH MEMORY
Figure 7. Random Data Output In a Page
tR
R/B
RE
Address
5Cycles
Address
2Cycles
Data Output
Data Output
E0h
I/Ox
00h
30h
05h
Col Add1,2 & Row Add1,2,3
Data Field
Data Field
Spare Field
Spare Field
PAGE PROGRAM
The device is programmed basically on a page basis, but it does allow multiple partial page programing of a word or consecutive
bytes up to 2112, in a single page program cycle. The number of consecutive partial page programming operation within the same
page without an intervening erase operation must not exceed 4 times for main array(1time/512byte) and 4 times for spare array(
1time/16byte). The addressing should be done in sequential order in a block. A page program cycle consists of a serial data loading
period in which up to 2112bytes of data may be loaded into the data register, followed by a non-volatile programming period where
the loaded data is programmed into the appropriate cell.
The serial data loading period begins by inputting the Serial Data Input command(80h), followed by the five cycle address inputs and
then serial data loading. The words other than those to be programmed do not need to be loaded. The device supports random data
input in a page. The column address for the next data, which will be entered, may be changed to the address which follows random
data input command(85h). Random data input may be operated multiple times regardless of how many times it is done in a page.
The Page Program confirm command(10h) initiates the programming process. Writing 10h alone without previously entering the serial
data will not initiate the programming process. The internal write state controller automatically executes the algorithms and timings
necessary for program and verify, thereby freeing the system controller for other tasks. Once the program process starts, the Read
Status Register command may be entered to read the status register. The system controller can detect the completion of a program
cycle by monitoring the R/B output, or the Status bit(I/O 6) of the Status Register. Only the Read Status command and Reset com-
mand are valid while programming is in progress. When the Page Program is complete, the Write Status Bit(I/O 0) may be
checked(Figure 8). The internal write verify detects only errors for "1"s that are not successfully programmed to "0"s. The command
register remains in Read Status command mode until another valid command is written to the command register.
Figure 8. Program & Read Status Operation
tPROG
R/B
"0"
Pass
80h
Address & Data Input
I/O0
Fail
I/Ox
10h
70h
Col Add1,2 & Row Add1,2,3
Data
"1"
29
K9K2G08U0A
FLASH MEMORY
Figure 9. Random Data Input In a Page
tPROG
R/B
"0"
Pass
80h
Address & Data Input
Address & Data Input
I/O0
Fail
I/Ox
85h
10h
70h
Col Add1,2
Data
Col Add1,2 & Row Add1,2,3
Data
"1"
Cache Program
Cache Program is an extension of Page Program, which is executed with 2112byte data registers, and is available only within a block.
Since the device has 1 page of cache memory, serial data input may be executed while data stored in data register are programmed
into memory cell.
After writing the first set of data up to 2112byte into the selected cache registers, Cache Program command (15h) instead of actual
Page Program (10h) is inputted to make cache registers free and to start internal program operation. To transfer data from cache reg-
isters to data registers, the device remains in Busy state for a short period of time(tCBSY) and has its cache registers ready for the
next data-input while the internal programming gets started with the data loaded into data registers. Read Status command (70h) may
be issued to find out when cache registers become ready by polling the Cache-Busy status bit(I/O 6). Pass/fail status of only the pre-
viouse page is available upon the return to Ready state. When the next set of data is inputted with the Cache Program command,
tCBSY is affected by the progress of pending internal programming. The programming of the cache registers is initiated only when the
pending program cycle is finished and the data registers are available for the transfer of data from cache registers. The status bit(I/
O5) for internal Ready/Busy may be polled to identify the completion of internal programming. If the system monitors the progress of
programming only with R/B, the last page of the target programming sequence must be progammed with actual Page Program com-
mand (10h). If the Cache Program command (15h) is used instead, status bit (I/O5) must be polled to find out when the last program-
ming is actually finished before starting other operations such as read. Pass/fail status is available in two steps. I/O 1 returns with the
status of the previous page upon Ready or I/O6 status bit changing to "1", and later I/O 0 with the status of current page upon true
Ready (returning from internal programming) or I/O 5 status bit changing to "1". I/O 1 may be read together when I/O 0 is checked.
Figure 10. Cache Program(available only within a block)
tPROG
tCBSY
tCBSY
tCBSY
R/B
Address &
Data Input
Address &
Data Input
Address &
Data Input*
Address &
Data Input
80h
70h
10h
80h
15h
80h
80h
15h
15h
Col Add1,2 & Row Add1,2,3
Data
Col Add1,2 & Row Add1,2,3
Data
Col Add1,2 & Row Add1,2,3
Data
Col Add1,2 & Row Add1,2,3
Data
tCBSY
tCBSY
tCBSY
R/B
I/Ox
Address &
Data Input
Status
output
Address &
Data Input
Status
output
Address &
Data Input
80h
80h
80h
15h
70h
15h
70h
15h
Col Add1,2 & Row Add1,2,3
Data
Col Add1,2 & Row Add1,2,3
Data
Col Add1,2 & Row Add1,2,3
Data
tCBSY
Address &
Data Input
Status
Status
output
Status
output
80h
70h
70h
15h
output
Col Add1,2 & Row Add1,2,3
Data
Check I/O1 for pass/fail
Check I/O5 for internal ready/busy
Check I/O0,1 for pass/fail
30
K9K2G08U0A
FLASH MEMORY
NOTE : Since programming the last page does not employ caching, the program time has to be that of Page Program. However, if the
previous program cycle with the cache data has not finished, the actual program cycle of the last page is initiated only after comple-
tion of the previous cycle, which can be expressed as the following formula.
tPROG= Program time for the last page+ Program time for the ( last -1 )th page
- (Program command cycle time + Last page data loading time)
Copy-Back Program
The copy-back program is configured to quickly and efficiently rewrite data stored in one page without utilizing an external memory.
Since the time-consuming cycles of serial access and re-loading cycles are removed, the system performance is improved. The ben-
efit is especially obvious when a portion of a block is updated and the rest of the block also need to be copied to the newly assigned
free block. The operation for performing a copy-back program is a sequential execution of page-read without serial access and copy-
ing-program with the address of destination page. A read operation with "35h" command and the address of the source page moves
the whole 2112byte data into the internal data buffer. As soon as the device returns to Ready state, Page-Copy Data-input command
(85h) with the address cycles of destination page followed may be written. The Program Confirm command (10h) is required to actu-
ally begin the programming operation. Copy-Back Program operation is allowed only within the same memory plane. Once the Copy-
Back Program is finished, any additional partial page programming into the copied pages is prohibited before erase. A27 must be the
same between source and target page. Data input cycle for modifying a portion or multiple distant portions of the source page is
allowed as shown in Figure 11. "When there is a program-failure at Copy-Back operation, error is reported by pass/fail status. But, if
Copy-Back operations are accumulated over time, bit error due to charge loss is not checked by external error detection/correction
scheme. For this reason, two bit error correction is recommended for the use of Copy-Back operation."
Figure 11. Page Copy-Back program Operation
tR
tPROG
R/B
I/Ox
Add.(5Cycles)
Pass
00h
35h
Add.(5Cycles)
10h
I/O0
Fail
85h
70h
Col. Add1,2 & Row Add1,2,3
Destination Address
Col. Add1,2 & Row Add1,2,3
Source Address
Figure 12. Page Copy-Back program Operation with Random Data Input
tPROG
tR
R/B
Add.(5Cycles)
Add.(2Cycles)
Col Add1,2
I/Ox
35h
00h
Add.(5Cycles)
85h
70h
Data
85h
Data
10h
Col. Add1,2 & Row Add1,2,3
Source Address
Col. Add1,2 & Row Add1,2,3
Destination Address
There is no limitation for the number of repetition.
31
K9K2G08U0A
FLASH MEMORY
BLOCK ERASE
The Erase operation is done on a block basis. Block address loading is accomplished in three cycles initiated by an Erase Setup
command(60h). Only address A18 to A28 is valid while A12 to A17 is ignored. The Erase Confirm command(D0h) following the block
address loading initiates the internal erasing process. This two-step sequence of setup followed by execution command ensures that
memory contents are not accidentally erased due to external noise conditions.
At the rising edge of WE after the erase confirm command input, the internal write controller handles erase and erase-verify. When
the erase operation is completed, the Write Status Bit(I/O 0) may be checked. Figure 13 details the sequence.
Figure 13. Block Erase Operation
tBERS
R/B
"0"
Pass
60h
I/O0
Fail
70h
Address Input(3Cycle)
Row Add. : A12 ~ A28
I/Ox
D0h
"1"
READ STATUS
The device contains a Status Register which may be read to find out whether program or erase operation is completed, and whether
the program or erase operation is completed successfully. After writing 70h command to the command register, a read cycle outputs
the content of the Status Register to the I/O pins on the falling edge of CE or RE, whichever occurs last. This two line control allows
the system to poll the progress of each device in multiple memory connections even when R/B pins are common-wired. RE or CE
does not need to be toggled for updated status. Refer to table 2 for specific Status Register definitions. The command register
remains in Status Read mode until further commands are issued to it. Therefore, if the status register is read during a random read
cycle, the read command(00h) should be given before starting read cycles.
Table2. Read Staus Register Definition
I/O No.
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
Page Program
Pass/Fail
Block Erase
Pass/Fail
Not use
Cache Prorgam
Pass/Fail(N)
Pass/Fail(N-1)
Not use
Read
Not use
Definition
Pass : "0"
Fail : "1"
Fail : "1"
Not use
Not use
Pass : "0"
Not use
Not use
Not use
Don’t -cared
Don’t -cared
Don’t -cared
Busy : "0"
Not Use
Not Use
Not Use
Not Use
Not Use
Not Use
Not Use
Not Use
Ready/Busy
Ready/Busy
Write Protect
Ready/Busy
Ready/Busy
Write Protect
True Ready/Busy
Ready/Busy
Write Protect
Ready/Busy
Ready/Busy
Write Protect
Ready : "1"
Ready : "1"
Busy : "0"
Protected : "0"
Not Protected
NOTE : 1. True Ready/Busy represents internal program operation status which is being executed in cache program mode.
2. I/Os defined ’Not use’ are recommended to be masked out when Read Status is being executed.
32
K9K2G08U0A
Read ID
FLASH MEMORY
The device contains a product identification mode, initiated by writing 90h to the command register, followed by an address input of
00h. Five read cycles sequentially output the manufacturer code(ECh), and the device code and XXh, 4th cycle ID, 44h respectively.
The command register remains in Read ID mode until further commands are issued to it. Figure 14 shows the operation sequence.
Figure 14. Read ID Operation
tCLR
CLE
CE
tCEA
WE
ALE
RE
tAR1
tWHR
Device
Code*
tREA
I/OX
90h
00h
Address. 1cycle
ECh
XXh
4th Cyc.*
Maker code
Device code
Device
K9K2G08U0A
Device Code*(2nd Cycle)
DAh
4th Cycle*
15h
RESET
The device offers a reset feature, executed by writing FFh to the command register. When the device is in Busy state during random
read, program or erase mode, the reset operation will abort these operations. The contents of memory cells being altered are no
longer valid, as the data will be partially programmed or erased. The command register is cleared to wait for the next command, and
the Status Register is cleared to value C0h when WP is high. Refer to table 3 for device status after reset operation. If the device is
already in reset state a new reset command will be accepted by the command register. The R/B pin transitions to low for tRST after
the Reset command is written. Refer to Figure 15 below.
Figure 15. RESET Operation
tRST
R/B
I/OX
FFh
Table3. Device Status
After Power-up
After Reset
Operation Mode
00h command is latched
Waiting for next command
33
K9K2G08U0A
READY/BUSY
FLASH MEMORY
The device has a R/B output that provides a hardware method of indicating the completion of a page program, erase and random
read completion. The R/B pin is normally high but transitions to low after program or erase command is written to the command regis-
ter or random read is started after address loading. It returns to high when the internal controller has finished the operation. The pin is
an open-drain driver thereby allowing two or more R/B outputs to be Or-tied. Because pull-up resistor value is related to tr(R/B) and
current drain during busy(ibusy) , an appropriate value can be obtained with the following reference chart(Fig 17). Its value can be
determined by the following guidance.
Rp
ibusy
VCC
3.3V device - VOL : 0.4V, VOH : 2.4V
Ready Vcc
R/B
VOH
open drain output
CL
VOL
Busy
tf
tr
GND
Device
Figure 17. Rp vs tr ,tf & Rp vs ibusy
@ Vcc = 3.3V, Ta = 25°C , CL = 50pF
200
2.4
Ibusy
300n
3m
150
0.8
1.2
200n
100n
100
2m
1m
tr
tf
50
0.6
1.8
1.8
2K
1.8
1.8
4K
1K
3K
Rp(ohm)
Rp value guidance
VCC(Max.) - VOL(Max.)
3.2V
8mA + SIL
Rp(min, 3.3V part) =
=
IOL + SIL
where IL is the sum of the input currents of all devices tied to the R/B pin.
Rp(max) is determined by maximum permissible limit of tr
34
K9K2G08U0A
FLASH MEMORY
Data Protection & Power up sequence
The device is designed to offer protection from any involuntary program/erase during power-transitions. An internal voltage detector
disables all functions whenever Vcc is below about 2V(3.3V device). WP pin provides hardware protection and is recommended to be
kept at VIL during power-up and power-down. A recovery time of minimum 10ms is required before internal circuit gets ready for any
command sequences as shown in Figure 18. The two step command sequence for program/erase provides additional software pro-
tection.
Figure 18. AC Waveforms for Power Transition
3.3V device : ~ 2.5V
3.3V device : ~ 2.5V
VCC
High
WP
WE
10ms
35
相关型号：
K9K2G08U0M-FCB00
Flash, 256MX8, 30ns, PDSO48, 12 X 17 MM, 0.70 MM HEIGHT, LEAD FREE, PLASTIC, WSOP1-48
SAMSUNG
K9K2G08U0M-FIB00
Flash, 256MX8, 30ns, PDSO48, 12 X 17 MM, 0.70 MM HEIGHT, LEAD FREE, PLASTIC, WSOP1-48
SAMSUNG
K9K2G08U0M-PCB00
Flash, 256MX8, 30ns, PDSO48, 12 X 20 MM, 0.50 MM PITCH, LEAD FREE, PLASTIC, TSOP1-48
SAMSUNG
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