K9K4G08U0M-PCB0T [SAMSUNG]
Flash, 512MX8, 30ns, PDSO48,;型号: | K9K4G08U0M-PCB0T |
厂家: | SAMSUNG |
描述: | Flash, 512MX8, 30ns, PDSO48, 光电二极管 |
文件: | 总38页 (文件大小:741K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
K9W8G08U1M
K9K4G08U0M
FLASH MEMORY
Document Title
512M x 8 Bit / 1G x 8 Bit NAND Flash Memory
Revision History
Revision No History
Draft Date
Feb. 19. 2003
Mar. 31. 2003
Apr. 9. 2003
Remark
Advance
0.0
0.1
0.2
1. Initial issue
1. Add two-K9K4GXXU0M-YCB0/YIB0 Stacked Package
Preliminary
Preliminary
1. The 3rd Byte ID after 90h ID read command is don’t cared.
The 5th Byte ID after 90h ID read command is deleted.
0.3
1. The K9W8G16U1M-YCB0,YIB0,PCB0,PIB0 is deleted in line up.
2. Note is added.
Apr. 30. 2003
Preliminary
(VIL can undershoot to -0.4V and VIH can overshoot to VCC +0.4V for
durations of 20 ns or less.)
3. Pb-free Package is added.
K9K4G08Q0M-PCB0,PIB0
K9K4G08U0M-PCB0,PIB0
K9K4G16U0M-PCB0,PIB0
K9K4G16Q0M-PCB0,PIB0
K9W8G08U1M-PCB0,PIB0
Preliminary
Preliminary
0.4
0.5
1. Added Addressing method for program operation.
Jan. 27. 2004
May.31. 2004
1. The tADL(Address to Data Loading Time) is added.
- tADL Minimum 100ns
- tADL is the time from the WE rising edge of final address cycle
to the WE rising edge of first data cycle at program operation.
2. Added addressing method for program operation
3. PKG(TSOP1) Dimension Change
Preliminary
Preliminary
0.6
1. Technical note is changed
Feb. 01. 2005
2. Notes of AC timing characteristics are added
3. The description of Copy-back program is changed
4. 1.8V part is deleted
0.7
0.8
1. CE access time : 23ns->35ns (p.11)
Feb. 14. 2005
May 4. 2005
1. The value of tREA is changed.(18ns->20ns)
2. The value of output load capacitance is changed.
3. EDO mode is added.
0.9
1. The flow chart to creat the initial invalid block table is changed.
May 6. 2005
The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right
to change the specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions about device. If you have
any questions, please contact the SAMSUNG branch office near your office.
1
K9W8G08U1M
K9K4G08U0M
FLASH MEMORY
512M x 8 Bit / 1G x 8 Bit NAND Flash Memory
PRODUCT LIST
Part Number
Vcc Range
Organization
PKG Type
K9K4G08U0M-Y,P
K9W8G08U1M-Y,P
2.7 ~ 3.6V
X8
TSOP1
FEATURES
• Voltage Supply
• Fast Write Cycle Time
- 2.7 V ~3.6 V
- Program time : 200µs(Typ.)
• Organization
- Block Erase Time : 2ms(Typ.)
- Memory Cell Array
- (512M + 16,384K)bit x 8bit
- Data Register
- (2K + 64)bit x8bit
- Cache Register
- (2K + 64)bit x8bit
• Automatic Program and Erase
- Page Program
• Command/Address/Data Multiplexed I/O Port
• Hardware Data Protection
- Program/Erase Lockout During Power Transitions
• Reliable CMOS Floating-Gate Technology
- Endurance : 100K Program/Erase Cycles
- Data Retention : 10 Years
• Command Register Operation
• Cache Program Operation for High Performance Program
• Power-On Auto-Read Operation
- (2K + 64)Byte
- Block Erase
• Intelligent Copy-Back Operation
- (128K + 4K)Byte
• Page Read Operation
- Page Size
• Unique ID for Copyright Protection
• Package :
- K9K4G08U0M-YCB0/YIB0
- 2K-Byte
- Random Read : 25µs(Max.)
- Serial Access : 30ns(Min.)
48 - Pin TSOP I (12 x 20 / 0.5 mm pitch)
- K9W8G08U1M-YCB0/YIB0 : Two K9K4G08U0M stacked.
48 - Pin TSOP I (12 x 20 / 0.5 mm pitch)
- K9K4G08U0M-PCB0/PIB0 : Pb-FREE PACKAGE
48 - Pin TSOP I (12 x 20 / 0.5 mm pitch)
- K9W8G08U1M-PCB0/PIB0 : Two K9K4G08U0M stacked.
48 - Pin TSOP I (12 x 20 / 0.5 mm pitch)
GENERAL DESCRIPTION
Offered in 512Mx8bit, the K9K4G08U0M is 4G bit with spare 128M bit capacity. Its NAND cell provides the most cost-effective solu-
tion for the solid state mass storage market. A program operation can be performed in typical 200µs on the 2112-byte page and an
erase operation can be performed in typical 2ms on a 128K-byte block. Data in the data page can be read out at 30ns cycle time per
byte. The I/O pins serve as the ports for address and data input/output as well as command input. The on-chip write controller auto-
mates all program and erase functions including pulse repetition, where required, and internal verification and margining of data.
Even the write-intensive systems can take advantage of the K9K4G08U0M′s extended reliability of 100K program/erase cycles by
providing ECC(Error Correcting Code) with real time mapping-out algorithm. The K9K4G08U0M is an optimum solution for large non-
volatile storage applications such as solid state file storage and other portable applications requiring non-volatility. An ultra high den-
sity solution having two 4Gb stacked with two chip selects is also available in standard TSOPI package.
2
K9W8G08U1M
K9K4G08U0M
FLASH MEMORY
PIN CONFIGURATION (TSOP1)
K9K4G08U0M-YCB0,PCB0/YIB0,PIB0
N.C
N.C
N.C
N.C
I/O7
I/O6
I/O5
I/O4
N.C
N.C
PRE
Vcc
Vss
N.C
N.C
N.C
I/O3
I/O2
I/O1
I/O0
N.C
N.C
N.C
N.C
N.C
N.C
N.C
N.C
N.C
N.C
R/B
RE
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
1
2
3
4
5
6
7
8
CE
9
N.C
N.C
Vcc
Vss
N.C
N.C
CLE
ALE
WE
WP
N.C
N.C
N.C
N.C
N.C
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48-pin TSOP1
Standard Type
12mm x 20mm
PACKAGE DIMENSIONS
48-PIN LEAD/LEAD FREE PLASTIC THIN SMALL OUT-LINE PACKAGE TYPE(I)
48 - TSOP1 - 1220AF
Unit :mm/Inch
20.00±0.20
0.787±0.008
#1
#48
#24
#25
1.00±0.05
0.039±0.002
0.05
0.002
MIN
1.20
0.047
MAX
18.40±0.10
0.724±0.004
0~8°
0.45~0.75
0.018~0.030
0.50
0.020
(
)
3
K9W8G08U1M
K9K4G08U0M
FLASH MEMORY
PIN CONFIGURATION (TSOP1)
K9W8G08U1M-YCB0,PCB0/YIB0,PIB0
N.C
N.C
N.C
N.C
I/O7
I/O6
I/O5
I/O4
N.C
N.C
PRE
Vcc
Vss
N.C
N.C
N.C
I/O3
I/O2
I/O1
I/O0
N.C
N.C
N.C
N.C
N.C
N.C
N.C
N.C
N.C
R/B2
R/B1
RE
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
1
2
3
4
5
6
7
8
CE1
CE2
N.C
Vcc
Vss
N.C
N.C
CLE
ALE
WE
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48-pin TSOP1
Standard Type
12mm x 20mm
WP
N.C
N.C
N.C
N.C
N.C
PACKAGE DIMENSIONS
48-PIN LEAD/LEAD FREE PLASTIC THIN SMALL OUT-LINE PACKAGE TYPE(I)
48 - TSOP1 - 1220AF
Unit :mm/Inch
20.00±0.20
0.787±0.008
#1
#48
#24
#25
1.00±0.05
0.039±0.002
0.02
0.002
MIN
1.20
0.047
MAX
18.40±0.10
0.724±0.004
0~8°
0.45~0.75
0.018~0.030
0.50
0.020
(
)
4
K9W8G08U1M
K9K4G08U0M
FLASH MEMORY
PIN DESCRIPTION
Pin Name
Pin Function
DATA INPUTS/OUTPUTS
I/O0 ~ I/O7
CLE
The I/O pins are used to input command, address and data, and to output data during read operations. The I/
O pins float to high-z when the chip is deselected or when the outputs are disabled.
COMMAND LATCH ENABLE
The CLE input controls the activating path for commands sent to the command register. When active high,
commands are latched into the command register through the I/O ports on the rising edge of the WE signal.
ADDRESS LATCH ENABLE
ALE
The ALE input controls the activating path for address to the internal address registers. Addresses are
latched on the rising edge of WE with ALE high.
CHIP ENABLE
The CE / CE1 input is the device selection control. When the device is in the Busy state, CE / CE1 high is
ignored, and the device does not return to standby mode in program or erase operation. Regarding CE /
CE1 control during read operation, refer to ’Page read’ section of Device operation .
CE / CE1
CHIP ENABLE
The CE2 input enables the second K9K4G08U0M
CE2
RE
READ ENABLE
The RE input is the serial data-out control, and when active drives the data onto the I/O bus. Data is valid
tREA after the falling edge of RE which also increments the internal column address counter by one.
WRITE ENABLE
WE
WP
The WE input controls writes to the I/O port. Commands, address and data are latched on the rising edge of
the WE pulse.
WRITE PROTECT
The WP pin provides inadvertent write/erase protection during power transitions. The internal high voltage
generator is reset when the WP pin is active low.
READY/BUSY OUTPUT
The R/B / R/B1 output indicates the status of the device operation. When low, it indicates that a program,
erase or random read operation is in process and returns to high state upon completion. It is an open drain
output and does not float to high-z condition when the chip is deselected or when outputs are disabled.
R/B1/ R/B2
PRE
POWER-ON READ ENABLE
The PRE controls auto read operation executed during power-on. The power-on auto-read is enabled when
PRE pin is tied to Vcc.
POWER
Vcc
Vss
N.C
VCC is the power supply for device.
GROUND
NO CONNECTION
Lead is not internally connected.
NOTE: Connect all VCC and VSS pins of each device to common power supply outputs.
Do not leave VCC or VSS disconnected.
5
K9W8G08U1M
K9K4G08U0M
FLASH MEMORY
Figure 1-1. K9K4G08U0M Functional Block Diagram
VCC
VSS
4096M + 128M Bit
NAND Flash
ARRAY
X-Buffers
A12 - A29
Latches
& Decoders
(2048 + 64)Byte x 262144
Data Register & S/A
Y-Buffers
Latches
& Decoders
A0 - A11
Cache Register
Y-Gating
Command
Command
Register
VCC
VSS
I/O Buffers & Latches
Global Buffers
CE
RE
WE
Control Logic
& High Voltage
Generator
I/0 0
Output
Driver
I/0 7
CLE ALE PRE
WP
Figure 2-1. K9K4G08U0M Array Organization
1 Block = 64 Pages
(128K + 4k) Byte
1 Page = (2K + 64)Bytes
1 Block = (2K + 64)B x 64 Pages
= (128K + 4K) Bytes
1 Device = (2K+64)B x 64Pages x 4096 Blocks
= 4224Mbits
256K Pages
(=4,096 Blocks)
8 bit
2K Bytes
64 Bytes
64 Bytes
I/O 0 ~ I/O 7
Page Register
2K Bytes
I/O 0
A0
I/O 1
A1
I/O 2
I/O 3
A3
I/O 4
A4
I/O 5
A5
I/O 6
A6
I/O 7
A7
Column Address
Column Address
Row Address
1st Cycle
2nd Cycle
3rd Cycle
4th Cycle
5th Cycle
A2
A10
A14
A22
*L
A8
A9
A11
A15
A23
*L
*L
*L
*L
*L
A12
A20
A28
A13
A21
A29
A16
A24
*L
A17
A25
*L
A18
A26
*L
A19
A27
*L
Row Address
Row Address
NOTE : Column Address : Starting Address of the Register.
* L must be set to "Low".
* The device ignores any additional input of address cycles than reguired.
6
K9W8G08U1M
K9K4G08U0M
FLASH MEMORY
Product Introduction
The K9K4G08U0M is a 4224Mbit (4,429,185,024 bit) memory organized as 262,144 rows(pages) by 2112x8 columns. Spare 64 col-
umns are located from column address of 2048~2111. A 2112-byte data register and a 2112-byte cache register are serially con-
nected to each other. Those serially connected registers are connected to memory cell arrays for accommodating data transfer
between the I/O buffers and memory cells during page read and page program operations. The memory array is made up of 32 cells
that are serially connected to form a NAND structure. Each of the 32 cells resides in a different page. A block consists of two NAND
structured strings. A NAND structure consists of 32 cells. Total 1081344 NAND cells reside in a block. The program and read opera-
tions are executed on a page basis, while the erase operation is executed on a block basis. The memory array consists of 4096 sep-
arately erasable 128K-byte blocks. It indicates that the bit by bit erase operation is prohibited on the K9K4G08U0M.
The K9K4G08U0M has addresses multiplexed into 8 I/Os. This scheme dramatically reduces pin counts and allows system upgrades
to future densities by maintaining consistency in system board design. Command, address and data are all written through I/O's by
bringing WE to low while CE is low. Those are latched on the rising edge of WE. Command Latch Enable(CLE) and Address Latch
Enable(ALE) are used to multiplex command and address respectively, via the I/O pins. Some commands require one bus cycle. For
example, Reset Command, Status Read Command, etc require just one cycle bus. Some other commands, like page read and block
erase and page program, require two cycles: one cycle for setup and the other cycle for execution. The 528M byte physical space
requires 30 addresses, thereby requiring five cycles for addressing: 2 cycles of column address, 3 cycles of row address, in that order.
Page Read and Page Program need the same five address cycles following the required command input. In Block Erase operation,
however, only the three row address cycles are used. Device operations are selected by writing specific commands into the command
register. Table 1 defines the specific commands of the K9K4G08U0M.
The device provides cache program in a block. It is possible to write data into the cache registers while data stored in data registers
are being programmed into memory cells in cache program mode. The program performace may be dramatically improved by cache
program when there are lots of pages of data to be programmed.
The device embodies power-on auto-read feature which enables serial access of data of the 1st page without command and address
input after power-on.
In addition to the enhanced architecture and interface, the device incorporates copy-back program feature from one page to another
page without need for transporting the data to and from the external buffer memory. Since the time-consuming serial access and
data-input cycles are removed, system performance for solid-state disk application is significantly increased.
Table 1. Command Sets
Function
1st. Cycle
00h
2nd. Cycle
Acceptable Command during Busy
Read
30h
35h
-
Read for Copy Back
Read ID
00h
90h
Reset
FFh
80h
-
O
Page Program
Cache Program
Copy-Back Program
Block Erase
10h
15h
10h
D0h
-
80h
85h
60h
Random Data Input*1
Random Data Output*1
Read Status
85h
05h
E0h
70h
O
NOTE : 1. Random Data Input/Output can be executed in a page.
Caution : Any undefined command inputs are prohibited except for above command set of Table 1.
7
K9W8G08U1M
K9K4G08U0M
FLASH MEMORY
ABSOLUTE MAXIMUM RATINGS
Parameter
Symbol
VIN/OUT
VCC
Rating
Unit
-0.6 to + 4.6
-0.6 to + 4.6
-10 to +125
-40 to +125
Voltage on any pin relative to VSS
V
K9K4G08U0M-XCB0
Temperature Under Bias
Storage Temperature
TBIAS
°C
K9K4G08U0M-XIB0
K9K4G08U0M-XCB0
K9K4G08U0M-XIB0
TSTG
Ios
-65 to +150
5
°C
Short Circuit Current
mA
NOTE :
1. Minimum DC voltage is -0.6V on input/output pins. During transitions, this level may undershoot to -2.0V for periods <30ns.
Maximum DC voltage on input/output pins is VCC,+0.3V which, during transitions, may overshoot to VCC+2.0V for periods <20ns.
2. Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to the conditions
as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
RECOMMENDED OPERATING CONDITIONS
(Voltage reference to GND, K9K4G08U0M-XCB0 :TA=0 to 70°C, K9K4G08U0M-XIB0:TA=-40 to 85°C)
Parameter
Supply Voltage
Supply Voltage
Symbol
VCC
Min
2.7
0
Typ.
3.3
0
Max
3.6
0
Unit
V
VSS
V
DC AND OPERATING CHARACTERISTICS(Recommended operating conditions otherwise noted.)
Parameter
Symbol
Test Conditions
tRC=30ns, CE=VIL
IOUT=0mA
Min
Typ
Max
Unit
Page Read with Serial
Access
ICC1
-
15
30
Operating
Current
Program
Erase
ICC2
ICC3
ISB1
-
-
-
-
-
15
15
-
30
30
1
mA
Stand-by Current(TTL)
CE=VIH, WP=PRE=0V/VCC
CE=VCC-0.2,
Stand-by Current(CMOS)
ISB2
-
20
100
WP=PRE=0V/VCC
µA
Input Leakage Current
Output Leakage Current
Input High Voltage
ILI
VIN=0 to Vcc(max)
-
-
-
±20
ILO
VOUT=0 to Vcc(max)
-
±20
VIH*
VIL*
VOH
VOL
-
-
0.8xVcc
-
VCC+0.3
Input Low Voltage, All inputs
Output High Voltage Level
Output Low Voltage Level
Output Low Current(R/B)
-0.3
2.4
-
-
0.2xVcc
V
K9K4G08U0M :IOH=-400µA
K9K4G08U0M :IOL=2.1mA
-
-
0.4
-
-
IOL(R/B) K9K4G08U0M :VOL=0.4V
8
10
mA
NOTE :
1. VIL can undershoot to -0.4V and VIH can overshoot to VCC +0.4V for durations of 20 ns or less.
3. The typical value of the K9W8G08U1M’s ISB2 is 40µA and the maximum value is 200µA.
4. The maximum value of K9W8G08U1M’s ILI and ILO is ±40µA.
8
K9W8G08U1M
K9K4G08U0M
FLASH MEMORY
VALID BLOCK
Parameter
Symbol
NVB
Min
4016
8032*
Max
4096
8192*
Unit
K9K4G08U0M
K9W8G08U1M
Valid Block Number
Valid Block Number
Blocks
Blocks
NVB
NOTE :
1. The device may include invalid blocks when first shipped. Additional invalid blocks may develop while being used. The number of valid blocks is pre-
sented with both cases of invalid blocks considered. Invalid blocks are defined as blocks that contain one or more bad bits. Do not erase or pro-
gram factory-marked bad blocks. Refer to the attached technical notes for appropriate management of invalid blocks.
2. The 1st block, which is placed on 00h block address, is guaranteed to be a valid block, does not require Error Correction up to 1K program/erase
cycles.
* : Each K9K4G08U0M chip in the K9W8G08U1M has Maximum 80 invalid blocks.
AC TEST CONDITION
(K9K4G08U0M-XCB0 :TA=0 to 70°C, K9K4G08U0M-XIB0:TA=-40 to 85°C
K9K4G08U0M : Vcc=2.7V~3.6V unless otherwise noted)
Parameter
K9K4G08U0M
Input Pulse Levels
0V to Vcc
Input Rise and Fall Times
5ns
Input and Output Timing Levels
Vcc/2
1 TTL GATE and CL=50pF (K9K4G08U0M-Y,P)
1 TTL GATE and CL=30pF (K9W8G08U1M-Y,P)
Output Load
CAPACITANCE(TA=25°C, VCC=3.3V, f=1.0MHz)
Max
Item
Symbol
Test Condition
Unit
K9K4G08U0M
K9W8G08U1M
Input/Output Capacitance
Input Capacitance
CI/O
CIN
VIL=0V
VIN=0V
20
20
40
40
pF
pF
NOTE : Capacitance is periodically sampled and not 100% tested.
MODE SELECTION
CLE
H
L
ALE
L
CE
L
WE
RE
H
WP
PRE
Mode
Command Input
X
X
Read Mode
H
L
H
X
X
Address Input(5clock)
Command Input
H
L
L
L
H
H
X
Write Mode
H
L
H
H
X
Address Input(5clock)
L
L
L
H
H
X
Data Input
L
L
L
H
X
X
X
X
X
X
X
Data Output
X
X
X
X
X
X
H
H
X
X
X
X
X
X
During Read(Busy)
During Program(Busy)
During Erase(Busy)
Write Protect
X
X
H
X
X
X
X
H
L
X(1)
X
X
X
*2
*2
X
Stand-by
0V/VCC
0V/VCC
NOTE : 1. X can be VIL or VIH.
2. WP and PRE should be biased to CMOS high or CMOS low for standby.
9
K9W8G08U1M
K9K4G08U0M
FLASH MEMORY
Program / Erase Characteristics
Parameter
Symbol
Min
Typ
Max
700
700
4
Unit
µs
*1
Program Time
-
200
tPROG
*2
Dummy Busy Time for Cache Program
3
-
µs
tCBSY
Main Array
Spare Array
-
-
-
cycles
cycles
ms
Number of Partial Program Cycles
in the Same Page
Nop
-
4
Block Erase Time
tBERS
2
3
NOTE : 1.Typical program time is defined as the time within which more than 50% of the whole pages are programmed at Vcc of 3.3V and 25’C
2.Max. time of tCBSY depends on timing between internal program completion and data in
AC Timing Characteristics for Command / Address / Data Input
Min
Max
Parameter
Symbol
Unit
K9K4G08U0M*
K9K4G08U0M
K9K4G08U0M*
K9K4G08U0M
*1
CLE setup Time
25
10
35
10
25
25
10
20
10
45
15
100
15
5
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tCLS
CLE Hold Time
tCLH
*1
CE setup Time
20
5
tCS
CE Hold Time
tCH
tWP
WE Pulse Width
ALE setup Time
ALE Hold Time
15
15
5
*1
tALS
tALH
*1
Data setup Time
Data Hold Time
Write Cycle Time
WE High Hold Time
ALE to Data Loading Time
15
5
tDS
tDH
tWC
tWH
30
10
100
*2
tADL
NOTES : 1. The transition of the corresponding control pins must occur only once while WE is held low.
2. tADL is the time from the WE rising edge of final address cycle to the WE rising edge of first data cycle.
3. For cache program operation, the whole AC Charcateristics must be same as that of K9K4G08U0M*.
10
K9W8G08U1M
K9K4G08U0M
FLASH MEMORY
AC Characteristics for Operation
Min
K9K4G08U0M*
Max
K9K4G08U0M*
Parameter
Symbol
Unit
K9K4G08U0M
K9K4G08U0M
Data Transfer from Cell to Register
ALE to RE Delay
tR
-
10
10
20
25
-
-
10
10
20
15
-
25
10
-
25
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tAR
-
CLE to RE Delay
tCLR
tRR
-
-
Ready to RE Low
-
RE Pulse Width
tRP
-
-
WE High to Busy
tWB
tRC
100
-
100
-
Read Cycle Time
50
-
30
-
RE Access Time
tREA
tCEA
tRHZ
tCHZ
tOH
30
45
30
20
-
20
35
30
20
-
CE Access Time
-
-
RE High to Output Hi-Z
CE High to Output Hi-Z
RE or CE High to Output hold
RE High Hold Time
Output Hi-Z to RE Low
RE High to WE Low
WE High to RE Low
-
-
-
-
15
15
0
15
10
0
tREH
tIR
-
-
-
-
tRHW
tWHR
100
60
100
60
-
-
-
-
Device Resetting Time
(Read/Program/Erase)
5/10/500*1
5/10/500*1
tRST
-
-
µs
NOTE: 1. If reset command(FFh) is written at Ready state, the device goes into Busy for maximum 5us.
2. For cache program operation, the whole AC Charcateristics must be same as that of K9K4G08U0M*.
11
K9W8G08U1M
K9K4G08U0M
FLASH MEMORY
NAND Flash Technical Notes
Initial Invalid Block(s)
Initial invalid blocks are defined as blocks that contain one or more initial invalid bits whose reliability is not guaranteed by Samsung.
The information regarding the initial invalid block(s) is so called as the initial invalid block information. Devices with initial invalid
block(s) have the same quality level as devices with all valid blocks and have the same AC and DC characteristics. An initial invalid
block(s) does not affect the performance of valid block(s) because it is isolated from the bit line and the common source line by a
select transistor. The system design must be able to mask out the initial invalid block(s) via address mapping. The 1st block, which is
placed on 00h block address, is guaranteed to be a valid block, does not require Error Correction up to 1K program/erase cycles.
Identifying Initial Invalid Block(s)
All device locations are erased(FFh) except locations where the initial invalid block(s) information is written prior to shipping. The ini-
tial invalid block(s) status is defined by the 1st byte in the spare area. Samsung makes sure that either the 1st or 2nd page of every
initial invalid block has non-FFh data at the column address of 2048. Since the initial invalid block information is also erasable in most
cases, it is impossible to recover the information once it has been erased. Therefore, the system must be able to recognize the initial
invalid block(s) based on the initial invalid block information and create the initial invalid block table via the following suggested flow
chart(Figure 3). Any intentional erasure of the initial invalid block information is prohibited.
Start
Set Block Address = 0
Increment Block Address
Check "FFh( or FFFFh)" at the column address
of the 1st and 2nd page in the block
2048
*
No
No
Check "FFh
or FFFFh" ?
Create (or update)
Initial Invalid Block(s) Table
Yes
Last Block ?
Yes
End
Figure 3. Flow chart to create initial invalid block table.
12
K9W8G08U1M
K9K4G08U0M
FLASH MEMORY
NAND Flash Technical Notes (Continued)
Error in write or read operation
Within its life time, additional invalid blocks may develop with NAND Flash memory. Refer to the qualification report for the block
failure rate.The following possible failure modes should be considered to implement a highly reliable system. In the case of status
read failure after erase or program, block replacement should be done. Because program status fail during a page program does not
affect the data of the other pages in the same block, block replacement can be executed with a page-sized buffer by finding an erased
empty block and reprogramming the current target data and copying the rest of the replaced block. In case of Read, ECC must be
employed. To improve the efficiency of memory space, it is recommended that the read failure due to single bit error should be
reclaimed by ECC without any block replacement. The block failure rate in the qualification report does not include those reclaimed
blocks.
Failure Mode
Erase Failure
Detection and Countermeasure sequence
Status Read after Erase --> Block Replacement
Status Read after Program --> Block Replacement
Verify ECC -> ECC Correction
Write
Read
Program Failure
Single Bit Failure
: Error Correcting Code --> Hamming Code etc.
Example) 1bit correction & 2bit detection
ECC
Program Flow Chart
Start
Write 80h
Write Address
Write Data
Write 10h
Read Status Register
No
I/O 6 = 1 ?
or R/B = 1 ?
Yes
*
No
Program Error
I/O 0 = 0 ?
Yes
Program Completed
: If program operation results in an error, map out
the block including the page in error and copy the
target data to another block.
*
13
K9W8G08U1M
K9K4G08U0M
FLASH MEMORY
NAND Flash Technical Notes (Continued)
Erase Flow Chart
Read Flow Chart
Start
Write 00h
Start
Write 60h
Write Block Address
Write Address
Write 30h
Write D0h
Read Data
Read Status Register
ECC Generation
No
I/O 6 = 1 ?
or R/B = 1 ?
No
Verify ECC
Reclaim the Error
Yes
*
No
Yes
Erase Error
I/O 0 = 0 ?
Page Read Completed
Yes
Erase Completed
: If erase operation results in an error, map out
the failing block and replace it with another block.
*
Block Replacement
Block A
1st
{
(n-1)th
1
nth
an error occurs.
(page)
Buffer memory of the controller.
Block B
1st
2
{
(n-1)th
nth
(page)
* Step1
When an error happens in the nth page of the Block ’A’ during erase or program operation.
* Step2
Copy the data in the 1st ~ (n-1)th page to the same location of another free block. (Block ’B’)
* Step3
Then, copy the nth page data of the Block ’A’ in the buffer memory to the nth page of the Block ’B’.
* Step4
Do not erase or program to Block ’A’ by creating an ’invalid Block’ table or other appropriate scheme.
14
K9W8G08U1M
K9K4G08U0M
FLASH MEMORY
NAND Flash Technical Notes (Continued)
Addressing for program operation
Within a block, the pages must be programmed consecutively from the LSB (least significant bit) page of the block to MSB (most sig-
nificant bit) pages of the block. Random page address programming is prohibited.
(64)
(64)
Page 63
Page 31
Page 63
Page 31
:
:
(1)
:
(32)
:
(3)
(2)
(1)
Page 2
Page 1
Page 0
(3)
(32)
(2)
Page 2
Page 1
Page 0
Data register
Data register
From the LSB page to MSB page
DATA IN: Data (1)
Ex.) Random page program (Prohibition)
DATA IN: Data (1)
Data (64)
Data (64)
15
K9W8G08U1M
K9K4G08U0M
FLASH MEMORY
System Interface Using CE don’t-care.
For an easier system interface, CE may be inactive during the data-loading or serial access as shown below. The internal 2112byte
data registers are utilized as separate buffers for this operation and the system design gets more flexible. In addition, for voice or
audio applications which use slow cycle time on the order of u-seconds, de-activating CE during the data-loading and serial access
would provide significant savings in power consumption.
Figure 4. Program Operation with CE don’t-care.
CLE
CE don’t-care
CE
WE
ALE
I/Ox
80h
Address(5Cycles)
Data Input
Data Input
10h
tCH
tCEA
tCS
CE
RE
CE
tREA
tWP
WE
out
I/O0~7
Figure 5. Read Operation with CE don’t-care.
CLE
CE
CE don’t-care
RE
ALE
tR
R/B
WE
I/Ox
Data Output(serial access)
00h
Address(5Cycle)
30h
16
K9W8G08U1M
K9K4G08U0M
FLASH MEMORY
NOTE
I/O
I/Ox
DATA
ADDRESS
Device
Data In/Out
~2112byte
Col. Add1
Col. Add2
Row Add1
Row Add2
Row Add3
K9K4G08U0M
I/O 0 ~ I/O 7
A0~A7
A8~A11
A12~A19
A20~A27
A28~A29
Command Latch Cycle
CLE
tCLH
tCLS
tCS
tCH
CE
tWP
WE
tALS
tALH
ALE
I/Ox
tDH
tDS
Command
Address Latch Cycle
tCLS
CLE
tCS
tWC
tWC
tWC
tWC
CE
tWP
tWP
tWP
tWP
WE
tWH
tWH
tALH
tWH
tALH
tWH
tALH
tALH
tALS
tALH
tDH
tALS
tALS
tALS
tALS
ALE
I/Ox
tDH
tDH
tDH
tDH
tDS
tDS
tDS
tDS
tDS
Col. Add2
Row Add1
Col. Add1
Row Add2
Row Add3
17
K9W8G08U1M
K9K4G08U0M
FLASH MEMORY
Input Data Latch Cycle
tCLH
CLE
tCH
CE
tWC
ALE
tALS
tWP
tWP
tWP
WE
tWH
tDH
tDH
tDH
tDS
tDS
tDS
I/Ox
DIN final*
DIN 0
DIN 1
NOTES : DIN final means 2112
Serial Access Cycle after Read(CLE=L, WE=H, ALE=L)
tCEA
CE
tCHZ*
tOH
tREH
tREA
tREA
tREA
RE
tRHZ*
tRHZ*
tOH
I/Ox
R/B
Dout
Dout
Dout
tRC
tRR
NOTES : Transition is measured ±200mV from steady state voltage with load.
This parameter is sampled and not 100% tested.
18
K9W8G08U1M
K9K4G08U0M
FLASH MEMORY
Status Read Cycle
tCLR
CLE
CE
tCLS
tCS
tCLH
tCH
tWP
WE
tCEA
tCHZ*
tOH
tWHR
RE
tRHZ*
tOH
tDH
tREA
tDS
tIR*
I/Ox
Status Output
70h
19
K9W8G08U1M
K9K4G08U0M
FLASH MEMORY
Read Operation
tCLR
CLE
CE
tWC
WE
ALE
RE
tWB
tAR
tRHZ
tR
tRC
tRR
Col. Add2 Row Add1 Row Add2
00h
Col. Add1
30h
Dout N
Dout N+1
Dout M
Row Add3
I/Ox
Column Address
Row Address
Busy
R/B
Read Operation(Intercepted by CE)
CLE
CE
WE
ALE
RE
tWB
tCHZ
tOH
tAR
tR
tRC
tRR
Row Add2 Row Add3
Dout N+2
00h
Col. Add1 Col. Add2 Row Add1
30h
Dout N+1
Dout N
I/Ox
R/B
Row Address
Column Address
Busy
20
K9W8G08U1M
K9K4G08U0M
FLASH MEMORY
21
K9W8G08U1M
K9K4G08U0M
FLASH MEMORY
Page Program Operation
CLE
CE
tWC
tWC
tWC
WE
ALE
RE
tPROG
tWB
tADL
Din
N
Din
M
Co.l Add1 Col. Add2 Row Add1 Row Add2 Row Add3
80h
I/Ox
R/B
10h
70h
I/O0
SerialData
Input Command
Program
Command
1 up to m Byte
Serial Input
Read Status
Command
Column Address
Row Address
I/O
0
=0 Successful Program
=1 Error in Program
I/O0
m = 2112byte
NOTES : tADL is the time from the WE rising edge of final address cycle to the WE rising edge of first data cycle.
22
K9W8G08U1M
K9K4G08U0M
FLASH MEMORY
≈
≈ ≈
≈
≈ ≈
≈
23
K9W8G08U1M
K9K4G08U0M
FLASH MEMORY
≈
≈ ≈
≈
24
K9W8G08U1M
K9K4G08U0M
FLASH MEMORY
≈
≈ ≈
≈
≈
≈ ≈
≈
25
K9W8G08U1M
K9K4G08U0M
FLASH MEMORY
BLOCK ERASE OPERATION
CLE
CE
tWC
WE
tBERS
tWB
ALE
RE
I/Ox
Row Add1 Row Add2 Row Add3
60h
D0h
70h
I/O 0
Row Address
Busy
R/B
Auto Block Erase
Setup Command
Erase Command
I/O
0
=0 Successful Erase
Read Status I/O
Command
0=1 Error in Erase
26
K9W8G08U1M
K9K4G08U0M
FLASH MEMORY
Read ID Operation
CLE
CE
WE
ALE
RE
tAR
tREA
Device
Code*
I/Ox
4th cyc.*
00h
ECh
C1h
90h
Read ID Command
Maker Code Device Code
Address. 1cycle
Device
Device Code*(2nd Cycle)
4th Cycle*
K9K4G08U0M
K9W8G08U1M
DCh
15h
Same as each K9K4G08U0M in it
ID Defintition Table
90 ID : Access command = 90H
Description
1st Byte
2nd Byte
3rd Byte
4th Byte
Maker Code
Device Code
Don’t care
Page Size, Block Size, Spare Size, Organization
27
K9W8G08U1M
K9K4G08U0M
FLASH MEMORY
4th ID Data
Description
1KB
2KB
Reserved
Reserved
I/O7
I/O6
I/O5 I/O4
I/O3
I/O2
I/O1 I/O0
0
0
1
1
0
1
0
1
Page Size
(w/o redundant area )
64KB
0
0
1
1
0
1
0
1
Blcok Size
(w/o redundant area )
128KB
256KB
Reserved
Redundant Area Size
( byte/512byte)
8
16
0
1
x8
x16
0
1
Organization
50ns/30ns
25ns
Reserved
Reserved
0
1
0
1
0
0
1
1
Serial AccessMinimum
28
K9W8G08U1M
K9K4G08U0M
FLASH MEMORY
Device Operation
PAGE READ
Page read is initiated by writing 00h-30h to the command register along with five address cycles. After initial power up, 00h command
is latched. Therefore only five address cycles and 30h command initiates that operation after initial power up. The 2,112 bytes of data
within the selected page are transferred to the data registers in less than 25µs(tR). The system controller can detect the completion of
this data transfer(tR) by analyzing the output of R/B pin. Once the data in a page is loaded into the data registers, they may be read
out in 30ns cycle time by sequentially pulsing RE. The repetitive high to low transitions of the RE clock make the device output the
data starting from the selected column address up to the last column address.
The device may output random data in a page instead of the consecutive sequential data by writing random data output command.
The column address of next data, which is going to be out, may be changed to the address which follows random data output com-
mand. Random data output can be operated multiple times regardless of how many times it is done in a page.
Figure 6. Read Operation
CLE
CE
WE
ALE
tR
R/B
RE
I/Ox
00h
Address(5Cycle)
30h
Data Output(Serial Access)
Col Add1,2 & Row Add1,2,3
Data Field
Spare Field
29
K9W8G08U1M
K9K4G08U0M
FLASH MEMORY
Figure 7. Random Data Output In a Page
tR
R/B
RE
Address
5Cycles
Address
2Cycles
Data Output
Data Output
30h
E0h
00h
05h
I/Ox
Col Add1,2 & Row Add1,2,3
Data Field
Data Field
Spare Field
Spare Field
PAGE PROGRAM
The device is programmed basically on a page basis, but it does allow multiple partial page programing of a word or consecutive
bytes up to 2112, in a single page program cycle. The number of consecutive partial page programming operation within the same
page without an intervening erase operation must not exceed 4 times for main array(1time/512byte) and 4 times for spare array
(1time/16byte). The addressing should be done in sequential order in a block. A page program cycle consists of a serial data loading
period in which up to 2112bytes of data may be loaded into the data register, followed by a non-volatile programming period where the
loaded data is programmed into the appropriate cell.
The serial data loading period begins by inputting the Serial Data Input command(80h), followed by the five cycle address inputs and
then serial data loading. The words other than those to be programmed do not need to be loaded. The device supports random data
input in a page. The column address for the next data, which will be entered, may be changed to the address which follows random
data input command(85h). Random data input may be operated multiple times regardless of how many times it is done in a page.
The Page Program confirm command(10h) initiates the programming process. Writing 10h alone without previously entering the serial
data will not initiate the programming process. The internal write state controller automatically executes the algorithms and timings
necessary for program and verify, thereby freeing the system controller for other tasks. Once the program process starts, the Read
Status Register command may be entered to read the status register. The system controller can detect the completion of a program
cycle by monitoring the R/B output, or the Status bit(I/O 6) Page Program is complete, the Write Status Bit(I/O 0) may be checked(Fig-
ure 8). The internal write verify detects only errors for "1"s that are not successfully programmed to "0"s. The command register
remains in Read Status command mode until another valid command is written to the command register.
Figure 8. Program & Read Status Operation
tPROG
R/B
"0"
Pass
80h
Address & Data Input
I/O0
Fail
I/Ox
10h
70h
Col Add1,2 & Row Add1,2,3
Data
"1"
30
K9W8G08U1M
K9K4G08U0M
FLASH MEMORY
Figure 9. Random Data Input In a Page
tPROG
R/B
"0"
Pass
80h
Address & Data Input
Address & Data Input
I/O0
Fail
I/Ox
85h
10h
70h
Col Add1,2
Data
Col Add1,2 & Row Add1,2,3
Data
"1"
Cache Program
Cache Program is an extension of Page Program, which is executed with 2112byte data registers, and is available only within a block.
Since the device has 1 page of cache memory, serial data input may be executed while data stored in data register are programmed
into memory cell.
After writing the first set of data up to 2112byte into the selected cache registers, Cache Program command (15h) instead of actual
Page Program (10h) is inputted to make cache registers free and to start internal program operation. To transfer data from cache reg-
isters to data registers, the device remains in Busy state for a short period of time(tCBSY) and has its cache registers ready for the
next data-input while the internal programming gets started with the data loaded into data registers. Read Status command (70h) may
be issued to find out when cache registers become ready by polling the Cache-Busy status bit(I/O 6). Pass/fail status of only the pre-
viouse page is available upon the return to Ready state. When the next set of data is inputted with the Cache Program command,
tCBSY is affected by the progress of pending internal programming. The programming of the cache registers is initiated only when the
pending program cycle is finished and the data registers are available for the transfer of data from cache registers. The status bit(I/
O5) for internal Ready/Busy may be polled to identify the completion of internal programming. If the system monitors the progress of
programming only with R/B, the last page of the target programming sequence must be progammed with actual Page Program com-
mand (10h).
Figure 10. Cache Program (available only within a block)
tPROG
tCBSY
tCBSY
tCBSY
R/B
Address &
Data Input
Address &
Data Input
Address &
Data Input*
Address &
Data Input
80h
70h
10h
80h
15h
80h
80h
15h
15h
Col Add1,2 & Row Add1,2,3
Data
Col Add1,2 & Row Add1,2,3
Data
Col Add1,2 & Row Add1,2,3
Data
Col Add1,2 & Row Add1,2,3
Data
31
K9W8G08U1M
K9K4G08U0M
FLASH MEMORY
NOTE : Since programming the last page does not employ caching, the program time has to be that of Page Program. However, if the
previous program cycle with the cache data has not finished, the actual program cycle of the last page is initiated only after comple-
tion of the previous cycle, which can be expressed as the following formula.
tPROG= Program time for the last page+ Program time for the ( last -1 )th page
- (Program command cycle time + Last page data loading time)
Copy-Back Program
The copy-back program is configured to quickly and efficiently rewrite data stored in one page without utilizing an external memory.
Since the time-consuming cycles of serial access and re-loading cycles are removed, the system performance is improved. The ben-
efit is especially obvious when a portion of a block is updated and the rest of the block also need to be copied to the newly assigned
free block. The operation for performing a copy-back program is a sequential execution of page-read without serial access and copy-
ing-program with the address of destination page. A read operation with "35h" command and the address of the source page moves
the whole 2112byte data into the internal data buffer. As soon as the device returns to Ready state, Page-Copy Data-input command
(85h) with the address cycles of destination page followed may be written. The Program Confirm command (10h) is required to actu-
ally begin the programming operation. Copy-Back Program operation is allowed only within the same memory plane. Once the Copy-
Back Program is finished, any additional partial page programming into the copied pages is prohibited before erase. The MSB(A29)
must be the same between source and target page during copy-back program.Data input cycle for modifying a portion or multiple dis-
tant portions of the source page is allowed as shown in Figure 11."When there is a program-failure at Copy-Back operation, error
is reported by pass/fail status. But if the soure page has an error bit by charge loss, accumulated copy-back operations
could also accumulate bit errors. In this case, verifying the source page for a bit error is recommended before Copy-back
program"
Figure 11. Page Copy-Back program Operation
tR
tPROG
R/B
I/Ox
Add.(5Cycles)
Pass
00h
35h
Add.(5Cycles)
10h
I/O0
Fail
85h
70h
Col. Add1,2 & Row Add1,2,3
Destination Address
Col. Add1,2 & Row Add1,2,3
Source Address
NOTE: It’s prohibited to operate Copy-Back program from an odd address page(source page) to an even address page(target page) or from an even
address page(source page) to an odd address page(target page). Therefore, the Copy-Back program is permitted just between odd address pages or even
address pages.
Figure 12. Page Copy-Back program Operation with Random Data Input
tPROG
tR
R/B
Add.(5Cycles)
Add.(2Cycles)
Col Add1,2
I/Ox
35h
Add.(5Cycles)
70h
00h
85h
Data
85h
Data
10h
Col. Add1,2 & Row Add1,2,3
Source Address
Col. Add1,2 & Row Add1,2,3
Destination Address
There is no limitation for the number of repetition.
32
K9W8G08U1M
K9K4G08U0M
FLASH MEMORY
BLOCK ERASE
The Erase operation is done on a block basis. Block address loading is accomplished in three cycles initiated by an Erase Setup
command(60h). Only address A18 to A29 is valid while A12 to A17 is ignored. The Erase Confirm command(D0h) following the block
address loading initiates the internal erasing process. This two-step sequence of setup followed by execution command ensures that
memory contents are not accidentally erased due to external noise conditions.
At the rising edge of WE after the erase confirm command input, the internal write controller handles erase and erase-verify. When
the erase operation is completed, the Write Status Bit(I/O 0) may be checked. Figure 13 details the sequence.
Figure 13. Block Erase Operation
tBERS
R/B
"0"
Pass
60h
I/O0
Fail
70h
Address Input(3Cycle)
Block Add. : A12 ~ A29
I/Ox
D0h
"1"
READ STATUS
The device contains a Status Register which may be read to find out whether program or erase operation is completed, and whether
the program or erase operation is completed successfully. After writing 70h command to the command register, a read cycle outputs
the content of the Status Register to the I/O pins on the falling edge of CE or RE, whichever occurs last. This two line control allows
the system to poll the progress of each device in multiple memory connections even when R/B pins are common-wired. RE or CE
does not need to be toggled for updated status. Refer to table 2 for specific Status Register definitions. The command register
remains in Status Read mode until further commands are issued to it. Therefore, if the status register is read during a random read
cycle, the read command(00h) should be given before starting read cycles.
Table2. Read Staus Register Definition
I/O No.
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
Page Program
Pass/Fail
Block Erase
Pass/Fail
Not use
Cache Prorgam
Pass/Fail(N)
Pass/Fail(N-1)
Not use
Read
Not use
Definition
Pass : "0"
Fail : "1"
Fail : "1"
Not use
Not use
Pass : "0"
Not use
Not use
Not use
Don’t -cared
Don’t -cared
Don’t -cared
Busy : "0"
Not Use
Not Use
Not Use
Not Use
Not Use
Not Use
Not Use
Not Use
Ready/Busy
Ready/Busy
Write Protect
Ready/Busy
Ready/Busy
Write Protect
True Ready/Busy
Ready/Busy
Write Protect
Ready/Busy
Ready/Busy
Write Protect
Ready : "1"
Ready : "1"
Busy : "0"
Protected : "0"
Not Protected
NOTE : 1. True Ready/Busy represents internal program operation status which is being executed in cache program mode.
2. I/Os defined ’Not use’ are recommended to be masked out when Read Status is being executed.
33
K9W8G08U1M
K9K4G08U0M
FLASH MEMORY
Read ID
The device contains a product identification mode, initiated by writing 90h to the command register, followed by an address input of
00h. Five read cycles sequentially output the manufacturer code(ECh), and the device code and XXh, 4th cycle ID respectively. The
command register remains in Read ID mode until further commands are issued to it. Figure 14 shows the operation sequence.
Figure 14. Read ID Operation
tCLR
CLE
CE
tCEA
WE
ALE
RE
tAR1
tWHR
Device
Code*
tREA
I/OX
90h
00h
Address. 1cycle
ECh
C1h
4th Cyc.*
Maker code
Device code
Device
Device Code*(2nd Cycle)
3rd Cycle
4th Cycle*
K9K4G08U0M
K9W8G08U1M
DCh
C1h
15h
Same as each K9K4G08U0M in it
RESET
The device offers a reset feature, executed by writing FFh to the command register. When the device is in Busy state during random
read, program or erase mode, the reset operation will abort these operations. The contents of memory cells being altered are no
longer valid, as the data will be partially programmed or erased. The command register is cleared to wait for the next command, and
the Status Register is cleared to value C0h when WP is high. Refer to table 3 for device status after reset operation. If the device is
already in reset state a new reset command will be accepted by the command register. The R/B pin transitions to low for tRST after
the Reset command is written. Refer to Figure 15 below.
Figure 15. RESET Operation
tRST
R/B
I/OX
FFh
Table3. Device Status
After Power-up
After Reset
PRE status
High
First page data access is ready
Low
Waiting for next command
Operation Mode
00h command is latched
34
K9W8G08U1M
K9K4G08U0M
FLASH MEMORY
Power-On Auto-Read
The device is designed to offer automatic reading of the first page without command and address input sequence during power-on.
An internal voltage detector enables auto-page read functions when Vcc reaches about 1.8V. PRE pin controls activation of auto-
page read function. Auto-page read function is enabled only when PRE pin is tied to Vcc. Serial access may be done after power-on
without latency.
Figure 16. Power-On Auto-Read
~ 1.8V
VCC
CLE
CE
WE
ALE
PRE
R/B
tR
RE
I/OX
1st
2nd
3rd
....
n th
35
K9W8G08U1M
K9K4G08U0M
FLASH MEMORY
READY/BUSY
The device has a R/B output that provides a hardware method of indicating the completion of a page program, erase and random
read completion. The R/B pin is normally high but transitions to low after program or erase command is written to the command regis-
ter or random read is started after address loading. It returns to high when the internal controller has finished the operation. The pin is
an open-drain driver thereby allowing two or more R/B outputs to be Or-tied. Because pull-up resistor value is related to tr(R/B) and
current drain during busy(ibusy) , an appropriate value can be obtained with the following reference chart(Fig 17). Its value can be
determined by the following guidance.
Rp
ibusy
VCC
3.3V device - VOL : 0.4V, VOH : 2.4V
Ready Vcc
R/B
VOH
open drain output
CL
VOL
Busy
tf
tr
GND
Device
Figure 17. Rp vs tr ,tf & Rp vs ibusy
@ Vcc = 3.3V, Ta = 25°C , CL = 100pF
200
2.4
Ibusy
150n
3m
150
0.8
1.2
100n
50n
100
2m
1m
tr
tf
50
0.6
1.8
1.8
2K
1.8
1.8
4K
1K
3K
Rp(ohm)
Rp value guidance
VCC(Max.) - VOL(Max.)
3.2V
Rp(min, 3.3V part) =
=
IOL + ΣIL
8mA + ΣIL
where IL is the sum of the input currents of all devices tied to the R/B pin.
Rp(max) is determined by maximum permissible limit of tr
36
K9W8G08U1M
K9K4G08U0M
FLASH MEMORY
Data Protection & Power up sequence
The device is designed to offer protection from any involuntary program/erase during power-transitions. An internal voltage detector
disables all functions whenever Vcc is below about 2V. WP pin provides hardware protection and is recommended to be kept at VIL
during power-up and power-down. A recovery time of minimum 10µs is required before internal circuit gets ready for any command
sequences as shown in Figure 18. The two step command sequence for program/erase provides additional software protection.
Figure 18. AC Waveforms for Power Transition
3.3V device : ~ 2.5V
3.3V device : ~ 2.5V
VCC
High
WP
WE
10µs
37
K9W8G08U1M
K9K4G08U0M
FLASH MEMORY
Extended Data Out Mode
For the EDO mode, the device should hold the data on the system memory bus until the beginning of the next cycle, so that controller
could fetch the data at the falling edge. However NAND flash dosen’t support the EDO mode exactly.
The device stops the data input into the I/O bus after RE rising edge. But since the previous data remains in the I/O bus, the flow of I/
O data seems like Figure 18 and the system can access serially the data with EDO mode. tRLOH which is the parameter for fetching
data at RE falling time is necessary. Its appropriate value can be obtained with the reference chart as shown in Figure 19. The tRHOH
value depands on output load(CL) and I/O bus Pull-up resistor (Rp).
Figure 19. Serial Access Cycle after Read(EDO Type, CLE=L, WE=H, ALE=L)
CE
tRC
tRP
tREH
RE
tREA
tCEA
tREA
tRLOH
tRHOH
I/Ox
R/B
Dout
Dout
tRR
tRHOH
NOTES : Transition is measured at ±200mV from steady state voltage with load.
This parameter is sampled and not 100% tested.
Figure 20. Rp vs tRHOH vs CL
Rp
VCC
@ Vcc = 3.3V, Ta = 25°C
tRHOH
Rp = 100k
600
600
600n
Rp = 50k
I/O Drive
500n
425
360
400n
CL
300
300n
180
200n
120
60
Rp = 10k
Rp = 5k
85
100n
60
GND
36
50n
42
30
50p
18
Device
CL (F)
100p
30p
70p
tRLOH / tRHOH value guidance
tRHOH = CL * VOL * Rp / Vcc
tRLOH(min, 3.3V part) = tRHOH - tREH
38
相关型号:
K9K4G08U0M-PIB00
Flash, 512MX8, 18ns, PDSO48, 12 X 20 MM, 0.50 MM PITCH, LEAD FREE, PLASTIC, TSOP1-48
SAMSUNG
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