K9WBG08U5A-9IB00 [SAMSUNG]
Flash, 4GX8, 20ns, PDSO56;
| 型号： | K9WBG08U5A-9IB00 |
| 厂家： | 
SAMSUNG |
| 描述： | Flash, 4GX8, 20ns, PDSO56 光电二极管 内存集成电路 |
| 文件： | 总47页 (文件大小：830K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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FLASH MEMORY
K9WBG08U5A
K9F8G08U0A
K9F8G08U0A
INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS,
AND IS SUBJECT TO CHANGE WITHOUT NOTICE.
NOTHING IN THIS DOCUMENT SHALL BE CONSTRUED AS GRANTING ANY LICENSE,
EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE,
TO ANY INTELLECTUAL PROPERTY RIGHTS IN SAMSUNG PRODUCTS OR TECHNOLOGY. ALL
INFORMATION IN THIS DOCUMENT IS PROVIDED
ON AS "AS IS" BASIS WITHOUT GUARANTEE OR WARRANTY OF ANY KIND.
1. For updates or additional information about Samsung products, contact your nearest Samsung office.
2. Samsung products are not intended for use in life support, critical care, medical, safety equipment, or similar
applications where Product failure could result in loss of life or personal or physical harm, or any military or
defense application, or any governmental procurement to which special terms or provisions may apply.
* Samsung Electronics reserves the right to change products or specification without notice.
Samsung Only
1
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FLASH MEMORY
K9WBG08U5A
K9F8G08U0A
Document Title
1G x 8 Bit / 4Gb x 8bit NAND Flash Memory
Revision History
Revision No History
Draft Date
Remark
0.0
0.1
0.2
1. Initial issue
Jan. 15th 2009 Advance
Jan. 21th 2009 Advance
1. Cycle 25ns => 30ns
1. 4th ID cycle is modified.
Feb. 5th 2009
Advance
The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right
to change the specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions about device. If you have
any questions, please contact the SAMSUNG branch office near your office.
Samsung Only
2
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FLASH MEMORY
K9WBG08U5A
K9F8G08U0A
2G x 8 Bit/ 4G x 8 Bit/ 8G x 8 Bit NAND Flash Memory
PRODUCT LIST
Part Number
K9F8G08U0A-P
K9WBG08U5A-9
Vcc Range
Organization
PKG Type
48 TSOP1
56 TSOP1
2.7V ~ 3.6V
x8
FEATURES
• Voltage Supply
- 2.7V ~ 3.6V
• Command/Address/Data Multiplexed I/O Port
• Hardware Data Protection
• Organization
- Memory Cell Array : (1G + 54.5M) x 8bit
- Data Register
• Automatic Program and Erase
- Page Program : (4K + 218)Byte
- Block Erase : (256K + 13.6K)Byte
• Page Read Operation
- Program/Erase Lockout During Power Transitions
• Reliable CMOS Floating-Gate Technology
- Endurance : TBD Cycles(with 8bit/512Byte ECC)
- Data Retention : TBD Years
• Command Register Operation
• Unique ID for Copyright Protection
• Package :
: (4K + 218) x 8bit
- Page Size : (4K + 218)Byte
- Random Read : 50µs(Max.)
- Serial Access : 30ns(Min.)
• Memory Cell : 2bit / Memory Cell
• Fast Write Cycle Time
- K9F8G08U0A-PCB0/PIB0 : Pb-FREE PACKAGE
48 - Pin TSOP I (12 x 20 / 0.5 mm pitch)
- K9WBG08U5A-9CB0/9IB0 : Pb-FREE PACKAGE
56 - Pin TSOP I (14 x 16 / 0.5 mm pitch)
- Program time : 400µs(Typ.)
- Block Erase Time : 1.5ms(Typ.)
GENERAL DESCRIPTION
Offered in 1Gx8bit, the K9F8G08U0A is a 8G-bit NAND Flash Memory with spare 436M-bit. The device is offered in 3.3V Vcc. Its
NAND cell provides the most cost-effective solution for the solid state mass storage market. A program operation can be performed
in typical 400µs on the 4,314-byte page and an erase operation can be performed in typical 1.5ms on a (256K+13.6K)byte block.
Data in the data register can be read out at 30ns cycle time per byte. The I/O pins serve as the ports for address and data input/out-
put as well as command input. The on-chip write controller automates all program and erase functions including pulse repetition,
where required, and internal verification and margining of data. Even the write-intensive systems can take advantage of the
K9F8G08U0A′s extended reliability of TBD cycles by providing ECC(Error Correcting Code) with real time mapping-out algorithm.
The K9F8G08U0A is an optimum solution for large nonvolatile storage applications such as solid state file storage and other portable
applications requiring non-volatility.
Samsung Only
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FLASH MEMORY
K9WBG08U5A
K9F8G08U0A
PIN CONFIGURATION (48-TSOP1)
K9F8G08U0A-PCB0
N.C
N.C
N.C
N.C
I/O7
I/O6
I/O5
I/O4
N.C
N.C
N.C
Vcc
Vss
N.C
N.C
N.C
I/O3
I/O2
I/O1
I/O0
N.C
N.C
N.C
N.C
N.C
N.C
N.C
N.C
N.C
N.C
R/B
RE
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
1
2
3
4
5
6
7
8
CE
9
N.C
N.C
Vcc
Vss
N.C
N.C
CLE
ALE
WE
WP
N.C
N.C
N.C
N.C
N.C
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48-pin TSOP1
Standard Type
12mm x 20mm
PACKAGE DIMENSIONS
48-PIN LEAD FREE PLASTIC THIN SMALL OUT-LINE PACKAGE TYPE(I)
48 - TSOP1 - 1220AF
Unit :mm/Inch
20.00±0.20
0.787±0.008
#1
#48
#24
#25
1.00±0.05
0.039±0.002
0.05
0.002
MIN
1.20
0.047
MAX
18.40±0.10
0.724±0.004
0~8°
0.45~0.75
0.018~0.030
0.50
0.020
(
)
Samsung Only
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FLASH MEMORY
K9WBG08U5A
K9F8G08U0A
PIN CONFIGURATION (56-TSOP1)
Channel_1
K9WBG08U5A-PCB0/PIB0
Channel_2
N.C
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
N.C
WP
WE
1
2
WP
WE
3
ALE
ALE
CLE
Vss
Vcc
4
CLE
5
Vss
Vcc
6
7
CE3
CE4
CE1
CE2
RE
8
9
RE
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
R/B3
R/B4
N.C
R/B1
R/B2
N.C
I/O7
I/O6
I/O5
I/O4
N.C
Vcc
Vss
N.C
N.C
I/O3
I/O2
I/O1
I/O0
56-pin TSOP1
Standard Type
14mm x 16mm
I/O7
I/O6
I/O5
I/O4
N.C
Vcc
Vss
N.C
N.C
I/O3
I/O2
I/O1
I/O0
N.C
N.C
25
26
27
28
N.C
N.C
PACKAGE DIMENSIONS
56-PIN LEAD FREE PLASTIC THIN SMALL OUT-LINE PACKAGE TYPE(I)
Unit :mm
56-TSOP1
16.00±0.20
#1
#56
#28
#29
1.05±0.03
0.02 MIN
1.20 MAX
14.40±0.10
0~8°
(
)
0.50
0.45~0.75
Samsung Only
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FLASH MEMORY
K9WBG08U5A
K9F8G08U0A
PIN DESCRIPTION
Pin Name
Pin Function
DATA INPUTS/OUTPUTS
I/O0 ~ I/O7
CLE
ALE
CE
The I/O pins are used to input command, address and data, and to output data during read operations. The
I/O pins float to high-z when the chip is deselected or when the outputs are disabled.
COMMAND LATCH ENABLE
The CLE input controls the activating path for commands sent to the command register. When active high,
commands are latched into the command register through the I/O ports on the rising edge of the WE signal.
ADDRESS LATCH ENABLE
The ALE input controls the activating path for address to the internal address registers. Addresses are
latched on the rising edge of WE with ALE high.
CHIP ENABLE
The CE input is the device selection control. When the device is in the Busy state, CE high is ignored, and
the device does not return to standby mode in program or erase operation.
READ ENABLE
RE
The RE input is the serial data-out control, and when active drives the data onto the I/O bus. Data is valid
tREA after the falling edge of RE which also increments the internal column address counter by one.
WRITE ENABLE
WE
The WE input controls writes to the I/O port. Commands, address and data are latched on the rising edge
of the WE pulse.
WRITE PROTECT
WP
The WP pin provides inadvertent program/erase protection during power transitions. The internal high volt-
age generator is reset when the WP pin is active low.
READY/BUSY OUTPUT
The R/B output indicates the status of the device operation. When low, it indicates that a program, erase or
random read operation is in process and returns to high state upon completion. It is an open drain output
and does not float to high-z condition when the chip is deselected or when outputs are disabled.
R/B
POWER
Vcc
Vss
N.C
VCC is the power supply for device.
GROUND
NO CONNECTION
Lead is not internally connected.
NOTE : Connect all VCC and VSS pins of each device to common power supply outputs.
Do not leave VCC or VSS disconnected.
Samsung Only
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FLASH MEMORY
K9WBG08U5A
K9F8G08U0A
Figure 1. K9F8G08U0A Functional Block Diagram
VCC
VSS
8,192M + 436M Bit
NAND Flash
ARRAY
X-Buffers
A13 - A30
Latches
& Decoders
(4,096 + 218)Byte x 262,144
Y-Buffers
A0 - A12
Latches
& Decoders
Data Register & S/A
Y-Gating
Command
Command
Register
VCC
VSS
I/O Buffers & Latches
CE
RE
WE
Control Logic
& High Voltage
Generator
I/0 0
Output
Driver
Global Buffers
I/0 7
CLE ALE
WP
Figure 2. K9F8G08U0A Array Organization
1 Block = 64 Pages
(256K + 13.6K) Bytes
1 Page = (4K + 218)Bytes
1 Block = (4K + 218)B x 64 Pages
= (256K +13.6K) Bytes
1 Device = (4K + 218)B x 64 Pages x 4,096 Blocks
= 8,628 Mbits
256K Pages
(=4,096 Blocks)
8 bit
4K Bytes
218 Bytes
I/O 0 ~ I/O 7
Page Register
4K Bytes
218 Bytes
I/O 0
A0
I/O 1
A1
I/O 2
A2
I/O 3
A3
I/O 4 I/O 5
I/O 6
A6
I/O 7
1st Cycle
2nd Cycle
3rd Cycle
4th Cycle
5th Cycle
A4
A12
A17
A25
*L
A5
*L
A7
*L
Column Address
Row Address;
A8
A9
A10
A15
A23
*L
A11
A16
A24
*L
*L
A13
A21
A29
A14
A22
A30
A18
A26
*L
A19
A27
*L
A20
A28
*L
Page Address : A13 ~ A18
Plane Address : A19
Block Address : A20 ~ the last Address
NOTE : Column Address : Starting Address of the Register.
* L must be set to ’Low’.
* The device ignores any additional input of address cycles than required.
* Row Address consists of Page address (A13 ~ A18) & Plane address(A19) & Block address(A20 ~ the last Address)
Samsung Only
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FLASH MEMORY
K9WBG08U5A
K9F8G08U0A
Product Introduction
NAND Flash Memory has addresses multiplexed into 8 I/Os. This scheme dramatically reduces pin counts and allows system
upgrades to future densities by maintaining consistency in system board design. Command, address and data are all written through
I/O's by bringing WE to low while CE is low. Those are latched on the rising edge of WE. Command Latch Enable(CLE) and Address
Latch Enable(ALE) are used to multiplex command and address respectively, via the I/O pins. Some commands require one bus
cycle. For example, Reset Command, Status Read Command, etc. require just one cycle bus. Some other commands, like page read
and block erase and page program, require two cycles: one cycle for setup and the other cycle for execution.. Page Read and Page
Program need the same five address cycles following the required command input. In Block Erase operation, however, only the three
row address cycles are used. Device operations are selected by writing specific commands into the command register. Table 1
defines the specific commands of the K9F8G08U0A.
Table 1. Command Sets
Function
1st Set
00h
2nd Set
Read
30h
Read for Copy Back
Page Program
Copy-Back Program
Block Erase
00h
35h
80h
10h
85h
10h
60h
D0h
Random Data Input(1)
85h
-
Random Data Output(1)
05h
E0h
Two-Plane Read (3)
60h----60h
60h----60h
00h----05h
80h----11h
85h----11h
60h----60h
90h
30h
Two-Plane Read for Copy-Back(3)
Two-Plane Random Data Output (1) (3)
Two-Plane Page Program(2)
35h
E0h
81h----10h
Two-Plane Copy-Back Program(2)
Two-Plane Block Erase
81h----10h
D0h
Read ID
-
-
-
-
Read Status
Read Status 2
Reset
70h
O
O
O
F1h
FFh
NOTE : 1. Random Data Input/Output can be executed in a page.
2. Any command between 11h and 80h/85h is prohibited except 70h/F1h and FFh.
3. Two-Plane Random Data out must be used after Two-Plane Read operation
Caution : Any undefined command inputs are prohibited except for above command set of Table 1.
Samsung Only
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FLASH MEMORY
K9WBG08U5A
K9F8G08U0A
ABSOLUTE MAXIMUM RATINGS
Parameter
Symbol
VCC
Rating
-0.6 to + 4.6
Unit
Voltage on any pin relative to VSS
V
VIN
-0.6 to + 4.6
VI/O
-0.6 to Vcc+0.3 (<4.6V)
-10 to +125
K9XXG08UXX-XCB0
Temperature Under Bias
Storage Temperature
TBIAS
°C
K9XXG08UXX-XIB0
K9XXG08UXX-XCB0
K9XXG08UXX-XIB0
-40 to +125
TSTG
Ios
-65 to +150
5
°C
Short Circuit Current
mA
NOTE :
1. Minimum DC voltage is -0.6V on input/output pins. During transitions, this level may undershoot to -2.0V for periods <30ns.
Maximum DC voltage on input/output pins is VCC+0.3V which, during transitions, may overshoot to VCC+2.0V for periods <20ns.
2. Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to the conditions
as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
RECOMMENDED OPERATING CONDITIONS
(Voltage reference to GND, K9XXG08XXX-XCB0 :TA=0 to 70°C, K9XXG08XXX-XIB0:TA=-40 to 85°C)
3.3V
Parameter
Symbol
Unit
Min
2.7
0
Typ.
3.3
0
Max
3.6
0
Supply Voltage
Supply Voltage
VCC
VSS
V
V
Samsung Only
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FLASH MEMORY
K9WBG08U5A
K9F8G08U0A
DC AND OPERATING CHARACTERISTICS(Recommended operating conditions otherwise noted.)
3.3V
Parameter
Symbol
Test Conditions
Unit
Min
Typ
Max
Page Read with
tRC=30ns
CE=VIL, IOUT=0mA
ICC1
Serial Access
Program
Erase
Operating
Current
-
15
30
ICC2
ICC3
ISB1
ISB2
ILI
-
mA
-
CE=VIH, WP=0V/VCC
CE=VCC-0.2, WP=0V/VCC
VIN=0 to Vcc(max)
VOUT=0 to Vcc(max)
-
Stand-by Current(TTL)
Stand-by Current(CMOS)
Input Leakage Current
Output Leakage Current
Input High Voltage
-
-
10
-
1
-
50
-
±10
µA
ILO
-
-
±10
(1)
0.8 xVcc
-
Vcc +0.3
VIH
(1)
Input Low Voltage, All inputs
Output High Voltage Level
Output Low Voltage Level
Output Low Current(R/B)
VIL
-
-0.3
2.4
-
-
0.2 xVcc
V
VOH
VOL
IOH=-400µA
-
-
0.4
-
IOL=2.1mA
-
IOL(R/B) VOL=0.4V
8
10
mA
NOTE : 1. VIL can undershoot to -0.4V and VIH can overshoot to VCC +0.4V for durations of 20 ns or less.
2. Typical value is measured at Vcc=3.3V, TA=25°C. Not 100% tested.
3. The typical value of the K9WB08U5A’s ISB2 is 40µA and the maximum value is 200µA.
4. The maximum value of K9WB08U5A’s ILI and ILO is ±20µA
VALID BLOCK
Parameter
K9F8G08U0A
K9WBG08U5A
Symbol
NVB
Min
Typ.
Max
Unit
4,016
16,064
-
4,096
Blocks
Blocks
NVB
16,384
NOTE :
1. The device may include initial invalid blocks when first shipped. Additional invalid blocks may develop while being used. The number of valid blocks is
presented with both cases of invalid blocks considered. Invalid blocks are defined as blocks that contain one or more bad bits which cause status fail-
ure during program and erase operation. Do not erase or program factory-marked bad blocks. Refer to the attached technical notes for appropriate
management of invalid blocks.
2. The 1st block, which is placed on 00h block address, is guaranteed to be a valid block at the time of shipment
3. The number of valid blocks is on the basis of single plane operations, and this may be decreased with two plane operations.
* : Each K9F8G08U0A chip in the K9WBG08U5A has Maximum 80 invalid blocks.
Samsung Only
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FLASH MEMORY
K9WBG08U5A
K9F8G08U0A
AC TEST CONDITION
(K9XXG08XXA-XCB0 :TA=0 to 70°C, K9XXG08XXA-XIB0:TA=-40 to 85°C,
K9XXG08UXA: Vcc=2.7V ~ 3.3V,unless otherwise noted)
Parameter
Input Pulse Levels
Value
0V to Vcc
Input Rise and Fall Times
Input and Output Timing Levels
Output Load
5ns
Vcc/2
1 TTL GATE and CL=50pF
CAPACITANCE(TA=25°C, VCC=3.3V, f=1.0MHz)
Item
Symbol
CI/O
Test Condition
Min
Max
Unit
pF
-
-
-
-
8
5
8
5
Input/Output Capacitance
VIL=0V
CI/O(W)*
CIN
pF
pF
Input Capacitance
VIN=0V
CIN(W)*
pF
NOTE : 1. Capacitance is periodically sampled and not 100% tested.
2. C and C are tested at wafer level.
I/O(W)
IN(W)
3. K9WBG08U5A’s capacitance(I/O, Input) is 13pF.
MODE SELECTION
CLE
H
L
ALE
L
CE
L
WE
RE
H
WP
Mode
X
Command Input
Read
Mode
H
L
H
X
Address Input(5clock)
Command Input
H
L
L
L
H
H
Write
Mode
H
L
H
H
Address Input(5clock)
L
L
L
H
H
Data Input
L
L
L
H
X
X
X
X
X
X
Data Output
X
X
X
X
X
X
H
H
X
X
X
X
X
During Read(Busy)
During Program(Busy)
During Erase(Busy)
Write Protect
X
X
H
X
X
H
L
X(1)
X
X
(2)
X
Stand-by
0V/VCC
NOTE : 1. X can be VIL or VIH.
2. WP should be biased to CMOS high or CMOS low for standby.
Program / Erase Characteristics
Parameter
Symbol
Min
Typ
400
0.5
-
Max
Unit
µs
Program Time
tPROG
tDBSY
Nop
-
-
-
-
700
1
Dummy Busy Time for Two-Plane Program
Number of Partial Program Cycles in the Same Page
Block Erase Time
µs
1
cycle
ms
tBERS
1.5
10
NOTE: 1.Typical program time is measured at Vcc=3.3V, TA=25°C. Not 100% tested.
2. Typical Program time is defined as the time within which more than 50% of the whole pages are programed at 3.3V Vcc and 25°C temperature.
Samsung Only
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FLASH MEMORY
K9WBG08U5A
K9F8G08U0A
AC Timing Characteristics for Command / Address / Data Input
Parameter
Symbol
Min
15
5
Max
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
(1)
CLE Setup Time
CLE Hold Time
CE Setup Time
CE Hold Time
-
-
-
-
-
-
-
-
-
-
-
-
tCLS
tCLH
(1)
20
5
tCS
tCH
tWP
WE Pulse Width
ALE Setup Time
ALE Hold Time
Data Setup Time
Data Hold Time
Write Cycle Time
15
15
5
(1)
tALS
tALH
(1)
15
5
tDS
tDH
tWC
tWH
30
10
100
WE High Hold Time
(2)
Address to Data Loading Time
tADL
NOTES : 1. The transition of the corresponding control pins must occur only once while WE is held low
2. tADL is the time from the WE rising edge of final address cycle to the WE rising edge of first data cycle
AC Characteristics for Operation
Parameter
Data Transfer from Cell to Register
ALE to RE Delay
Symbol
tR
Min
-
Max
Unit
50
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
tAR
10
10
20
15
-
-
CLE to RE Delay
tCLR
tRR
-
Ready to RE Low
-
-
RE Pulse Width
tRP
WE High to Busy
tWB
100
WP High to WE Low
tWW
tRC
100
30
-
Read Cycle Time
-
RE Access Time
tREA
tCEA
tRHZ
tCHZ
tCSD
tRHOH
tRLOH
tREH
tIR
20
CE Access Time
-
25
RE High to Output Hi-Z
CE High to Output Hi-Z
CE High to ALE or CLE Don’t Care
RE High to Output Hold
RE Low to Output Hold
RE High Hold Time
-
100
-
30
0
-
15
5
-
-
10
0
-
Output Hi-Z to RE Low
RE High to WE Low
-
tRHW
tWHR
tRST
100
60
-
-
WE High to RE Low
-
5/10/500(1)
Device Resetting Time(Read/Program/Erase)
NOTE: 1. If reset command(FFh) is written at Ready state, the device goes into Busy for maximum 5µs.
Samsung Only
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FLASH MEMORY
K9WBG08U5A
K9F8G08U0A
NAND Flash Technical Notes
Initial Invalid Block(s)
Initial invalid blocks are defined as blocks that contain one or more initial invalid bits whose reliability is not guaranteed by Samsung.
The information regarding the initial invalid block(s) is called the initial invalid block information. Devices with initial invalid block(s)
have the same quality level as devices with all valid blocks and have the same AC and DC characteristics. An initial invalid
block(s) does not affect the performance of valid block(s) because it is isolated from the bit line and the common source line by a
select transistor. The system design must be able to mask out the initial invalid block(s) via address mapping. The 1st block, which
is placed on 00h block address, is guaranteed to be a valid block at the time of shipment
Identifying Initial Invalid Block(s)
All device locations are erased(FFh) except locations where the initial invalid block(s) information is written prior to shipping. The ini-
tial invalid block(s) status is defined by the 1st byte in the spare area. Samsung makes sure that either the 1st or 2nd page of every
initial invalid block has non-FFh data at the column address of 4,096. Since the initial invalid block information is also erasable in
most cases, it is impossible to recover the information once it has been erased. Therefore, the system must be able to recognize the
initial invalid block(s) based on the original initial invalid block information and create the initial invalid block table via the following
suggested flow chart(Figure 3). Any intentional erasure of the original initial invalid block information is prohibited.
Start
Set Block Address = 0
Increment Block Address
Check "FFh" at the column address 4,096
*
of the 1st and 2nd page in the block
No
Create (or update)
Check "FFh"
Initial
Invalid Block(s) Table
Yes
No
Last Block ?
Yes
End
Figure 3. Flow chart to create initial invalid block table
Samsung Only
13
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FLASH MEMORY
K9WBG08U5A
K9F8G08U0A
Error in write or read operation
Within its life time, additional invalid blocks may develop with NAND Flash memory. Refer to the qualification report for the actual
data. Block replacement should be done upon erase or program error.
Failure Mode
Detection and Countermeasure sequence
Status Read after Erase --> Block Replacement
Status Read after Program --> Block Replacement
Verify ECC -> ECC Correction
Erase Failure
Write
Read
Program Failure
Up to Eight Bit Failure
: Error Correcting Code --> RS Code or BCH Code etc.
Example) 8bit correction / 512-byte
ECC
Program Flow Chart
Start
Write 80h
Write Address
Write Data
Write 10h
Read Status Register
No
I/O 6 = 1 ?
or R/B = 1 ?
Yes
*
No
Program Error
I/O 0 = 0 ?
Yes
Program Completed
: If program operation results in an error, map out
the block including the page in error and copy the
target data to another block.
*
Samsung Only
14
Advance
FLASH MEMORY
K9WBG08U5A
K9F8G08U0A
NAND Flash Technical Notes (Continued)
Erase Flow Chart
Read Flow Chart
Start
Write 00h
Start
Write 60h
Write Block Address
Write Address
Write 30h
Write D0h
Read Data
Read Status Register
ECC Generation
No
I/O 6 = 1 ?
or R/B = 1 ?
No
Verify ECC
Reclaim the Error
Yes
*
No
Yes
Erase Error
I/O 0 = 0 ?
Page Read Completed
Yes
Erase Completed
: If erase operation results in an error, map out
the failing block and replace it with another block.
*
Block Replacement
Block A
1st
{
(n-1)th
1
nth
an error occurs.
(page)
Buffer memory of the controller.
Block B
1st
2
{
(n-1)th
nth
(page)
* Step1
When an error happens in the nth page of the Block ’A’ during erase or program operation.
* Step2
Copy the data in the 1st ~ (n-1)th page to the same location of another free block. (Block ’B’)
* Step3
Then, copy the nth page data of the Block ’A’ in the buffer memory to the nth page of the Block ’B’.
* Step4
Do not erase or program Block ’A’ by creating an ’invalid block’ table or other appropriate scheme.
Samsung Only
15
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FLASH MEMORY
K9WBG08U5A
K9F8G08U0A
Addressing for program operation
Within a block, the pages must be programmed consecutively from the LSB (least significant bit) page of the block to MSB (most sig-
nificant bit) pages of the block. Random page address programming is prohibited. In this case, the definition of LSB page is the LSB
among the pages to be programmed. Therefore, LSB doesn’t need to be page 0.
(64)
(64)
Page 64
Page 31
Page 64
Page 31
:
:
(1)
:
(32)
:
(3)
(2)
(1)
Page 2
Page 1
Page 0
(3)
(32)
(2)
Page 2
Page 1
Page 0
Data register
Data register
From the LSB page to MSB page
DATA IN: Data (1)
Ex.) Random page program (Prohibition)
Data (64)
DATA IN: Data (1)
Data (64)
Samsung Only
16
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FLASH MEMORY
K9WBG08U5A
K9F8G08U0A
System Interface Using CE don’t-care.
For an easier system interface, CE may be inactive during the data-loading or serial access as shown below. The internal 4,314byte
data registers are utilized as separate buffers for this operation and the system design gets more flexible. In addition, for voice or
audio applications which use slow cycle time on the order of µ-seconds, de-activating CE during the data-loading and serial access
would provide significant savings in power consumption.
Figure 4. Program Operation with CE don’t-care.
CLE
CE don’t-care
CE
WE
ALE
I/Ox
80h
Address(5Cycles)
tCS
Data Input
Data Input
10h
tCH
tCEA
CE
CE
tREA
tWP
RE
WE
out
I/O0~7
Figure 5. Read Operation with CE don’t-care.
CLE
CE
CE don’t-care
RE
ALE
tR
R/B
WE
I/Ox
Data Output(serial access)
00h
Address(5Cycle)
30h
Samsung Only
17
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FLASH MEMORY
K9WBG08U5A
K9F8G08U0A
Command Latch Cycle
CLE
tCLH
tCH
tCLS
tCS
CE
tWP
WE
tALS
tALH
ALE
I/Ox
tDH
tDS
Command
Address Latch Cycle
tCLS
CLE
tCS
tWC
tWC
tWC
tWC
CE
tWP
tWP
tWP
tWP
WE
tWH
tALH
tWH
tWH
tALH
tWH
tALS tALH
tALS tALH
tALS
tALH
tDH
tALS
tALS
ALE
I/Ox
tDH
tDH
tDH
tDH
tDS
tDS
tDS
tDS
tDS
Col. Add2
Row Add1
Col. Add1
Row Add2
Row Add3
Samsung Only
18
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FLASH MEMORY
K9WBG08U5A
K9F8G08U0A
Input Data Latch Cycle
tCLH
CLE
tCH
CE
tWC
ALE
tALS
tWP
tWP
tWP
WE
tWH
tDH
tDH
tDH
tDS
tDS
tDS
I/Ox
DIN final
DIN 0
DIN 1
* Serial Access Cycle after Read(CLE=L, WE=H, ALE=L)
tRC
CE
tCHZ
tREH
tREA
tREA
tREA
RE
tRHZ
tRHZ
tRHOH
I/Ox
Dout
Dout
Dout
tRR
R/B
NOTES : 1.Transition is measured at ±200mV from steady state voltage with load.
This parameter is sampled and not 100% tested.
2. tRLOH is valid when frequency is higher than 20MHz.
tRHOH starts to be valid when frequency is lower than 20MHz.
Samsung Only
19
Advance
FLASH MEMORY
K9WBG08U5A
K9F8G08U0A
Serial Access Cycle after Read(EDO Type, CLE=L, WE=H, ALE=L)
CE
tRC
tCHZ
tRP
tREH
RE
tRHZ
tREA
tCEA
tREA
tRLOH
tRHOH
I/Ox
R/B
Dout
Dout
tRR
NOTES : 1. Transition is measured at ±200mV from steady state voltage with load.
This parameter is sampled and not 100% tested.
2. tRLOH is valid when frequency is higher than 20MHz.
tRHOH starts to be valid when frequency is lower than 20MHz.
Status Read Cycle
tCLR
CLE
CE
tCLS
tCLH
tCS
tCH
tWP
WE
tCEA
tCHZ
tWHR
RE
tRHZ
tDH
tREA
tDS
tIR
tRHOH
I/Ox
70h/F1h
Status Output
Samsung Only
20
Advance
FLASH MEMORY
K9WBG08U5A
K9F8G08U0A
Read Operation
tCLR
CLE
CE
tWC
WE
ALE
RE
tWB
tAR
tRHZ
tR
tRC
tRR
Col. Add2 Row Add1 Row Add2
00h
Col. Add1
30h
Dout N
Dout N+1
Dout M
Row Add3
I/Ox
Column Address
Row Address
Busy
R/B
Read Operation(Intercepted by CE)
tCLR
CLE
CE
tCSD
WE
ALE
RE
tCHZ
tWB
tAR
tR
tRC
tRR
Row Add2 Row Add3
Dout N+2
00h
Col. Add1 Col. Add2 Row Add1
30h
Dout N+1
Dout N
I/Ox
R/B
Row Address
Column Address
Busy
Samsung Only
21
Advance
FLASH MEMORY
K9WBG08U5A
K9F8G08U0A
Samsung Only
22
Advance
FLASH MEMORY
K9WBG08U5A
K9F8G08U0A
Samsung Only
23
Advance
FLASH MEMORY
K9WBG08U5A
K9F8G08U0A
Page Program Operation
CLE
CE
tWC
tWC
tWC
WE
ALE
RE
tPROG
tWHR
tWB
tADL
Din
N
Din
M
Co.l Add1 Col. Add2 Row Add1 Row Add2 Row Add3
80h
I/Ox
R/B
10h
70h
I/O0
SerialData
Input Command
Program
Command
1 up to m Byte
Serial Input
Read Status
Command
Column Address
Row Address
I/O
0
=0 Successful Program
=1 Error in Program
I/O0
NOTES : tADL is the time from the WE rising edge of final address cycle to the WE rising edge of first data cycle.
Samsung Only
24
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FLASH MEMORY
K9WBG08U5A
K9F8G08U0A
≈
≈
≈ ≈
≈ ≈
≈
Samsung Only
25
Advance
FLASH MEMORY
K9WBG08U5A
K9F8G08U0A
≈
≈ ≈
≈ ≈
≈
Samsung Only
26
Advance
FLASH MEMORY
K9WBG08U5A
K9F8G08U0A
≈
≈ ≈
≈
≈
≈ ≈
≈
Samsung Only
27
Advance
FLASH MEMORY
K9WBG08U5A
K9F8G08U0A
Block Erase Operation
CLE
CE
tWC
WE
tBERS
tWB
tWHR
ALE
RE
I/Ox
Row Add1 Row Add2 Row Add3
60h
D0h
70h
I/O 0
Row Address
Busy
R/B
Auto Block Erase
Setup Command
Erase Command
I/O
0
=0 Successful Erase
Read Status I/O
Command
0=1 Error in Erase
Samsung Only
28
Advance
FLASH MEMORY
K9WBG08U5A
K9F8G08U0A
Samsung Only
29
Advance
FLASH MEMORY
K9WBG08U5A
K9F8G08U0A
Read ID Operation
CLE
CE
WE
ALE
RE
tAR
tREA
00h
Device
Code
I/Ox
4th cyc.
5th cyc.
6th cyc.
3rd cyc.
ECh
90h
Read ID Command
Maker Code Device Code
Address 1cycle
Device
Device Code (2nd Cycle)
D3h
3rd Cycle
4th Cycle
19h
5th Cycle
34h
6th Cycle
K9F8G08U0A
K9WBG08U5A
10h
41h
Same as K9F8G08U0A in it
Samsung Only
30
Advance
FLASH MEMORY
K9WBG08U5A
K9F8G08U0A
ID Definition Table
90 ID : Access command = 90H
Description
1st Byte
Maker Code
2nd Byte
3rd Byte
4th Byte
5th Byte
6th Byte
Device Code
Internal Chip Number, Cell Type, Number of Simultaneously Programmed Pages, Etc.
Page Size, Block Size,Redundant Area Size.
Plane Number, ECC Level, Organization.
Device Technology, EDO, Interface.
3rd ID Data
Description
I/O7
I/O6
I/O5 I/O4
I/O3 I/O2
I/O1 I/O0
1
2
4
8
0
0
1
1
0
1
0
1
Internal Chip Number
2 Level Cell
4 Level Cell
8 Level Cell
16 Level Cell
0
0
1
1
0
1
0
1
Cell Type
1
2
4
8
0
0
1
1
0
1
0
1
Number of
Simultaneously
Programmed Pages
Interleave Program
Between multiple chips
Not Support
Support
0
1
Not Support
Support
0
1
Cache Program
4th ID Data
Description
I/O7
I/O6
I/O5 I/O4
I/O3
I/O2
I/O1 I/O0
2KB
4KB
8KB
Reserved
0
0
1
1
0
1
0
1
Page Size
(w/o redundant area )
128KB
256KB
512KB
1MB
Reserved
Reserved
Reserved
Reserved
0
0
0
0
1
1
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Block Size
(w/o redundant area )
0
0
1
1
Reserved
128B
218B
Reserved
Reserved
Reserved
Reserved
Reserved
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Redundant Area Size
( byte / Page Size)
Samsung Only
31
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FLASH MEMORY
K9WBG08U5A
K9F8G08U0A
5th ID Data
Description
I/O7
I/O6 I/O5 I/O4
I/O3 I/O2
I/O1
I/O0
1
2
4
8
0
0
1
1
0
1
0
1
Plane Number
1bit / 512B
2bit / 512B
4bit / 512B
8bit / 512B
16bit / 512B
Reserved
Reserved
Reserved
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
ECC Level
Reserved
0
0
0
6th ID Data
Description
I/O7
I/O6
I/O5 I/O4 I/O3
I/O2 I/O1 I/O0
50nm
40nm
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
0
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Device Version
Not Support
Support
0
1
EDO
SDR
DDR
0
1
Interface
Reserved
0
0
0
Samsung Only
32
Advance
FLASH MEMORY
K9WBG08U5A
K9F8G08U0A
Device Operation
PAGE READ
Page read is initiated by writing 00h-30h to the command register along with five address cycles. After initial power up, 00h command
is latched. Therefore only five address cycles and 30h command initiates that operation after initial power up. The 4,314 bytes of data
within the selected page are transferred to the data registers via data registers in less than 50µs(tR). The system controller can detect
the completion of this data transfer(tR) by analyzing the output of R/B pin. Once the data in a page is loaded into the data registers,
they may be read out in 30ns cycle time by sequentially pulsing RE. The repetitive high to low transitions of the RE clock make the
device output the data starting from the selected column address up to the last column address.
The device may output random data in a page instead of the consecutive sequential data by writing random data output command.
The column address of next data, which is going to be out, may be changed to the address which follows random data output com-
mand. Random data output can be operated multiple times regardless of how many times it is done in a page.
Figure 6. Read Operation
CLE
CE
WE
ALE
tR
R/B
RE
I/Ox
00h
Address(5Cycle)
30h
Data Output(Serial Access)
Col. Add.1,2 & Row Add.1,2,3
Data Field
Spare Field
Samsung Only
33
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FLASH MEMORY
K9WBG08U5A
K9F8G08U0A
Figure 7. Random Data Output In a Page
tR
R/B
RE
Address
5Cycles
Address
2Cycles
Data Output
Data Output
E0h
30h/35h
00h
05h
I/Ox
Col. Add.1,2 & Row Add.1,2,3
Col. Add.1,2
Data Field
Data Field
Spare Field
Spare Field
Samsung Only
34
Advance
FLASH MEMORY
K9WBG08U5A
K9F8G08U0A
TWO-PLANE PAGE READ
Two-Plane Page Read is an extension of Page Read, for a single plane with 4,314 byte data registers. Since the device is equipped
with two memory planes, activating the two sets of 4,314 byte data registers enables a random read of two pages. Two-Plane Page
Read is initiated by repeating command 60h followed by three address cycles twice. In this case, only same page of same block
can be selected from each plane.
After Read Confirm command(30h) the 8,628 bytes of data within the selected two page are transferred to the data registers via data
registers in less than 50us(tR). The system controller can detect the completion of data transfer(tR) by monitoring the output of R/B
pin.
Once the data is loaded into the data registers, the data output of first plane can be read out by issuing command 00h with Five
Address Cycles, command 05h with two column address and finally E0h. The data output of second plane can be read out using the
identical command sequences.
Figure 9. Two-Plane Page Read Operation with Two-Plane Random Data Out
tR
R/B
60h
30h
I/OX
60h
Address (3 Cycle)
Row Add.1,2,3
Address (3 Cycle)
Row Add.1,2,3
page address : Page M
plane address: Fixed ’Low’
block address: Block N
page address : Page M
plane address: Fixed ’High’
block address : Block N
1
2
R/B
I/Ox
E0h
Data Output
Address (2 Cycle)
Col. Add.1,2
05h
00h
Address (5 Cycle)
Col. Add. 1,2 & Row Add.1,2,3
column address : Fixed ’Low’
page address : Page M
column address : Valid
1
plane address: Fixed ’Low’
block address : Block N
R/B
I/Ox
E0h
Data Output
Address (2 Cycle)
Col. Add.1,2
05h
00h
Address (5 Cycle)
Col. Add. 1,2 & Row Add.1,2,3
column address : Fixed ’Low’
page address : Page M
column address : Valid
2
plane address: Fixed ’High’
block address : Block N
Samsung Only
35
Advance
FLASH MEMORY
K9WBG08U5A
K9F8G08U0A
PAGE PROGRAM
The device is programmed basically on a page basis, and the number of consecutive partial page programming operation within the
same page without an intervening erase operation must not exceed 1 time for the page. The addressing should be done in sequential
order in a block. A page program cycle consists of a serial data loading period in which up to 4,314bytes of data may be loaded into
the data registers, followed by a non-volatile programming period where the loaded data is programmed into the appropriate cell.
The serial data loading period begins by inputting the Serial Data Input command(80h), followed by the five cycle address inputs and
then serial data loading. The words other than those to be programmed do not need to be loaded. The device supports random data
input in a page. The column address for the next data, which will be entered, may be changed to the address which follows random
data input command(85h). Random data input may be operated multiple times regardless of how many times it is done in a page.
The Page Program confirm command(10h) initiates the programming process. Writing 10h alone without previously entering the
serial data will not initiate the programming process. The internal write state controller automatically executes the algorithms and tim-
ings necessary for program and verify, thereby freeing the system controller for other tasks. Once the program process starts, the
Read Status Register command may be entered to read the status register. The system controller can detect the completion of a pro-
gram cycle by monitoring the R/B output, or the Status bit(I/O 6) of the Status Register. Only the Read Status command and Reset
command are valid while programming is in progress. When the Page Program is complete, the Write Status Bit(I/O 0) may be
checked. The internal write verify detects only errors for "1"s that are not successfully programmed to "0"s. The command register
remains in Read Status command mode until another valid command is written to the command register.
Figure 11. Program & Read Status Operation
tPROG
R/B
"0"
Pass
80h
Address & Data Input
I/O0
Fail
I/Ox
10h
70h
Col. Add.1,2 & Row Add.1,2,3
Data
"1"
Figure 12. Random Data Input In a Page
tPROG
R/B
"0"
Pass
80h
Address & Data Input
Address & Data Input
I/O0
I/Ox
85h
10h
70h
Col. Add.1,2
Data
Col. Add.1,2 & Row Add1,2,3
Data
"1"
Fail
Samsung Only
36
Advance
FLASH MEMORY
K9WBG08U5A
K9F8G08U0A
COPY-BACK PROGRAM
Copy-Back program with Read for Copy-Back is configured to quickly and efficiently rewrite data stored in one page without data re-
loading when the bit error is not in data stored. Since the time-consuming re-loading cycles are removed, the system performance is
improved. The benefit is especially obvious when a portion of a block is updated and the rest of the block also needs to be copied to
the newly assigned free block. Copy-Back operation is a sequential execution of Read for Copy-Back and of copy-back program with
the destination page address. A read operation with "35h" command and the address of the source page moves the whole 4,314-byte
data into the internal data buffer. A bit error is checked by sequential reading the data output. In the case where there is no bit error,
the data do not need to be reloaded. Therefore Copy-Back program operation is initiated by issuing Page-Copy Data-Input command
(85h) with destination page address. Actual programming operation begins after Program Confirm command (10h) is issued. Once
the program process starts, the Read Status Register command (70h) may be entered to read the status register. The system control-
ler can detect the completion of a program cycle by monitoring the R/B output, or the Status bit(I/O 6) of the Status Register. When
the Copy-Back Program is complete, the Write Status Bit(I/O 0) may be checked(Figure 13 & Figure 14). The command register
remains in Read Status command mode until another valid command is written to the command register.
During copy-back program, data modification is possible using random data input command (85h) as shown in Figure14.
Figure 13. Page Copy-Back Program Operation
tR
tPROG
R/B
I/Ox
"0"
Data Output
Add.(5Cycles)
Add.(5Cycles)
Pass
00h
35h
85h
10h
70h
I/O0
Col. Add.1,2 & Row Add.1,2,3
Destination Address
Col. Add.1,2 & Row Add.1,2,3
Source Address
"1"
Fail
Note: 1. Copy-Back Program operation is allowed only within the same memory plane.
Figure 14. Page Copy-Back Program Operation with Random Data Input
tPROG
tR
R/B
Add.(5Cycles)
I/Ox
00h
35h
Data Output
85h Add.(5Cycles)
Add.(2Cycles)
Col. Add.1,2
10h
70h
Data 85h
Data
Col. Add.1,2 & Row Add.1,2,3
Source Address
Col. Add.1,2 & Row Add.1,2,3
Destination Address
There is no limitation for the number of repetition.
Samsung Only
37
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FLASH MEMORY
K9WBG08U5A
K9F8G08U0A
TWO-PLANE PAGE PROGRAM
Two-Plane Page Program is an extension of Page Program, for a single plane with 4,314 byte data registers. Since the device is
equipped with two memory planes, activating the two sets of 4,314 byte data registers enables a simultaneous programming of two
pages.
After writing the first set of data up to 4,314 byte into the selected data registers, Dummy Page Program command (11h) instead of
actual Page Program command (10h) is inputted to finish data-loading of the first plane. Since no programming process is involved,
R/B remains in Busy state for a short period of time(tDBSY). Read Status command (70h) may be issued to find out when the device
returns to Ready state by polling the Ready/Busy status bit(I/O 6). Then the next set of data for the other plane is inputted after the
81h command and address sequences. After inputting data for the last plane, actual True Page Program(10h) instead of dummy
Page Program command (11h) must be followed to start the programming process. The operation of R/B and Read Status is the
same as that of Page Program. Although two planes are programmed simultaneously, pass/fail is not available for each page when
the program operation completes. Status bit of I/O 0 is set to "1" when any of the pages fails.
Restriction in addressing with Two-Plane Page Program is shown is Figure16.
Figure 16. Two-Plane Page Program
tDBSY
tPROG
R/B
"0"
I/O0 ~ 7
Address & Data Input
Address & Data Input
80h
11h
70h/F1h
Pass
81h
10h
I/O0
Note*2
"1"
Fail
column address : Valid
page address : Page M
plane address: Fixed ’Low’
block address: Block N
column address : Valid
page address : Page M
plane address: Fixed ’High’
block address: Block N
NOTE :1. It is noticeable that same row address except for A19 is applied to the two blocks
2. Any command between 11h and 81h is prohibited except 70h/F1h and FFh.
80h
11h
81h
10h
Data
Input
Plane 0
Plane 1
(2048 Block)
(2048 Block)
Block 0
Block 2
Block 1
Block 3
Block 4092
Block 4094
Block 4093
Block 4095
Samsung Only
38
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FLASH MEMORY
K9WBG08U5A
K9F8G08U0A
TWO-PLANE COPY-BACK PROGRAM
Two-Plane Copy-Back Program is an extension of Copy-Back Program, for a single plane with 4314 byte data registers. Since the
device is equipped with two memory planes, activating the two sets of 4314 byte data registers enables a simultaneous programming
of two pages.
Figure 17. Two-Plane Copy-Back Program Operation
tR
R/B
60h
35h
I/OX
60h
Address (3 Cycle)
Row Add.1,2,3
Address (3 Cycle)
Row Add.1,2,3
page address : Page M
plane address: Fixed ’Low’
block address: Block N
page address : Page M
plane address: Fixed ’High’
block address: Block N
1
2
3
R/B
I/Ox
E0h
Data Output
Address (2 Cycle)
05h
00h
Address (5 Cycle)
Col. Add. 1,2 & Row Add.1,2,3
Col. Add.1,2
column address: Fixed ’Low’
page address : Page M
plane address: Fixed ’Low’
block address: Block N
column address: Valid
1
R/B
I/Ox
E0h
Data Output
Address (2 Cycle)
05h
00h
Address (5 Cycle)
Col. Add. 1,2 & Row Add.1,2,3
Col. Add.1,2
column address: Fixed ’Low’
page address : Page M
plane address: Fixed ’High’
block address: Block N
column address: Valid
2
tPROG
tDBSY
Note2
R/B
I/Ox
Add.(5Cycles)
11h
Add.(5Cycles)
10h
85h
81h
70h/F1h
Col. Add.1,2 & Row Add.1,2,3
Destination Address
Col. Add.1,2 & Row Add.1,2,3
Destination Address
3
column address: Fixed ’Low’
page address : Page M
plane address: Fixed ’Low’
block address: Block N
column address: Fixed ’Low’
page address : Page M
plane address: Fixed ’High’
block address: Block N
Samsung Only
39
Advance
FLASH MEMORY
K9WBG08U5A
K9F8G08U0A
Plane0
Plane1
Source page
Source page
(1) : Two-Plane Read for Copy Back
Target page
Target page
(2) : Two-Plane Random Data Out
(3) : Two-Plane Copy-Back Program
(1)
(3)
(1)
(3)
Data Field
Data Field
Spare Field
Spare Field
(2)
(2)
Note: 1. Copy-Back Program operation is allowed only within the same memory plane.
2. Any command between 11h and 81h is prohibited except 70h/F1h and FFh.
Samsung Only
40
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FLASH MEMORY
K9WBG08U5A
K9F8G08U0A
Figure 18. Two-Plane Copy-Back Program Operation with Random Data Input
tR
R/B
60h
35h
I/OX
60h
Address (3 Cycle)
Row Add.1,2,3
Address (3 Cycle)
Row Add.1,2,3
page address : Page M
plane address: Fixed ’Low’
block address: Block N
page address : Page M
plane address: Fixed ’High’
block address: Block N
1
2
3
R/B
I/Ox
E0h
Data Output
Address (2 Cycle)
05h
00h
Address (5 Cycle)
Col. Add. 1,2 & Row Add.1,2,3
Col. Add.1,2
column address: Fixed ’Low’
page address : Page M
plane address: Fixed ’Low’
block address: Block N
column address: Valid
1
R/B
I/Ox
E0h
Data Output
Address (2 Cycle)
05h
00h
Address (5 Cycle)
Col. Add. 1,2 & Row Add.1,2,3
Col. Add.1,2
2
column address: Valid
column address: Fixed ’Low’
page address : Page M
plane address: Fixed ’High’
block address: Block N
tDBSY
R/B
I/Ox
Add.(5Cycles)
11h
Data
85h
Data
Add.(2Cycles)
Col. Add.1,2
85h
Note2
Col. Add.1,2 & Row Add.1,2,3
Destination Address
4
3
column address: Valid
column address: Valid
page address : Page M
plane address: Fixed ’Low’
block address: Block N
tPROG
R/B
I/Ox
Add.(5Cycles)
10h
Data
85h
Data
Add.(2Cycles)
Col. Add.1,2
81h
Col. Add.1,2 & Row Add.1,2,3
Destination Address
4
column address: Valid
page address : Page M
plane address: Fixed ’High’
block address: Block N
column address: Valid
Note: 1. Copy-Back Program operation is allowed only within the same memory plane.
2. Any command between 11h and 81h is prohibited except 70h/F1h and FFh.
Samsung Only
41
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FLASH MEMORY
K9WBG08U5A
K9F8G08U0A
BLOCK ERASE
The Erase operation is done on a block basis. Block address loading is accomplished in three cycles initiated by an Erase Setup
command(60h). Only Plane address and Block address are valid while Page address is ignored. The Erase Confirm command(D0h)
following the block address loading initiates the internal erasing process. This two-step sequence of setup followed by execution
command ensures that memory contents are not accidentally erased due to external noise conditions.
At the rising edge of WE after the erase confirm command input, the internal write controller handles erase and erase-verify. When
the erase operation is completed, the Write Status Bit(I/O 0) may be checked. Figure 20 details the sequence.
Figure 20. Block Erase Operation
tBERS
R/B
"0"
Pass
60h
I/O0
70h
Address Input(3Cycle)
Row Add 1,2,3
I/Ox
D0h
"1"
TWO-PLANE BLOCK ERASE
Basic concept of Two-Plane Block Erase operation is identical to that of Two-Plane Page Program. Up to two blocks, one from each
plane can be simultaneously erased. Standard Block Erase command sequences (Block Erase Setup command(60h) followed by
three address cycles) may be repeated up to twice for erasing up to two blocks. Only one block should be selected from each plane.
The Erase Confirm command(D0h) initiates the actual erasing process. The completion is detected by monitoring R/B pin or Ready/
Busy status bit (I/O 6).
Figure 21. Two-Plane Block Erase Operation
tBERS
R/B
"0"
60h
D0h
70h/F1h
Pass
I/OX
60h
Address (3 Cycle)
Row Add 1,2,3
Address (3 Cycle)
Row Add 1,2,3
I/O0
"1"
Fail
page address : Fixed ’Low’
plane address :Fixed ’Low’
block address : Block N
page address : Fixed ’Low’
plane address : Fixed ’High’
block address : Block N
Samsung Only
42
Advance
FLASH MEMORY
K9WBG08U5A
K9F8G08U0A
READ STATUS
The device contains a Status Register which may be read to find out whether program or erase operation is completed, and whether
the program or erase operation is completed successfully. After writing 70h or F1h command to the command register, a read cycle
outputs the content of the Status Register to the I/O pins on the falling edge of CE or RE, whichever occurs last. This two line control
allows the system to poll the progress of each device in multiple memory connections even when R/B pins are common-wired. RE or
CE does not need to be toggled for updated status. Refer to Table 2 for specific 70h Status Register definitions and Table 3 for spe-
cific F1h status Register definitions. The command register remains in Status Read mode until further commands are issued to it.
Therefore, if the status register is read during a random read cycle, the read command(00h) should be given before starting read
cycles.
Table 2. Status Register Definition for 70h Command
I/O
Page Program
Pass/Fail
Not use
Block Erase
Pass/Fail
Not use
Read
Not use
Definition
Fail : "1"
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
Pass : "0"
Not use
Don’t -cared
Don’t -cared
Don’t -cared
Don’t -cared
Don’t -cared
Busy : "0"
Not use
Not use
Not use
Not Use
Not Use
Not Use
Not Use
Not Use
Not Use
Not Use
Not Use
Not Use
Ready/Busy
Write Protect
Ready/Busy
Write Protect
Ready/Busy
Write Protect
Ready : "1"
Protected : "0"
Not Protected : "1"
NOTE : 1. I/Os defined ’Not use’ are recommended to be masked out when Read Status is being executed.
Table 3. F1h Read Status Register Definition
I/O No.
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
Page Program
Chip Pass/Fail
Plane0 Pass/Fail
Plane1 Pass/Fail
Not Use
Block Erase
Chip Pass/Fail
Plane0 Pass/Fail
Plane1 Pass/Fail
Not Use
Read
Not use
Definition
Pass : "0"
Fail : "1"
Fail : "1"
Fail : "1"
Not use
Pass : "0"
Not use
Pass : "0"
Not Use
Don’t -cared
Don’t -cared
Don’t -cared
Busy : "0"
Not Use
Not Use
Not Use
Not Use
Not Use
Not Use
Ready/Busy
Write Protect
Ready/Busy
Write Protect
Ready/Busy
Write Protect
Ready : "1"
Protected : "0"
Not Protected : "1"
NOTE : 1. I/Os defined ’Not use’ are recommended to be masked out when Read Status is being executed.
Samsung Only
43
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FLASH MEMORY
K9WBG08U5A
K9F8G08U0A
Read ID
The device contains a product identification mode, initiated by writing 90h to the command register, followed by an address input of
00h. Six read cycles sequentially output the manufacturer code(ECh), the device code, 3rd, 4th, 5th and 6th cycle ID respectively.
The command register remains in Read ID mode until further commands are issued to it. Figure 22 shows the operation sequence.
Figure 22. Read ID Operation
tCLR
CLE
CE
tCEA
WE
ALE
RE
tAR
tWHR
tREA
Device
Code
I/OX
90h
ECh
3rd Cyc.
4th Cyc.
5th Cyc.
6th Cyc.
00h
Address. 1cycle
Maker code
Device code
Device
Device Code (2nd Cycle)
3rd Cycle
4th Cycle
5th Cycle
6th Cycle
K9F8G08U0A
K9WBG08U5A
D3h
10h
19h
34h
41h
Same as K9F8G08U0A in it
RESET
The device offers a reset feature, executed by writing FFh to the command register. When the device is in Busy state during random
read, program or erase mode, the reset operation will abort these operations. The contents of memory cells being altered are no
longer valid, as the data will be partially programmed or erased. The command register is cleared to wait for the next command, and
the Status Register is cleared to value C0h when WP is high. Refer to Table 4 for device status after reset operation. If the device is
already in reset state a new reset command will be accepted by the command register. The R/B pin changes to low for tRST after the
Reset command is written. Refer to Figure 23 below.
Figure 23. RESET Operation
tRST
R/B
I/OX
FFh
Table 4. Device Status
After Power-up
After Reset
Operation mode
00h Command is latched
Waiting for next command
Samsung Only
44
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FLASH MEMORY
K9WBG08U5A
K9F8G08U0A
READY/BUSY
The device has a R/B output that provides a hardware method of indicating the completion of a page program, erase and random
read completion. The R/B pin is normally high but transitions to low after program or erase command is written to the command regis-
ter or random read is started after address loading. It returns to high when the internal controller has finished the operation. The pin is
an open-drain driver thereby allowing two or more R/B outputs to be Or-tied. Because pull-up resistor value is related to tr(R/B) and
current drain during busy(ibusy) , an appropriate value can be obtained with the following reference chart(Fig.24). Its value can be
determined by the following guidance.
Rp
ibusy
VCC
3.3V device - VOL : 0.4V, VOH : 2.4V
Ready Vcc
R/B
VOH
open drain output
CL
VOL
Busy
tf
tr
GND
Device
Figure 24. Rp vs tr ,tf & Rp vs ibusy
@ Vcc = 3.3V, Ta = 25°C , CL = 50pF
2.4
200
Ibusy
200n
2m
1m
150
1.2
100
100n
0.8
tr
0.6
50
3.6
3.6
2K
3.6
3K
3.6
tf
4K
1K
Rp(ohm)
Rp value guidance
3.2V
VCC(Max.) - VOL(Max.)
Rp(min, 3.3V part) =
=
IOL + ΣIL
8mA + ΣIL
where IL is the sum of the input currents of all devices tied to the R/B pin.
Rp(max) is determined by maximum permissible limit of tr
Samsung Only
45
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FLASH MEMORY
K9WBG08U5A
K9F8G08U0A
DATA PROTECTION & POWER UP SEQUENCE
The device internal initialization starts after the power supply reaches an appropriate level in the power on sequence. During the ini-
tialization the device Ready/Busy signal indicates the Busy state as shown in the figure 25. In this time period, the acceptable com-
mand is 70h(F1h).
The device is designed to offer protection from any involuntary program/erase during power-transitions. An internal voltage detector
disables all functions whenever Vcc is below about 2V(3.3V device). WP pin provides hardware protection and is recommended to
be kept at VIL during power-up and power-down. The two step command sequence for program/erase provides additional software
protection.
Figure 25. AC Waveforms for Power Transition
~ 2.3V
~ 2.3V
VCC
High
WP
WE
Don’t care
Operation
5 ms max
100µs
Ready/Busy
Invalid
Note :During the initialization, the device consumes a maximum current of 30mA (ICC1)
Don’t care
Samsung Only
46
Advance
FLASH MEMORY
K9WBG08U5A
K9F8G08U0A
WP AC Timing guide
Enabling WP during erase and program busy is prohibited. The erase and program operations are enabled and disabled as follows:
Figure B-1. Program Operation
1. Enable Mode
WE
I/O
80h
10h
WP
R/B
tww(min.100ns)
2. Disable Mode
WE
I/O
80h
10h
WP
R/B
tww(min.100ns)
Figure B-2. Erase Operation
1. Enable Mode
WE
I/O
60h
D0h
WP
R/B
tww(min.100ns)
2. Disable Mode
WE
I/O
60h
D0h
WP
R/B
tww(min.100ns)
Samsung Only
47
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