KBC00B7A0M-D405 [SAMSUNG]
Memory Circuit, Flash+PSRAM+SRAM, Hybrid, PBGA111;
| 型号： | KBC00B7A0M-D405 |
| 厂家： | 
SAMSUNG |
| 描述： | Memory Circuit, Flash+PSRAM+SRAM, Hybrid, PBGA111 静态存储器 内存集成电路 |
| 文件： | 总46页 (文件大小：692K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Preliminary
MCP MEMORY
KBC00B7A0M
Document Title
Multi-Chip Package MEMORY
256M Bit (16Mx16) Nand Flash Memory / 64M Bit (4Mx16) UtRAM / 64M Bit (4Mx16) UtRAM / 8M Bit (512Kx16) SRAM
Revision History
Revision No. History
Draft Date
Remark
0.0
Initial draft.
May 19, 2003
Preliminary
0.1
Revised(SRAM)
June 27, 2003
Preliminary
- Changed Speed Bins from 70ns to 55ns.
- Added ISB1(Typ) 5.0mA in DC AND OPERATING CHARACTERISTIC.
- Changed Output load from CL=100pF+1TTL to CL=30pF+1TTL in AC
OPERATING CONDITIONS.
- Added IDR(Typ) 1.0mA in DATA RETENTION CHARACTERISTICS.
- Changed ball name from Vccqs to Vccs in Pin Configuration.
0.11
1.0
Revised
- Added Package D :FBGA(L/F)
July 11, 2003
Preliminary
Finalized
September 25, 2003 Final
<UtRAM>
- Changed tPC from Max 25ns to Min 25ns in the AC Characteristics.
<NAND>
- Corrected the FLASH READ1 OPERATION(READ ONE PAGE) timing
in Page 19.
Note : For more detailed features and specifications including FAQ, please refer to Samsung’s web site.
http://samsungelectronics.com/semiconductors/products/products_index.html
The attached datasheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right
to change the specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions about device. If you have
any questions, please contact the SAMSUNG branch office near you.
Revision 1.0
September 2003
- 1 -
Preliminary
MCP MEMORY
KBC00B7A0M
Multi-Chip Package MEMORY
256M Bit (16Mx16) Nand Flash Memory / 64M Bit (4Mx16) UtRAM / 64M Bit (4Mx16) UtRAM / 8M Bit (512Kx16) SRAM
FEATURES
<Common>
<UtRAM(each device)>
· Operating Temperature : -25°C ~ 85°C
· Package : 111 - ball FBGA Type - 11 x 11mm, 0.8 mm pitch
· Power Supply Voltage: 2.7~3.1V
· Organization: 4M x16 bit
· Three State Outputs
· Compatible with Low Power SRAM
· Support 4 page mode (Read only)
· Deep Power Down: Memory cell data hold invalid
<NAND Flash>
· Supply Voltage : 2.7~3.6V
· Organization
- Memory Cell Array : (16M + 512K)bit x 16bit
- Data Register : (256 + 8)bit x16bit
· Automatic Program and Erase
- Page Program : (256 + 8)Word
- Block Erase : (8K + 256)Word
· Page Read Operation
<SRAM>
· Process Technology: Full CMOS
· Organization: 512K x16
· Power Supply Voltage: 2.7~3.3V
· Low Data Retention Voltage: 1.5V(Min)
· Three State Outputs
- Page Size : (256 + 8)Byte
- Random Access
: 10ms(Max.)
- Serial Page Access : 50ns(Min.)
· Fast Write Cycle Time
- Program time : 200ms(Typ.)
- Block Erase Time : 2ms(Typ.)
· Command/Address/Data Multiplexed I/O Port
· Hardware Data Protection
- Program/Erase Lockout During Power Transitions
· Reliable CMOS Floating-Gate Technology
- Endurance
: 100K Program/Erase Cycles
- Data Retention : 10 Years
· Command Register Operation
· Intelligent Copy-Back
· Unique ID for Copyright Protection
· Power-On Auto-Read Operation
· Safe Lock Mechanism
GENERAL DESCRIPTION
The KBC00B7A0M is a Multi Chip Package Memory which combines 256Mbit Nand Flash and two 64Mbit Unit Transistor CMOS
RAM and 8Mbit SRAM.
256Mbit NAND Flash memory is organized as 16M x16 bit and 64Mbit UtRAM is organized as 4M x16 bit and 8Mbit SRAM is orga-
nized as 512K x16 bit.
In 256Mb NAND Flash, a program operation can be performed in typical 200ms on a 264-word page and an erase operation can be
performed in typical 2ms on a 8K-word block. Data in the page can be read out at 50ns cycle time per word. The DQ pins serve as
the ports for address and data input/output as well as command input. The on-chip write control automates all program and erase
functions including pulse repetition, where required, and internal verification and margining of data. Even the write-intensive systems
can take advantage of the FLASH¢s extended reliability of 100K program/erase cycles by providing ECC(Error Correcting Code) with
real time mapping-out algorithm. These algorithms have been implemented in many mass storage applications.
The 64Mbit UtRAM is fabricated by SAMSUNG¢s advanced CMOS technology using one transistor memory cell. The device support
page mode operation. The device also supports deep power down mode for low standby current.
The 8Mbit SRAM is fabricated by SAMSUNG¢s advanced full CMOS process technology. The device supports low data retention volt-
age for battery back-up operation with low data retention current.
The KBC00B7A0M is suitable for use in data memory of mobile communication system to reduce not only mount area but also power
consumption.
This device is available in 111-ball FBGA Type.
SAMSUNG ELECTRONICS CO., LTD. reserves the right to change products and specifications without notice.
Revision 1.0
September 2003
- 2 -
Preliminary
MCP MEMORY
KBC00B7A0M
PIN CONFIGURATION
1
2
3
4
5
6
7
8
9
10
11
12
A
DNU
DNU
DNU
DNU
DNU
DNU
DNU
DNU
DNU
B
C
D
E
F
DNU
DNU
A1
A2
A3
A4
A7
A6
A19
LB
Vccu
Vccs
UB
WE
A20
A21
ZZ1
WPF
CLE
R/B
A8
A9
A12
A13
A14
A15
ALE
Vss
Vss
A5
A17
A18
NC
A10
A11
REF
CEF
WEF
NC
ZZ2
DQ1F
DQ5F
CS2s
DQ8F
DQ11F
NC
DQ9F
DQ0F
DQ3F DQ10F DQ2F
G
H
J
DQ4F DQ12F
VccF
DQ13F DQ6F DQ14F CSu2
VccF
A16
DQ7
DQ15
Vss
DQ7F DQ15F
DQ0
DQ8
DQ1
DQ9
DQ2
DQ3
DQ10
DQ11
Vccs
Vccu
DQ5
NC
K
L
Vss
CS1s
Vss
A0
CSu1
OE
DQ13
DQ6
DQ14
DNU
DNU
DNU
DNU
DNU
DNU
Vccs
Vccqu
DQ4
DQ12
DNU
DNU
DNU
DNU
DNU
DNU
M
N
111-FBGA: Top View (Ball Down)
Revision 1.0
September 2003
- 3 -
Preliminary
MCP MEMORY
KBC00B7A0M
PIN DESCRIPTION
Ball Name
Description
Ball Name
R/B
Description
A0 to A18
Address Input Balls (UtRAM,SRAM)
Address Input Balls (UtRAM)
Ready/Busy (Flash Memory)
A19 to A21
ZZ1
Deep Power Down (UtRAM1)
Deep Power Down (UtRAM2)
Chip Enable (Flash Memory)
Chip Select (UtRAM1)
DQ0F to DQ15F Data Input/Output Balls (Flash Memory)
DQ0 to DQ15 Data Input/Output Balls (UtRAM, SRAM)
ZZ2
CEF
WPF
VCCF
Vccu
Vccs
Vccqu
Vss
Write Protection (Flash Memory)
Power Supply (Flash Memory)
Power Supply (UtRAM)
CSu1
CSu2
CS1s
CS2s
WEF
WE
Chip Select (UtRAM2)
Chip Select (SRAM)
Power Supply (SRAM)
Chip Select (SRAM)
Data Out Power (UtRAM)
Write Enable (Flash Memory)
Write Enable (UtRAM, SRAM)
Output Enable (UtRAM, SRAM)
Read Enable (Flash Memory)
No Connection
Ground (Common)
UB
Upper Byte Enable (UtRAM, SRAM)
Lower Byte Enable (UtRAM, SRAM)
Address Latch Enable (Flash Memory)
Command Latch Enable (Flash Memory)
OE
LB
REF
ALE
CLE
NC
DNU
Do Not Use
ORDERING INFORMATION
K B C 00 B 7 A 0 M - x 405
Access Time
405 : NAND Flash : 50ns
UtRAM : 70ns
Samsung
MCP(4 Chip) Memory
UtRAM : 70ns
SRAM : 55ns
Device Type
NAND Flash+UtRAM+UtRAM
+SRAM
Package
F : FBGA D : FBGA(L/F)
NOR Flash Density , Vcc , Org.
00 : NONE
Version
M : 1st Generation
NAND Flash Density , Vcc , Org.
B : 256Mbit, 3.0V, x16
SDRAM Density , Vcc , Org.
0 : NONE
UtRAM Density , Vcc , Org.
7 : 64Mbit + 64Mbit, 3.0V, x16(Page)
SRAM Density , Vcc , Org.
A : 8Mbit, 3.0V, x16
Revision 1.0
September 2003
- 4 -
Preliminary
MCP MEMORY
KBC00B7A0M
Figure 1. FUNCTIONAL BLOCK DIAGRAM
VccF Vss
WPF
CEF
R/B
CLE
ALE
256M bit
Flash Memory
DQ0F to DQ15F
REF
WEF
Vccu
Vss
Vccqu
Address(A0 to A18)
Address(A19 to A21)
OE
64M bit
UtRAM
DQ0 to DQ15
DQ0 to DQ15
DQ0 to DQ15
WE
UB
LB
CSu1
ZZ1
Vccu
Vss
Vccqu
64M bit
UtRAM
DQ0 to DQ15
CSu2
ZZ2
Vccs
Vss
8M bit
SRAM
CS1s
CS2s
Revision 1.0
September 2003
- 5 -
Preliminary
MCP MEMORY
KBC00B7A0M
256M Bit(16Mx16)
NAND Flash Memory
Revision 1.0
September 2003
- 6 -
Preliminary
MCP MEMORY
KBC00B7A0M
Figure 2. NAND Flash (X16) ARRAY ORGANIZATION
1 Block =32 Pages
= (8K + 256) Word
1 Page = 264 Word
1 Block = 264 Word x 32 Pages
= (8K + 256) Word
1 Device = 264Words x 32Pages x 2048 Blocks
= 264 Mbits
64K Pages
(=2,048 Blocks)
Page Register
(=256 Words)
16 bit
256Word
8 Word
8 Word
I/O 0 ~ I/O 15
Page Register
256 Word
I/O 0
A0
I/O 1
A1
I/O 2
A2
I/O 3
I/O 4
A4
I/O 5
A5
I/O 6
A6
I/O 7
A7
I/O8 to 15
1st Cycle
2nd Cycle
3rd Cycle
A3
L*
L*
L*
Column Address
Row Address
(Page Address)
A9
A10
A18
A11
A19
A12
A20
A13
A21
A14
A22
A15
A23
A16
A24
A17
NOTE : Column Address : Starting Address of the Register.
* L must be set to "Low".
Revision 1.0
September 2003
- 7 -
Preliminary
MCP MEMORY
KBC00B7A0M
PRODUCT INTRODUCTION
The device is a 264Mbit(276,824,064 bit) memory organized as 65,536 rows(pages) 264columns. Spare eight columns are located
from column address of 256~263. A 264-word data register is connected to memory cell arrays accommodating data transfer
between the I/O buffers and memory during page read and page program operations. The memory array is made up of 16 cells that
are serially connected to form a NAND structure. Each of the 16 cells resides in a different page. A block consists of two NAND
structures. A NAND structure consists of 16 cells. Total 16896 NAND cells reside in a block. The array organization is shown in Fig-
ure 2. The program and read operations are executed on a page basis, while the erase operation is executed on a block basis. The
memory array consists of 2048 separately erasable 8K-Word blocks. It indicates that the bit by bit erase operation is prohibited on
the device.
The device has addresses multiplexed into 8 I/Os(X16 device case : lower 8 I/Os). Device allows sixteen bit wide data transport into
and out of page registers. This scheme dramatically reduces pin counts while providing high performance and allows systems
upgrades to future densities by maintaining consistency in system board design. Command, address and data are all written through
I/O¢s by bringing WE to low while CE is low. Data is latched on the rising edge of WE. Command Latch Enable(CLE) and Address
Latch Enable(ALE) are used to multiplex command and address respectively, via the I/O pins. Some commands require one bus
cycle. For example, Reset command, Read command, Status Read command, etc require just one cycle bus. Some other com-
mands like Page Program and Copy-back Program and Block Erase, require two cycles: one cycle for setup and the other cycle for
execution. The 16M-word physical space requires 24 addresses, thereby requiring three cycles for word-level addressing: column
address, low row address and high row address, in that order. Page Read and Page Program need the same three address cycles
following the required command input. In Block Erase operation, however, only the two row address cycles are used. Device opera-
tions are selected by writing specific commands into the command register. Table 1 defines the specific commands of the device.
The device includes one block sized OTP(One Time Programmable), which can be used to increase system security or to provide
identification capabilities. Detailed information can be obtained by contact with Samsung.
Table 1. COMMAND SETS
Function
1st. Cycle
00h
2nd. Cycle
Acceptable Command during Busy
Read 1
Read 2
Read ID
Reset
-
50h
-
90h
-
FFh
80h
-
10h
8Ah
-
O
Page Program
Copy-Back Program
Lock
00h
2Ah
23h
Unlock
24h
-
Lock-tight
2Ch
7Ah
60h
Read Block Lock Status
Block Erase
Read Status
-
D0h
-
70h
O
Caution : Any undefined command inputs are prohibited except for above command set of Table 1.
Revision 1.0
September 2003
- 8 -
Preliminary
MCP MEMORY
KBC00B7A0M
ABSOLUTE MAXIMUM RATINGS
Parameter
Symbol
VIN/OUT
VCC
Rating
-0.6 to + 4.6
-0.6 to + 4.6
-0.6 to + 4.6
-40 to +125
-65 to +150
5
Unit
Voltage on any pin relative to VSS
V
VCCQ
TBIAS
TSTG
Temperature Under Bias
Storage Temperature
Short Circuit Current
NOTE :
°C
°C
Ios
mA
1. Minimum DC voltage is -0.6V on input/output pins. During transitions, this level may undershoot to -2.0V for periods <30ns.
Maximum DC voltage on input/output pins is VCC,+0.3V which, during transitions, may overshoot to VCC+2.0V for periods <20ns.
2. Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to the conditions
as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
RECOMMENDED OPERATING CONDITIONS
(Voltage reference to GND, TA=-40 to 85°C)
Parameter
Supply Voltage
Symbol
VCC
Min
2.7
2.7
0
Typ.
3.3
3.3
0
Max
3.6
3.6
0
Unit
V
Supply Voltage
Supply Voltage
VCCQ
VSS
V
V
DC AND OPERATING CHARACTERISTICS(Recommended operating conditions otherwise noted.)
Parameter
Symbol
Test Conditions
tRC=50ns, CE=VIL
IOUT=0mA
Min
Typ
Max
Unit
Sequential Read
ICC1
-
10
20
Operating
Current
Program
Erase
ICC2
ICC3
ISB1
ISB2
ILI
-
-
-
10
10
-
25
mA
-
-
25
Stand-by Current(TTL)
Stand-by Current(CMOS)
Input Leakage Current
Output Leakage Current
CE=VIH, WP=0V/VCC
CE=VCC-0.2, WP=0V/VCC
VIN=0 to Vcc(max)
VOUT=0 to Vcc(max)
I/O pins
1
-
10
-
50
-
±10
mA
ILO
-
-
±10
2.0
2.0
-0.3
2.4
-
-
VCCQ+0.3
Input High Voltage
VIH
Except I/O pins
-
-
VCC+0.3
Input Low Voltage, All inputs
Output High Voltage Level
Output Low Voltage Level
Output Low Current(R/B)
VIL
VOH
-
0.8
-
V
IOH=-400mA
-
VOL
IOL=2.1mA
-
0.4
-
IOL(R/B)
VOL=0.4V
8
10
mA
Revision 1.0
September 2003
- 9 -
Preliminary
MCP MEMORY
KBC00B7A0M
VALID BLOCK
Parameter
Symbol
Min
Typ.
Max
2048
Unit
Valid Block Number
NVB
2013
-
Blocks
NOTE :
1. The device may include invalid blocks when first shipped. Additional invalid blocks may develop while being used. The number of valid blocks is pre-
sented with both cases of invalid blocks considered. Invalid blocks are defined as blocks that contain one or more bad bits. Do not erase or program
factory-marked bad blocks. Refer to the attached technical notes for a appropriate management of invalid blocks.
2. The 1st block, which is placed on 00h block address, is fully guaranteed to be a valid block, does not require Error Correction.
3. Minimum 1004 valid blocks are guaranteed for each contiguous 128Mb memory space.
AC TEST CONDITION
(TA=-40 to 85°C, Vcc=2.7V~3.6V unless otherwise noted)
Parameter
NAND Flash
0.4V to 2.4V
Input Pulse Levels
Input Rise and Fall Times
5ns
Input and Output Timing Levels
Output Load (VccQ:3.0V +/-10%)
Output Load (VccQ:3.3V +/-10%)
1.5V
1 TTL GATE and CL=50pF
1 TTL GATE and CL=100pF
CAPACITANCE(TA=25°C, VCC=3.3V, f=1.0MHz)
Item
Symbol
Test Condition
Min
Max
10
Unit
pF
Input/Output Capacitance
Input Capacitance
CI/O
VIL=0V
-
-
CIN
VIN=0V
10
pF
NOTE : Capacitance is periodically sampled and not 100% tested.
MODE SELECTION
CLE
H
L
ALE
L
CE
L
WE
RE
H
PRE
X
WP
X
Mode
Command Input
Read Mode
Write Mode
H
L
H
X
X
Address Input(3clock)
Command Input
H
L
L
L
H
X
H
H
H
X
H
L
H
X
Address Input(3clock)
L
L
L
H
X
Data Input
Data Output
L
L
L
H
X
X
X
X
X
X
X
X
X
X
H
X
X
X
X
X
H
H
L
During Program(Busy)
During Erase(Busy)
Write Protect
X
X
X
X(1)
X
X
X
(2)
(2)
X
Stand-by
0V/VCC 0V/VCC
NOTE : 1. X can be VIL or VIH.
2. WP should be biased to CMOS high or CMOS low for standby.
Program/Erase Characteristics
Parameter
Symbol
Min
Typ
Max
500
10
2
Unit
Program Time
tPROG
tLBSY
-
-
-
-
-
200
ms
ms
Dummy Busy Time for the Lock or Lock-tight Block
5
-
Main Array
cycles
cycles
ms
Number of Partial Program Cycles
in the Same Page
Nop
Spare Array
-
3
Block Erase Time
tBERS
2
3
Revision 1.0
September 2003
- 10 -
Preliminary
MCP MEMORY
KBC00B7A0M
AC Timing Characteristics for Command / Address / Data Input
Parameter
Symbol
tCLS
tCLH
tCS
Min
Max
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
CLE Set-up Time
CLE Hold Time
CE Setup Time
CE Hold Time
0
-
-
10
0
.-
-
tCH
10
25 (1)
0
WE Pulse Width
ALE Setup Time
ALE Hold Time
Data Setup Time
Data Hold Time
Write Cycle Time
tWP
-
tALS
tALH
tDS
-
10
20
10
45
15
-
-
tDH
-
tWC
-
WE High Hold Time
tWH
-
NOTE :
1. If tCS is set less than 10ns, tWP must be minimum 35ns, otherwise, tWP may be minimum 25ns.
AC Characteristics for Operation
Parameter
Symbol
tR
Min
-
Max
Unit
ms
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
Data Transfer from Cell to Register
10
ALE to RE Delay
tAR
10
10
20
25
-
-
CLE to RE Delay
tCLR
tRR
-
-
Ready to RE Low
RE Pulse Width
tRP
-
WE High to Busy
tWB
100
-
Read Cycle Time
tRC
50
-
CE Access Time
tCEA
tREA
tRHZ
tCHZ
tOH
45
30
30
20
-
RE Access Time
-
RE High to Output Hi-Z
CE High to Output Hi-Z
RE or CE High to Output hold
RE High Hold Time
-
-
15
15
0
tREH
tIR
-
Output Hi-Z to RE Low
WE High to RE Low
-
tWHR1
tWHR2
tRST
60
100
-
-
WE High to RE Low in Block Lcok Mode
Device Resetting Time(Read/Program/Erase)
-
5/10/500(1)
NOTE :
1. If reset command(FFh) is written at Ready state, the device goes into Busy for maximum 5us.
2. To break the sequential read cycle, CE must be held high for longer time than tCEH.
3. The time to Ready depends on the value of the pull-up resistor tied R/B pin.
Revision 1.0
September 2003
- 11 -
Preliminary
MCP MEMORY
KBC00B7A0M
NAND Flash Technical Notes
Invalid Block(s)
Invalid blocks are defined as blocks that contain one or more invalid bits whose reliability is not guaranteed by Samsung. The infor-
mation regarding the invalid block(s) is so called as the invalid block information. Devices with invalid block(s) have the same quality
level as devices with all valid blocks and have the same AC and DC characteristics. An invalid block(s) does not affect the perfor-
mance of valid block(s) because it is isolated from the bit line and the common source line by a select transistor. The system design
must be able to mask out the invalid block(s) via address mapping. The 1st block, which is placed on 00h block address, is fully guar-
anteed to be a valid block, does not require Error Correction.
Identifying Invalid Block(s)
All device locations are erased(FFh) except locations where the invalid block(s) information is written prior to shipping. The invalid
block(s) status is defined by the 1st word in the spare area. Samsung makes sure that either the 1st or 2nd page of every invalid
block has non-FFFFh data at the column address of 256 and 261. Since the invalid block information is also erasable in most cases,
it is impossible to recover the information once it has been erased. Therefore, the system must be able to recognize the invalid
block(s) based on the original invalid block information and create the invalid block table via the following suggested flow chart(Fig-
ure 3). Any intentional erasure of the original invalid block information is prohibited.
Start
Set Block Address = 0
Increment Block Address
Check "FFh" at the column address
256 and 261(X16 device)
of the 1st and 2nd page in the block
*
No
Create (or update)
Invalid Block(s) Table
Check "FFh" ?
Yes
No
Last Block ?
Yes
End
Figure 3. Flow chart to create invalid block table.
Revision 1.0
September 2003
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Preliminary
MCP MEMORY
KBC00B7A0M
NAND Flash Technical Notes (Continued)
Error in write or read operation
Within its life time, the additional invalid blocks may develop with NAND Flash memory. Refer to the qualification report for the actual
data.The following possible failure modes should be considered to implement a highly reliable system. In the case of status read fail-
ure after erase or program, block replacement should be done. Because program status fail during a page program does not affect
the data of the other pages in the same block, block replacement can be executed with a page-sized buffer by finding an erased
empty block and reprogramming the current target data and copying the rest of the replaced block. To improve the efficiency of
memory space, it is recommended that the read or verification failure due to single bit error be reclaimed by ECC without any block
replacement. The said additional block failure rate does not include those reclaimed blocks.
Failure Mode
Detection and Countermeasure sequence
Erase Failure
Status Read after Erase --> Block Replacement
Status Read after Program --> Block Replacement
Read back ( Verify after Program) --> Block Replacement
or ECC Correction
Write
Read
Program Failure
Single Bit Failure
Verify ECC -> ECC Correction
: Error Correcting Code --> Hamming Code etc.
Example) 1bit correction & 2bit detection
ECC
Program Flow Chart
If ECC is used, this verification
operation is not needed.
Start
Write 80h
Write 00h
Write Address
Wait for tR Time
Write Address
Write Data
Write 10h
*
No
Program Error
Verify Data
Read Status Register
Yes
Program Completed
No
I/O 6 = 1 ?
or R/B = 1 ?
: If program operation results in an error, map out
the block including the page in error and copy the
target data to another block.
*
Yes
*
No
Program Error
I/O 0 = 0 ?
Yes
Revision 1.0
September 2003
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Preliminary
MCP MEMORY
KBC00B7A0M
NAND Flash Technical Notes (Continued)
Erase Flow Chart
Read Flow Chart
Start
Start
Write 60h
Write 00h
Write Block Address
Write Address
Read Data
Write D0h
Read Status Register
ECC Generation
No
No
I/O 6 = 1 ?
or R/B = 1 ?
Reclaim the Error
Verify ECC
Yes
Yes
*
No
Page Read Completed
Erase Error
I/O 0 = 0 ?
Yes
Erase Completed
: If erase operation results in an error, map out
the failing block and replace it with another block.
*
Block Replacement
Block A
1st
2
{
(n-1)th
nth
an error occurs.
(page)
Buffer memory of the controller.
Block B
1st
1
{
(n-1)th
nth
(page)
* Step1
When an error happens in the nth page of the Block ’A’ during erase or program operation.
* Step2
Copy the nth page data of the Block ’A’ in the buffer memory to the nth page of another free block. (Block ’B’)
* Step3
Then, copy the data in the 1st ~ (n-1)th page to the same location of the Block ’B’.
* Step4
Do not further erase Block ’A’ by creating an ’invalid Block’ table or other appropriate scheme.
Revision 1.0
September 2003
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Preliminary
MCP MEMORY
KBC00B7A0M
Pointer Operation
Samsung NAND Flash has two address pointer commands as a substitute for the most significant column address. ’00h’ command
sets the pointer to ’A’ area(0~255word), and ’50h’ command sets the pointer to ’B’ area(256~263word). With these commands, the
starting column address can be set to any of a whole page(0~263word). ’00h’ or ’50h’ is sustained until another address pointer com-
mand is inputted. To program data starting from ’A’ or ’B’ area, ’00h’ or ’50h’ command must be inputted before ’80h’ command is
written. A complete read operation prior to ’80h’ command is not necessary.
"A" area
"B" area
(00h plane)
(50h plane)
256 Word
8 Word
Table 3. Destination of the pointer
Command
Pointer position
Area
00h
50h
0 ~ 255 word
256 ~ 263 word
main array(A)
spare array(B)
"A"
"B"
Internal
Page Register
Pointer select
command
(00h, 50h)
Pointer
Figure 5. Block Diagram of Pointer Operation
(1) Command input sequence for programming ’A’ area
The address pointer is set to ’A’ area(0~255), and sustained
Address / Data input
Address / Data input
00h
80h
10h
00h
80h
10h
’A’,’B’ area can be programmed.
’00h’ command can be omitted.
It depends on how many data are inputted.
(2) Command input sequence for programming ’B’ area
The address pointer is set to ’B’ area(256~263), and sustained
Address / Data input
Address / Data input
80h 10h
50h
80h
10h
50h
Only ’B’ area can be programmed.
’50h’ command can be omitted.
Revision 1.0
September 2003
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Preliminary
MCP MEMORY
KBC00B7A0M
System Interface Using CE don’t-care.
For an easier system interface, CE may be inactive during the data-loading or sequential data-reading as shown below. The internal
264word page registers are utilized as seperate buffers for this operation and the system design gets more flexible. In addition, for
voice or audio applications which use slow cycle time on the order of u-seconds, de-activating CE during the data-loading and read-
ing would provide significant savings in power consumption.
Figure 6. Program Operation with CE don’t-care.
CLE
CE don’t-care
CE
WE
ALE
I/Ox
80h
Start Add.(3Cycle)
Data Input
Data Input
10h
tCS
tCH
tCEA
CE
RE
CE
tREA
tWP
tOH
WE
I/O0~15
out
Figure 7. Read Operation with CE don’t-care.
CLE
CE
CE don’t-care
RE
ALE
tR
R/B
WE
I/Ox
Data Output(sequential)
00h
Start Add.(3Cycle)
Revision 1.0
September 2003
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Preliminary
MCP MEMORY
KBC00B7A0M
I/O
I/Ox
I/O 0 ~ I/O 151)
DATA
Device
Data In/Out
~264word
NAND Flash
NOTE: 1. I/O8~15 must be set to "0" during command or address input.
2. I/O8~15 are used only for data bus.
* Command Latch Cycle
CLE
tCLH
tCH
tCLS
tCS
CE
tWP
WE
tALS
tALH
ALE
tDH
tDS
Command
I/Ox
* Address Latch Cycle
tCLS
CLE
tCS
tWC
tWC
CE
tCH
tWP
tWP
tWP
WE
tWH
tALH
tALS
tWH
tALH
tALS
tALH
tALS
ALE
I/Ox
tDH
tDH
tDH
tDS
tDS
tDS
A9~A16
A17~A24
AO~A7
Revision 1.0
September 2003
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Preliminary
MCP MEMORY
KBC00B7A0M
* Input Data Latch Cycle
tCLH
CLE
CE
tCH
tWC
tALS
ALE
tWP
tWP
tWP
WE
tWH
tDH
tDH
tDH
tDS
tDS
tDS
I/Ox
DIN 0
DIN 1
DIN n
* Sequential Out Cycle after Read(CLE=L, WE=H, ALE=L)
tRC
CE
tCHZ*
tOH
tREH
tREA
tREA
tREA
tRP
RE
tRHZ*
tRHZ*
tOH
I/Ox
Dout
Dout
Dout
tRR
R/B
NOTES : Transition is measured ±200mV from steady state voltage with load.
This parameter is sampled and not 100% tested.
Revision 1.0
September 2003
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Preliminary
MCP MEMORY
KBC00B7A0M
* Status Read Cycle
tCLR
CLE
CE
tCLS
tCS
tCLH
tCH
tWP
WE
tCEA
tCHZ
tOH
tWHR1
RE
tRHZ
tOH
tDH
tREA
tDS
tIR
Status Output
I/Ox
70h
FLASH READ1 OPERATION(READ ONE PAGE)
CLE
CE
tCHZ
tOH
tWC
WE
tWB
tAR
ALE
tRHZ
tOH
tRC
tR
RE
N Address
tRR
00h
A0 ~ A7
A9 ~ A16 A17 ~ A23
Dout N
Dout N+1
Dout N+2 Dout N+3
Dout 263
DQ0~15
R/B
Column
Address
Page(Row)
Address
Busy
Revision 1.0
September 2003
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Preliminary
MCP MEMORY
KBC00B7A0M
READ1 OPERATION (INTERCEPTED BY CE)
CLE
CE
WE
tWB
tCHZ
tOH
tAR
ALE
tR
tRC
RE
N Address
tRR
Read
CMD
Dout N+2
Dout N+3
Dout N
Dout N+1
Row Add1 Row Add2
I/Ox
Col. Add
Page(Row)
Address
Column
Address
Busy
R/B
READ2 OPERATION (READ ONE PAGE)
CLE
CE
WE
ALE
RE
tR
tWB
tAR
tRR
Dout
Dout
n+M
I/Ox
R/B
50h
Row Add1 Row Add2
Dout n+m
n+M+1
Col. Add
Selected
Row
M Address
A0~A2 are Valid Address & A3~A7 are "L"
m
n
n = 256, m = 8
Start
address M
Revision 1.0
September 2003
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Preliminary
MCP MEMORY
KBC00B7A0M
COPY-BACK PROGRAM OPERATION
CLE
CE
tWC
WE
tWB
tWB
tPROG
ALE
tR
RE
I/Ox
Row Add1 Row Add2
8Ah
00h
Col. Add
A0~A7 A9~A16 A17~A24
70h
I/O0
Program
Command
Column
Address
Column
Address
Read Status
Command
Page(Row)
Address
Page(Row)
Address
R/B
I/O0=0 Successful Program
I/O0=1 Error in Program
Busy
Busy
BLOCK ERASE OPERATION (ERASE ONE BLOCK)
CLE
CE
tWC
WE
tBERS
tWB
ALE
RE
I/Ox
A9~A16
A17~A24
60h
DOh
70h
I/O 0
Page(Row)
Address
Busy
R/B
I/O0=0 Successful Erase
Read Status I/O0=1 Error in Erase
Command
Auto Block Erase
Setup Command
Erase Command
Revision 1.0
September 2003
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Preliminary
MCP MEMORY
KBC00B7A0M
MANUFACTURE & DEVICE ID READ OPERATION
CLE
CE
WE
ALE
tAR
RE
tREA
I/Ox
90h
00h
ECh
XX55h
Device Code
Read ID Command
Address. 1cycle
Maker Code
Revision 1.0
September 2003
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Preliminary
MCP MEMORY
KBC00B7A0M
DEVICE OPERATION
PAGE READ
Upon initial device power up, the device defaults to Read1 mode. This operation is also initiated by writing 00h to the command reg-
ister along with three address cycles. Once the command is latched, it does not need to be written for the following page read opera-
tion. Two types of operations are available : random read, serial page read.
The random read mode is enabled when the page address is changed. The 264 words of data within the selected page are trans-
ferred to the data registers in less than 10ms(tR). The system controller can detect the completion of this data transfer(tR) by analyz-
ing the output of R/B pin. Once the data in a page is loaded into the registers, they may be read out in 50ns cycle time by sequentially
pulsing RE. High to low transitions of the RE clock output the data starting from the selected column address up to the last column
address[column 255 /263 depending on the state of GND input pin.
The way the Read1 and Read2 commands work is like a pointer set to either the main area or the spare area. The spare area of
256~263 words may be selectively accessed by writing the Read2 command with GND input pin low. Addresses A0~A2 set the start-
ing address of the spare area while addresses A3~A7 must be "L" in X16 device case. The Read1 command is needed to move the
pointer back to the main area. Figures 8,9 show typical sequence and timings for each read operation.
Figure8. Read1 Operation
CLE
CE
WE
ALE
tR
R/B
RE
I/Ox
Start Add.(3Cycle)
A0 ~ A7 & A9 ~ A24
00h
Data Output(Sequential)
(00h Command)
Main array
(01h Command)
1st half array 2st half array
Data Field
Spare Field
Data Field
Spare Field
Revision 1.0
September 2003
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Preliminary
MCP MEMORY
KBC00B7A0M
Figure 9. Read2 Operation
CLE
CE
WE
ALE
R/B
RE
tR
Start Add.(3Cycle)
I/Ox
50h
Data Output(Sequential)
Spare Field
A0 ~ A2 & A9 ~ A24
Main array
A3 ~ A7 are "L"
Data Field
Spare Field
Revision 1.0
September 2003
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Preliminary
MCP MEMORY
KBC00B7A0M
PAGE PROGRAM
The device is programmed basically on a page basis, but it does allow multiple partial page programing of a byte/word or consecutive
bytes/words up to 264, in a single page program cycle. The number of consecutive partial page programming operation within the
same page without an intervening erase operation should not exceed 2 for main array and 3 for spare array. The addressing may be
done in any random order in a block. A page program cycle consists of a serial data loading period in which up to 264 words of data
may be loaded into the page register, followed by a non-volatile programming period where the loaded data is programmed into the
appropriate cell. About the pointer operation, please refer to the attached technical notes.
The serial data loading period begins by inputting the Serial Data Input command(80h), followed by the three cycle address input and
then serial data loading. The words other than those to be programmed do not need to be loaded.The Page Program confirm com-
mand(10h) initiates the programming process. Writing 10h alone without previously entering the serial data will not initiate the pro-
gramming process. The internal write controller automatically executes the algorithms and timings necessary for program and verify,
thereby freeing the system controller for other tasks. Once the program process starts, the Read Status Register command may be
entered, with RE and CE low, to read the status register. The system controller can detect the completion of a program cycle by
monitoring the R/B output, or the Status bit(I/O 6) of the Status Register. Only the Read Status command and Reset command are
valid while programming is in progress. When the Page Program is complete, the Write Status Bit(I/O 0) may be checked(Figure 10).
The internal write verify detects only errors for "1"s that are not successfully programmed to "0"s. The command register remains in
Read Status command mode until another valid command is written to the command register.
Figure 10. Program Operation
tPROG
R/B
I/Ox
Pass
80h
Address & Data Input
I/O0
Fail
10h
70h
COPY-BACK PROGRAM
The copy-back program is configured to quickly and efficiently rewrite data stored in one page within the array to another page within
the same array without utilizing an external memory. Since the time-consuming sequently-reading and its re-loading cycles are
removed, the system performance is improved. The benefit is especially obvious when a portion of a block is updated and the rest of
the block also need to be copied to the newly assigned free block. The operation for performing a copy-back is a sequential execu-
tion of page-read without burst-reading cycle and copying-program with the address of destination page. A normal read operation
with "00h" command with the address of the source page moves the whole 264words data into the internal buffer. As soon as the
Flash returns to Ready state, copy-back programming command "8Ah" may be given with three address cycles of target page fol-
lowed. The data stored in the internal buffer is then programmed directly into the memory cells of the destination page. Once the
Copy-Back Program is finished, any additional partial page programming into the copied pages is prohibited before erase. Since the
memory array is internally partitioned into two different planes, copy-back program is allowed only within the same memory plane.
Thus, A14, the plane address, of source and destination page address must be the same.
Figure 11. Copy-Back Program Operation
tR
tPROG
R/B
I/Ox
Add.(3Cycles)
Pass
00h
Add.(3Cycles)
I/O0
Fail
8Ah
70h
Source Address
Destination Address
Revision 1.0
September 2003
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Preliminary
MCP MEMORY
KBC00B7A0M
BLOCK ERASE
The Erase operation is done on a block basis. Block address loading is accomplished in two cycles initiated by an Erase Setup com-
mand(60h). Only address A14 to A24 is valid while A9 to A13 is ignored. The Erase Confirm command(D0h) following the block
address loading initiates the internal erasing process. This two-step sequence of setup followed by execution command ensures that
memory contents are not accidentally erased due to external noise conditions.
At the rising edge of WE after the erase confirm command input, the internal write controller handles erase and erase-verify. When
the erase operation is completed, the Write Status Bit(I/O 0) may be checked. Figure 12 details the sequence.
Figure 12. Block Erase Operation
tBERS
R/B
Pass
60h
I/O0
Fail
I/Ox
70h
Address Input(2Cycle)
Block Add. : A9 ~ A24
D0h
READ STATUS
The device contains a Status Register which may be read to find out whether program or erase operation is completed, and whether
the program or erase operation is completed successfully. After writing 70h command to the command register, a read cycle outputs
the content of the Status Register to the I/O pins on the falling edge of CE or RE, whichever occurs last. This two line control allows
the system to poll the progress of each device in multiple memory connections even when R/B pins are common-wired. RE or CE
does not need to be toggled for updated status. Refer to table 4 for specific Status Register definitions. The command register
remains in Status Read mode until further commands are issued to it. Therefore, if the status register is read during a random read
cycle, a read command(00h or 50h) should be given before sequential page read cycle.
Table4. Read Status Register Definition
I/O #
Status
Definition
"0" : Successful Program / Erase
I/O 0
Program / Erase
"1" : Error in Program / Erase
I/O 1
I/O 2
"0"
"0"
"0"
"0"
"0"
Reserved for Future
Use
I/O 3
I/O 4
I/O 5
I/O 6
Device Operation
Write Protect
Not use
"0" : Busy
"1" : Ready
"1" : Not Protected
I/O 7
"0" : Protected
Don’t care
I/O 8~15
Revision 1.0
September 2003
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Preliminary
MCP MEMORY
KBC00B7A0M
READ ID
The device contains a product identification mode, initiated by writing 90h to the command register, followed by an address input of
00h. Two read cycles sequentially output the manufacture code(ECh), and the device code respectively. The command register
remains in Read ID mode until further commands are issued to it. Figure 13 shows the operation sequence.
Figure 13. Read ID Operation
CLE
tCEA
CE
WE
tAR
ALE
RE
tWHR1
tREA
I/Ox
ECh
XX55
00h
90h
Address. 1cycle
Maker code
Device code
RESET
The device offers a reset feature, executed by writing FFh to the command register. When the device is in Busy state during random
read, program or erase mode, the reset operation will abort these operations. The contents of memory cells being altered are no
longer valid, as the data will be partially programmed or erased. The command register is cleared to wait for the next command, and
the Status Register is cleared to value C0h when WP is high. Refer to table 5 for device status after reset operation. If the device is
already in reset state a new reset command will not be accepted by the command register. The R/B pin transitions to low for tRST
after the Reset command is written. Refer to Figure 14 below.
Figure 14. RESET Operation
tRST
R/B
I/Ox
FFh
Table5. Device Status
After Power-up
After Reset
Operation Mode
Read 1
Waiting for next command
Revision 1.0
September 2003
- 27 -
Preliminary
MCP MEMORY
KBC00B7A0M
Power-On Auto-Read
The device is designed to offer automatic reading of the first page without command and address input sequence during power-on.
An internal voltage detector enables auto-page read functions when Vcc reaches about 1.8V. LOCKPRE pin controls activation of
auto- page read function. Auto-page read function is enabled only when LOCKPRE pin is logic high state. Serial access may be done
after power-on without latency.
Figure 16. Power-On Auto-Read
~ 1.8V
VCC
CLE
CE
WE
ALE
LOCKPRE
R/B
tR
RE
I/OX
1st
2nd
3rd
....
n th
Revision 1.0
September 2003
- 28 -
Preliminary
MCP MEMORY
KBC00B7A0M
READY/BUSY
The device has a R/B output that provides a hardware method of indicating the completion of a page program, erase and random
read completion. The R/B pin is normally high but transitions to low after program or erase command is written to the command reg-
ister or random read is started after address loading. It returns to high when the internal controller has finished the operation. The pin
is an open-drain driver thereby allowing two or more R/B outputs to be Or-tied. Because pull-up resistor value is related to tr(R/B)
and current drain during busy(ibusy) , an appropriate value can be obtained with the following reference chart(Fig 17). Its value can
be determined by the following guidance.
Rp
ibusy
VCC
VOL : 0.4V, VOH : 2.4V
Ready Vcc
R/B
VOH
open drain output
CL
VOL
Busy
tf
tr
GND
Device
Fig 17 Rp vs tr ,tf & Rp vs ibusy
@ Vcc = 3.3V, Ta = 25
°
C , CL = 100pF
400
2.4
Ibusy
300n
3m
300
1.2
200n
100n
200
2m
1m
0.8
tr
100
3.6
0.6
3.6
2K
3.6
3.6
tf
4K
1K
3K
Rp(ohm)
Rp value guidance
VCC(Max.) - VOL(Max.)
3.2V
8mA + SIL
Rp(min, 3.3V part) =
=
IOL + SIL
where IL is the sum of the input currents of all devices tied to the R/B pin.
Rp(max) is determined by maximum permissible limit of tr
Revision 1.0
September 2003
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Preliminary
MCP MEMORY
KBC00B7A0M
Data Protection & Power up sequence
The device is designed to offer protection from any involuntary program/erase during power-transitions. An internal voltage detector
disables all functions whenever Vcc is below about 2V(3.3V device). WP pin provides hardware protection and is recommended to
be kept at VIL during power-up and power-down and recovery time of minimum 10ms is required before internal circuit gets ready for
any command sequences as shown in Figure 18. The two step command sequence for program/erase provides additional software
protection.
Figure 18. AC Waveforms for Power Transition
3.3V device : ~ 2.5V
3.3V device : ~ 2.5V
VCC
High
WP
WE
10ms
Revision 1.0
September 2003
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Preliminary
MCP MEMORY
KBC00B7A0M
64M Bit(4Mx16)
Page Mode UtRAM
For Each Device
Revision 1.0
September 2003
- 31 -
Preliminary
MCP MEMORY
KBC00B7A0M
POWER UP SEQUENCE
1. Apply power.
2. Maintain stable power(Vcc min.=2.7V) for a minimum 200ms with CS and ZZ high.
TIMING WAVEFORM OF POWER UP
VCC(Min)
VCC
Min. 0ns
ZZ
Min. 200ms
CS
Power Up Mode
Normal Operation
(POWER UP)
1. After VCC reaches VCC(Min.), wait 200ms with CS and ZZ high. Then you get into the normal operation.
FUNCTIONAL DESCRIPTION
CS
H
X1)
L
ZZ
H
L
OE
X1)
X1)
X1)
H
WE
X1)
X1)
X1)
H
LB
X1)
X1)
H
UB
X1)
X1)
H
DQ0~7
High-Z
High-Z
High-Z
High-Z
High-Z
Dout
DQ8~15
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
Dout
Mode
Power
Deselected
Deselected
Standby
Deep Power Down
Standby
Active
H
H
H
H
H
H
H
H
H
Deselected
X1)
L
L
L
Output Disabled
Output Disabled
Lower Byte Read
Upper Byte Read
Word Read
X1)
L
L
H
H
Active
L
L
H
H
Active
L
L
H
H
L
High-Z
Dout
Active
L
L
H
L
L
Dout
Active
X1)
X1)
X1)
L
L
L
H
Din
High-Z
Din
Lower Byte Write
Upper Byte Write
Word Write
Active
L
L
H
L
High-Z
Din
Active
L
L
L
L
Din
Active
1. X means don¢t care.(Must be low or high state)
Revision 1.0
September 2003
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Preliminary
MCP MEMORY
KBC00B7A0M
ABSOLUTE MAXIMUM RATINGS1)
Item
Voltage on any pin relative to Vss
Voltage on Vcc supply relative to Vss
Power Dissipation
Symbol
VIN, VOUT
VCC
Ratings
Unit
V
-0.2 to VCC+0.3V
-0.2 to 3.6V
1.0
V
PD
W
Storage temperature
TSTG
-65 to 150
-25 to 85
°C
°C
Operating Temperature
TA
1. Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. Functional operation should be
restricted to be used under recommended operating condition. Exposure to absolute maximum rating conditions longer than 1 second may affect reli-
ability.
STANDBY MODE STATE MACHINES
CS=VIL, UB or/and LB=VIL
Standby
ZZ=VIH
Mode
CS=VIH and ZZ=VIH
Initial State
(Wait 200ms)
CS=VIH
ZZ=VIH
Power On
Active
ZZ=VIL
ZZ=VIL
Deep Power
Down Mode
CS=VIH, ZZ=VIH
STANDBY MODE CHARACTERISTIC
Power Mode
Standby
Memory Cell Data
Standby Current(mA)
Wait Time(ms)
Valid
150
20
0
Deep Power Down
Invaild
200
Revision 1.0
September 2003
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Preliminary
MCP MEMORY
KBC00B7A0M
RECOMMENDED DC OPERATING CONDITIONS1)
Item
Symbol
Vcc
Min
2.7
0
Typ
Max
3.1
Unit
V
Supply voltage
Ground
2.9
Vss
0
-
0
V
Vcc+0.22)
0.6
Input high voltage
Input low voltage
VIH
2.2
-0.23)
V
VIL
-
V
1. TA=-25 to 85°C, otherwise specified.
2. Overshoot: Vcc+1.0V in case of pulse width £20ns.
3. Undershoot: -1.0V in case of pulse width £20ns.
4. Overshoot and undershoot are sampled, not 100% tested.
CAPACITANCE1)(f=1MHz, TA=25°C)
Item
Input capacitance
Symbol
CIN
Test Condition
Min
Max
8
Unit
pF
VIN=0V
VIO=0V
-
-
Input/Output capacitance
CIO
10
pF
1. Capacitance is sampled, not 100% tested.
DC AND OPERATING CHARACTERISTICS
Typ1)
Symbol
ILI
Item
Test Conditions
Min
Max
1
Unit
Input leakage current
Output leakage current
VIN=Vss to Vcc
-1
-1
-
-
mA
mA
ILO
CS=VIH, ZZ=VIH, OE=VIH or WE=VIL, VIO=Vss to Vcc
1
Cycle time=1ms, 100% duty, IIO=0mA, CS£0.2V,
ZZ³ Vcc-0.2V, VIN£0.2V or VIN³ VCC-0.2V
ICC1
-
-
15
mA
Average operating current
Cycle time=tRC+3tPC, IIO=0mA, 100% duty, CS=VIL, ZZ=VIH,
VIN=VIL or VIH
ICC2
-
-
45
mA
Output low voltage
Output high voltage
Standby Current(CMOS)
Deep Power Down
VOL
VOH
ISB1
ISBD
IOL=2.1mA
-
2.4
-
-
-
-
-
0.4
-
V
V
IOH=-1.0mA
CS³ Vcc-0.2V, ZZ³ Vcc-0.2V, Other inputs=Vss to Vcc
ZZ£0.2V, Other inputs=Vss to Vcc
150
20
mA
mA
-
1. Typical values are tested at VCC=2.9V, TA=25°C and not guaranteed.
Revision 1.0
September 2003
- 34 -
Preliminary
MCP MEMORY
KBC00B7A0M
AC OPERATING CONDITIONS
TEST CONDITIONS(Test Load and Test Input/Output Reference)
Input pulse level: 0.4 to 2.2V
Input rising and falling time: 5ns
Input and output reference voltage: 1.5V
Output load: CL=50pF
AC CHARACTERISTICS(Vcc=2.7~3.1V, TA=-25 to 85°C)
Speed Bins
70ns
Parameter List
Symbol
Units
Min
70
-
Max
Read Cycle Time
tRC
tAA
-
70
70
35
70
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Address Access Time
Chip Select to Output
tCO
tOE
tBA
-
Output Enable to Valid Output
UB, LB Access Time
-
-
Chip Select to Low-Z Output
UB, LB Enable to Low-Z Output
Output Enable to Low-Z Output
Chip Disable to High-Z Output
UB, LB Disable to High-Z Output
Output Disable to High-Z Output
Output Hold from Address Change
Page Cycle
tLZ
10
10
5
tBLZ
tOLZ
tHZ
-
Read
-
0
25
25
25
-
tBHZ
tOHZ
tOH
tPC
0
0
5
25
-
-
Page Access Time
tPA
20
-
Write Cycle Time
tWC
tCW
tAS
70
60
0
Chip Select to End of Write
Address Set-up Time
-
-
Address Valid to End of Write
UB, LB Valid to End of Write
Write Pulse Width
tAW
tBW
tWP
tWR
tWHZ
tDW
tDH
tOW
60
60
551)
0
-
-
Write
-
Write Recovery Time
-
Write to Output High-Z
0
25
-
Data to Write Time Overlap
Data Hold from Write Time
End Write to Output Low-Z
30
0
-
5
-
1. tWP(min)=70ns for continuous write operation over 50 times.
Revision 1.0
September 2003
- 35 -
Preliminary
MCP MEMORY
KBC00B7A0M
TIMING DIAGRAMS
TIMING WAVEFORM OF READ CYCLE(1)(Address Controlled, CS=OE=VIL, ZZ=WE=VIH, UB or/and LB=VIL)
tRC
Address
tAA
tOH
Data Out
Data Valid
Previous Data Valid
TIMING WAVEFORM OF READ CYCLE(2)(ZZ=WE=VIH)
tRC
Address
tAA
tOH
tCO
CS
tHZ
tBA
UB, LB
tBHZ
tOE
OE
tOLZ
tBLZ
tLZ
tOHZ
High-Z
Data out
Data Valid
TIMING WAVEFORM OF PAGE CYCLE(READ ONLY)
Valid
Address
A21~A2
Valid
Valid
Valid
Valid
Address
A1~A0
Address Address Address
tPC
tAA
CS
tCO
OE
tPA
tOHZ
tOE
High Z
Data
Valid
Data
Valid
Data
Valid
Data
Valid
Data out
(READ CYCLE)
1. tHZ and tOHZ are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage
levels.
2. At any given temperature and voltage condition, tHZ(Max.) is less than tLZ(Min.) both for a given device and from device to device
interconnection.
3. tOE(max) is met only when OE becomes enabled after tAA(max).
4. If invalid address signals shorter than min. tRC are continuously repeated for over 4us, the device needs a normal read timing(tRC) or
needs to sustain standby state for min. tRC at least once in every 4us.
Revision 1.0
September 2003
- 36 -
Preliminary
MCP MEMORY
KBC00B7A0M
TIMING WAVEFORM OF WRITE CYCLE(1)(WE Controlled, ZZ=VIH)
tWC
Address
tWR(4)
tCW(2)
CS
tAW
tBW
UB, LB
tWP(1)
WE
tAS(3)
tDW
tDH
High-Z
High-Z
Data in
Data Valid
tWHZ
tOW
Data Undefined
Data out
TIMING WAVEFORM OF WRITE CYCLE(2)(CS Controlled, ZZ=VIH)
tWC
Address
CS
tCW(2)
tAS(3)
tWR(4)
tAW
tBW
UB, LB
tWP(1)
WE
tDW
tDH
Data Valid
Data in
High-Z
Data out
High-Z
Revision 1.0
September 2003
- 37 -
Preliminary
MCP MEMORY
KBC00B7A0M
TIMING WAVEFORM OF WRITE CYCLE(3)(UB, LB Controlled, ZZ=VIH)
tWC
Address
tWR(4)
tCW(2)
CS
tAW
tBW
UB, LB
tAS(3)
tWP(1)
WE
tDH
tDW
Data in
Data Valid
High-Z
Data out
High-Z
(WRITE CYCLE)
1. A write occurs during the overlap(tWP) of low CS and low WE. A write begins when CS goes low and WE goes low with asserting UB
or LB for single byte operation or simultaneously asserting UB and LB for double byte operation. A write ends at the earliest transition
when CS goes high and WE goes high. The tWP is measured from the beginning of write to the end of write.
2. tCW is measured from the CS going low to the end of write.
3. tAS is measured from the address valid to the beginning of write.
4. tWR is measured from the end of write to the address change. tWR is applied in case a write ends with CS or WE going high.
TIMING WAVEFORM OF DEEP POWER DOWN MODE ENTRY AND EXIT
200ms
0.5ms
ZZ
Wake up
Normal Operation
Suspend
Normal Operation
MODE
Deep Power Down Mode
CS
(DEEP POWER DOWN MODE)
1. When you toggle ZZ pin low, the device gets into the Deep Power Down mode after 0.5ms suspend period.
2. To return to normal operation, the device needs Wake Up period.
3. Wake Up sequence is just the same as Power Up sequence.
Revision 1.0
September 2003
- 38 -
Preliminary
MCP MEMORY
KBC00B7A0M
8M Bit(512Kx16) SRAM
Revision 1.0
September 2003
- 39 -
Preliminary
MCP MEMORY
KBC00B7A0M
FUNCTIONAL DESCRIPTION
CS1
H
X1)
X1)
L
CS2
X1)
L
OE
X1)
X1)
X1)
H
WE
X1)
X1)
X1)
H
LB
X1)
X1)
H
UB
X1)
X1)
H
DQ0~7
High-Z
High-Z
High-Z
High-Z
High-Z
Dout
DQ8~15
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
Dout
Mode
Power
Deselected
Deselected
Standby
Standby
Standby
Active
Active
Active
Active
Active
Active
Active
Active
X1)
H
Deselected
X1)
L
L
Output Disabled
Output Disabled
Lower Byte Read
Upper Byte Read
Word Read
X1)
L
L
H
H
H
L
H
L
H
H
L
H
L
H
H
L
High-Z
Dout
L
H
L
H
L
L
Dout
X1)
X1)
X1)
L
H
L
L
H
Din
High-Z
Din
Lower Byte Write
Upper Byte Write
Word Write
L
H
L
H
L
High-Z
Din
L
H
L
L
L
Din
1. X means don¢t care. (Must be low or high state)
ABSOLUTE MAXIMUM RATINGS1)
Item
Voltage on any pin relative to Vss
Voltage on Vcc supply relative to Vss
Power Dissipation
Symbol
VIN, VOUT
VCC
Ratings
-0.2 to VCC+0.3V(Max. 3.6V)
-0.2 to 3.6
Unit
V
V
PD
1.0
W
Storage temperature
TSTG
-65 to 150
°C
°C
Operating Temperature
TA
-25 to 85
1. Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. Functional operation should be
restricted to be used under recommended operating condition. Exposure to absolute maximum rating conditions over 1 second may affect reliability.
Revision 1.0
September 2003
- 40 -
Preliminary
MCP MEMORY
KBC00B7A0M
RECOMMENDED DC OPERATING CONDITIONS1)
Item
Symbol
Vcc
Min
2.7
0
Typ
Max
3.3
0
Unit
V
Supply voltage
Ground
3.0
Vss
0
-
V
Vcc+0.22)
0.6
Input high voltage
Input low voltage
Note:
VIH
2.2
V
-0.23)
VIL
-
V
1. TA=-25 to 85°C, otherwise specified.
2. Overshoot: VCC+2.0V in case of pulse width £20ns.
3. Undershoot: -2.0V in case of pulse width £20ns.
4. Overshoot and undershoot are sampled, not 100% tested.
CAPACITANCE1) (f=1MHz, TA=25°C)
Item
Input capacitance
Symbol
CIN
Test Condition
VIN=0V
Min
Max
8
Unit
pF
-
-
Input/Output capacitance
CIO
VIO=0V
10
pF
1. Capacitance is sampled, not 100% tested.
DC AND OPERATING CHARACTERISTIC
Typ1)
Item
Symbol
Test Conditions
Min
Max
Unit
Input leakage current
ILI
VIN=Vss to Vcc
-1
-
1
1
mA
CS1=VIH or CS2=VIL or OE=VIH or WE=VIL or
LB=UB=VIH, VIO=Vss to Vcc
Output leakage current
ILO
-1
-
-
-
mA
mA
mA
Cycle time=1ms, 100%duty, IIO=0mA, CS1£0.2V,
LB£0.2V or/and UB£0.2V, CS2³ Vcc-0.2V, VIN£0.2V or
VIN³ VCC-0.2V
ICC1
ICC2
-
5
Average operating current
Cycle time=Min, IIO=0mA, 100% duty, CS1=VIL,
CS2=VIH, LB=VIL or/and UB=VIL, VIN=VIL or VIH
55ns
-
30
Output low voltage
Output high voltage
VOL
VOH
IOL = 2.1mA
-
-
-
0.4
-
V
V
IOH = -1.0mA
2.4
Other input =0~Vcc
Standby Current(CMOS)
ISB1
1) CS1³ Vcc-0.2V, CS2³ Vcc-0.2V(CS1 controlled) or
2) 0V£CS2£0.2V(CS2 controlled)
-
5.0
25
mA
1. Typical values are measured at VCC=3.0V, TA=25°C and not 100% tested.
Revision 1.0
September 2003
- 41 -
Preliminary
MCP MEMORY
KBC00B7A0M
3)
VTM
AC OPERATING CONDITIONS
TEST CONDITIONS(Test Load and Input/Output Reference)
Input pulse level: 0.4 to 2.2V
2)
R1
Input rising and falling time: 5ns
Input and output reference voltage: 1.5V
Output load(see right): CL=30pF+1TTL
1)
2)
CL
R2
1. Including scope and jig capacitance
2. R1=3070W, R2=3150W
3. VTM =2.8V
AC CHARACTERISTICS (Vcc=2.7~3.3V, TA=-25 to 85°C)
Speed Bins
55ns
Parameter List
Symbol
Units
Min
55
-
Max
Read Cycle Time
tRC
tAA
-
55
55
25
55
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Address Access Time
Chip Select to Output
Output Enable to Valid Output
UB, LB Access Time
tCO
tOE
-
-
tBA
-
Chip Select to Low-Z Output
Read
tLZ
10
10
5
UB, LB Enable to Low-Z Output
Output Enable to Low-Z Output
Chip Disable to High-Z Output
UB, LB Disable to High-Z Output
Output Disable to High-Z Output
Output Hold from Address Change
Write Cycle Time
tBLZ
tOLZ
tHZ
-
-
0
20
20
20
-
tBHZ
tOHZ
tOH
tWC
tCW
tAS
0
0
10
55
45
0
-
Chip Select to End of Write
Address Set-up Time
-
-
Address Valid to End of Write
UB, LB Valid to End of Write
tAW
tBW
tWP
tWR
tWHZ
tDW
tDH
45
45
40
0
-
-
Write
Write Pulse Width
-
Write Recovery Time
-
Write to Output High-Z
Data to Write Time Overlap
Data Hold from Write Time
End Write to Output Low-Z
0
20
-
25
0
-
tOW
5
-
DATA RETENTION CHARACTERISTICS
Typ2)
Item
Symbol
Test Condition
CS1³ Vcc-0.2V1)
Min
1.5
-
Max
3.3
15
-
Unit
Vcc for data retention
Data retention current
Data retention set-up time
Recovery time
VDR
-
1.0
-
V
Vcc=1.5V, CS1³ Vcc-0.2V1)
IDR
mA
tSDR
0
See data retention waveform
ns
tRDR
tRC
-
-
1. 1) CS1³ Vcc-0.2V, CS2³ Vcc-0.2V(CS1 controlled) or
2) 0£CS2£0.2V(CS2 controlled)
2. Typical values are measured at TA=25°C and not 100% tested.
Revision 1.0
September 2003
- 42 -
Preliminary
MCP MEMORY
KBC00B7A0M
TIMING DIAGRAMS
TIMING WAVEFORM OF READ CYCLE(1) (Address Controlled, CS1=OE=VIL, CS2=WE=VIH, UB or/and LB=VIL)
tRC
Address
tAA
tOH
Data Out
Data Valid
Previous Data Valid
TIMING WAVEFORM OF READ CYCLE(2) (WE=VIH)
tRC
Address
tOH
tAA
tCO
CS1
CS2
tHZ
tBA
UB, LB
OE
tBHZ
tOHZ
tOE
tOLZ
tBLZ
tLZ
Data out
High-Z
Data Valid
NOTES (READ CYCLE)
1. tHZ and tOHZ are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage
levels.
2. At any given temperature and voltage condition, tHZ(Max.) is less than tLZ(Min.) both for a given device and from device to device
interconnection.
Revision 1.0
September 2003
- 43 -
Preliminary
MCP MEMORY
KBC00B7A0M
TIMING WAVEFORM OF WRITE CYCLE(1) (WE Controlled)
tWC
Address
CS1
tCW(2)
tWR(4)
CS2
tAW
tBW
UB, LB
tWP(1)
WE
tAS(3)
tDW
tDH
High-Z
High-Z
Data in
Data Valid
tWHZ
tOW
Data Undefined
Data out
TIMING WAVEFORM OF WRITE CYCLE(2) (CS1 Controlled)
tWC
Address
tAS(3)
tCW(2)
tAW
tWR(4)
CS1
CS2
tBW
UB, LB
tWP(1)
WE
tDW
tDH
Data Valid
Data in
Data out
High-Z
High-Z
Revision 1.0
September 2003
- 44 -
Preliminary
MCP MEMORY
KBC00B7A0M
TIMING WAVEFORM OF WRITE CYCLE(3) (UB, LB Controlled)
tWC
Address
CS1
tCW(2)
tAW
tWR(4)
CS2
tBW
UB, LB
tAS(3)
tWP(1)
WE
tDH
tDW
Data in
Data Valid
High-Z
Data out
High-Z
NOTES (WRITE CYCLE)
1. A write occurs during the overlap(tWP) of low CS1 and low WE. A write begins when CS1 goes low and WE goes low with asserting
UB or LB for single byte operation or simultaneously asserting UB and LB for double byte operation. A write ends at the earliest tran-
sition when CS1 goes high and WE goes high. The tWP is measured from the beginning of write to the end of write.
2. tCW is measured from the CS1 going low to the end of write.
3. tAS is measured from the address valid to the beginning of write.
4. tWR is measured from the end of write to the address change. tWR is applied in case a write ends with CS1 or WE going high.
DATA RETENTION WAVE FORM
CS1 controlled
Data Retention Mode
tSDR
tRDR
VCC
2.7V
2.2V
VDR
CS1³ VCC - 0.2V
CS1
GND
CS2 controlled
Data Retention Mode
VCC
2.7V
CS2
tSDR
tRDR
VDR
CS2£0.2V
0.4V
GND
Revision 1.0
September 2003
- 45 -
Preliminary
MCP MEMORY
KBC00B7A0M
PACKAGE DIMENSION
111-Ball FINE PITCH BGA Package (measured in millimeters)
#A1 INDEX MARK
A
11.00 ±0.10
0.80 x 11 = 8.80
11.00 ±0.10
(Datum A)
0.80
0.10 MAX
12 11 10
9 8 7 6 5 4 3 2 1
B
A
B
C
D
#A1
(Datum B)
E
F
G
H
J
K
L
M
N
0.32 ±0.05
1.30 ±0.10
4.40
111 -
Æ0.45 ±0.05
Æ
0.20
M A B
BOTTOM VIEW
TOP VIEW
Revision 1.0
September 2003
- 46 -
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