KBF080800M-D4080_技术文档

Preliminary

KBF0x0800M

MCP MEMORY

Document Title

Multi-Chip Package MEMORY

128M Bit(8Mx16) Synchronous Burst , Multi Bank NOR Flash *2 / 64M Bit(4Mx16) Synchronous Burst UtRAM *2

Revision History

Revision No. History

Draft Date

Remark

0.0

Initial Draft

November 18, 2003 Preliminary

(128M NOR Flash M-die_rev0.7)

(64M UtRAM B-die_rev0.6)

Note : For more detailed features and specifications including FAQ, please refer to Samsung’s web site.

http://samsungelectronics.com/semiconductors/products/products_index.html

The attached datasheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right

to change the specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions about device. If you have

any questions, please contact the SAMSUNG branch office near you.

1

Revision 0.0

November 2003

Preliminary

KBF0x0800M

MCP MEMORY

Multi-Chip Package MEMORY

128M Bit(8Mx16) Synchronous Burst , Multi Bank NOR Flash *2 / 64M Bit(4Mx16) Synchronous Burst UtRAM *2

FEATURES

<UtRAM(for each device)>

· Process Technology: CMOS

· Organization: 4M x16 bit

· Power Supply Voltage: VCC 2.5~2.7V

· Operating Temperature : -25°C ~ 85°C

· Package : 115Ball FBGA Type - 8.0mm x 12.0mm

0.8mm ball pitch

VCCQ 1.7~2.0V

1.4mm (Max.) Thickness

· Single Voltage, 1.7V to 1.9V for Read and Write operations

· Organization

· Three State Outputs

· Compatible with Low Power SRAM

· Supports MRS (Mode Register Set)

· Supports Asynchronous Read/Write Operation in Asynchronous

mode

· Supports Synchronous Burst Read and Asynchronous Write

Operation in Synchronous mode

- 8,388,608 x 16 bit ( Word Mode Only)

· Read While Program/Erase Operation

· Multiple Bank Architecture

- 16 Banks (8Mb Partition)

· Synchronous Burst Read Operation

· Read Access Time (@ CL=30pF)

- Asynchronous Random Access Time :

88.5ns (54MHz) / 70ns (66MHz)

- Synchronous Random Access Time :

88.5ns (54MHz) / 71ns (66MHz)

- Burst Access Time :

- Supports 4 word / 8 word / 16 word Burst Read mode

- Supports Linear Burst type & Interleave Burst type

- Latency support : 3, 4, 5, 6 (depends on clock frequency)

· Max. Burst Clock Frequency : 54MHz

14.5ns (54MHz) / 11ns (66MHz)

· Burst Length :

- Continuous Linear Burst

- Linear Burst : 8-word & 16-word with No-wrap & Wrap

· Block Architecture

GENERAL DESCRIPTION

The KBF0x0800M is a Multi Chip Package Memory which com-

bines two 128Mbit Synchronous Burst Multi Bank NOR Flash

Memory and two 64Mbit Synchronous Burst UtRAM.

128Mbit Synchronous Burst Multi Bank NOR Flash Memory is

organized as 8M x16 bits and 64Mbit Synchronous Burst UtRAM

is organized as 4M x16 bits.

- Eight 4Kword blocks and two hundreds fifty-five 32Kword

blocks

- Bank 0 contains eight 4 Kword blocks and fifteen 32Kword

blocks

In 128Mbit Synchronous Burst Multi Bank NOR Flash Memory,

the memory architecture of the device is designed to divide its

memory arrays into 263 blocks with independent hardware pro-

tection. This block architecture provides highly flexible erase and

program capability. The NOR Flash consists of sixteen banks.

This device is capable of reading data from one bank while pro-

gramming or erasing in the other bank.

- Bank 1 ~ Bank 15 contain two hundred forty 32Kword blocks

· Reduce program time using the VPP

· Power Consumption (Typical value, CL=30pF)

- Burst Access Current : 25mA

- Program/Erase Current : 15mA

- Read While Program/Erase Current : 35mA

- Standby Mode/Auto Sleep Mode : 5uA

· Block Protection/Unprotection

- Using the software command sequence

- Last two boot blocks are protected by WP=VIL

- All blocks are protected by VPP=VIL

· Handshaking Feature

Regarding read access time, at 54MHz, the device provides a

burst access of 14.5ns with initial access times of 88.5ns at 30pF.

At 66MHz, the device provides a burst access of 11ns with initial

access times of 71ns at 30pF. The device performs a program

operation in units of 16 bits (Word) and erases in units of a block.

Single or multiple blocks can be erased. The block erase opera-

tion is completed within typically 0.7 sec. The device requires

15mA as program/erase current in the extended temperature

ranges.

- Provides host system with minimum latency by monitoring

RDY

· Erase Suspend/Resume

· Program Suspend/Resume

· Unlock Bypass Program/Erase

· Hardware Reset (RESET)

· Data Polling and Toggle Bits

- Provides a software method of detecting the status of program

or erase completion

· Endurance

100K Program/Erase Cycles Minimum

· Data Retention : 10 years

· Support Common Flash Memory Interface

· Low Vcc Write Inhibit

In 64Mbit Synchronous Burst UtRAM, The device supports

DPD(Deep Power Down) mode for power saving. DPD mode is

controlled by MRS pin. The device supports MRS(Mode Register

Set) and synchronous burst read mode.

The KBF0x0800M is suitable for use in data memory of mobile

communication system to reduce not only mount area but also

power consumption. This device is available in 115-ball FBGA

Type.

SAMSUNG ELECTRONICS CO., LTD. reserves the right to change products and specifications without notice.

2

Revision 0.0

November 2003

Preliminary

KBF0x0800M

MCP MEMORY

PIN CONFIGURATION

1

2

3

4

5

6

7

8

9

10

DNU

ADVf

WP1

A3

DNU

A

B

C

D

E

F

WP2

A7

CLKf

LB

NC

Vpp

Vccu

WE

ADVu

A8

CLKu

A11

NC

DNU

A6

UB

RESET

RDY

NC

MRS

A20

NC

A19

A9

A12

A15

A21

A22

A16

NC

A2

A5

A18

A17

DQ1

DQ9

DQ10

DQ2

Vss

A13

A1

A4

A10

DQ6

DQ13

DQ12

DQ5

NC

A14

G

H

J

A0

Vss

OE

DQ0

DQ8

NC

Vccu

DQ3

Vccf

NC

CEf1

CSu

CEf2

NC

DQ4

Vccqu

NC

DQ15

DQ7

DQ14

NC

Vss

NC

K

L

DQ11

Vccf

NC

M

N

P

DNU

115-FBGA: Top View (Ball Down)

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Preliminary

KBF0x0800M

MCP MEMORY

PIN DESCRIPTION

Ball Name

Description

Ball Name

RDY

ADVf

ADVu

MRS

LB

Description

A0 to A22

DQ0 to DQ15

CEf1 , CEf2

CSu

Address Input Balls (Common)

Data Input/Output Balls (Common)

Chip Enable (Flash1, Flash2)

Chip Select (UtRAM)

Ready Output (Flash Memory)

Address Input Valid (Flash Memory)

Address Input Valid (UtRAM)

Mode Register Set (UtRAM)

Lower Byte Enable (UtRAM)

Upper Byte Enable (UtRAM)

Power Supply (Flash Memory)

Power Supply (UtRAM)

Data Out Power (UtRAM)

Ground (Common)

OE

Output Enable (Common)

Hardware Reset (Flash Memory)

Accelerates Programming (Flash Memory)

Write Enable (Common)

RESET

VPP

UB

Vccf

WE

Vccu

Vccqu

Vss

WP1

Write Protection (Flash1)

Write Protection (Flash2)

Clock (Flash Memory)

WP2

CLKf

NC

No Connection

CLKu

Clock (UtRAM)

DNU

Do Not Use

ORDERING INFORMATION

K B F 0x 0 8 0 0 M - D 408

Samsung

MCP(4 Chip) Memory

Access Time

408 : 18.5ns, 18.5ns, 18.5ns, 18.5ns

Device Type

NOR Flash + NOR Flash

Package

D : FBGA(Lead Free)

+ UtRAM + UtRAM

NOR Flash Density , Vcc , Org.

: 128Mbit + 128Mbit, Vcc=1.8V,

x16(Burst)

: Bank Size(Boot Block)

08 : 16M, 16Bank(Bottom)

09 : 16M, 16Bank(TOP)

Version

M : 1st Generation

SDRAM Density , Vcc , Org.

NAND Flash Density , Vcc , Org.

0 : NONE

UtRAM Density , Vcc/Vccq , Org.

8 : 64Mbit + 64Mbit, 2.6V/1.8V, x16, Burst

SRAM Density , Vcc , Org.

0 : NONE

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Preliminary

KBF0x0800M

MCP MEMORY

Figure 1. FUNCTIONAL BLOCK DIAGRAM

Vccf

Vss

Address(A0 to A22)

OE

WE

CEF1

RESET

Vpp

DQ0 to DQ15

128M bit

Flash Memory

WP1

CLKF

RDY

ADVF

Vccf

Vss

DQ0 to DQ15

128M bit

Flash Memory

WP2

CEF2

Vccu

Vccqu Vss

DQ0 to DQ15

CSu

UB

64M bit

UtRAM

DQ0 to DQ15

LB

CLKu

ADVu

MRS

Vccu Vccqu

Vss

DQ0 to DQ15

64M bit

UtRAM

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November 2003

Preliminary

KBF0x0800M

MCP MEMORY

128M Bit(8Mx16)

Synchronous Burst, Multi Bank NOR Flash M-die

For Each Device

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Preliminary

KBF0x0800M

MCP MEMORY

Table 1. PRODUCT LINE-UP

Synchronous/Burst

7B

(54MHz) (66MHz)

Asynchronous

7C

7B

7C

Speed Option

(54MHz) (66MHz)

Max. Initial Access Time (tIAA, ns)

Max. Burst Access Time (tBA, ns)

Max. OE Access Time (tOE, ns)

88.5

14.5

20

71

11

20

Max Access Time (tAA, ns)

88.5

14.5

20

70

20

VCC=1.7V-1.9V

Max CE Access Time (tCE, ns)

Max OE Access Time (tOE, ns)

Table 2. NOR Flash DEVICE BANK DIVISIONS

Bank 0

Bank 1 ~ Bank 15

Mbit

Block Sizes

Mbit

Block Sizes

Eight 4Kwords,

Fifteen 32Kwords

Two hundred

forty 32Kwords

8 Mbit

120 Mbit

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Preliminary

KBF0x0800M

MCP MEMORY

Table 3-1. Top Boot Block Address Table

Bank

Block

BA262

BA261

Block Size

4 Kwords

(x16) Address Range

7FF000h-7FFFFFh

7FE000h-7FEFFFh

4 Kwords

BA260

BA259

BA258

7FD000h-7FDFFFh

7FC000h-7FCFFFh

7FB000h-7FBFFFh

BA257

BA256

BA255

BA254

BA253

BA252

BA251

BA250

BA249

BA248

BA247

BA246

BA245

BA244

BA243

BA242

BA241

BA240

BA239

BA238

BA237

BA236

BA235

BA234

BA233

BA232

BA231

BA230

BA229

BA228

BA227

BA226

BA225

BA224

BA223

BA222

BA221

BA220

BA219

7FA000h-7FAFFFh

7F9000h-7F9FFFh

7F8000h-7F8FFFh

7F0000h-7F7FFFh

7E8000h-7EFFFFh

7E0000h-7E7FFFh

7D8000h-7DFFFFh

7D0000h-7D7FFFh

7C8000h-7CFFFFh

7C0000h-7C7FFFh

7B8000h-7BFFFFh

7B0000h-7B7FFFh

7A8000h-7AFFFFh

7A0000h-7A7FFFh

798000h-79FFFFh

790000h-797FFFh

788000h-78FFFFh

780000h-787FFFh

778000h-77FFFFh

770000h-777FFFh

768000h-76FFFFh

760000h-767FFFh

758000h-75FFFFh

750000h-757FFFh

748000h-74FFFFh

740000h-747FFFh

738000h-73FFFFh

730000h-737FFFh

728000h-72FFFFh

720000h-727FFFh

718000h-71FFFFh

710000h-717FFFh

708000h-70FFFFh

700000h-707FFFh

6F8000h-6FFFFFh

6F0000h-6F7FFFh

6E8000h-6EFFFFh

6E0000h-6E7FFFh

6D8000h-6DFFFFh

4 Kwords

32 Kwords

32 kwords

32 Kwords

Bank 0

Bank 1

Bank 2

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Preliminary

KBF0x0800M

MCP MEMORY

Table 3-1. Top Boot Block Address Table

Bank

Block

BA218

BA217

BA216

BA215

BA214

BA213

BA212

BA211

BA210

BA209

BA208

BA207

BA206

BA205

BA204

BA203

BA202

BA201

BA200

BA199

BA198

BA197

BA196

BA195

BA194

BA193

BA192

BA191

BA190

BA189

BA188

BA187

BA186

BA185

BA184

BA183

BA182

BA181

BA180

BA179

BA178

BA177

BA176

BA175

Block Size

32 Kwords

(x16) Address Range

6D0000h-6D7FFFh

6C8000h-6CFFFFh

6C0000h-6C7FFFh

6B8000h-6BFFFFh

6B0000h-6B7FFFh

6A8000h-6AFFFFh

6A0000h-6A7FFFh

698000h-69FFFFh

690000h-697FFFh

688000h-68FFFFh

680000h-687FFFh

678000h-67FFFFh

670000h-677FFFh

668000h-66FFFFh

660000h-667FFFh

658000h-65FFFFh

650000h-657FFFh

648000h-64FFFFh

640000h-647FFFh

638000h-63FFFFh

630000h-637FFFh

628000h-62FFFFh

620000h-627FFFh

618000h-61FFFFh

610000h-617FFFh

608000h-60FFFFh

600000h-607FFFh

5F8000h-5FFFFFh

5F0000h-5F7FFFh

5E8000h-5EFFFFh

5E0000h-5E7FFFh

5D8000h-5DFFFFh

5D0000h-5D7FFFh

5C8000h-5CFFFFh

5C0000h-5C7FFFh

5B8000h-5BFFFFh

5B0000h-5B7FFFh

5A8000h-5AFFFFh

5A0000h-5A7FFFh

598000h-59FFFFh

590000h-597FFFh

588000h-58FFFFh

580000h-587FFFh

578000h-57FFFFh

Bank 2

Bank 3

Bank 4

Bank 5

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Preliminary

KBF0x0800M

MCP MEMORY

Table 3-1. Top Boot Block Address Table

Bank

Block

BA174

BA173

BA172

BA171

BA170

BA169

BA168

BA167

BA166

BA165

BA164

BA163

BA162

BA161

BA160

BA159

BA158

BA157

BA156

BA155

BA154

BA153

BA152

BA151

BA150

BA149

BA148

BA147

BA146

BA145

BA144

BA143

BA142

BA141

BA140

BA139

BA138

BA137

BA136

BA135

BA134

BA133

BA132

BA131

BA130

Block Size

32 Kwords

(x16) Address Range

570000h-577FFFh

568000h-56FFFFh

560000h-567FFFh

558000h-55FFFFh

550000h-557FFFh

548000h-54FFFFh

540000h-547FFFh

538000h-53FFFFh

530000h-537FFFh

528000h-52FFFFh

520000h-527FFFh

518000h-51FFFFh

510000h-517FFFh

508000h-50FFFFh

500000h-507FFFh

4F8000h-4FFFFFh

4F0000h-4F7FFFh

4E8000h-4EFFFFh

4E0000h-4E7FFFh

4D8000h-4DFFFFh

4D0000h-4D7FFFh

4C8000h-4CFFFFh

4C0000h-4C7FFFh

4B8000h-4BFFFFh

4B0000h-4B7FFFh

4A8000h-4AFFFFh

4A0000h-4A7FFFh

498000h-49FFFFh

490000h-497FFFh

488000h-48FFFFh

480000h-487FFFh

478000h-47FFFFh

470000h-477FFFh

468000h-46FFFFh

460000h-467FFFh

458000h-45FFFFh

450000h-457FFFh

448000h-44FFFFh

440000h-447FFFh

438000h-43FFFFh

430000h-437FFFh

428000h-42FFFFh

420000h-427FFFh

418000h-41FFFFh

410000h-417FFFh

Bank 5

Bank 6

Bank 7

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Preliminary

KBF0x0800M

MCP MEMORY

Table 3-1. Top Boot Block Address Table

Bank

Block

BA129

BA128

BA127

BA126

BA125

BA124

BA123

BA122

BA121

BA120

BA119

BA118

BA117

BA116

BA115

BA114

BA113

BA112

BA111

BA110

BA109

BA108

BA107

BA106

BA105

BA104

BA103

BA102

BA101

BA100

BA99

Block Size

32 Kwords

(x16) Address Range

408000h-40FFFFh

400000h-407FFFh

3F8000h-3FFFFFh

3F0000h-3F7FFFh

3E8000h-3EFFFFh

3E0000h-3E7FFFh

3D8000h-3DFFFFh

3D0000h-3D7FFFh

3C8000h-3CFFFFh

3C0000h-3C7FFFh

3B8000h-3BFFFFh

3B0000h-3B7FFFh

3A8000h-3AFFFFh

3A0000h-3A7FFFh

398000h-39FFFFh

390000h-397FFFh

388000h-38FFFFh

380000h-387FFFh

378000h-37FFFFh

370000h-377FFFh

368000h-36FFFFh

360000h-367FFFh

358000h-35FFFFh

350000h-357FFFh

348000h-34FFFFh

340000h-347FFFh

338000h-33FFFFh

330000h-337FFFh

328000h-32FFFFh

320000h-327FFFh

318000h-31FFFFh

310000h-317FFFh

308000h-30FFFFh

300000h-307FFFh

2F8000h-2FFFFFh

2F0000h-2F7FFFh

2E8000h-2EFFFFh

2E0000h-2E7FFFh

2D8000h-2DFFFFh

2D0000h-2D7FFFh

2C8000h-2CFFFFh

2C0000h-2C7FFFh

2B8000h-2BFFFFh

2B0000h-2B7FFFh

2A8000h-2AFFFFh

Bank 7

Bank 8

Bank 9

BA98

BA97

BA96

BA95

BA94

BA93

BA92

BA91

Bank 10

BA90

BA89

BA88

BA87

BA86

BA85

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Preliminary

KBF0x0800M

MCP MEMORY

Table 3-1. Top Boot Block Address Table

Bank

Block

BA84

BA83

BA82

BA81

BA80

BA79

BA78

BA77

BA76

BA75

BA74

BA73

BA72

BA71

BA70

BA69

BA68

BA67

BA66

BA65

BA64

BA63

BA62

BA61

BA60

BA59

BA58

BA57

BA56

BA55

BA54

BA53

BA52

BA51

BA50

BA49

BA48

BA47

BA46

BA45

BA44

BA43

BA42

BA41

BA40

Block Size

32 Kwords

(x16) Address Range

2A0000h-2A7FFFh

298000h-29FFFFh

290000h-297FFFh

288000h-28FFFFh

280000h-287FFFh

278000h-27FFFFh

270000h-277FFFh

268000h-26FFFFh

260000h-267FFFh

258000h-25FFFFh

250000h-257FFFh

248000h-24FFFFh

240000h-247FFFh

238000h-23FFFFh

230000h-237FFFh

228000h-22FFFFh

220000h-227FFFh

218000h-21FFFFh

210000h-217FFFh

208000h-20FFFFh

200000h-207FFFh

1F8000h-1FFFFFh

1F0000h-1F7FFFh

1E8000h-1EFFFFh

1E0000h-1E7FFFh

1D8000h-1DFFFFh

1D0000h-1D7FFFh

1C8000h-1CFFFFh

1C0000h-1C7FFFh

1B8000h-1BFFFFh

1B0000h-1B7FFFh

1A8000h-1AFFFFh

1A0000h-1A7FFFh

198000h-19FFFFh

190000h-197FFFh

188000h-18FFFFh

180000h-187FFFh

178000h-17FFFFh

170000h-177FFFh

168000h-16FFFFh

160000h-167FFFh

158000h-15FFFFh

150000h-157FFFh

148000h-14FFFFh

140000h-147FFFh

Bank 10

Bank 11

Bank 12

Bank 13

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Preliminary

KBF0x0800M

MCP MEMORY

Table 3-1. Top Boot Block Address Table

Bank

Block

BA39

BA38

BA37

BA36

BA35

BA34

BA33

BA32

BA31

BA30

BA29

BA28

BA27

BA26

BA25

BA24

BA23

BA22

BA21

BA20

BA19

BA18

BA17

BA16

BA15

BA14

BA13

BA12

BA11

BA10

BA9

Block Size

32 Kwords

(x16) Address Range

138000h-13FFFFh

130000h-137FFFh

128000h-12FFFFh

120000h-127FFFh

118000h-11FFFFh

110000h-117FFFh

108000h-10FFFFh

100000h-107FFFh

0F8000h-0FFFFFh

0F0000h-0F7FFFh

0E8000h-0EFFFFh

0E0000h-0E7FFFh

0D8000h-0DFFFFh

0D0000h-0D7FFFh

0C8000h-0CFFFFh

0C0000h-0C7FFFh

0B8000h-0BFFFFh

0B0000h-0B7FFFh

0A8000h-0AFFFFh

0A0000h-0A7FFFh

098000h-09FFFFh

090000h-097FFFh

088000h-08FFFFh

080000h-087FFFh

078000h-07FFFFh

070000h-077FFFh

068000h-06FFFFh

060000h-067FFFh

058000h-05FFFFh

050000h-057FFFh

048000h-04FFFFh

040000h-047FFFh

038000h-03FFFFh

030000h-037FFFh

028000h-02FFFFh

020000h-027FFFh

018000h-01FFFFh

010000h-017FFFh

008000h-00FFFFh

000000h-007FFFh

Bank 13

32 Kwords

Bank 14

BA8

Bank 15

BA7

BA6

BA5

BA4

BA3

BA2

BA1

BA0

13

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Preliminary

KBF0x0800M

MCP MEMORY

Table 3-2. Bottom Boot Block Address Table

Bank

Block

BA262

BA261

BA260

BA259

BA258

BA257

BA256

BA255

BA254

BA253

BA252

BA251

BA250

BA249

BA248

BA247

BA246

BA245

BA244

BA243

BA242

BA241

BA240

BA239

BA238

BA237

BA236

BA235

BA234

BA233

BA232

BA231

BA230

BA229

BA228

BA227

BA226

Block Size

(x16) Address Range

7F8000h-7FFFFFh

7F0000h-7F7FFFh

7E8000h-7EFFFFh

7E0000h-7E7FFFh

7D8000h-7DFFFFh

7D0000h-7D7FFFh

7C8000h-7CFFFFh

7C0000h-7C7FFFh

7B8000h-7BFFFFh

7B0000h-7B7FFFh

7A8000h-7AFFFFh

7A0000h-7A7FFFh

798000h-79FFFFh

790000h-797FFFh

788000h-78FFFFh

780000h-787FFFh

778000h-77FFFFh

770000h-777FFFh

768000h-76FFFFh

760000h-767FFFh

758000h-75FFFFh

750000h-757FFFh

748000h-74FFFFh

740000h-747FFFh

738000h-73FFFFh

730000h-737FFFh

728000h-72FFFFh

720000h-727FFFh

718000h-71FFFFh

710000h-717FFFh

708000h-70FFFFh

700000h-707FFFh

6F8000h-6FFFFFh

6F0000h-6F7FFFh

6E8000h-6EFFFFh

6E0000h-6E7FFFh

6D8000h-6DFFFFh

32 Kwords

32 kwords

32 Kwords

Bank 15

Bank 14

Bank 13

14

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Preliminary

KBF0x0800M

MCP MEMORY

Table 3-2. Bottom Boot Block Address Table

Bank

Block

BA225

BA224

BA223

BA222

BA221

BA220

BA219

BA218

BA217

BA216

BA215

BA214

BA213

BA212

BA211

BA210

BA209

BA208

BA207

BA206

BA205

BA204

BA203

BA202

BA201

BA200

BA199

BA198

BA197

BA196

BA195

BA194

BA193

BA192

BA191

BA190

BA189

BA188

BA187

BA186

BA185

BA184

BA183

Block Size

32 Kwords

(x16) Address Range

6D0000h-6D7FFFh

6C8000h-6CFFFFh

6C0000h-6C7FFFh

6B8000h-6BFFFFh

6B0000h-6B7FFFh

6A8000h-6AFFFFh

6A0000h-6A7FFFh

698000h-69FFFFh

690000h-697FFFh

688000h-68FFFFh

680000h-687FFFh

678000h-67FFFFh

670000h-677FFFh

668000h-66FFFFh

660000h-667FFFh

658000h-65FFFFh

650000h-657FFFh

648000h-64FFFFh

640000h-647FFFh

638000h-63FFFFh

630000h-637FFFh

628000h-62FFFFh

620000h-627FFFh

618000h-61FFFFh

610000h-617FFFh

608000h-60FFFFh

600000h-607FFFh

5F8000h-5FFFFFh

5F0000h-5F7FFFh

5E8000h-5EFFFFh

5E0000h-5E7FFFh

5D8000h-5DFFFFh

5D0000h-5D7FFFh

5C8000h-5CFFFFh

5C0000h-5C7FFFh

5B8000h-5BFFFFh

5B0000h-5B7FFFh

5A8000h-5AFFFFh

5A0000h-5A7FFFh

598000h-59FFFFh

590000h-597FFFh

588000h-58FFFFh

580000h-587FFFh

Bank 13

Bank 12

Bank 11

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Table 3-2. Bottom Boot Block Address Table

Bank

Block

BA182

BA181

BA180

BA179

BA178

BA177

BA176

BA175

BA174

BA173

BA172

BA171

BA170

BA169

BA168

BA167

BA166

BA165

BA164

BA163

BA162

BA161

BA160

BA159

BA158

BA157

BA156

BA155

BA154

BA153

BA152

BA151

BA150

BA149

BA148

BA147

BA146

BA145

BA144

BA143

BA142

BA141

BA140

BA139

BA138

BA137

Block Size

32 Kwords

(x16) Address Range

578000h-57FFFFh

570000h-577FFFh

568000h-56FFFFh

560000h-567FFFh

558000h-55FFFFh

550000h-557FFFh

548000h-54FFFFh

540000h-547FFFh

538000h-53FFFFh

530000h-537FFFh

528000h-52FFFFh

520000h-527FFFh

518000h-51FFFFh

510000h-517FFFh

508000h-50FFFFh

500000h-507FFFh

4F8000h-4FFFFFh

4F0000h-4F7FFFh

4E8000h-4EFFFFh

4E0000h-4E7FFFh

4D8000h-4DFFFFh

4D0000h-4D7FFFh

4C8000h-4CFFFFh

4C0000h-4C7FFFh

4B8000h-4BFFFFh

4B0000h-4B7FFFh

4A8000h-4AFFFFh

4A0000h-4A7FFFh

498000h-49FFFFh

490000h-497FFFh

488000h-48FFFFh

480000h-487FFFh

478000h-47FFFFh

470000h-477FFFh

468000h-46FFFFh

460000h-467FFFh

458000h-45FFFFh

450000h-457FFFh

448000h-44FFFFh

440000h-447FFFh

438000h-43FFFFh

430000h-437FFFh

428000h-42FFFFh

420000h-427FFFh

418000h-41FFFFh

410000h-417FFFh

Bank 10

Bank 9

Bank 8

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Table 3-2. Bottom Boot Block Address Table

Bank

Block

BA136

BA135

BA134

BA133

BA132

BA131

BA130

BA129

BA128

BA127

BA126

BA125

BA124

BA123

BA122

BA121

BA120

BA119

BA118

BA117

BA116

BA115

BA114

BA113

BA112

BA111

BA110

BA109

BA108

BA107

BA106

BA105

BA104

BA103

BA102

BA101

BA100

BA99

Block Size

32 Kwords

(x16) Address Range

408000h-40FFFFh

400000h-407FFFh

3F8000h-3FFFFFh

3F0000h-3F7FFFh

3E8000h-3EFFFFh

3E0000h-3E7FFFh

3D8000h-3DFFFFh

3D0000h-3D7FFFh

3C8000h-3CFFFFh

3C0000h-3C7FFFh

3B8000h-3BFFFFh

3B0000h-3B7FFFh

3A8000h-3AFFFFh

3A0000h-3A7FFFh

398000h-39FFFFh

390000h-397FFFh

388000h-38FFFFh

380000h-387FFFh

378000h-37FFFFh

370000h-377FFFh

368000h-36FFFFh

360000h-367FFFh

358000h-35FFFFh

350000h-357FFFh

348000h-34FFFFh

340000h-347FFFh

338000h-33FFFFh

330000h-337FFFh

328000h-32FFFFh

320000h-327FFFh

318000h-31FFFFh

310000h-317FFFh

308000h-30FFFFh

300000h-307FFFh

2F8000h-2FFFFFh

2F0000h-2F7FFFh

2E8000h-2EFFFFh

2E0000h-2E7FFFh

2D8000h-2DFFFFh

2D0000h-2D7FFFh

2C8000h-2CFFFFh

2C0000h-2C7FFFh

2B8000h-2BFFFFh

2B0000h-2B7FFFh

2A8000h-2AFFFFh

Bank 8

Bank 7

Bank 6

BA98

Bank 5

BA97

BA96

BA95

BA94

BA93

BA92

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Table 3-2. Bottom Boot Block Address Table

Bank

Block

BA91

BA90

BA89

BA88

BA87

BA86

BA85

BA84

BA83

BA82

BA81

BA80

BA79

BA78

BA77

BA76

BA75

BA74

BA73

BA72

BA71

BA70

BA69

BA68

BA67

BA66

BA65

BA64

BA63

BA62

BA61

BA60

BA59

BA58

BA57

BA56

BA55

BA54

BA53

BA52

BA51

BA50

BA49

BA48

BA47

Block Size

32 Kwords

(x16) Address Range

2A0000h-2A7FFFh

298000h-29FFFFh

290000h-297FFFh

288000h-28FFFFh

280000h-287FFFh

278000h-27FFFFh

270000h-277FFFh

268000h-26FFFFh

260000h-267FFFh

258000h-25FFFFh

250000h-257FFFh

248000h-24FFFFh

240000h-247FFFh

238000h-23FFFFh

230000h-237FFFh

228000h-22FFFFh

220000h-227FFFh

218000h-21FFFFh

210000h-217FFFh

208000h-20FFFFh

200000h-207FFFh

1F8000h-1FFFFFh

1F0000h-1F7FFFh

1E8000h-1EFFFFh

1E0000h-1E7FFFh

1D8000h-1DFFFFh

1D0000h-1D7FFFh

1C8000h-1CFFFFh

1C0000h-1C7FFFh

1B8000h-1BFFFFh

1B0000h-1B7FFFh

1A8000h-1AFFFFh

1A0000h-1A7FFFh

198000h-19FFFFh

190000h-197FFFh

188000h-18FFFFh

180000h-187FFFh

178000h-17FFFFh

170000h-177FFFh

168000h-16FFFFh

160000h-167FFFh

158000h-15FFFFh

150000h-157FFFh

148000h-14FFFFh

140000h-147FFFh

Bank 5

Bank 4

Bank 3

Bank 2

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Table 3-2. Bottom Boot Block Address Table

Bank

Block

BA46

BA45

BA44

BA43

BA42

BA41

BA40

BA39

BA38

BA37

BA36

BA35

BA34

BA33

BA32

BA31

BA30

BA29

BA28

BA27

BA26

BA25

BA24

BA23

BA22

BA21

BA20

BA19

BA18

BA17

BA16

BA15

BA14

BA13

BA12

BA11

BA10

BA9

Block Size

32 Kwords

(x16) Address Range

138000h-13FFFFh

130000h-137FFFh

128000h-12FFFFh

120000h-127FFFh

118000h-11FFFFh

110000h-117FFFh

108000h-10FFFFh

100000h-107FFFh

0F8000h-0FFFFFh

0F0000h-0F7FFFh

0E8000h-0EFFFFh

0E0000h-0E7FFFh

0D8000h-0DFFFFh

0D0000h-0D7FFFh

0C8000h-0CFFFFh

0C0000h-0C7FFFh

0B8000h-0BFFFFh

0B0000h-0B7FFFh

0A8000h-0AFFFFh

0A0000h-0A7FFFh

098000h-09FFFFh

090000h-097FFFh

088000h-08FFFFh

080000h-087FFFh

078000h-07FFFFh

070000h-077FFFh

068000h-06FFFFh

060000h-067FFFh

058000h-05FFFFh

050000h-057FFFh

048000h-04FFFFh

040000h-047FFFh

038000h-03FFFFh

030000h-037FFFh

028000h-02FFFFh

020000h-027FFFh

018000h-01FFFFh

010000h-017FFFh

008000h-00FFFFh

007000h-007FFFh

006000h-006FFFh

005000h-005FFFh

004000h-004FFFh

003000h-003FFFh

002000h-002FFFh

001000h-001FFFh

000000h-000FFFh

Bank 2

32 Kwords

4 Kwords

Bank 1

Bank 0

BA8

BA7

BA6

4 Kwords

BA5

4 Kwords

BA4

4 Kwords

BA3

4 Kwords

BA2

4 Kwords

BA1

4 Kwords

BA0

4 Kwords

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PRODUCT INTRODUCTION

The device is an 128Mbit (134,217,728 bits) NOR-type Burst Flash memory. The device features 1.8V single voltage power supply

operating within the range of 1.7V to 1.9V. The device is programmed by using the Channel Hot Electron (CHE) injection mechanism

which is used to program EPROMs. The device is erased electrically by using Fowler-Nordheim tunneling mechanism. To provide

highly flexible erase and program capability, the device adapts a block memory architecture that divides its memory array into 263

blocks (32-Kword x 255 , 4-Kword x 8, ). Programming is done in units of 16 bits (Word). All bits of data in one or multiple blocks can

be erased when the device executes the erase operation. To prevent the device from accidental erasing or over-writing the pro-

grammed data, 263 memory blocks can be hardware protected. Regarding read access time, at 54MHz, the device provides a burst

access of 14.5ns with initial access times of 88.5ns at 30pF. At 66MHz, the device provides a burst access of 11ns with initial access

times of 71ns at 30pF. The command set of device is compatible with standard Flash devices. The device uses Chip Enable (CE),

Write Enable (WE), Address Valid(AVD) and Output Enable (OE) to control asynchronous read and write operation. For burst opera-

tions, the device additionally requires Ready (RDY) and Clock (CLK). Device operations are executed by selective command codes.

The command codes to be combined with addresses and data are sequentially written to the command registers using microproces-

sor write timing. The command codes serve as inputs to an internal state machine which controls the program/erase circuitry. Reg-

ister contents also internally latch addresses and data necessary to execute the program and erase operations. The device is

implemented with Internal Program/Erase Routines to execute the program/erase operations. The Internal Program/Erase Routines

are invoked by program/erase command sequences. The Internal Program Routine automatically programs and verifies data at

specified addresses. The Internal Erase Routine automatically pre-programs the memory cell which is not programmed and then

executes the erase operation. The device has means to indicate the status of completion of program/erase operations. The status

can be indicated via Data polling of DQ7, or the Toggle bit (DQ6). Once the operations have been completed, the device automati-

cally resets itself to the read mode. The device requires only 25 mA as burst and asynchronous mode read current and 15 mA for

program/erase operations.

Table 4. Device Bus Operations

Operation

CE

OE

WE

A0-22

DQ0-15

RESET

CLK

AVD

Asynchronous Read Operation

L

H

Add In

I/O

H

L

X

Write

L

H

X

L

H

X

H

L

Add In

I/O

High-Z

X

H

L

X

Standby

X

H

X

H

X

Hardware Reset

Load Initial Burst Address

X

Add In

X

H

L

Burst

DOUT

Burst Read Operation

L

H

X

Terminate Burst Read Cycle

H

X

L

X

H

X

High-Z

I/O

X

Terminate Burst Read Cycle via RESET

X

Terminate Current Burst Read Cycle and Start

New Burst Read Cycle

Add In

H

Note : L=VIL (Low), H=VIH (High), X=Don’t Care.

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COMMAND DEFINITIONS

The device operates by selecting and executing its operational modes. Each operational mode has its own command set. In order to

select a certain mode, a proper command with specific address and data sequences must be written into the command register. Writ-

ing incorrect information which include address and data or writing an improper command will reset the device to the read mode. The

defined valid register command sequences are stated in Table 5.

Table 5. Command Sequences

Command Definitions

Cycle

1st Cycle 2nd Cycle 3rd Cycle

4th Cycle

5th Cycle 6th Cycle

Add

Data

Add

Data

Add

Data

Add

Data

Add

Data

Add

Data

Add

Data

Add

Data

Add

Data

Add

Data

Add

Data

Add

Data

Add

Data

Add

Data

Add

Data

Add

Data

Add

Data

Add

Data

RA

RD

Asynchronous Read

1

XXXH

F0H

Reset(Note 5)

1

4

3

2

6

1

555H

AAH

2AAH

55H

(DA)555H

90H

(DA)X00H

ECH

Autoselect

Manufacturer ID(Note 6)

555H

AAH

2AAH

55H

(DA)555H

90H

(DA)X01H

Note6

Autoselect

Device ID(Note 6)

555H

AAH

2AAH

55H

(BA)555H

90H

(BA)X02H

00H/01H

(DA)X03H

0H/1H

Autoselect

Block Protection Verify(Note 7)

555H

AAH

2AAH

55H

(DA)555H

90H

Autoselect

Handshaking(Note 6, 8)

555H

AAH

2AAH

55H

555H

PA

Program

A0H

PD

555H

AAH

2AAH

55H

555H

Unlock Bypass

20H

XXX

PA

Unlock Bypass Program(Note 9)

Unlock Bypass Block Erase(Note 9)

Unlock Bypass Chip Erase(Note 9)

Unlock Bypass Reset

Chip Erase

A0H

PD

XXX

BA

80H

30H

XXXH

80H

XXXH

10H

XXXH

90H

XXXH

00H

555H

AAH

2AAH

55H

555H

80H

555H

AAH

555H

AAH

2AAH

55H

555H

10H

BA

555H

AAH

2AAH

55H

555H

80H

2AAH

55H

Block Erase

30H

(DA)XXXH

B0H

Erase Suspend (Note 10)

Erase Resume (Note 11)

Program Suspend (Note12)

Program Resume (Note11)

(DA)XXXH

30H

(DA)XXXH

B0H

(DA)XXXH

30H

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Table 5. Command Sequences (Continued)

Command Definitions

Cycle

1st Cycle 2nd Cycle 3rd Cycle 4th Cycle 5th Cycle 6th Cycle

Add

Block Protection/Unprotection (Note 13)

Data

XXX

60H

XXX

60H

ABP

60H

3

Add

(DA)X55H

98H

CFI Query (Note 14)

Data

1

3

Add

Set Burst Mode Configuration Register (Note 15)

Data

555H

2AAH

55H

(CR)555H

C0H

AAH

Notes:

1. RA : Read Address , PA : Program Address, RD : Read Data, PD : Program Data , BA : Block Address (A22 ~ A12)

DA : Bank Address (A22 ~ A19) , ABP : Address of the block to be protected or unprotected, CR : Configuration Register Setting

2. The 4th cycle data of autoselect mode and RD are output data. The others are input data.

3. Data bits DQ15–DQ8 are don’t care in command sequences, except for RD, PD and Device ID.

4. Unless otherwise noted, address bits A22–A11 are don’t cares.

5. The reset command is required to return to read mode.

If a bank entered the autoselect mode during the erase suspend mode, writing the reset command returns that bank to the erase suspend mode.

If a bank entered the autoselect mode during the program suspend mode, writing the reset command returns that bank to the program suspend mode.

If DQ5 goes high during the program or erase operation, writing the reset command returns that bank to read mode or erase suspend mode if that

bank was in erase suspend mode.

6. The 3rd and 4th cycle bank address of autoselect mode must be same.

Device ID Data : "22F4H" for Top Boot Block Device, "22F5H" for Bottom Boot Block Device

7. 00H for an unprotected block and 01H for a protected block.

8. 0H for handshaking, 1H for non-handshaking

9. The unlock bypass command sequence is required prior to this command sequence.

10. The system may read and program in non-erasing blocks when in the erase suspend mode.

The system may enter the autoselect mode when in the erase suspend mode.

The erase suspend command is valid only during a block erase operation, and requires the bank address.

11. The erase/program resume command is valid only during the erase/program suspend mode, and requires the bank address.

12. This mode is used only to enable Data Read by suspending the Program operation.

13. Set ABP(Address of the block to be protected or unprotected) as either A6 = VIH, A1 = VIH and A0 = VIL for unprotected or A6 = VIL, A1 = VIH

and A0 = VIL for protected.

14. Command is valid when the device is in Read mode or Autoselect mode.

15. See "Set Burst Mode Configuration Register" for details.

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DEVICE OPERATION

To write a command or command sequence (which includes programming data to the device and erasing blocks of memory), the

system must drive CLK, WE and CE to VIL and OE to VIH when providing address or data. The device provide the unlock bypass

mode to save its program time for program operation. Unlike the standard program command sequence which is comprised of four

bus cycles, only two program cycles are required to program a word in the unlock bypass mode. One block, multiple blocks, or the

entire device can be erased. Table 3 indicates the address space that each block occupies. The device’s address space is divided

into sixteen banks: Bank 0 contains the boot/parameter blocks, and the other banks(from Bank 1 to 15) consist of uniform blocks. A

“bank address” is the address bits required to uniquely select a bank. Similarly, a “block address” is the address bits required to

uniquely select a block. ICC2 in the DC Characteristics table represents the active current specification for the write mode. The AC

Characteristics section contains timing specification tables and timing diagrams for write operations.

Read Mode

The device automatically enters to asynchronous read mode after device power-up. No commands are required to retrieve data in

asynchronous mode. After completing an Internal Program/Erase Routine, each bank is ready to read array data. The reset com-

mand is required to return a bank to the read(or erase-suspend-read)mode if DQ5 goes high during an active program/erase opera-

tion, or if the bank is in the autoselect mode.

The synchronous(burst) mode will automatically be enabled on the first rising edge on the CLK input while AVD is held low. That

means device enters burst read mode from asynchronous read mode to burst read mode using CLK and AVD signal. When the burst

read is finished(or terminated), the device return to asynchronous read mode automatically.

Asynchronous Read Mode

For the asynchronous read mode a valid address should be asserted on A0-A22, while driving AVD and CE to VIL. WE should

remain at VIH . The data will appear on DQ0-DQ15. Since the memory array is divided into sixteen banks, each bank remains

enabled for read access until the command register contents are altered.

Address access time (tAA) is equal to the delay from valid addresses to valid output data. The chip enable access time(tCE) is the

delay from the falling edge of CE to valid data at the outputs. The output enable access time(tOE) is the delay from the falling edge of

OE to valid data at the output. To prevent the memory content from spurious altering during power transition, the initial state machine

is set for reading array data upon device power-up, or after a hardware reset.

Synchronous (Burst) Read Mode

The device is capable of continuous linear burst operation and linear burst operation of a preset length. For the burst mode, the sys-

tem should determine how many clock cycles are desired for the initial word(tIACC) of each burst access and what mode of burst

operation is desired using "Burst Mode Configuration Register" command sequences. See "Set Burst Mode Configuration" for further

details. The status data also can be read during burst read mode by using AVD signal with a bank address. To initiate the synchro-

nous read again, a new address and AVD pulse is needed after the host has completed status reads or the device has completed

the program or erase operation.

Continuous Linear Burst Read

The synchronous(burst) mode will automatically be enabled on the first rising edge on the CLK input while AVD is held low. Note that

the device is enabled for asynchronous mode when it first powers up. The initial word is output tIAA after the rising edge of the first

CLK cycle. Subsequent words are output tBA after the rising edge of each successive clock cycle, which automatically increments the

internal address counter. Note that the device has internal address boundary that occurs every 16 words. When the device is cross-

ing the first word boundary, additional clock cycles are needed before data appears for the next address. The number of addtional

clock cycle can varies from zero to three cycles, and the exact number of additional clock cycle depends on the starting address of

burst read.(Refer to Figure 13) The RDY output indicates this condition to the system by pulsing low. The device will continue to out-

put sequential burst data, wrapping around to address 000000h after it reaches the highest addressable memory location until the

system asserts CE high, RESET low or AVD low in conjunction with a new address.(See Table 4.) The reset command does not ter-

minate the burst read operation.

If the host system crosses the bank boundary while reading in burst mode, and the accessed bank is not programming or erasing, a

additional clock cycles are needed as previously mentioned. If the host system crosses the bank boundary while the accessed bank

is programming or erasing, that is busy bank, the synchronous read will be terminated.

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8-,16-Word Linear Burst Read

As well as the Continuous Linear Burst Mode, there are two(8 & 16 word) linear wrap & no-wrap mode, in which a fixed number of

words are read from consecutive addresses. In these modes, the addresses for burst read are determined by the group within which

the starting address falls. The groups are sized according to the number of words read in a single burst sequence for a given

mode.(See Table. 6)

Table 6. Burst Address Groups(Wrap mode only)

Burst Mode

8 word

Group Size

8 words

Group Address Ranges

0-7h, 8-Fh, 10-17h, ....

0-Fh, 10-1Fh, 20-2Fh, ....

16 word

16words

As an example:

In wrap mode case, if the starting address in the 8-word mode is 2h, the address range to be read would be 0-7h, and the wrap burst

sequence would be 2-3-4-5-6-7-0-1h. The burst sequence begins with the starting address written to the device, but wraps back to

the first address in the selected group. In a similar manner, 16-word wrap mode begin their burst sequence on the starting address

written to the device, and then wrap back to the first address in the selected address group.

In no-wrap mode case, if the starting address in the 8-word mode is 2h, the no-wrap burst sequence would be 2-3-4-5-6-7-8-9h. The

burst sequence begins with the starting address written to the device, and continue to the 8th address from starting address. In a

similar manner, 16-word no-wrap mode begin their burst sequence on the starting address written to the device, and continue to the

16th address from starting address. Also, when the address cross the word boundary in no-wrap mode, same number of additional

clock cycles as continuous linear mode is needed.

Programmable Wait State

The programmable wait state feature indicates to the device the number of additional clock cycles that must elapse after AVD is

driven active for burst read mode. Upon power up, the number of total initial access cycles defaults to seven.

Handshaking

The handshaking feature allows the host system to simply monitor the RDY signal from the device to determine when the initial word

of burst data is ready to be read. To set the number of initial cycle for optimal burst mode, the host should use the programmable wait

state configuration.(See "Set Burst Mode Configuration Register" for details.) The rising edge of RDY after OE goes low indicates

the initial word of valid burst data. Using the autoselect command sequence the handshaking feature may be verified in the device.

Set Burst Mode Configuration Register

The device uses a configuration register to set the various burst parameters : the number of initial cycles for burst and burst read

mode. The burst mode configuration register must be set before the device enter burst mode.

The burst mode configuration register is loaded with a three-cycle command sequences. On the third cycle, the data should be C0h,

address bits A11-A0 should be 555h, and address bits A18-A12 set the code to be latched. The device will power up or after a hard-

ware reset with the default setting.

Table 7. Burst Mode Configuration Register Table

Address Bit

Function

Settings(Binary)

1 = RDY active one clock cycle before data

0 = RDY active with data(default)

A18

RDY Active

A17

A16

000 = Continuous(default)

001 = 8-word linear with wrap

010 = 16-word linear with wrap

011 = 8-word linear with no-wrap

100 = 16-word linear with no-wrap

101 ~ 111 = Reserve

Burst Read Mode

A15

A14

A13

000 = Data is valid on the 4th active CLK edge after AVD transition to VIH

001 = Data is valid on the 5th active CLK edge after AVD transition to VIH

010 = Data is valid on the 6th active CLK edge after AVD transition to VIH

011 = Data is valid on the 7th active CLK edge after AVD transition to VIH (default)

Programmable Wait State

100 = Reserve

101 = Reserve

110 = Reserve

111 = Reserve

A12

Programmable Wait State Configuration

This feature informs the device of the number of clock cycles that must elapse after AVD# is driven active before data will be avail-

able. This value is determined by the input frequency of the device. Address bits A14-A12 determine the setting. (See Burst Mode

Configuration Register Table)

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The Programmable wait state setting instructs the device to set a particular number of clock cycles for the initial access in burst

mode. Note that hardware reset will set the wait state to the default setting, that is 7 initial cycles.

Burst Read Mode Setting

The device supports five different burst read modes : continuous linear mode, 8 and 16 word linear burst modes with wrap and 8 and

16 word linear burst modes with no-wrap.

RDY Configuration

By default, the RDY pin will be high whenever there is valid data on the output. The device can be set so that RDY goes active one

data cycle before active data. Address bit A18 determine this setting. Note that RDY always go high with valid data in case of word

boundary crossing.

Table 8. Burst Address Sequences

Burst Address Sequence(Decimal)

Start

Addr.

Continuous Burst

0-1-2-3-4-5-6...

1-2-3-4-5-6-7...

2-3-4-5-6-7-8...

8-word Burst

0-1-2-3-4-5-6-7

1-2-3-4-5-6-7-0

2-3-4-5-6-7-0-1

16-word Burst

0

1

2

0-1-2-3-4-....-13-14-15

1-2-3-4-5-....-14-15-0

2-3-4-5-6-....-15-0-1

Wrap

.

0

1

2

0-1-2-3-4-5-6...

1-2-3-4-5-6-7...

2-3-4-5-6-7-8...

0-1-2-3-4-5-6-7

1-2-3-4-5-6-7-8

2-3-4-5-6-7-8-9

0-1-2-3-4-....-13-14-15

1-2-3-4-5-....-14-15-16

2-3-4-5-6-....-15-16-17

No-wrap

.

Autoselect Mode

By writing the autoselect command sequences to the system, the device enters the autoselect mode. This mode can be read only by

asynchronous read mode. The system can then read autoselect codes from the internal register(which is separate from the memory

array). Standard asynchronous read cycle timings apply in this mode. The device offers the Autoselect mode to identify manufacturer

and device type by reading a binary code. In addition, this mode allows the host system to verify the block protection or unprotection.

Table 5 shows the address and data requirements. The autoselect command sequence may be written to an address within a bank

that is in the read mode, erase-suspend-read mode or program-suspend-read mode. The autoselect command may not be written

while the device is actively programming or erasing in the device. The autoselect command sequence is initiated by first writing two

unlock cycles. This is followed by a third write cycle that contains the address and the autoselect command. Note that the block

address is needed for the verification of block protection. The system may read at any address within the same bank any number of

times without initiating another autoselect command sequence. And the burst read should be prohibited during Autoselect Mode. To

terminate the autoselect operation, write Reset command(F0H) into the command register.

Table 9. Autoselct Mode Description

Description

Manufacturer ID

Address

(DA) + 00H

(DA) + 01H

(BA) + 02H

(DA) + 03H

Read Data

ECH

Device ID

22F4H(Top Boot Block), 22F5H(Bottom Boot Block)

01H (protected), 00H (unprotected)

Block Protection/Unprotection

Die revision ID & Handshaking

0H : handshaking, 1H : non-handshaking

Standby Mode

When the CE and RESET inputs are both held at VCC ± 0.2V or the system is not reading or writing, the device enters Stand-by mode

to minimize the power consumption. In this mode, the device outputs are placed in the high impedence state, independent of the OE

input. When the device is in either of these standby modes, the device requires standard access time (tCE ) for read access before it

is ready to read data. If the device is deselected during erasure or programming, the device draws active current until the operation is

completed. ICC5 in the DC Characteristics table represents the standby current specification.

Automatic Sleep Mode

The device features Automatic Sleep Mode to minimize the device power consumption during both asynchronous and burst mode.

When addresses remain stable for tAA+60ns, the device automatically enables this mode. The automatic sleep mode is independent

of the CE, WE, and OE control signals. In a sleep mode, output data is latched and always available to the system. When addresses

are changed, the device provides new data without wait time. Automatic sleep mode current is equal to standby mode current.

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Output Disable Mode

When the OE input is at VIH , output from the device is disabled. The outputs are placed in the high impedance state.

Block Protection & Unprotection

To protect the block from accidental writes, the block protection/unprotection command sequence is used. On power up, all blocks in

the device are protected. To unprotect a block, the system must write the block protection/unprotection command sequence. The first

two cycles are written: addresses are don’t care and data is 60h. Using the third cycle, the block address (ABP) and command (60h)

is written, while specifying with addresses A6, A1 and A0 whether that block should be protected (A6 = VIL, A1 = VIH, A0 = VIL) or

unprotected (A6 = VIH, A1 = VIH, A0 = VIL). After the third cycle, the system can continue to protect or unprotect additional cycles, or

exit the sequence by writing F0h (reset command).

The device offers three types of data protection at the block level:

· The block protection/unprotection command sequence disables or re-enables both program and erase operations in any block.

· When WP is at VIL, the two outermost blocks are protected.

· When VPP is at VIL, all blocks are protected.

Note that user never float the Vpp and WP, that is, Vpp is always connected with VIH, VIL or VID and WP is VIH or VIL.

Hardware Reset

The device features a hardware method of resetting the device by the RESET input. When the RESET pin is held low(VIL) for at least

a period of tRP, the device immediately terminates any operation in progress, tristates all outputs, and ignores all read/write com-

mands for the duration of the RESET pulse. The device also resets the internal state machine to asynchronous read mode. To

ensure data integrity, the interrupted operation should be reinitiated once the device is ready to accept another command sequence.

As previously noted, when RESET is held at VSS ± 0.2V, the device enters standby mode. The RESET pin may be tied to the system

reset pin. If a system reset occurs during the Internal Program or Erase Routine, the device will be automatically reset to the asyn-

chronous read mode; this will enable the systems microprocessor to read the boot-up firmware from the Flash memory. If RESET is

asserted during a program or erase operation, the device requires a time of tREADY (during Internal Routines) before the device is

ready to read data again. If RESET is asserted when a program or erase operation is not executing, the reset operation is completed

within a time of tREADY (not during Internal Routines). tRH is needed to read data after RESET returns to VIH. Refer to the AC Char-

acteristics tables for RESET parameters and to Figure 6 for the timing diagram.

Software Reset

The reset command provides that the bank is reseted to read mode, erase-suspend-read mode or program-suspend-read mode. The

addresses are in Don’t Care state. The reset command may be written between the sequence cycles in an erase command

sequence before erasing begins, or in an program command sequence before programming begins. If the device begins erasure or

programming, the reset command is ignored until the operation is completed. If the program command sequence is written to a bank

that is in the Erase Suspend mode, writing the reset command returns that bank to the erase-suspend-read mode. The reset com-

mand valid between the sequence cycles in an autoselect command sequence. In an autoselect mode, the reset command must be

written to return to the read mode. If a bank entered the autoselect mode while in the Erase Suspend mode, writing the reset com-

mand returns that bank to the erase-suspend-read mode. Also, if a bank entered the autoselect mode while in the Program Suspend

mode, writing the reset command returns that bank to the program-suspend-read mode. If DQ5 goes high during a program or erase

operation, writing the reset command returns the banks to the read mode. (or erase-suspend-read mode if the bank was in Erase

Suspend)

Program

The device can be programmed in units of a word. Programming is writing 0's into the memory array by executing the Internal Pro-

gram Routine. In order to perform the Internal Program Routine, a four-cycle command sequence is necessary. The first two cycles

are unlock cycles. The third cycle is assigned for the program setup command. In the last cycle, the address of the memory location

and the data to be programmed at that location are written. The device automatically generates adequate program pulses and veri-

fies the programmed cell margin by the Internal Program Routine. During the execution of the Routine, the system is not required to

provide further controls or timings. During the Internal Program Routine, commands written to the device will be ignored.

Note that a hardware reset during a program operation will cause data corruption at the corresponding location.

Accelerated Program Operation

The device provides accelerated program operations through the Vpp input. Using this mode, faster manufacturing throughput at the

factory is possible. When VID is asserted on the Vpp input, the device automatically enters the Unlock Bypass mode, temporarily

unprotects any protected blocks, and uses the higher voltage on the input to reduce the time required for program operations. In

accelerated program mode, the system would use a two-cycle program command sequence. By removing VID returns the device to

normal operation mode.

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Unlock Bypass

The device provides the unlock bypass mode to save its operation time. This mode is possible for program, block erase and chip

erase operation. There are two methods to enter the unlock bypass mode. The mode is invoked by the unlock bypass command

sequence or the assertion of VID on VPP pin. Unlike the standard program/erase command sequence that contains four bus cycles,

the unlock bypass program/erase command sequence comprises only two bus cycles. The unlock bypass mode is engaged by issu-

ing the unlock bypass command sequence which is comprised of three bus cycles. Writing first two unlock cycles is followed by a

third cycle containing the unlock bypass command (20H). Once the device is in the unlock bypass mode, the unlock bypass pro-

gram/erase command sequence is necessary. The unlock bypass program command sequence is comprised of only two bus cycles;

writing the unlock bypass program command (A0H) is followed by the program address and data. This command sequence is the

only valid one for programming the device in the unlock bypass mode. Also, The unlock bypass erase command sequence is com-

prised of two bus cycles; writing the unlock bypass block erase command(80H-30H) or writing the unlock bypass chip erase com-

mand(80H-10H). This command sequences are the only valid ones for erasing the device in the unlock bypass mode. The unlock

bypass reset command sequence is the only valid command sequence to exit the unlock bypass mode. The unlock bypass reset

command sequence consists of two bus cycles. The first cycle must contain the data (90H). The second cycle contains only the data

(00H). Then, the device returns to the read mode.

To enter the unlock bypass mode in hardware level, the VID also can be used. By assertion VID on the VPP pin, the device enters the

unlock bypass mode. Also, the all blocks are temporarily unprotected when the device using the VID for unlock bypass mode. To exit

the unlock bypass mode, just remove the asserted VID from the VPP pin.(Note that user never float the Vpp, that is, Vpp is always

connected with VIH, VIL or VID.).

Chip Erase

To erase a chip is to write 1¢s into the entire memory array by executing the Internal Erase Routine. The Chip Erase requires six bus

cycles to write the command sequence. The erase set-up command is written after first two "unlock" cycles. Then, there are two

more write cycles prior to writing the chip erase command. The Internal Erase Routine automatically pre-programs and verifies the

entire memory for an all zero data pattern prior to erasing. The automatic erase begins on the rising edge of the last WE pulse in the

command sequence and terminates when DQ7 is "1". After that the device returns to the read mode.

Block Erase

To erase a block is to write 1¢s into the desired memory block by executing the Internal Erase Routine. The Block Erase requires six

bus cycles to write the command sequence shown in Table 5. After the first two "unlock" cycles, the erase setup command (80H) is

written at the third cycle. Then there are two more "unlock" cycles followed by the Block Erase command. The Internal Erase Routine

automatically pre-programs and verifies the entire memory prior to erasing it. Multiple blocks can be erased sequentially by writing

the sixth bus-cycle. Upon completion of the last cycle for the Block Erase, additional block address and the Block Erase command

(30H) can be written to perform the Multi-Block Erase. For the Multi-Block Erase, only sixth cycle(block address and 30H) is

needed.(Similarly, only second cycle is needed in unlock bypass block erase.) An 50us (typical) "time window" is required between

the Block Erase command writes. The Block Erase command must be written within the 50us "time window", otherwise the Block

Erase command will be ignored. The 50us "time window" is reset when the falling edge of the WE occurs within the 50us of "time

window" to latch the Block Erase command. During the 50us of "time window", any command other than the Block Erase or the

Erase Suspend command written to the device will reset the device to read mode. After the 50 us of "time window", the Block Erase

command will initiate the Internal Erase Routine to erase the selected blocks. Any Block Erase address and command following the

exceeded "time window" may or may not be accepted. No other commands will be recognized except the Erase Suspend command

during Block Erase operation.

Erase Suspend / Resume

The Erase Suspend command interrupts the Block Erase to read or program data in a block that is not being erased. Also, it is pos-

sible to protect or unprotect of the block that is not being erased in erase suspend mode. The Erase Suspend command is only valid

during the Block Erase operation including the time window of 50 us. The Erase Suspend command is not valid while the Chip Erase

or the Internal Program Routine sequence is running. When the Erase Suspend command is written during a Block Erase operation,

the device requires a maximum of 20 us(recovery time) to suspend the erase operation. Therefore

system must wait for

20us(recovery time) to read the data from the bank which include the block being erased. Otherwise, system can read the data

immediately from a bank which don’t include the block being erased without recovery time(max. 20us) after Erase Suspend com-

mand. And, after the maximum 20us recovery time, the device is availble for programming data in a block that is not being erased.

But, when the Erase Suspend command is written during the block erase time window (50 us) , the device immediately terminates

the block erase time window and suspends the erase operation. The system may also write the autoselect command sequence

when the device is in the Erase Suspend mode. When the Erase Resume command is executed, the Block Erase operation will

resume. When the Erase Suspend or Erase Resume command is executed, the addresses are in Don't Care state.

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Program Suspend / Resume

The device provides the Program Suspend/Resume mode. This mode is used to enable Data Read by suspending the Program

operation. The device accepts a Program Suspend command in Program mode(including Program operations performed during

Erase Suspend) but other commands are ignored. After input of the Program Suspend command, 2us is needed to enter the Pro-

gram Suspend Read mode. Therefore system must wait for 2us(recovery time) to read the data from the block being programmed.

Otherwise, system can read the data immediately from a any block(except for the block being programmed) without recovery time

after Program Suspend command. Like an Erase Suspend mode, the device can be returned to Program mode by using a Program

Resume command.

Read While Write Operation

The device is capable of reading data from one bank while writing in the other banks. This is so called the Read While Write opera-

tion. An erase operation may also be suspended to read from or program to another location within the same bank(except the block

being erased). The Read While Write operation is prohibited during the chip erase operation. Figure 12 shows how read and write

cycles may be initiated for simultaneous operation with zero latency. Refer to the DC Characteristics table for read-while-write cur-

rent specifications.

Low VCC Write Inhibit

To avoid initiation of a write cycle during Vcc power-up and power-down, a write cycle is locked out for Vcc less than VLKO. If the Vcc

< VLKO (Lock-Out Voltage), the command register and all internal program/erase circuits are disabled. Under this condition the

device will reset itself to the read mode.Subsequent writes will be ignored until the Vcc level is greater than VLKO. It is the user’s

responsibility to ensure that the control pins are logically correct to prevent unintentional writes when Vcc is above VLKO.

Write Pulse “Glitch” Protection

Noise pulses of less than 5ns (typical) on OE, CE, AVD or WE do not initiate a write cycle.

Logical Inhibit

Write cycles are inhibited by holding any one of OE = VIL , CE = VIH or WE = VIH. To initiate a write cycle, CE and WE must be a log-

ical zero while OE is a logical one.

Power-up Protection

To avoid initiation of a write cycle during VCC power-up, RESET low must be asserted during Power-up. After RESET goes high. the

device is reset to the read mode.

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FLASH MEMORY STATUS FLAGS

The device has means to indicate its status of operation in the bank where a program or erase operation is in processes. Address

must include bank address being executed internal routine operation. The status is indicated by raising the device status flag via cor-

responding DQ pins. This status read is supported in burst mode and asynchronous mode. The status data can be read during burst

read mode by using AVD signal with a bank address. That means status read is supported in synchronous mode. If status read is

performed, the data provided in the burst read is identical to the data in the initial access. To initiate the synchronous read again, a

new address and AVD pulse is needed after the host has completed status reads or the device has completed the program or erase

operation. The corresponding DQ pins are DQ7, DQ6, DQ5, DQ3 and DQ2.

Table 10. Hardware Sequence Flags

Status

DQ7

0

DQ6

Toggle

DQ5

DQ3

DQ2

1

Programming

0

1

Block Erase or Chip Erase

Erase Suspend Read

Toggle

Erase Suspended

Block

Toggle

(Note 1)

1

Data

Toggle

1

0

Data

0

Data

0

Non-EraseSuspended

Block

Erase Suspend Read

Data

DQ7

Data

1

In Progress

Erase Suspend

Program

Non-EraseSuspended

Block

Program Suspended

Block

Toggle

(Note 1)

Program Suspend Read

0

Non- program

Suspended Block

Data

No

Toggle

Programming

DQ7

0

Toggle

1

0

1

0

Exceeded

Time Limits

Block Erase or Chip Erase

Erase Suspend Program

(Note 2)

No

Toggle

DQ7

Notes :

1. DQ2 will toggle when the device performs successive read operations from the erase/program suspended block.

2. If DQ5 is High (exceeded timing limits), successive reads from a problem block will cause DQ2 to toggle.

DQ7 : Data Polling

When an attempt to read the device is made while executing the Internal Program, the complement of the data is written to DQ7 as

an indication of the Routine in progress. When the Routine is completed an attempt to access to the device will produce the true data

written to DQ7. When a user attempts to read the block being erased, DQ7 will be low. If the device is placed in the Erase/Program

Suspend Mode, the status can be detected via the DQ7 pin. If the system tries to read an address which belongs to a block that is

being erase suspended, DQ7 will be high. And, if the system tries to read an address which belongs to a block that is being program

suspended, the output will be the true data of DQ7 itself. If a non-erase-suspended or non-program-suspended block address is

read, the device will produce the true data to DQ7. If an attempt is made to program a protected block, DQ7 outputs complements

the data for approximately 1ms and the device then returns to the Read Mode without changing data in the block. If an attempt is

made to erase a protected block, DQ7 outputs complement data in approximately 100us and the device then returns to the Read

Mode without erasing the data in the block.

DQ6 : Toggle Bit

Toggle bit is another option to detect whether an Internal Routine is in progress or completed. Once the device is at a busy state,

DQ6 will toggle. Toggling DQ6 will stop after the device completes its Internal Routine. If the device is in the Erase/Program Sus-

pend Mode, an attempt to read an address that belongs to a block that is being erased or programmed will produce a high output of

DQ6. If an address belongs to a block that is not being erased or programmed, toggling is halted and valid data is produced at DQ6.

If an attempt is made to program a protected block, DQ6 toggles for approximately 1us and the device then returns to the Read

Mode without changing the data in the block. If an attempt is made to erase a protected block, DQ6 toggles for approximately 100ms

and the device then returns to the Read Mode without erasing the data in the block.

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DQ5 : Exceed Timing Limits

If the Internal Program/Erase Routine extends beyond the timing limits, DQ5 will go High, indicating program/erase failure.

DQ3 : Block Erase Timer

The status of the multi-block erase operation can be detected via the DQ3 pin. DQ3 will go High if 50ms of the block erase time win-

dow expires. In this case, the Internal Erase Routine will initiate the erase operation.Therefore, the device will not accept further write

commands until the erase operation is completed. DQ3 is Low if the block erase time window is not expired. Within the block erase

time window, an additional block erase command (30H) can be accepted. To confirm that the block erase command has been

accepted, the software may check the status of DQ3 following each block erase command.

DQ2 : Toggle Bit 2

The device generates a toggling pulse in DQ2 only if an Internal Erase Routine or an Erase/Program Suspend is in progress. When

the device executes the Internal Erase Routine, DQ2 toggles only if an erasing block is read. Although the Internal Erase Routine is

in the Exceeded Time Limits, DQ2 toggles only if an erasing block in the Exceeded Time Limits is read. When the device is in the

Erase/Program Suspend mode, DQ2 toggles only if an address in the erasing or programming block is read. If a non-erasing or non-

programmed block address is read during the Erase/Program Suspend mode, then DQ2 will produce valid data. DQ2 will go High if

the user tries to program a non-erase suspend block while the device is in the Erase Suspend mode.

RDY: Ready

Normally the RDY signal is used to indicate if new burst data is available at the rising edge of the clock cycle or not. If RDY is low

state, data is not valid at expected time, and if high state, data is valid. Note that, if CE is low and OE is high, the RDY is high state.

Start

Yes

No

DQ7 = Data ?

No

DQ6 = Toggle ?

Yes

No

DQ5 = 1 ?

Yes

No

Yes

DQ6 = Toggle ?

DQ7 = Data ?

Yes

Fail

No

Pass

Fail

Figure 2. Toggle Bit Algorithms

Figure 1. Data Polling Algorithms

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Commom Flash Memory Interface

Common Flash Momory Interface is contrived to increase the compatibility of host system software. It provides the specific informa-

tion of the device, such as memory size and electrical features. Once this information has been obtained, the system software will

know which command sets to use to enable flash writes, block erases, and control the flash component.

When the system writes the CFI command(98H) to address 55H , the device enters the CFI mode. And then if the system writes the

address shown in Table 11, the system can read the CFI data. Query data are always presented on the lowest-order data out-

puts(DQ0-7) only. In word(x16) mode, the upper data outputs(DQ8-15) is 00h. To terminate this operation, the system must write

the reset command.

Table 11. Common Flash Memory Interface Code

Addresses

Description

Data

(Word Mode)

10H

11H

12H

0051H

0052H

0059H

Query Unique ASCII string "QRY"

13H

14H

0002H

0000H

Primary OEM Command Set

15H

16H

0040H

0000H

Address for Primary Extended Table

17H

18H

0000H

Alternate OEM Command Set (00h = none exists)

19H

1AH

0000H

Address for Alternate OEM Extended Table (00h = none exists)

Vcc Min. (write/erase)

D7-D4: volt, D3-D0: 100 millivolt

1BH

1CH

0017H

0019H

Vcc Max. (write/erase)

D7-D4: volt, D3-D0: 100 millivolt

Vpp(Acceleration Program) Supply Minimum

00 = Not Supported, D7 - D4 : Volt, D3 - D0 : 100mV

1DH

1EH

0085H

0095H

Vpp(Acceleration Program) Supply Maximum

00 = Not Supported, D7 - D4 : Volt, D3 - D0 : 100mV

Typical timeout per single word write 2^Nus

1FH

20H

21H

22H

23H

24H

25H

26H

27H

0004H

0000H

000AH

0012H

0005H

0000H

0004H

0000H

0018H

Typical timeout for Min. size buffer write 2^Nus(00H = not supported)

Typical timeout per individual block erase 2^Nms

Typical timeout for full chip erase 2^Nms(00H = not supported)

Max. timeout for word write 2^Ntimes typical

Max. timeout for buffer write 2^Ntimes typical

Max. timeout per individual block erase 2^Ntimes typical

Max. timeout for full chip erase 2^Ntimes typical(00H = not supported)

Device Size = 2^Nbyte

28H

29H

0000H

Flash Device Interface description

2AH

2BH

0000H

Max. number of byte in multi-byte write = 2^N

Number of Erase Block Regions within device

2CH

0002H

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Table 11. Common Flash Memory Interface Code (Continued)

Description

Addresses

(Word Mode)

Data

2DH

2EH

2FH

30H

0007H

0000H

0020H

0000H

Erase Block Region 1 Information

Bits 0~15: y+1=block number

Bits 16~31: block size= z x 256bytes

31H

32H

33H

34H

00FEH

0000H

0001H

Erase Block Region 2 Information

Erase Block Region 3 Information

35H

36H

37H

38H

0000H

39H

3AH

3BH

3CH

0000H

Erase Block Region 4 Information

Query-unique ASCII string "PRI"

40H

41H

42H

0050H

0052H

0049H

Major version number, ASCII

Minor version number, ASCII

43H

44H

0031H

0030H

Address Sensitive Unlock(Bits 1-0)

0 = Required, 1= Not Required

Silcon Revision Number(Bits 7-2)

45H

0000H

Erase Suspend

0 = Not Supported, 1 = To Read Only, 2 = To Read & Write

46H

47H

0002H

0001H

Block Protect

00 = Not Supported, 01 = Supported

Block Temporary Unprotect 00 = Not Supported, 01 = Supported

Block Protect/Unprotect scheme 00 = Not Supported, 01 = Supported

48H

49H

0000H

0001H

Simultaneous Operation

00 = Not Supported, 01 = Supported

4AH

4BH

4CH

0001H

0000H

Burst Mode Type 00 = Not Supported, 01 = Supported

Page Mode Type

00 = Not Supported, 01 = 4 Word Page 02 = 8 Word Page

Top/Bottom Boot Block Flag

02H = Bottom Boot Device, 03H = Top Boot Device

4DH

0003H

Max. Operating Clock Frequency (MHz )

4EH

4FH

0042H

0000H

RWW(Read While Write) Functionality Restriction (00H = non exists , 01H = exists)

Handshaking

00 = Not Supported at both mode, 01 = Supported at Sync. Mode

10 = Supported at Async. Mode, 11 = Supported at both Mode

50H

0001H

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ABSOLUTE MAXIMUM RATINGS

Parameter

Symbol

Rating

-0.5 to +2.5

-0.5 to +9.5

-0.5 to +2.5

-10 to +125

-25 to +125

-65 to +150

5

Unit

Vcc

Voltage on any pin relative to VSS

V

VPP

VIN

All Other Pins

Commercial

Extended

Temperature Under Bias

Tbias

°C

Storage Temperature

Tstg

°C

mA

°C

Short Circuit Output Current

IOS

TA (Commercial Temp.)

TA (Extended Temp.)

0 to +70

Operating Temperature

-25 to + 85

°C

Notes :

1. Minimum DC voltage is -0.5V on Input/ Output pins. During transitions, this level may fall to -2.0V for periods <20ns.

Maximum DC voltage is Vcc+0.6V on input / output pins which, during transitions, may overshoot to Vcc+2.0V for periods <20ns.

2. Minimum DC input voltage is -0.5V on VPP . During transitions, this level may fall to -2.0V for periods <20ns.

Maximum DC input voltage is +9.5V on VPP which, during transitions, may overshoot to +12.0V for periods <20ns.

3. Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to the conditions

detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect reliability.

RECOMMENDED OPERATING CONDITIONS ( Voltage reference to GND )

Parameter

Symbol

Min

1.7

0

Typ.

1.8

0

Max

1.9

0

Unit

V

Supply Voltage

VCC

Supply Voltage

VSS

V

DC CHARACTERISTICS

Parameter

Symbol

ILI

Test Conditions

Min

Typ

Max

+ 1.0

35

Unit

Input Leakage Current

VPP Leakage Current

Output Leakage Current

Active Burst Read Current

VIN=VSS to VCC, VCC=VCCmax

VCC=VCCmax , VPP=9.5V

- 1.0

-

mA

ILIP

-

ILO

VOUT=VSS to VCC, VCC=VCCmax, OE=VIH

CE=VIL, OE=VIH

- 1.0

-

+ 1.0

30

mA

ICCB1

-

25

3

mA

10MHz

30

Active Asynchronous

Read Current

ICC1

CE=VIL, OE=VIH

1MHz

4

Active Write Current (Note 2)

Read While Write Current

Accelerated Program Current

Standby Current

ICC2

ICC3

ICC4

ICC5

ICC6

CE=VIL, OE=VIH, WE=VIL, VPP=VIH

CE=VIL, OE=VIH

15

35

15

5

30

55

CE=VIL, OE=VIH , VPP=9.5V

CE= RESET=VCC ± 0.2V

RESET = VSS ± 0.2V

30

Standby Current During Reset

5

30

mA

CE=VSS ± 0.2V, Other Pins=VIL or VIH

VIL = VSS ± 0.2V, VIH = VCC ± 0.2V

Automatic Sleep Mode(Note 3)

ICC7

-

5

30

mA

Input Low Voltage

VIL

VIH

-0.5

VCC-0.4

-

0.4

VCC+0.4

0.1

V

Input High Voltage

-

Output Low Voltage

VOL

VOH

VID

IOL = 100 mA , VCC=VCCmin

IOH = -100 mA , VCC=VCCmin

-

Output High Voltage

VCC-0.1

8.5

-

Voltage for Accelerated Program

Low VCC Lock-out Voltage

9.0

-

9.5

VLKO

1.0

1.3

Notes:

1. Maximum ICC specifications are tested with VCC = VCCmax.

2. ICC active while Internal Erase or Internal Program is in progress.

3. Device enters automatic sleep mode when addresses are stable for tAA + 60ns.

33

Revision 0.0

November 2003

Preliminary

KBF0x0800M

MCP MEMORY

CAPACITANCE(TA = 25 °C, VCC = 1.8V, f = 1.0MHz)

Item

Symbol

Test Condition

Min

Max

Unit

pF

Input Capacitance

CIN

VIN=0V

-

10

Output Capacitance

Control Pin Capacitance

COUT

CIN2

VOUT=0V

VIN=0V

pF

Note : Capacitance is periodically sampled and not 100% tested.

AC TEST CONDITION

Parameter

Value

0V to VCC

5ns

Input Pulse Levels

Input Rise and Fall Times

Input and Output Timing Levels

Output Load

VCC/2

CL = 30pF

Device

Under

Test

VCC

Input & Output

VCC/2

Test Point

* CL = 30pF including scope

and Jig capacitance

0V

Input Pulse and Test Point

Output Load

AC CHARACTERISTICS

Synchronous/Burst Read

7B

(54 MHz)

7C

(66 MHz)

Parameter

Symbol

Unit

Min

Max

Min

Max

Initial Access Time

tIAA

tBA

-

88.5

-

71

ns

Burst Access Time Valid Clock to Output

Delay

-

14.5

-

11

AVD Setup Time to CLK

AVD Hold Time from CLK

AVD High to OE Low

tAVDS

tAVDH

tAVDO

tACS

5

7

0

5

7

4

-

5

6

0

5

6

4

-

ns

-

Address Setup Time to CLK

Address Hold Time from CLK

Data Hold Time from Next Clock Cycle

Output Enable to Data

-

tACH

tBDH

tOE

-

20

14.5

20

15

-

20

11

20

15

-

Output Enable to RDY valid

CE Disable to High Z

tOER

tCEZ

-

OE Disable to High Z

tOEZ

-

CE Setup Time to CLK

CLK to RDY Setup Time

RDY Setup Time to CLK

CLK High or Low Time

tCES

9

-

9

-

tRDYA

tRDYS

tCH/L

tCHCL

14.5

-

11

-

4

4.5

-

4

3.5

-

CLK Fall or Rise Time

3

34

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November 2003

Preliminary

KBF0x0800M

MCP MEMORY

SWITCHING WAVEFORMS

5 cycles for initial access shown.

CR setting : A14=0, A13=0, A12=1

15.2 ns typ.

tCES

tCEZ

CE

CLK

tAVDS

tAVDH

AVD

A0-A22

tBDH

tACS

tBA

tACH

Hi-Z

DQ0-DQ15

Da

Da+1 Da+2

tIAA

Da+3

Da+n

tOEZ

OE

tOER

tRDYS

Hi-Z

tRDYA

Hi-Z

RDY

Figure 3. Burst Mode Read (66 MHz)

Note: In order to avoid a bus conflict the OE signal is enabled on the next rising edge after AVD is going high.

5 cycles for initial access shown.

CR setting : A14=0, A13=0, A12=1

18.5 ns typ.

tCES

tCEZ

CE

CLK

tAVDS

AVD

A0-A22

tAVDH

tBDH

tACS

tBA

tACH

Hi-Z

DQ0-DQ15

Da

Da+1 Da+2

tIAA

Da+3

Da+n

tOEZ

OE

tOER

tRDYS

Hi-Z

tRDYA

Hi-Z

RDY

Figure 4. Burst Mode Read (54 MHz)

Note: In order to avoid a bus conflict the OE signal is enabled on the next rising edge after AVD is going high.

35

Revision 0.0

November 2003

Preliminary

KBF0x0800M

MCP MEMORY

SWITCHING WAVEFORMS

5 cycles for initial access shown.

CR setting : A14=0, A13=0, A12=1

15.2 ns typ.

tCES

CE

CLK

tAVDS

tAVDH

AVD

A0-A22

tBDH

tACS

tBA

tACH

DQ0-DQ15

tIAA

D6

D7

D0

D2

D7

D1

D3

D0

OE

tOER

tRDYS

Hi-Z

tRDYA

RDY

Figure 5. 8 word Linear Burst Mode with Wrap Around (66 MHz)

Note: In order to avoid a bus conflict the OE signal is enabled on the next rising edge after AVD is going high.

5 cycles for initial access shown.

CR setting : A14=0, A13=0, A12=1

15.2 ns typ.(66MHz)

tCES

CE

CLK

tAVDS

AVD

A0-A22

tAVDH

tBDH

tACS

tBA

tACH

DQ0-DQ15

tIAA

D6

D7

D0

D2

D7

D1

D3

D0

OE

tOER

tRDYS

Hi-Z

tRDYA

RDY

Figure 6. 8 word Linear Burst with RDY Set One Cycle Before Data (CR setting : A18=1)

Note: In order to avoid a bus conflict the OE signal is enabled on the next rising edge after AVD is going high.

36

Revision 0.0

November 2003

Preliminary

KBF0x0800M

MCP MEMORY

SWITCHING WAVEFORMS

5 cycles for initial access shown.

CR setting : A14=0, A13=0, A12=1

15.2 ns typ(66MHz).

tCES

tCEZ

CE

CLK

tAVDS

tAVDH

AVD

A0-A22

tBDH

tACS

tBA

tACH

Hi-Z

DQ0-DQ15

D6

D7

D8

tIAA

D9

D13

tOEZ

OE

tOER

tRDYS

Hi-Z

tRDYA

Hi-Z

RDY

Figure 7. 8 word Linear Burst Mode (No Wrap Case)

Note: In order to avoid a bus conflict the OE signal is enabled on the next rising edge after AVD is going high.

37

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November 2003

Preliminary

KBF0x0800M

MCP MEMORY

AC CHARACTERISTICS

Asynchronous Read

7B

7C

Parameter

Symbol

Unit

Min

Max

88.5

-

Min

Max

70

-

Access Time from CE Low

Asynchronous Access Time

AVD Low Time

tCE

tAA

-

ns

tAVDP

tOE

12

-

12

-

Output Enable to Output Valid

20

-

Read

0

-

0

Output Enable Hold

Time

tOEH

tOEZ

Toggle and

Data Polling

10

-

10

-

ns

Output Disable to High Z(Note 1)

15

Note: 1. Not 100% tested.

SWITCHING WAVEFORMS

Asynchronous Mode Read

VIL

CLK

CE

OE

tOE

tOEH

WE

tCE

tOEZ

DQ0-DQ15

Valid RD

tAA

A0-A22

VA

Figure 8. Asynchronous Mode Read

Note: VA=Valid Read Address, RD=Read Data.

38

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November 2003

Preliminary

KBF0x0800M

MCP MEMORY

AC CHARACTERISTICS

Hardware Reset(RESET)

Parameter

All Speed Options

Symbol

Unit

Max

Min

RESET Pin Low(During Internal Routines)

to Read Mode (Note)

tReady

-

20

ms

RESET Pin Low(NOT During Internal Routines)

to Read Mode (Note)

-

500

ns

RESET Pulse Width

tRP

tRH

200

20

-

ns

ms

Reset High Time Before Read (Note)

RESET Low to Standby Mode

tRPD

Note: Not 100% tested.

SWITCHING WAVEFORMS

CE, OE

RESET

tRH

tRP

tReady

Reset Timings NOT during Internal Routines

CE, OE

RESET

tReady

tRP

Reset Timings during Internal Routines

Figure 9. Reset Timings

39

Revision 0.0

November 2003

Preliminary

KBF0x0800M

MCP MEMORY

AC CHARACTERISTICS

Erase/Program Operation

7B, 7C

Parameter

Symbol

Unit

Min

100

0

Typ

Max

WE Cycle Time(Note 1)

Address Setup Time(Note 2)

Address Hold Time(Note 2)

Data Setup Time

tWC

tAS

-

ns

ms

-

tAH

50

0

-

tDS

-

Data Hold Time

tDH

-

Read Recovery Time Before Write

tGHWL

tCS

-

0

5

-

CE Setup Time

CE Hold Time

tCH

5

-

WE Pulse Width

tWP

80

30

0

-

WE Pulse Width High

tWPH

tSR/W

tPGM

tACCPGM

tBERS

tVPP

tVPS

tVCS

-

Latency Between Read and Write Operations

Word Programming Operation

Accelerated Programming Operation

Block Erase Operation (Note 3)

VPP Rise and Fall Time

-

11.5

-

7

ms

-

0.7

sec

ns

ms

500

1

-

VPP Setup Time (During Accelerated Programming)

VCC Setup Time

ms

50

Notes:

1. Not 100% tested.

2. In write timing, addresses are latched on the falling edge of WE.

3. Not include the preprogramming time.

FLASH Erase/Program Performance

Limits

Typ.

Parameter

Unit

sec

ms

Comments

Min.

Max.

14

32 Kword

4 Kword

-

0.7

0.6

184

138

11.5

7

Block Erase Time

Chip Erase Time

12

Excludes 00h programming prior to

erasure

-

Accelerated Chip Erase Time

Word Programming Time

-

210

120

276

168

Accelerated Word Programming Time

Chip Programming Time

Excludes system level overhead

92

sec

Accelerated Chip Programming Time

56

Minimum 100,000 cycles guaran-

teed in all Bank

Erase/Program Endurance (Note 3)

100,000

-

Cycles

Notes:

1. 25°C, VCC = 1.8V, 100,000 cycles, typical pattern.

2. System-level overhead is defined as the time required to execute the two or four bus cycle command necessary to program each

word. In the preprogramming step of the Internal Erase Routine, all words are programmed to 00H before erasure.

3. 100K Program/Erase Cycle in all Bank

40

Revision 0.0

November 2003

Preliminary

KBF0x0800M

MCP MEMORY

SWITCHING WAVEFORMS

Program Operations

Program Command Sequence (last two cycles)

Read Status Data

tAS

tAH

A0:A22

555h

PA

VA

In

DQ0-DQ15

Complete

Progress

A0h

PD

tDS

tDH

CE

OE

WE

tCH

tWP

tWPH

tPGM

tCS

tWC

VIL

tVCS

CLK

VCC

Notes:

1. PA = Program Address, PD = Program Data, VA = Valid Address for reading status bits.

2. “In progress” and “complete” refer to status of program operation.

3. A16–A22 are don’t care during command sequence unlock cycles.

4. Status reads in this figure is asynchronous read, but status read in synchronous mode is also supported.

Figure 10. Program Operation Timing

41

Revision 0.0

November 2003

Preliminary

KBF0x0800M

MCP MEMORY

SWITCHING WAVEFORMS

Erase Operation

Erase Command Sequence (last two cycles)

Read Status Data

555h for

chip erase

tAS

tAH

A0:A22

DQ0-DQ15

CE

2AAh

BA

VA

10h for

chip erase

In

Complete

Progress

55h

30h

tDS

tDH

tCH

OE

tWP

WE

tWPH

tBERS

tCS

tWC

VIL

CLK

VCC

tVCS

Notes:

1. BA is the block address for Block Erase.

2. Address bits A16–A22 are don’t cares during unlock cycles in the command sequence.

3. Status reads in this figure is asynchronous read, but status read in synchronous mode is also supported.

Figure 11. Chlp/Block Erase Operations

42

Revision 0.0

November 2003

Preliminary

KBF0x0800M

MCP MEMORY

SWITCHING WAVEFORMS

Unlock Bypass Program Operations(Accelerated Program)

CE

WE

PA

A0:A22

DQ0-DQ15

Don’t Care

A0h

Don’t Care

PD

Don’t Care

OE

1us

tVPS

VID

tVPP

VPP

VIL or VIH

Unlock Bypass Block Erase Operations

CE

WE

BA

A0:A22

555h for

chip erase

10h for

chip erase

DQ0-DQ15

OE

Don’t Care

80h

Don’t Care

30h

Don’t Care

1us

tVPS

VID

tVPP

VPP

VIL or VIH

Notes:

1. VPP can be left high for subsequent programming pulses.

2. Use setup and hold times from conventional program operations.

3. Unlock Bypass Program/Erase commands can be used when the VID is applied to Vpp.

Figure 12. Unlock Bypass Operation Timings

43

Revision 0.0

November 2003

Preliminary

KBF0x0800M

MCP MEMORY

SWITCHING WAVEFORMS

Data Polling Operations

tCES

CE

CLK

tAVDS

AVD

tAVDH

tACS

A0-A22

VA

tACH

DQ0-DQ15

Status Data

tIAA

OE

tRDYS

Hi-Z

RDY

Notes:

1. VA = Valid Address. When the Internal Routine operation is complete, and Data Polling will output true data.

Figure 13. Data Polling Timings (During Internal Routine)

Toggle Bit Operations

tCES

CE

CLK

tAVDS

AVD

tAVDH

tACS

A0-A22

VA

tACH

DQ0-DQ15

Status Data

tIAA

OE

tRDYS

Hi-Z

RDY

Notes:

1. VA = Valid Address. When the Internal Routine operation is complete, the toggle bits will stop toggling.

Figure 14. Toggle Bit Timings(During Internal Routine)

44

Revision 0.0

November 2003

Preliminary

KBF0x0800M

MCP MEMORY

SWITCHING WAVEFORMS

Read While Write Operations

Last Cycle in

Program or

Block Erase

Begin another

Program or Erase

Command Sequences

Read status in same bank

and/or array data from other bank

Command Sequence

tWC

tRC

tWC

CE

OE

tOE

tOEH

tGHWL

WE

tWPH

tWP

tDS

tAA

tDH

tOEH

RD

DQ0-DQ15

A0-A22

PD/30h

RD

AAh

tSR/W

PA/BA

RA

555h

Figure 15. Read While Write Operation

Note:

Breakpoints in waveforms indicate that system may alternately read array data from the “non-busy bank” and checking the status of the program or

erase operation in the “busy” bank.

45

Revision 0.0

November 2003

Preliminary

KBF0x0800M

MCP MEMORY

Crossing of First Word Boundary in Burst Read Mode

The additional clock insertion for word boundary is needed only at the first crossing of word boundary. This means that no

addtional clock cycle is needed from 2nd word boundary crossing to the end of continuous burst read. Also, the number of addtional

clock cycle for the first word boundary can varies from zero to three cycles, and the exact number of additional clock cycle depends

on the starting address of burst read.

The rule to determine the additional clock cycle is as follows. All addresses can be divided into 4 groups. The applied rule is "The res-

idue obtained when the address is divided by 4" or "two LSB bits of address". Using this rule, all address can be divided by 4 different

groups as shown in below table. For simplicity of terminology, "4N" stands for the address of which the residue is "0"(or the two LSB

bits are "00") and "4N+1" for the address of which the residue is "1"(or the two LSB bits are "01"), etc.

The additional clock cycles for first word boundary crossing are zero, one, two or three when the burst read start from "4N" address,

"4N+1" address, "4N+2" address or "4N+3" address respectively.

Starting Address vs. Additional Clock Cycles for first word boundary

Srarting Address Group

for Burst Read

Additional Clock Cycles for

First Word Boundary Crossing

The Residue of (Address/4)

LSB Bits of Address

4N

0

1

2

3

00

01

10

11

0 cycle

1 cycle

4N+1

4N+2

4N+3

2 cycles

3 cycles

Case 1 : Start from "4N" address group

5 cycle for initial access shown.(54MHz case)

A0-A22

C

D

E

10

11

12

13

Data Bus

F

CLK

AVD

C

D

11

12

13

14

F

10

E

No Additional Cycle for First Word Boundary

CE

OE

tCEZ

tOEZ

tOER

RDY

Notes:

1. Address boundry occurs every 16 words beginning at address 00000FH , 00001FH , 00002FH , etc.

2. Address 000000H is also a boundry crossing.

3. No additional clock cycles are needed except for 1st boundary crossing.

Figure 16. Crossing of first word boundary in burst read mode.

46

Revision 0.0

November 2003

Preliminary

KBF0x0800M

MCP MEMORY

Case2 : Start from "4N+1" address group

5 cycle for initial access shown.(54MHz case)

A0-A22

Data Bus

D

E

F

10

11

12

13

CLK

AVD

D

E

11

12

13

14

F

10

Additional 1 Cycle for First Word Boundary

CE

OE

tCEZ

tOEZ

tOER

RDY

Case 3 : Start from "4N+2" address group

5 cycle for initial access shown.(54MHz case)

A0-A22

Data Bus

E

F

10

11

12

13

CLK

AVD

E

F

11

12

13

14

10

Additional 2 Cycle for First Word Boundary

CE

OE

tCEZ

tOEZ

tOER

RDY

Notes:

1. Address boundry occurs every 16 words beginning at address 00000FH , 00001FH , 00002FH , etc.

2. Address 000000H is also a boundry crossing.

3. No additional clock cycles are needed except for 1st boundary crossing.

Figure 16. Crossing of first word boundary in burst read mode.

47

Revision 0.0

November 2003

Preliminary

KBF0x0800M

MCP MEMORY

Case4 : Start from "4N+3" address group

5 cycle for initial access shown.(54MHz case)

A0-A22

Data Bus

F

10

1

12

13

CLK

AVD

F

10

11

12

13

14

Additional 3 Cycle for First Word Boundary

CE

OE

tCEZ

tOEZ

tOER

RDY

Notes:

1. Address boundry occurs every 16 words beginning at address 00000FH , 00001FH , 00002FH , etc.

2. Address 000000H is also a boundry crossing.

3. No additional clock cycles are needed except for 1st boundary crossing.

Figure 16. Crossing of first word boundary in burst read mode.

48

Revision 0.0

November 2003

Preliminary

KBF0x0800M

MCP MEMORY

64Mb(4Mbx16) x 2

Synchronous Burst UtRAM B-die

49

Revision 0.0

November 2003

Preliminary

KBF0x0800M

MCP MEMORY

POWER UP SEQUENCE

1. Apply power.

2. Maintain stable power(Vcc min.=2.5V) for a minimum 200ms with CS and MRS high.

TIMING WAVEFORM OF POWER UP

200ms

VCC(Min)

VCC

VCCQ(Min)

VCCQ

Min. 0ns

MRS

Min. 200ms

Min. 0ns

CS

Power Up Mode

Normal Operation

(POWER UP)

1. After VCC reaches VCC(Min.), wait 200ms with CS and MRS high. Then the device gets into the normal operation.

50

Revision 0.0

November 2003

Preliminary

KBF0x0800M

MCP MEMORY

FUNCTIONAL DESCRIPTION for ASYNCHRONOUS MODE(A15=0)

CS

H

L

MRS

H

OE

X¹⁾

H

WE

X¹⁾

H

LB

X¹⁾

H

UB

X¹⁾

H

DQ0~7

High-Z

Dout

DQ8~15

High-Z

Dout

Mode

Power

Deselected

Standby

DPD

L

H

Output Disabled

Lower Byte Read

Upper Byte Read

Word Read

Active

X¹⁾

L

X¹⁾

H

L

H

L

H

L

H

L

H

L

H

L

High-Z

Dout

L

H

L

H

L

Dout

L

H

L

H

Din

High-Z

Din

Lower Byte Write

Upper Byte Write

Word Write

L

H

L

H

L

High-Z

Din

L

H

L

Din

X¹⁾

High-Z

L

H

L

Mode Register Set

1. X must be low or high state.

2. In asynchronous mode, Clock and ADV are ignored.

FUNCTIONAL DESCRIPTION for SYNCHRONOUS MODE(A15=1)

CS

H

L

MRS

H

OE

X¹⁾

H

WE

X¹⁾

H

LB

X¹⁾

H

UB

X¹⁾

H

DQ0~7

High-Z

Dout

DQ8~15

High-Z

Dout

CLK

X²⁾

ADV

X²⁾

H

Mode

Power

Standby

DPD

Deselected

X²⁾

L

Deselected

X²⁾

H

Output Disabled

Read Add. Input Load

Lower Byte Read

Upper Byte Read

Word Read

Active

X¹⁾

L

X¹⁾

H

X²⁾

L

H

X¹⁾

L

X¹⁾

H

L

H

L

H

L

H

L

H

L

High-Z

Dout

L

H

L

H

L

Dout

H

X²⁾

L

H

L

H

Din

High-Z

Din

Lor

L or

L

Lower Byte Write

Upper Byte Write

Word Write

L

H

L

H

L

High-Z

Din

L

H

L

Din

X¹⁾

L

H

L

High-Z

Mode Register Set

1. X must be low or high state.

2. X means "Don’t care"(can be low, high or toggling).

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KBF0x0800M

MCP MEMORY

ABSOLUTE MAXIMUM RATINGS¹⁾

Item

Voltage on any pin relative to Vss

Power supply voltage relative to Vss

Output power supply voltage relative to Vss

Power Dissipation

Symbol

VIN, VOUT

VDD

Ratings

Unit

-0.2 to VDD+0.3V

-0.2 to 3.0V

-0.2 to 2.5V

1.0

V

VDDQ

PD

W

°C

Storage temperature

TSTG

TA

-65 to 150

-25 to 85

Operating Temperature

1. Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. Functional operation should be

restricted to be used under recommended operating condition. Exposure to absolute maximum rating conditions longer than 1 second may affect reli-

ability.

STANDBY MODE STATE MACHINES

CS=VIL, UB or LB=VIL

WE=VIL, MRS=VIL

CS=VIH

MRS=VIH

CS=VIL, UB or LB=VIL

MRS=VIH

Initial State

(Wait 200ms)

Standby

Mode

DPD

Mode

Power On

MRS Setting

Active

MRS=VIL

CS=VIH

MRS=VIH

NOTE : Default mode after power up is Asynchronous mode and DPD enable. But this default mode is not 100% guaranteed so MRS

setting sequence is highly recommended after power up or after getting out of DPD mode.

If Synchronous operation is needed, set A15=1. For more detail, please refer to the Mode Register Set(See Page 54).

Once the device gets out of DPD mode, all the register settings are initialized into the default mode.

For entry to DPD mode, drive MRS pin into VIL for over 0.5us(suspend period) during standby mode after MRS setting has

been completed(A4=0). To get out of the DPD mode, drive MRS pin into VIH with wake up sequence(See Page 69).

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KBF0x0800M

MCP MEMORY

RECOMMENDED DC OPERATING CONDITIONS¹⁾

Item

Symbol

VCC

Min

2.5

1.7

0

Typ

2.6

1.85

0

Max

Unit

V

Power supply voltage

I/O power supply voltage

Ground

2.7

VCCQ

Vss

2.0

V

0

V

VDDQ+0.2²⁾

0.4

Input high voltage

Input low voltage

VIH

1.5

-0.2³⁾

-

V

VIL

-

V

1. TA=-25 to 85°C, otherwise specified.

2. Overshoot: VCC+1.0V in case of pulse width £20ns.

3. Undershoot: -1.0V in case of pulse width £20ns.

4. Overshoot and undershoot are sampled, not 100% tested.

CAPACITANCE¹⁾(f=1MHz, TA=25°C)

Item

Input capacitance

Symbol

CIN

Test Condition

Min

Max

16

Unit

pF

VIN=0V

VIO=0V

-

Input/Output capacitance

CIO

20

pF

1. Capacitance is sampled, not 100% tested.

DC AND OPERATING CHARACTERISTICS

Symbol

ILI

Item

Test Conditions

Min

Max

2

Unit

Typ

Input leakage current

Output leakage current

VIN=Vss to VCCQ

-2

-

mA

ILO

CS=VIH, MRS=VIH, OE=VIH or WE=VIL, VIO=Vss to VCCQ

2

Cycle time=Min, IIO=0mA, 100% duty, CS=VIL, MRS=VIH,

VIN=VIL or VIH

Average operating current

ICC2

-

45

mA

Output low voltage

Output high voltage

Standby Current(CMOS)

Deep Power Down

VOL

VOH

ISB1

ISBD

IOL=0.1mA

-

1.4

-

0.2

-

V

IOH=-0.1mA

CS³ VCCQ-0.2V, MRS³ VCCQ-0.2V, Other inputs=Vss to VCCQ

MRS£0.2V, CS³ VCCQ-0.2V, Other inputs=Vss to VCCQ

350

50

mA

-

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Preliminary

KBF0x0800M

MCP MEMORY

DEVICE OPERATION

The device has several modes : Synchronous Burst Read mode, Asynchronous Write mode, Standby mode and Deep Power

Down(DPD) mode.

Deep Power Down(DPD) mode is defined through Mode Register Set(MRS) option. Mode Register Set(MRS) option also defines

Burst Length, Burst Type and First Access Latency Count at Synchronous Burst Read mode.

To set Mode Register, the system must drive CS, ADV, WE and MRS to VIL and drive OE to VIH during valid address. To get into the

Standby mode, the system must drive CS to VIH. To get into the Deep Power Down(DPD) mode, the system must drive CS to CMOS

VIH(VCC-0.2V) and MRS to CMOS VIL(0.2V).

Mode Register Set (MRS)

The mode register stores the data for controlling the various operation modes of UtRAM. It programs Deep Power Down(DPD) mode,

Burst Length, Burst Type, First Access Latency Count and various vendor specific options to make UtRAM useful for a variety of differ-

ent applications. The default values of mode register are defined, therefore unless user specifies the specific modes, the device runs

at default modes. If user wants to set modes other than default modes, user should write specific mode value on mode register after

power up. The mode register is written by driving CS, ADV, WE and MRS to VIL and driving OE to VIH during valid address. The mode

register is divided into various fields depending on the fields of functions. The Deep Power Down(DPD) field uses A4, Burst Length

field uses A6~A7, Burst Type uses A8 and First Access Latency Count uses A9~A11. Refer to the Table below for detailed Mode Reg-

ister Setting.

Mode Register Setting according to field of function

Address

Function

An~A16

A15

A14~A12

A11~A9

A8

A7~A6

A5

A4

RFU

MS

RFU

Latency

BT

BL

RFU

DPD

NOTE : RFU(Reserved for Future Use), BT(Burst Type), BL(Burst Length), DPD(Deep Power Down), MS(Mode Select)

Mode Select

Async./Sync.

First Access Latency Count

Burst Type

Type

Burst Length

A9⁾

0

A15

0

A11

0

A10

0

Latency

A8

0

A7

0

A6

0

Length

Async. Mode

Reserved

Linear

4

1

Sync. Mode

0

1

3

1

Interleave

0

1

8

16

0

1

0

4

1

0

1

5

1

Reserved

1

0

6

1

0

1

Reserved

1

0

1

Deep power Down

A4

DPD

0

1

DPD Enable

DPD Disable

NOTE : Default mode(when user does not write any specific value to the mode register) is Async. mode and DPD enable.

Even though the device used to work in the sync. mode, once the device gets out of DPD mode, all the register settings are

initialized into the default mode.But this default mode is not 100% guaranteed so MRS setting sequence is highly recom-

mended after power up or after getting out of DPD mode.

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KBF0x0800M

MCP MEMORY

Asynchronous Read Operation

Asynchronous read operation starts when CS, OE and UB or LB are driven to VIL under the valid address.(MRS and WE should be

driven to VIH during asynchronous read operation)

Asynchronous Write Operation

Asynchronous write operation starts when CS, WE and UB or LB are driven to VIL under the valid address.(MRS and OE should be

driven to VIH during write operation.)

Asynchronous Write Operation in Synchronous Mode

A write operation starts when CS, WE and UB & LB are driven to VIL under the valid address. Clock input does not have any affect to

the write operation.(MRS and OE should be driven to VIH during write operation. ADV can be toggling for address latch or can be

driven to VIL)

Synchronous Burst Read Operation

The device supports Linear Synchronous Burst Read mode and Interleave Synchronous Burst Read mode.

For the optimized Burst Mode to each system, the system should determine how many clock cycles are desirable for the initial word of

each burst access(First Access Latency Count), how many words the device outputs at an access(Burst Length) and which type of

burst operation(Burst Type : Linear or Interleave) is desired.(See Table "Mode Register Set")

Clock(CLK)

The clock input is used as the reference for synchronous burst read operation of UtRAM. Synchronous burst read operation is syn-

chronized to the rising edge of the clock. The clock transitions must swing between VIL and VIH.

First Access Latency Count

The First Access Latency Count configuration tells the device how many clocks must elapse from ADV de-assertion(VIH) before the

first data word should be driven onto its data pins. This value depends on the input clock frequency.

The supported Latency Count is as follows.

Latency Count support : 3, 4, 5, 6

Clock Frequency

Latency Count

Upto 54MHz

Upto 40MHz

4, 5, 6

3, 4, 5, 6

First Access Latency Configuration

T

Clock

ADV

Address

Latency 3

Data out

DQ1

DQ2

DQ1

DQ3

DQ2

DQ1

DQ4

DQ3

DQ2

DQ1

DQ5

DQ6

DQ5

DQ4

DQ3

DQ7

DQ6

DQ5

DQ4

DQ8

DQ7

DQ6

DQ5

DQ9

DQ8

DQ7

DQ6

Latency 4

DQ4

DQ3

DQ2

Data out

Latency 5

Data out

Latency 6

Data out

NOTE : Other First Access Latency Configuration settings are reserved.

Only one rising edge of the clock is allowed during ADV low pulse

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KBF0x0800M

MCP MEMORY

Burst Sequence

Start

Burst Address Sequence

8 word Burst

4 word Burst

16 word Burst

Address

Linear

0-1-2-3

1-2-3-0

2-3-0-1

3-0-1-2

Interleave

0-1-2-3

1-0-3-2

2-3-0-1

3-2-1-0

Linear

Interleave

Linear

Interleave

0-1-2-3-4...14-15

1-0-3-2-5...15-14

2-3-0-1-6...12-13

3-2-1-0-7...13-12

4-5-6-7-0...10-11

5-4-7-6-1...11-10

6-7-4-5-2...8-9

7-6-5-4-3...9-8

~

0

1

0-1-2-3-4-5-6-7

1-2-3-4-5-6-7-0

2-3-4-5-6-7-0-1

3-4-5-6-7-0-1-2

4-5-6-7-0-1-2-3

5-6-7-0-1-2-3-4

6-7-0-1-2-3-4-5

7-0-1-2-3-4-5-6

0-1-2-3-4-5-6-7

1-0-3-2-5-4-7-6

2-3-0-1-6-7-4-5

3-2-1-0-7-6-5-4

4-5-6-7-0-1-2-3

5-4-7-6-1-0-3-2

6-7-4-5-2-3-0-1

7-6-5-4-3-2-1-0

0-1-2-3-4...14-15

1-2-3-4...14-15-0

2-3-4...14-15-0-1

3-4-5...15-0-1-2

4-5-6...15-0-1-2-3

5-6...15-0-1-2-3-4

6-7...15-0-1-2-3-4-5

7-8...15-0-1...5-6

~

2

3

4

5

6

7

~

14

15

14-15-0-1...12-13

15-0-1...12-13-14

14-15-12-13-10...0-1

15-14-13-12-11...1-0

Burst Stop

Burst stop is used when the system wants to stop burst operation on special purpose. If driving CS to VIH during burst read operation,

then burst operation will be stopped. During burst read operation, the new burst operation by ADV can not be issued. The new burst

operation can be issued only after the previous burst operation is finished.

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Preliminary

KBF0x0800M

MCP MEMORY

AC OPERATING CONDITIONS

TEST CONDITIONS(Test Load and Test Input/Output Reference)

Input pulse level: 0.2 to VCCQ-0.2V

Input rising and falling time: 3ns

Input and output reference voltage: 0.5 x VCCQ

Output load: CL=50pF

ASYNCHRONOUS AC CHARACTERISTICS (VCC=2.5~2.7V, VCCQ=1.7~2.0V, TA=-25 to 85°C)

Speed

Parameter List

Symbol

Units

Min

Max

Read Cycle Time

tRC

tAA

85

-

85

40

-

ns

Address Access Time

Chip Select to Output

tCO

tOE

-

Output Enable to Valid Output

UB, LB Access Time

-

tBA

-

Async.

Read

Chip Select to Low-Z Output

UB, LB Enable to Low-Z Output

Output Enable to Low-Z Output

Chip Disable to High-Z Output

UB, LB Disable to High-Z Output

Output Disable to High-Z Output

Output Hold

tLZ

10

5

tBLZ

tOLZ

tHZ

-

0

25

-

tBHZ

tOHZ

tOH

tWC

tCW

tAS

0

10

85

70

0

Write Cycle Time

-

Chip Select to End of Write

Address Set-up Time to Beginning of Write

Address Valid to End of Write

UB, LB Valid to End of Write

Write Pulse Width

-

tAW

tBW

tWP

tWR

tDW

tDH

70

60¹⁾

0

-

Async.

Write

-

Write Recovery Time

-

Data to Write Time Overlap

Data Hold from Write Time

MRS Enable to Register Write Start

Register Write Recovery Time

End of Write to MRS Disable

35

0

-

tMW

tRWR

tWU

0

500

-

MRS

5

0

-

1. tWP(min)=85ns for continuous write operation over 50 times.

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KBF0x0800M

MCP MEMORY

ASYNCHRONOUS READ TIMING WAVEFORM

TIMING WAVEFORM OF ASYNCHRONOUS READ CYCLE(1)(Address Controlled, CS=OE=VIL, MRS=WE=VIH, UB or LB=VIL)

tRC

Address

tAA

tOH

Data Out

Data Valid

Previous Data Valid

TIMING WAVEFORM OF ASYNCHRONOUS READ CYCLE(2)(MRS=WE=VIH)

tRC

Address

tAA

tOH

tCO

CS

tHZ

tBA

UB, LB

tBHZ

tOE

OE

tOLZ

tBLZ

tLZ

tOHZ

High-Z

Data out

Data Valid

(ASYNCHRONOUS READ CYCLE)

1. tHZ and tOHZ are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage

levels.

2. At any given temperature and voltage condition, tHZ(Max.) is less than tLZ(Min.) both for a given device and from device to device

interconnection.

3. tOE(max) is met only when OE becomes enabled after tAA(max).

4. If invalid address signals shorter than min. tRC are continuously repeated for over 4us, the device needs a normal read timing(tRC) or

needs to sustain standby state for min. tRC at least once in every 4us.

5. In asynchronous mode, Clock and ADV are ignored.

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Preliminary

KBF0x0800M

MCP MEMORY

ASYNCHRONOUS WRITE TIMING WAVEFORM

TIMING WAVEFORM OF WRITE CYCLE(1)(MRS=VIH, OE=VIH, WE Controlled)

tWC

Address

tWR(4)

tCW(2)

CS

tAW

tBW

UB, LB

tWP(1)

WE

tAS(3)

tDW

tDH

High-Z

Data in

Data Valid

Data out

High-Z

TIMING WAVEFORM OF WRITE CYCLE(2)(MRS=VIH, OE=VIH, UB & LB Controlled)

tWC

Address

tWR(4)

tCW(2)

CS

tAW

tBW

UB, LB

tAS(3)

tWP(1)

WE

tDH

tDW

Data in

Data Valid

High-Z

Data out

High-Z

(WRITE CYCLE)

1. A write occurs during the overlap(tWP) of low CS and low WE. A write begins when CS goes low and WE goes low with asserting UB

or LB for single byte operation or simultaneously asserting UB and LB for double byte operation. A write ends at the earliest transition

when CS goes high and WE goes high. The tWP is measured from the beginning of write to the end of write.

2. tCW is measured from the CS going low to the end of write.

3. tAS is measured from the address valid to the beginning of write.

4. tWR is measured from the end of write to the address change. tWR is applied in case a write ends with CS or WE going high.

5. In asynchronous mode, Clock and ADV are ignored.

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KBF0x0800M

MCP MEMORY

AC OPERATING CONDITIONS

TEST CONDITIONS(Test Load and Test Input/Output Reference)

Input pulse level: 0.2 to VCCQ-0.2V

Input rising and falling time: 3ns

Input and output reference voltage: 0.5 x VCCQ

Output load: CL=50pF

SYNCHRONOUS AC CHARACTERISTICS (VCC=2.5~2.7V, VCCQ=1.7~2.0V, TA=-25 to 85°C, Maximum Main

Clock Frequency=54MHz)

Speed

Parameter List

Symbol

Units

Min

18.5

0

Max

Clock Cycle Time

T

200

ns

Clock

ns

-

Address Set-up Time to ADV Falling

Address Hold Time from ADV Rising

ADV Setup Time

tAS(R)

tAH(R)

tADVS

tADVH

tCSS(R)

tCSLH

tCSHP

tADHP

tBEL

-

7

-

7

-

ADV Hold Time

7

-

CS Setup Time to Clock Rising

CS Low Hold Time from Clock

CS High Pulse Width

7

-

10

5

-

Sync.

Burst

Read

-

ADV High Pulse Width

5

-

UB, LB Valid to End of Latency

Output Enable to End of Latency

UB, LB Valid to Low-Z Output

Output Enable to Low-Z Output

Latency Clock Rising Edge to Data Output

Output Hold

1

-

tOEL

1

-

tBLZ

10

5

-

tOLZ

-

tCD

-

12

tOH

3

-

Output High-Z

tHZ

-

10

2)

Write Cycle Time

85

0

-

tWC

Address Set-up Time to ADV Falling

Address Hold Time from ADV Rising

CS Setup Time to ADV Rising

Address Set-up Time to Beginning of Write

Write Recovery Time

tAS(W)

tAH(W)

tCSS(W)

tAS

-

7

-

10

0

-

tWR

0

-

Async.

Write

Burst Read End Clock to Next ADV Falling

Chip Select to End of Write

Address Valid to End of Write

UB, LB Valid to End of Write

Write Pulse Width

tBEWA

tCW

3

-

70

60¹⁾

5 ns

35

0

-

tAW

-

tBW

-

tWP

-

WE High Pulse Width

tWHP

tDW

Latency-1 clock

Data to Write Time Overlap

Data Hold from Write Time

MRS Enable to Register Write Start

Register Write Recovery Time

End of Write to MRS Disable

-

ns

tDH

-

tMW

0

500

MRS

tRWR

tWU

5

-

0

1. tWP(min)=85ns for continuous write operation over 50 times.

2. In ADDRESS LATCH TYPE WRITE TIMING, tWC is same as tAW.

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KBF0x0800M

MCP MEMORY

SYNCHRONOUS BURST READ TIMING WAVEFORM

TIMING WAVEFORM OF BURST READ CYCLE(1) [Latency=5, Burst Length=4](WE=VIH, MRS=VIH)

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

T

CLK

tADVH

tADVS

tADVH

tADVS

ADV

tAH(R)

tAS(R)

Address

CS

Valid

Don’t Care

Valid

tCSS(R)

tBEL

LB, UB

OE

tBLZ

tOEL

tOLZ

Latency 5

tCD

tOH

tHZ

Data

Undefined DQ0 DQ1 DQ2 DQ3

(SYNCHRONOUS BURST READ CYCLE)

1. Only one rising edge of the clock is allowed during ADV low pulse.

2. The new burst operation can be issued only after the previous burst operation is finished.

TIMING WAVEFORM OF BURST READ CYCLE(2) [Latency=5, Burst Length=4](WE=VIH, MRS=VIH)

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

T

CLK

tADVH

tADVS

ADV

tAH(R)

tAS(R)

Address

CS

Valid

Don’t Care

tCSS(R)

tBEL

LB, UB

OE

tBLZ

tOEL

tOLZ

Latency 5

tCD

tOH

Data

Undefined DQ0 DQ1 DQ2 DQ3

(SYNCHRONOUS BURST READ CYCLE)

1.Only one rising edge of the clock is allowed during ADV low pulse.

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KBF0x0800M

MCP MEMORY

BURST STOP TIMING WAVEFORM

TIMING WAVEFORM OF BURST STOP by CS [Latency=5, Burst Length=4](WE=VIH, MRS=VIH)

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

T

CLK

tADVH

tADVS

ADV

Address

CS

tAH(R)

tAS(R)

Valid

Don’t Care

Valid

tCSS(R)

tCSHP

tCSLH

tBEL

LB, UB

OE

tBLZ

tOEL

tOLZ

Latency 5

tOH

tHZ

tCD

Data

Undefined DQ0

DQ1

(SYNCHRONOUS BURST STOP)

1. Only one rising edge of the clock is allowed during ADV low pulse.

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KBF0x0800M

MCP MEMORY

ASYNCHRONOUS WRITE TIMING WAVEFORM in SYNCHRONOUS MODE

TIMING WAVEFORM OF WRITE CYCLE(Address Latch Type)(MRS=VIH, OE=VIH, WE Controlled)

0

1

2

3

4

5

6

7

8

9

10

11

12

13

CLK

ADV

tAS(W)

tAH(W)

Address

Valid

Don’t Care

tCSS(W)

tAW(2), tCW(3)

tBW(4)

CS

UB, LB

tWP(1)

WE

tAS

tDW

tDH

Data in

Data Valid

Read Latency 5

Read Latency - 1 Clock

High-Z

Data out

High-Z

TIMING WAVEFORM OF WRITE CYCLE(Address Latch Type)(MRS=VIH, OE=VIH, UB & LB Controlled)

0

1

2

3

4

5

6

7

8

9

10

11

12

13

CLK

ADV

tAS(W)

tAH(W)

Address

Valid

Don’t Care

tCSS(W)

tAW(2), tCW(3)

CS

tBW(4)

UB, LB

WE

tAS

tWP(1)

tDW

tDH

Data in

Data Valid

Read Latency 5

Read Latency - 1 Clock

High-Z

Data out

(ADDRESS LATCH TYPE WRITE CYCLE)

1. A write occurs during the overlap(tWP) of low CS and low WE. A write begins when CS goes low and WE goes low with asserting UB

or LB for single byte operation or simultaneously asserting UB and LB for double byte operation. A write ends at the earliest transition

when CS goes high and WE goes high. The tWP is measured from the beginning of write to the end of write.

2. tAW is measured from the address valid to the end of write. In this address latch type write timing, tWC is same as tAW.

3. tCW is measured from the CS going low to the end of write.

4. tBW is measured from the UB and LB going low to the end of write.

5. Clock input does not have any affect to the write operation if WE is driven to low before Read Latency-1 clock. Read Latency-1 clock

in write timing is just a reference to WE low going for proper write operation.

63

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Preliminary

KBF0x0800M

MCP MEMORY

ASYNCHRONOUS WRITE TIMING WAVEFORM in SYNCHRONOUS MODE

TIMING WAVEFORM OF WRITE CYCLE(Low ADV Type)(MRS=VIH, OE=VIH, WE Controlled)

0

1

2

3

4

5

6

7

8

9

CLK

ADV

tWC

Address

tWR(4)

tCW(2)

CS

tAW

tBW

UB, LB

tWP(1)

WE

tAS(3)

tDH

tDW

Data in

Data Valid

Read Latency 5

Read Latency - 1 Clock

High-Z

Data out

High-Z

TIMING WAVEFORM OF WRITE CYCLE(Low ADV Type)(MRS=VIH, OE=VIH, UB & LB Controlled)

0

1

2

3

4

5

6

7

8

9

CLK

ADV

tWC

Address

tWR(4)

tCW(2)

CS

tAW

tBW

UB, LB

tAS(3)

tWP(1)

WE

tDH

tDW

Data Valid

Data in

Read Latency 5

Read Latency - 1 Clock

High-Z

Data out

High-Z

(LOW ADV TYPE WRITE CYCLE)