KFG1G16Q2C-AEB6T [SAMSUNG]
EEPROM Card, 64MX16, 11ns, Parallel, CMOS, PBGA63;型号: | KFG1G16Q2C-AEB6T |
厂家: | SAMSUNG |
描述: | EEPROM Card, 64MX16, 11ns, Parallel, CMOS, PBGA63 可编程只读存储器 电动程控只读存储器 电可擦编程只读存储器 |
文件: | 总142页 (文件大小:2252K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
OneNAND1Gb(KFG1G16Q2C-xEBx)
FLASH MEMORY
KFG1G16Q2C
1Gb OneNAND C-die
INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS,
AND IS SUBJECT TO CHANGE WITHOUT NOTICE.
NOTHING IN THIS DOCUMENT SHALL BE CONSTRUED AS GRANTING ANY LICENSE,
EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE,
TO ANY INTELLECTUAL PROPERTY RIGHTS IN SAMSUNG PRODUCTS OR TECHNOLOGY. ALL
INFORMATION IN THIS DOCUMENT IS PROVIDED
ON AS "AS IS" BASIS WITHOUT GUARANTEE OR WARRANTY OF ANY KIND.
1. For updates or additional information about Samsung products, contact your nearest Samsung office.
2. Samsung products are not intended for use in life support, critical care, medical, safety equipment, or similar
applications where Product failure could result in loss of life or personal or physical harm, or any military or
defense application, or any governmental procurement to which special terms or provisions may apply.
OneNAND™‚ is a trademark of Samsung Electronics Company, Ltd. Other names and brands may be claimed as
the property of their rightful owners.
* Samsung Electronics reserves the right to change products or specification without notice.
- 1 -
OneNAND1Gb(KFG1G16Q2C-xEBx)
Revision History
FLASH MEMORY
Document Title
OneNAND
Revision History
Revision No.
History
Draft Date
Remark
0.0
1. Initial issue.
Apr. 30, 2008
Advanced
1.0
1. Chapter 1.0 INTRODUCTION revised.
2. Chapter 1.2 Ordering Information revised.
3. Chapter 1.4 Product Features revised.
4. Chapter 3.3.1 Cold Reset Mode Operation revised.
5. Chapter 6.15 Cold Reset Timing revised.
Oct. 10. 2008
Final
Dec. 16, 2008
Final
1.1
1. Corrected errata.
2. Chapter 2.8.18 Command Register F220h (R/W) revised.
3. Chpater 3.4.3 NAND Array Write Protection States revised.
4. Chapter 3.4.3.1 Unlocked NAND Array Write Protection State revised.
5. Chapter 3.4.3.3 Locked-tight NAND Array Write Protection State revised.
6. Chapter 3.4.4 All Block Unlock Flow Diagram revised.
7. Chapter 3.13.3 Multi-Block Erase Verify Read Operation revised.
8. Chapter 5.7 AC Characteristics for Asynchronous Write revised.
9. Chapter 5.9 AC Characteristics for Load / Program / Erase Performance
revised.
- 2 -
OneNAND1Gb(KFG1G16Q2C-xEBx)
1.0 INTRODUCTION
FLASH MEMORY
This specification contains information about the Samsung Electronics Company OneNANDꢀ‚ Flash memory product family. Section 1.0
includes a general overview, revision history, and product ordering information.
Section 2.0 describes the OneNAND device. Section 3.0 provides information about device operation. Electrical specifications and timing
waveforms are in Sections 4.0 through 6.0. Section 7.0 provides additional application and technical notes pertaining to use of the
OneNAND. Package dimensions are found in Section 8.0.
Density
Part No.
VCC(core & IO)
Temperature
PKG
1Gb
KFG1G16Q2C-xEBx
1.8V(1.7V~1.95V)
Extended
63FBGA
1.1 Flash Product Type Selector
Samsung offers a variety of Flash solutions including NAND Flash, OneNANDꢀ and NOR Flash. Samsung offers Flash products both compo-
nent and a variety of card formats including RS-MMC, MMC, CompactFlash, and SmartMedia.
To determine which Samsung Flash product solution is best for your application, refer the product selector chart.
Samsung Flash Products
Application Requires
NAND
OneNANDꢀ
NOR
Fast Random Read
Fast Sequential Read
Fast Write/Program
Multi Block Erase
Erase Suspend/Resume
Copyback
•
•
•
•
•
• (Max 64 Blocks)
•
•
•
• (EDC)
• (ECC)
Lock/Unlock/Lock-Tight
ECC
•
Internal
•
•
External (Hardware/Software)
X
Scalability
•
- 3 -
OneNAND1Gb(KFG1G16Q2C-xEBx)
FLASH MEMORY
1.2 Ordering Information
KF G 1G 16 Q 2 C - x E x x
Speed
Samsung
OneNAND Memory
6 : 66MHz
8 : 83MHz
Product Line designator
B : Include Bad Block
D : Daisy Sample
Device Type
G : Single Chip
Operating Temperature Range
E : Extended Temp. (-30 °C to 85 °C)
Density
1G : 1Gb
Package
D : FBGA(Lead Free)
A : FBGA(Halogen Free)
Organization
Version
16 : x16 Organization
C : 4th Generation
Operating Voltage Range
Q : 1.8V(1.7 V to 1.95V)
Page Architecture
2 : 2KB Page
1.3 Architectural Benefits
OneNAND is a highly integrated non-volatile memory solution based around a NAND Flash memory array.
The chip integrates system features including:
• A BootRAM and bootloader
• Two independent bi-directional 2KB DataRAM buffers
• A High-Speed x16 Host Interface
• On-chip Error Correction
• On-chip NOR interface controller
This on-chip integration enables system designers to reduce external system logic and use high-density NAND Flash in applications that
would otherwise have to use more NOR components.
OneNAND takes advantage of the higher performance NAND program time, low power, and high density and combines it with the synchro-
nous read performance of NOR. The NOR Flash host interface makes OneNAND an ideal solution for applications like G3 Smart Phones,
Camera Phones, and mobile applications that have large, advanced multimedia applications and operating systems, but lack a NAND control-
ler.
When integrated into a Samsung Multi-Chip-Package with Samsung Mobile DDR SDRAM, designers can complete a high-performance, small
footprint solution.
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OneNAND1Gb(KFG1G16Q2C-xEBx)
FLASH MEMORY
1.4 Product Features
Device Architecture
• Design Technology:
• Supply Voltage:
• Host Interface:
C die
1.8V (1.7V ~ 1.95V)
16 bit
• 5KB Internal BufferRAM:
• SLC NAND Array:
1KB BootRAM, 4KB DataRAM
(2K+64)B Page Size, (128K+4K)B Block Size
Device Performance
• Host Interface Type:
Synchronous Burst Read
- Up to 66MHz / 83MHz clock frequency
- Linear Burst 4-, 8-, 16-, 32-words with wrap around
- Continuous 1K words Sequential Burst
Synchronous Burst Block Read
- Up to 66MHz / 83MHz clock frequency
- Linear Burst 4-, 8-, 16-, 32-, 1K-words with no-wrap
- Continuous (1K words) 64 Page Sequential Burst
Synchronous Write
- Up to 66MHz / 83MHz clock frequency
- Linear Burst 4-, 8-, 16-, 32-, 1K-words with wrap around
- Continuous 1K words Sequential Burst
Asynchronous Random Read
- 76ns access time
Asynchronous Random Write
• Programmable Burst Read Latency:
Latency 3,4(Default),5,6 and 7.
1~40MHz : Latency 3 available
1~66MHz : Latency 4,5,6 and 7 available
Over 66MHz : Latency 6,7 available.
Up to 4 sectors using Sector Count Register
Cold/Warm/Hot/NAND Flash Core Reset
up to 64 Blocks
• Multiple Sector Read/Write:
• Multiple Reset Modes:
• Multi Block Erase:
• Low Power Dissipation:
Typical Power,
- Standby current : 10uA
- Synchronous Burst Read current(66/83MHz) : 15/20mA
- Synchronous Burst Write current(66/83MHz) : 15/20mA
- Load current : 30mA
- Program current : 25mA
- Erase current : 20mA
- Multi Block Erase current : 20mA
• Reliability
- Data retention 10year after 10K Program/Erase Cycles
- Data retention 1 year after 100K Program/Erase Cycles
System Hardware
• Voltage detector generating internal reset signal from Vcc
• Hardware reset input (RP)
• Data Protection Modes
- Write Protection for BootRAM
- Write Protection for NAND Flash Array
- Write Protection during power-up
- Write Protection during power-down
- 1st block OTP
• User-controlled One Time Programmable(OTP) area
• Internal 2bit EDC / 1bit ECC
• Internal Bootloader supports Booting Solution in system
• Handshaking Feature
- INT pin indicates Ready / Busy
- Polling the interrupt register status bit
- by ID register
• Detailed chip information
Packaging
• 1Gb products
63ball, 10mm x 13mm x max 1.0mmt , 0.8mm ball pitch FBGA
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OneNAND1Gb(KFG1G16Q2C-xEBx)
FLASH MEMORY
1.5 General Overview
OneNANDꢀ‚ is a monolithic integrated circuit with a NAND Flash array using a NOR Flash interface. This device includes control logic, a
NAND Flash array, and 5KB of internal BufferRAM. The BufferRAM reserves 1KB for boot code buffering (BootRAM) and 4KB for data buffer-
ing (DataRAM), split between 2 independent buffers. It has a x16 Host Interface and a random access time speed of ~76ns.
The device operates up to a maximum host-driven clock frequency of 66MHz / 83MHz for synchronous reads at Vcc(or Vccq. Refer to chapter
4.2) with minimum 6-clock latency. Below 40MHz it is accessible with minimum 3-clock latency. Appropriate wait cycles are determined by
programmable read latency.
OneNAND provides for multiple sector read operations by assigning the number of sectors to be read in the sector counter register. The
device includes one block-sized OTP (One Time Programmable) area and user-controlled 1st block OTP(Block 0) that can be used to
increase system security or to provide identification capabilities.
The attached datasheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to
change the specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions about device. If you have any ques-
tions, please contact the SAMSUNG branch office near you.
- 6 -
OneNAND1Gb(KFG1G16Q2C-xEBx)
2.0 DEVICE DESCRIPTION
FLASH MEMORY
2.1 Detailed Product Description
The OneNAND is an advanced generation, high-performance NAND-based Flash memory.
It integrates on-chip a single-level-cell (SLC) NAND Flash Array memory with two independent data buffers, boot RAM buffer, a page buffer for
the Flash array, and a one-time-programmable block.
The combination of these memory areas enable high-speed pipelining of reads from host, BufferRAM, Page Buffer, and NAND Flash Array.
Clock speeds up to 66MHz / 83MHz with a x16 wide I/O yields a 108MByte/second bandwidth.
The OneNAND also includes a Boot RAM and boot loader. This enables the device to efficiently load boot code at device startup from the
NAND Array without the need for off-chip boot device.
One block of the NAND Array is set aside as an OTP memory area, and 1st Block (Block 0) can be used as OTP area. This area, available to
the user, can be configured and locked with secured user information.
On-chip controller interfaces enable the device to operate in systems without NAND Host controllers.
- 7 -
OneNAND1Gb(KFG1G16Q2C-xEBx)
FLASH MEMORY
2.2 Definitions
B (capital letter)
W (capital letter)
b (lower-case letter)
ECC
Byte, 8bits
Word, 16bits
Bit
Error Correction Code
Calculated ECC
Written ECC
BufferRAM
ECC that has been calculated during a load or program access
ECC that has been stored as data in the NAND Flash array or in the BufferRAM
On-chip internal buffer consisting of BootRAM and DataRAM
A 1KB portion of the BufferRAM reserved for Boot Code buffering
A 4KB portion of the BufferRAM reserved for Data buffering
BootRAM
DataRAM
Part of a Page of which 512B is the main data area and 16B is the spare data area.
It is also the minimum Load/Program/Copy-Back Program unit
during a 1~4 sector operation is available.
Sector
Possible data unit to be read from memory to BufferRAM or to be programmed to memory.
-
528B of which 512B is in main area and 16B in spare area
Data unit
- 1056B of which 1024B is in main area and 32B in spare area
- 1584B of which 1536B is in main area and 48B in spare area
- 2112B of which 2048B is in main area and 64B in spare area
- 8 -
OneNAND1Gb(KFG1G16Q2C-xEBx)
FLASH MEMORY
2.3 Pin Configuration
2.3.1 1Gb Product (KFG1G16Q2C)
NC
NC
NC
NC
NC
NC
NC
VSS
OE
VSS
DQ9
DQ3
DQ5
NC
WE
RP
DQ14
DQ1
DQ11
DQ0
DQ2
AVD
A1
DQ13
VCC
Core
DQ12
DQ7
DQ8
DQ4
A12
VCC
IO
DQ10
A15
DQ15
DQ6
A9
CLK
A14
CE
NC
A7
NC
A2
A13
A11
A10
A3
A8
INT
A0
A4
A6
A5
NC
RDY
NC
NC
NC
NC
NC
NC
NC
NC
(TOP VIEW, Balls Facing Down)
63ball FBGA OneNAND Chip
63ball, 10mm x 13mm x max 1.0mmt , 0.8mm ball pitch FBGA
- 9 -
OneNAND1Gb(KFG1G16Q2C-xEBx)
FLASH MEMORY
2.4 Pin Description
Pin Name
Type
Nameand Description
Host Interface
Address Inputs
A15~A0
I
- Inputs for addresses during read and write operation, which are for addressing
BufferRAM & Register.
Data Inputs/Outputs
- Inputs data during program and commands for all operations, outputs data during memory array/
register read cycles.
DQ15~DQ0
I/O
Data pins float to high-impedance when the chip is deselected or outputs are disabled.
Interrupt
INT
RDY
CLK
WE
O
O
I
Notifies the Host when a command is completed. After power-up, it is at hi-z condition. Once IOBE is set to 1, it does not float
to hi-z condition even when CE is disabled or OE is disabled.
Ready
Indicates data valid in synchronous read modes and is activated while CE is low
Clock
CLK synchronizes the device to the system bus frequency in synchronous read mode.
The first rising edge of CLK in conjunction with AVD low latches address input.
Write Enable
I
WE controls writes to the bufferRAM and registers. Datas are latched on the WE pulse’s rising edge
Address Valid Detect
IIndicates valid address presence on address inputs. During asynchronous read operation, all addresses are valid while AVD
is low, and during synchronous read operation, all addresses are latched on CLK’s rising edge while AVD is held low for one
AVD
I
I
clock cycle.
> Low : for asynchronous mode, indicates valid address; for burst mode, causes starting address to be latched on rising edge
on CLK
> High : device ignores address inputs
Reset Pin
RP
CE
When low, RP resets internal operation of OneNAND. RP status is don’t care during power-up
and bootloading. When high, RP level must be equivalent to Vcc-IO / Vccq level.
Chip Enable
I
I
CE-low activates internal control logic, and CE-high deselects the device, places it in standby state,
and places DQ in Hi-Z.
Output Enable
OE
OE-low enables the device’s output data buffers during a read cycle.
Power Supply
VCC-Core
/ Vcc
Power for OneNAND Core
This is the power supply for OneNAND Core.
Power for OneNAND I/O
This is the power supply for OneNAND I/O
Vcc-IO / Vccq is internally separated from Vcc-Core / Vcc.
VCC-IO
/ Vccq
VSS
Ground for OneNAND
etc.
Do Not Use
DNU
Leave it disconnected. These pins are used for testing.
No Connection
Lead is not internally connected.
NC
NOTE :
Do not leave power supply(Vcc-Core/Vcc-IO, VSS) disconnected.
- 10 -
OneNAND1Gb(KFG1G16Q2C-xEBx)
FLASH MEMORY
2.5 Block Diagram
BufferRAM
1st Block OTP
Bootloader
DQ15~DQ0
A15~A0
CLK
(Block 0)
BootRAM
StateMachine
DataRAM0
DataRAM1
CE
OE
NAND Flash
Array
WE
RP
Error
Correction
Logic
AVD
INT
Internal Registers
(Address/Command/Configuration
/Status Registers)
OTP
RDY
(One Block)
2.6 Memory Array Organization
The OneNAND architecture integrates several memory areas on a single chip.
2.6.1 Internal (NAND Array) Memory Organization
The on-chip internal memory is a single-level-cell (SLC) NAND array used for data storage and code. The internal memory is divided into a
main area and a spare area.
Main Area
The main area is the primary memory array. This main area is divided into Blocks of 64 Pages. Within a Block, each Page is 2KB and is com-
prised of 4 Sectors. Within a Page, each Sector is 512B and is comprised of 256 Words.
Spare Area
The spare area is used for invalid block information and ECC storage. Spare area internal memory is associated with corresponding main
area memory. Within a Block, each Page has four 16B Sectors of spare area. Each spare area Sector is 8 words.
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OneNAND1Gb(KFG1G16Q2C-xEBx)
FLASH MEMORY
Internal Memory Array Information
Area
Main
Block
128KB
4KB
Page
2KB
64B
Sector
512B
16B
Spare
Internal Memory Array Organization
Sector
Main Area
512B
Spare Area
16B
Page
Main Area
Spare Area
512B Sector0
512B Sector1
512B Sector3
512B Sector2
16B Sector0 16B Sector1 16B Sector2
16B Sector3
2KB
64B
Block
Main Area
Spare Area
64B Page0
2KB Page0
Page 0
2KB Page63
128KB
64B Page63
4KB
Page 63
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OneNAND1Gb(KFG1G16Q2C-xEBx)
FLASH MEMORY
2.6.2 External (BufferRAM) Memory Organization
The on-chip external memory is comprised of 3 buffers used for Boot Code storage and data buffering.
The BootRAM is a 1KB buffer that receives Boot Code from the internal memory and makes it available to the host at start up.
There are two independent 2KB bi-directional data buffers, DataRAM0 and DataRAM1. These dual buffers enable the host to execute simul-
taneous Read-While load, and Write-While-program operations after Boot Up. During Boot Up, the BootRam is used by the host to initialize
the main memory, and deliver boot code from NAND Flash core to host.
Internal (Nand Array)
Memory
External (BufferRAM)
Memory
Boot code (1KB)
BootRAM (1KB)
Nand Array
Host
DataRAM0 (2KB)
DataRAM1 (2KB)
OTP Block
The external memory is divided into a main area and a spare area. Each buffer is the equivalent size of a Sector.
The main area data is 512B. The spare area data is 16B.
External Memory Array Information
Area
BootRAM
1KB+32B
2
DataRAM0
2KB+64B
4
DataRAM1
2KB+64B
4
Total Size
Number of Sectors
Main
Spare
512B
512B
512B
Sector
16B
16B
16B
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OneNAND1Gb(KFG1G16Q2C-xEBx)
FLASH MEMORY
External Memory Array Organization
Spare area data
(16B)
Main area data
(512B)
BootRAM 0
BootRAM
Sector: (512 + 16) Byte
BootRAM 1
DataRAM 0_0
DataRAM 0_1
DataRAM0
DataRAM 0_2
DataRAM 0_3
DataRAM 1_0
DataRAM 1_1
DataRAM1
DataRAM 1_2
DataRAM 1_3
- 14 -
OneNAND1Gb(KFG1G16Q2C-xEBx)
FLASH MEMORY
2.7 Memory Map
The following tables are the memory maps for the OneNAND.
2.7.1 Internal (NAND Array) Memory Organization
The following tables show the Internal Memory address map in word order.
Page and Sector
Page and Sector
Block
Block Address
Size
Block
Block Address
Size
Address
Address
Block0
Block1
0000h
0001h
0002h
0003h
0004h
0005h
0006h
0007h
0008h
0009h
000Ah
000Bh
000Ch
000Dh
000Eh
000Fh
0010h
0011h
0012h
0013h
0014h
0015h
0016h
0017h
0018h
0019h
001Ah
001Bh
001Ch
001Dh
001Eh
001Fh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
Block32
Block33
Block34
Block35
Block36
Block37
Block38
Block39
Block40
Block41
Block42
Block43
Block44
Block45
Block46
Block47
Block48
Block49
Block50
Block51
Block52
Block53
Block54
Block55
Block56
Block57
Block58
Block59
Block60
Block61
Block62
Block63
0020h
0021h
0022h
0023h
0024h
0025h
0026h
0027h
0028h
0029h
002Ah
002Bh
002Ch
002Dh
002Eh
002Fh
0030h
0031h
0032h
0033h
0034h
0035h
0036h
0037h
0038h
0039h
003Ah
003Bh
003Ch
003Dh
003Eh
003Fh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
Block2
Block3
Block4
Block5
Block6
Block7
Block8
Block9
Block10
Block11
Block12
Block13
Block14
Block15
Block16
Block17
Block18
Block19
Block20
Block21
Block22
Block23
Block24
Block25
Block26
Block27
Block28
Block29
Block30
Block31
- 15 -
OneNAND1Gb(KFG1G16Q2C-xEBx)
FLASH MEMORY
Page and Sector
Page and Sector
Block
Block Address
Size
Block
Block Address
Size
Address
Address
Block64
Block65
Block66
Block67
Block68
Block69
Block70
Block71
Block72
Block73
Block74
Block75
Block76
Block77
Block78
Block79
Block80
Block81
Block82
Block83
Block84
Block85
Block86
Block87
Block88
Block89
Block90
Block91
Block92
Block93
Block94
Block95
0040h
0041h
0042h
0043h
0044h
0045h
0046h
0047h
0048h
0049h
004Ah
004Bh
004Ch
004Dh
004Eh
004Fh
0050h
0051h
0052h
0053h
0054h
0055h
0056h
0057h
0058h
0059h
005Ah
005Bh
005Ch
005Dh
005Eh
005Fh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
Block96
Block97
0060h
0061h
0062h
0063h
0064h
0065h
0066h
0067h
0068h
0069h
006Ah
006Bh
006Ch
006Dh
006Eh
006Fh
0070h
0071h
0072h
0073h
0074h
0075h
0076h
0077h
0078h
0079h
007Ah
007Bh
007Ch
007Dh
007Eh
007Fh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
Block98
Block99
Block100
Block101
Block102
Block103
Block104
Block105
Block106
Block107
Block108
Block109
Block110
Block111
Block112
Block113
Block114
Block115
Block116
Block117
Block118
Block119
Block120
Block121
Block122
Block123
Block124
Block125
Block126
Block127
- 16 -
OneNAND1Gb(KFG1G16Q2C-xEBx)
FLASH MEMORY
Page and Sector
Page and Sector
Block
Block Address
Size
Block
Block Address
Size
Address
Address
Block128
Block129
Block130
Block131
Block132
Block133
Block134
Block135
Block136
Block137
Block138
Block139
Block140
Block141
Block142
Block143
Block144
Block145
Block146
Block147
Block148
Block149
Block150
Block151
Block152
Block153
Block154
Block155
Block156
Block157
Block158
Block159
0080h
0081h
0082h
0083h
0084h
0085h
0086h
0087h
0088h
0089h
008Ah
008Bh
008Ch
008Dh
008Eh
008Fh
0090h
0091h
0092h
0093h
0094h
0095h
0096h
0097h
0098h
0099h
009Ah
009Bh
009Ch
009Dh
009Eh
009Fh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
Block160
Block161
Block162
Block163
Block164
Block165
Block166
Block167
Block168
Block169
Block170
Block171
Block172
Block173
Block174
Block175
Block176
Block177
Block178
Block179
Block180
Block181
Block182
Block183
Block184
Block185
Block186
Block187
Block188
Block189
Block190
Block191
00A0h
00A1h
00A2h
00A3h
00A4h
00A5h
00A6h
00A7h
00A8h
00A9h
00AAh
00ABh
00ACh
00ADh
00AEh
00AFh
00B0h
00B1h
00B2h
00B3h
00B4h
00B5h
00B6h
00B7h
00B8h
00B9h
00BAh
00BBh
00BCh
00BDh
00BEh
00BFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
- 17 -
OneNAND1Gb(KFG1G16Q2C-xEBx)
FLASH MEMORY
Page and Sector
Page and Sector
Block
Block Address
Size
Block
Block Address
Size
Address
Address
Block192
Block193
Block194
Block195
Block196
Block197
Block198
Block199
Block200
Block201
Block202
Block203
Block204
Block205
Block206
Block207
Block208
Block209
Block210
Block211
Block212
Block213
Block214
Block215
Block216
Block217
Block218
Block219
Block220
Block221
Block222
Block223
00C0h
00C1h
00C2h
00C3h
00C4h
00C5h
00C6h
00C7h
00C8h
00C9h
00CAh
00CBh
00CCh
00CDh
00CEh
00CFh
00D0h
00D1h
00D2h
00D3h
00D4h
00D5h
00D6h
00D7h
00D8h
00D9h
00DAh
00DBh
00DCh
00DDh
00DEh
00DFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
Block224
Block225
Block226
Block227
Block228
Block229
Block230
Block231
Block232
Block233
Block234
Block235
Block236
Block237
Block238
Block239
Block240
Block241
Block242
Block243
Block244
Block245
Block246
Block247
Block248
Block249
Block250
Block251
Block252
Block253
Block254
Block255
00E0h
00E1h
00E2h
00E3h
00E4h
00E5h
00E6h
00E7h
00E8h
00E9h
00EAh
00EBh
00ECh
00EDh
00EEh
00EFh
00F0h
00F1h
00F2h
00F3h
00F4h
00F5h
00F6h
00F7h
00F8h
00F9h
00FAh
00FBh
00FCh
00FDh
00FEh
00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
- 18 -
OneNAND1Gb(KFG1G16Q2C-xEBx)
FLASH MEMORY
Page and Sector
Page and Sector
Block
Block Address
Size
Block
Block Address
Size
Address
Address
Block256
Block257
Block258
Block259
Block260
Block261
Block262
Block263
Block264
Block265
Block266
Block267
Block268
Block269
Block270
Block271
Block272
Block273
Block274
Block275
Block276
Block277
Block278
Block279
Block280
Block281
Block282
Block283
Block284
Block285
Block286
Block287
0100h
0101h
0102h
0103h
0104h
0105h
0106h
0107h
0108h
0109h
010Ah
010Bh
010Ch
010Dh
010Eh
010Fh
0110h
0111h
0112h
0113h
0114h
0115h
0116h
0117h
0118h
0119h
011Ah
011Bh
011Ch
011Dh
011Eh
011Fh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
Block288
Block289
Block290
Block291
Block292
Block293
Block294
Block295
Block296
Block297
Block298
Block299
Block300
Block301
Block302
Block303
Block304
Block305
Block306
Block307
Block308
Block309
Block310
Block311
Block312
Block313
Block314
Block315
Block316
Block317
Block318
Block319
0120h
0121h
0122h
0123h
0124h
0125h
0126h
0127h
0128h
0129h
012Ah
012Bh
012Ch
012Dh
012Eh
012Fh
0130h
0131h
0132h
0133h
0134h
0135h
0136h
0137h
0138h
0139h
013Ah
013Bh
013Ch
013Dh
013Eh
013Fh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
- 19 -
OneNAND1Gb(KFG1G16Q2C-xEBx)
FLASH MEMORY
Page and Sector
Page and Sector
Block
Block Address
Size
Block
Block Address
Size
Address
Address
Block320
Block321
Block322
Block323
Block324
Block325
Block326
Block327
Block328
Block329
Block330
Block331
Block332
Block333
Block334
Block335
Block336
Block337
Block338
Block339
Block340
Block341
Block342
Block343
Block344
Block345
Block346
Block347
Block348
Block349
Block350
Block351
0140h
0141h
0142h
0143h
0144h
0145h
0146h
0147h
0148h
0149h
014Ah
014Bh
014Ch
014Dh
014Eh
014Fh
0150h
0151h
0152h
0153h
0154h
0155h
0156h
0157h
0158h
0159h
015Ah
015Bh
015Ch
015Dh
015Eh
015Fh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
Block352
Block353
Block354
Block355
Block356
Block357
Block358
Block359
Block360
Block361
Block362
Block363
Block364
Block365
Block366
Block367
Block368
Block369
Block370
Block371
Block372
Block373
Block374
Block375
Block376
Block377
Block378
Block379
Block380
Block381
Block382
Block383
0160h
0161h
0162h
0163h
0164h
0165h
0166h
0167h
0168h
0169h
016Ah
016Bh
016Ch
016Dh
016Eh
016Fh
0170h
0171h
0172h
0173h
0174h
0175h
0176h
0177h
0178h
0179h
017Ah
017Bh
017Ch
017Dh
017Eh
017Fh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
- 20 -
OneNAND1Gb(KFG1G16Q2C-xEBx)
FLASH MEMORY
Page and Sector
Page and Sector
Block
Block Address
Size
Block
Block Address
Size
Address
Address
Block384
Block385
Block386
Block387
Block388
Block389
Block390
Block391
Block392
Block393
Block394
Block395
Block396
Block397
Block398
Block399
Block400
Block401
Block402
Block403
Block404
Block405
Block406
Block407
Block408
Block409
Block410
Block411
Block412
Block413
Block414
Block415
0180h
0181h
0182h
0183h
0184h
0185h
0186h
0187h
0188h
0189h
018Ah
018Bh
018Ch
018Dh
018Eh
018Fh
0190h
0191h
0192h
0193h
0194h
0195h
0196h
0197h
0198h
0199h
019Ah
019Bh
019Ch
019Dh
019Eh
019Fh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
Block416
Block417
Block418
Block419
Block420
Block421
Block422
Block423
Block424
Block425
Block426
Block427
Block428
Block429
Block430
Block431
Block432
Block433
Block434
Block435
Block436
Block437
Block438
Block439
Block440
Block441
Block442
Block443
Block444
Block445
Block446
Block447
01A0h
01A1h
01A2h
01A3h
01A4h
01A5h
01A6h
01A7h
01A8h
01A9h
01AAh
01ABh
01ACh
01ADh
01AEh
01AFh
01B0h
01B1h
01B2h
01B3h
01B4h
01B5h
01B6h
01B7h
01B8h
01B9h
01BAh
01BBh
01BCh
01BDh
01BEh
01BFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
- 21 -
OneNAND1Gb(KFG1G16Q2C-xEBx)
FLASH MEMORY
Page and Sector
Page and Sector
Block
Block Address
Size
Block
Block Address
Size
Address
Address
Block448
Block449
Block450
Block451
Block452
Block453
Block454
Block455
Block456
Block457
Block458
Block459
Block460
Block461
Block462
Block463
Block464
Block465
Block466
Block467
Block468
Block469
Block470
Block471
Block472
Block473
Block474
Block475
Block476
Block477
Block478
Block479
01C0h
01C1h
01C2h
01C3h
01C4h
01C5h
01C6h
01C7h
01C8h
01C9h
01CAh
01CBh
01CCh
01CDh
01CEh
01CFh
01D0h
01D1h
01D2h
01D3h
01D4h
01D5h
01D6h
01D7h
01D8h
01D9h
01DAh
01DBh
01DCh
01DDh
01DEh
01DFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
Block480
Block481
Block482
Block483
Block484
Block485
Block486
Block487
Block488
Block489
Block490
Block491
Block492
Block493
Block494
Block495
Block496
Block497
Block498
Block499
Block500
Block501
Block502
Block503
Block504
Block505
Block506
Block507
Block508
Block509
Block510
Block511
01E0h
01E1h
01E2h
01E3h
01E4h
01E5h
01E6h
01E7h
01E8h
01E9h
01EAh
01EBh
01ECh
01EDh
01EEh
01EFh
01F0h
01F1h
01F2h
01F3h
01F4h
01F5h
01F6h
01F7h
01F8h
01F9h
01FAh
01FBh
01FCh
01FDh
01FEh
01FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
- 22 -
OneNAND1Gb(KFG1G16Q2C-xEBx)
FLASH MEMORY
Page and Sector
Page and Sector
Block
Block Address
Size
Block
Block Address
Size
Address
Address
Block512
Block513
Block514
Block515
Block516
Block517
Block518
Block519
Block520
Block521
Block522
Block523
Block524
Block525
Block526
Block527
Block528
Block529
Block530
Block531
Block532
Block533
Block534
Block535
Block536
Block537
Block538
Block539
Block540
Block541
Block542
Block543
0200h
0201h
0202h
0203h
0204h
0205h
0206h
0207h
0208h
0209h
020Ah
020Bh
020Ch
020Dh
020Eh
020Fh
0210h
0211h
0212h
0213h
0214h
0215h
0216h
0217h
0218h
0219h
021Ah
021Bh
021Ch
021Dh
021Eh
021Fh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
Block544
Block545
Block546
Block547
Block548
Block549
Block550
Block551
Block552
Block553
Block554
Block555
Block556
Block557
Block558
Block559
Block560
Block561
Block562
Block563
Block564
Block565
Block566
Block567
Block568
Block569
Block570
Block571
Block572
Block573
Block574
Block575
0220h
0221h
0222h
0223h
0224h
0225h
0226h
0227h
0228h
0229h
022Ah
022Bh
022Ch
022Dh
022Eh
022Fh
0230h
0231h
0232h
0233h
0234h
0235h
0236h
0237h
0238h
0239h
023Ah
023Bh
023Ch
023Dh
023Eh
023Fh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
- 23 -
OneNAND1Gb(KFG1G16Q2C-xEBx)
FLASH MEMORY
Page and Sector
Page and Sector
Block
Block Address
Size
Block
Block Address
Size
Address
Address
Block576
Block577
Block578
Block579
Block580
Block581
Block582
Block583
Block584
Block585
Block586
Block587
Block588
Block589
Block590
Block591
Block592
Block593
Block594
Block595
Block596
Block597
Block598
Block599
Block600
Block601
Block602
Block603
Block604
Block605
Block606
Block607
0240h
0241h
0242h
0243h
0244h
0245h
0246h
0247h
0248h
0249h
024Ah
024Bh
024Ch
024Dh
024Eh
024Fh
0250h
0251h
0252h
0253h
0254h
0255h
0256h
0257h
0258h
0259h
025Ah
025Bh
025Ch
025Dh
025Eh
025Fh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
Block608
Block609
Block610
Block611
Block612
Block613
Block614
Block615
Block616
Block617
Block618
Block619
Block620
Block621
Block622
Block623
Block624
Block625
Block626
Block627
Block628
Block629
Block630
Block631
Block632
Block633
Block634
Block635
Block636
Block637
Block638
Block639
0260h
0261h
0262h
0263h
0264h
0265h
0266h
0267h
0268h
0269h
026Ah
026Bh
026Ch
026Dh
026Eh
026Fh
0270h
0271h
0272h
0273h
0274h
0275h
0276h
0277h
0278h
0279h
027Ah
027Bh
027Ch
027Dh
027Eh
027Fh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
- 24 -
OneNAND1Gb(KFG1G16Q2C-xEBx)
FLASH MEMORY
Page and Sector
Page and Sector
Block
Block Address
Size
Block
Block Address
Size
Address
Address
Block640
Block641
Block642
Block643
Block644
Block645
Block646
Block647
Block648
Block649
Block650
Block651
Block652
Block653
Block654
Block655
Block656
Block657
Block658
Block659
Block660
Block661
Block662
Block663
Block664
Block665
Block666
Block667
Block668
Block669
Block670
Block671
0280h
0281h
0282h
0283h
0284h
0285h
0286h
0287h
0288h
0289h
028Ah
028Bh
028Ch
028Dh
028Eh
028Fh
0290h
0291h
0292h
0293h
0294h
0295h
0296h
0297h
0298h
0299h
029Ah
029Bh
029Ch
029Dh
029Eh
029Fh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
Block672
Block673
Block674
Block675
Block676
Block677
Block678
Block679
Block680
Block681
Block682
Block683
Block684
Block685
Block686
Block687
Block688
Block689
Block690
Block691
Block692
Block693
Block694
Block695
Block696
Block697
Block698
Block699
Block700
Block701
Block702
Block703
02A0h
02A1h
02A2h
02A3h
02A4h
02A5h
02A6h
02A7h
02A8h
02A9h
02AAh
02ABh
02ACh
02ADh
02AEh
02AFh
02B0h
02B1h
02B2h
02B3h
02B4h
02B5h
02B6h
02B7h
02B8h
02B9h
02BAh
02BBh
02BCh
02BDh
02BEh
02BFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
- 25 -
OneNAND1Gb(KFG1G16Q2C-xEBx)
FLASH MEMORY
Page and Sector
Page and Sector
Block
Block Address
Size
Block
Block Address
Size
Address
Address
Block704
Block705
Block706
Block707
Block708
Block709
Block710
Block711
Block712
Block713
Block714
Block715
Block716
Block717
Block718
Block719
Block720
Block721
Block722
Block723
Block724
Block725
Block726
Block727
Block728
Block729
Block730
Block731
Block732
Block733
Block734
Block735
02C0h
02C1h
02C2h
02C3h
02C4h
02C5h
02C6h
02C7h
02C8h
02C9h
02CAh
02CBh
02CCh
02CDh
02CEh
02CFh
02D0h
02D1h
02D2h
02D3h
02D4h
02D5h
02D6h
02D7h
02D8h
02D9h
02DAh
02DBh
02DCh
02DDh
02DEh
02DFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
Block736
Block737
Block738
Block739
Block740
Block741
Block742
Block743
Block744
Block745
Block746
Block747
Block748
Block749
Block750
Block751
Block752
Block753
Block754
Block755
Block756
Block757
Block758
Block759
Block760
Block761
Block762
Block763
Block764
Block765
Block766
Block767
02E0h
02E1h
02E2h
02E3h
02E4h
02E5h
02E6h
02E7h
02E8h
02E9h
02EAh
02EBh
02ECh
02EDh
02EEh
02EFh
02F0h
02F1h
02F2h
02F3h
02F4h
02F5h
02F6h
02F7h
02F8h
02F9h
02FAh
02FBh
02FCh
02FDh
02FEh
02FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
- 26 -
OneNAND1Gb(KFG1G16Q2C-xEBx)
FLASH MEMORY
Page and Sector
Page and Sector
Block
Block Address
Size
Block
Block Address
Size
Address
Address
Block768
Block769
Block770
Block771
Block772
Block773
Block774
Block775
Block776
Block777
Block778
Block779
Block780
Block781
Block782
Block783
Block784
Block785
Block786
Block787
Block788
Block789
Block790
Block791
Block792
Block793
Block794
Block795
Block796
Block797
Block798
Block799
0300h
0301h
0302h
0303h
0304h
0305h
0306h
0307h
0308h
0309h
030Ah
030Bh
030Ch
030Dh
030Eh
030Fh
0310h
0311h
0312h
0313h
0314h
0315h
0316h
0317h
0318h
0319h
031Ah
031Bh
031Ch
031Dh
031Eh
031Fh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
Block800
Block801
Block802
Block803
Block804
Block805
Block806
Block807
Block808
Block809
Block810
Block811
Block812
Block813
Block814
Block815
Block816
Block817
Block818
Block819
Block820
Block821
Block822
Block823
Block824
Block825
Block826
Block827
Block828
Block829
Block830
Block831
0320h
0321h
0322h
0323h
0324h
0325h
0326h
0327h
0328h
0329h
032Ah
032Bh
032Ch
032Dh
032Eh
032Fh
0330h
0331h
0332h
0333h
0334h
0335h
0336h
0337h
0338h
0339h
033Ah
033Bh
033Ch
033Dh
033Eh
033Fh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
- 27 -
OneNAND1Gb(KFG1G16Q2C-xEBx)
FLASH MEMORY
Page and Sector
Page and Sector
Block
Block Address
Size
Block
Block Address
Size
Address
Address
Block832
Block833
Block834
Block835
Block836
Block837
Block838
Block839
Block840
Block841
Block842
Block843
Block844
Block845
Block846
Block847
Block848
Block849
Block850
Block851
Block852
Block853
Block854
Block855
Block856
Block857
Block858
Block859
Block860
Block861
Block862
Block863
0340h
0341h
0342h
0343h
0344h
0345h
0346h
0347h
0348h
0349h
034Ah
034Bh
034Ch
034Dh
034Eh
034Fh
0350h
0351h
0352h
0353h
0354h
0355h
0356h
0357h
0358h
0359h
035Ah
035Bh
035Ch
035Dh
035Eh
035Fh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
Block864
Block865
Block866
Block867
Block868
Block869
Block870
Block871
Block872
Block873
Block874
Block875
Block876
Block877
Block878
Block879
Block880
Block881
Block882
Block883
Block884
Block885
Block886
Block887
Block888
Block889
Block890
Block891
Block892
Block893
Block894
Block895
0360h
0361h
0362h
0363h
0364h
0365h
0366h
0367h
0368h
0369h
036Ah
036Bh
036Ch
036Dh
036Eh
036Fh
0370h
0371h
0372h
0373h
0374h
0375h
0376h
0377h
0378h
0379h
037Ah
037Bh
037Ch
037Dh
037Eh
037Fh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
- 28 -
OneNAND1Gb(KFG1G16Q2C-xEBx)
FLASH MEMORY
Page and Sector
Page and Sector
Block
Block Address
Size
Block
Block Address
Size
Address
Address
Block896
Block897
Block898
Block899
Block900
Block901
Block902
Block903
Block904
Block905
Block906
Block907
Block908
Block909
Block910
Block911
Block912
Block913
Block914
Block915
Block916
Block917
Block918
Block919
Block920
Block921
Block922
Block923
Block924
Block925
Block926
Block927
0380h
0381h
0382h
0383h
0384h
0385h
0386h
0387h
0388h
0389h
038Ah
038Bh
038Ch
038Dh
038Eh
038Fh
0390h
0391h
0392h
0393h
0394h
0395h
0396h
0397h
0398h
0399h
039Ah
039Bh
039Ch
039Dh
039Eh
039Fh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
Block928
Block929
Block930
Block931
Block932
Block933
Block934
Block935
Block936
Block937
Block938
Block939
Block940
Block941
Block942
Block943
Block944
Block945
Block946
Block947
Block948
Block949
Block950
Block951
Block952
Block953
Block954
Block955
Block956
Block957
Block958
Block959
03A0h
03A1h
03A2h
03A3h
03A4h
03A5h
03A6h
03A7h
03A8h
03A9h
03AAh
03ABh
03ACh
03ADh
03AEh
03AFh
03B0h
03B1h
03B2h
03B3h
03B4h
03B5h
03B6h
03B7h
03B8h
03B9h
03BAh
03BBh
03BCh
03BDh
03BEh
03BFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
- 29 -
OneNAND1Gb(KFG1G16Q2C-xEBx)
FLASH MEMORY
Page and Sector
Page and Sector
Block
Block Address
Size
Block
Block Address
Size
Address
Address
Block960
Block961
Block962
Block963
Block964
Block965
Block966
Block967
Block968
Block969
Block970
Block971
Block972
Block973
Block974
Block975
Block976
Block977
Block978
Block979
Block980
Block981
Block982
Block983
Block984
Block985
Block986
Block987
Block988
Block989
Block990
Block991
03C0h
03C1h
03C2h
03C3h
03C4h
03C5h
03C6h
03C7h
03C8h
03C9h
03CAh
03CBh
03CCh
03CDh
03CEh
03CFh
03D0h
03D1h
03D2h
03D3h
03D4h
03D5h
03D6h
03D7h
03D8h
03D9h
03DAh
03DBh
03DCh
03DDh
03DEh
03DFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
Block992
Block993
03E0h
03E1h
03E2h
03E3h
03E4h
03E5h
03E6h
03E7h
03E8h
03E9h
03EAh
03EBh
03ECh
03EDh
03EEh
03EFh
03F0h
03F1h
03F2h
03F3h
03F4h
03F5h
03F6h
03F7h
03F8h
03F9h
03FAh
03FBh
03FCh
03FDh
03FEh
03FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
0000h~00FFh
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
128KB
Block994
Block995
Block996
Block997
Block998
Block999
Block1000
Block1001
Block1002
Block1003
Block1004
Block1005
Block1006
Block1007
Block1008
Block1009
Block1010
Block1011
Block1012
Block1013
Block1014
Block1015
Block1016
Block1017
Block1018
Block1019
Block1020
Block1021
Block1022
Block1023
- 30 -
OneNAND1Gb(KFG1G16Q2C-xEBx)
FLASH MEMORY
2.7.2 Internal Memory Spare Area Assignment
The figure below shows the assignment of the spare area in the Internal Memory NAND Array.
Spare Spare Spare Spare
Main area Main area Main area Main area area area area area
256W 256W 256W 256W 8W 8W 8W 8W
ECCm ECCm ECCm ECCs ECCs
Note1 Note1 Note2 Note2 Note2 Note3 Note3 Note3
Note3 Note4 Note4
1st
2nd
3rd
1st
2nd
LSB
MSB
LSB MSB LSB MSB LSB MSB LSB MSB LSB MSB LSB MSB LSB MSB LSB MSB
1st W
2nd
W
3rd W
4th W
5th W
6th W
7th W
8th W
Spare Area Assignment in the Internal Memory NAND Array Information
Word
Byte
LSB
MSB
LSB
MSB
LSB
MSB
LSB
MSB
Note
Description
1
1
Invalid Block information in 1st and 2nd page of an invalid block
2
3
4
2
3
Managed by internal ECC logic for Logical Sector Number data
Reserved for future use
Dedicated to internal ECC logic. Read Only.
ECCm 1st for main area data
LSB
MSB
LSB
MSB
LSB
5
6
Dedicated to internal ECC logic. Read Only.
ECCm 2nd for main area data
Dedicated to internal ECC logic. Read Only.
ECCm 3rd for main area data
Dedicated to internal ECC logic. Read Only.
ECCs 1st for 2nd word of spare area data
Dedicated to internal ECC logic. Read Only.
ECCs 2nd for 3rd word of spare area data
7
8
MSB
LSB
MSB
3
4
Reserved for future use
Available to the user (note 5)
NOTE 5 :
For all blocks, 8th word is available to the user.
However,in case of OTP Block, 8th word of sector 0, page 0 is reserved as OTP Locking Bit area.
Therefore, in case of OTP Block, user usage on this area is prohibited.
- 31 -
OneNAND1Gb(KFG1G16Q2C-xEBx)
FLASH MEMORY
2.7.3 External Memory (BufferRAM) Address Map
The following table shows the External Memory address map in Word and Byte Order.
Note that the data output is unknown while host reads a register bit of reserved area.
Address
(word order)
Address
(byte order)
Size
(total 128KB)
Division
Usage
Description
0000h~00FFh
0100h~01FFh
0200h~02FFh
0300h~03FFh
0400h~04FFh
0500h~05FFh
0600h~06FFh
0700h~07FFh
0800h~08FFh
0900h~09FFh
0A00h~7FFFh
8000h~8007h
8008h~800Fh
8010h~8017h
8018h~801Fh
8020h~8027h
8028h~802Fh
8030h~8037h
8038h~803Fh
8040h~8047h
8048h~804Fh
8050h~8FFFh
00000h~001FEh
00200h~003FEh
00400h~005FEh
00600h~007FEh
00800h~009FEh
00A00h~00BFEh
00C00h~00DFEh
00E00h~00FFEh
01000h~011FEh
01200h~013FEh
01400h~0FFFEh
10000h~1000Eh
10010h~1001Eh
10020h~1002Eh
10030h~1003Eh
10040h~1004Eh
10050h~1005Eh
10060h~1006Eh
10070h~1007Eh
10080h~1008Eh
10090h~1009Eh
100A0h~11FFEh
512B
512B
512B
512B
512B
512B
512B
512B
512B
512B
59K
BootM 0
BootM 1
BootRAM Main sector0
BootRAM Main sector1
1KB
R
DataM 0_0 DataRAM Main page0/sector0
DataM 0_1 DataRAM Main page0/sector1
DataM 0_2 DataRAM Main page0/sector2
DataM 0_3 DataRAM Main page0/sector3
DataM 1_0 DataRAM Main page1/sector0
DataM 1_1 DataRAM Main page1/sector1
DataM 1_2 DataRAM Main page1/sector2
DataM 1_3 DataRAM Main page1/sector3
Reserved Reserved
Main area
(64KB)
4KB
R/W
59K
32B
-
16B
BootS 0
BootS 1
BootRAM Spare sector0
BootRAM Spare sector1
R
16B
16B
DataS 0_0 DataRAM Spare page0/sector0
DataS 0_1 DataRAM Spare page0/sector1
DataS 0_2 DataRAM Spare page0/sector2
DataS 0_3 DataRAM Spare page0/sector3
DataS 1_0 DataRAM Spare page1/sector0
DataS 1_1 DataRAM Spare page1/sector1
DataS 1_2 DataRAM Spare page1/sector2
DataS 1_3 DataRAM Spare page1/sector3
Reserved Reserved
16B
16B
Spare area
(8KB)
16B
128B
R/W
16B
16B
16B
16B
8032B
8032B
24KB
-
-
Reserved
(24KB)
9000h~BFFFh
C000h~CFFFh
D000h~EFFFh
F000h~FFFFh
12000h~17FFEh
18000h~19FFEh
1A000h~1DFFEh
1E000h~1FFFEh
24KB
8KB
Reserved Reserved
Reserved Reserved
Reserved Reserved
Reserved
(8KB)
8KB
16KB
8KB
-
-
Reserved
(16KB)
16KB
8KB
Registers
(8KB)
R or R/W Registers Registers
- 32 -
OneNAND1Gb(KFG1G16Q2C-xEBx)
FLASH MEMORY
2.7.4 External Memory Map Detail Information
The tables below show Word Order Address Map information for the BootRAM and DataRAM main and spare areas.
• BootRAM(Main area)
-0000h~01FFh: 2(sector) x 512byte(NAND main area) = 1KB
0000h~00FFh(512B)
BootM 0
0100h~01FFh(512B)
BootM 1
(sector 0 of page 0)
(sector 1 of page 0)
• DataRAM(Main area)
-0200h~09FFh: 8(sector) x 512byte(NAND main area) = 4KB
0200h~02FFh(512B)
DataM 0_0
0300h~03FFh(512B)
DataM 0_1
0400h~04FFh(512B)
0500h~05FFh(512B)
DataM 0_3
DataM 0_2
(sector 0 of page 0)
(sector 1 of page 0)
(sector 2 of page 0)
(sector 3 of page 0)
0600h~06FFh(512B)
DataM 1_0
0700h~07FFh(512B)
DataM 1_1
0800h~08FFh(512B)
DataM 1_2
0900h~09FFh(512B)
DataM 1_3
(sector 0 of page 1)
(sector 1 of page 1)
(sector 2 of page 1)
(sector 3 of page 1)
• BootRAM(Spare area)
-8000h~800Fh: 2(sector) x 16byte(NAND spare area) = 32B
8000h~8007h(16B)
BootS 0
8008h~800Fh(16B)
BootS 1
(sector 0 of page 0)
(sector 1 of page 0)
• DataRAM(Spare area)
-8010h~804Fh: 8(sector) x 16byte(NAND spare area) = 128B
8010h~8017h(16B)
DataS 0_0
8018h~801Fh(16B)
DataS 0_1
8020h~8027h(16B)
8028h~802Fh(16B)
DataS 0_3
DataS 0_2
(sector 0 of page 0)
(sector 1 of page 0)
(sector 2 of page 0)
(sector 3 of page 0)
8030h~8037h(16B)
DataS 1_0
8038h~803Fh(16B)
DataS 1_1
8040h~8047h(16B)
DataS 1_2
8048h~804Fh(16B)
DataS 1_3
(sector 0 of page 1)
(sector 1 of page 1)
(sector 2 of page 1)
(sector 3 of page 1)
*NAND Flash array consists of 2KB page size and 128KB block size.
- 33 -
OneNAND1Gb(KFG1G16Q2C-xEBx)
FLASH MEMORY
2.7.5 External Memory Spare Area Assignment
Equivalent to 1word of NAND Flash
Word
Address
Byte
Address
Buf.
F
E
D
C
B
A
9
8
7
6
5
4
3
2
1
0
8000h
8001h
8002h
8003h
8004h
8005h
8006h
8007h
8008h
8009h
800Ah
800Bh
800Ch
800Dh
800Eh
800Fh
8010h
8011h
8012h
8013h
8014h
8015h
8016h
8017h
8018h
8019h
801Ah
801Bh
801Ch
801Dh
801Eh
801Fh
10000h
10002h
10004h
10006h
10008h
1000Ah
1000Ch
1000Eh
10010h
10012h
10014h
10016h
10018h
1001Ah
1001Ch
1001Eh
10020h
10022h
10024h
10026h
10028h
1002Ah
1002Ch
1002Eh
10030h
10032h
10034h
10036h
10038h
1003Ah
1003Ch
1003Eh
BI
Managed by Internal ECC logic
Reserved for the future use Managed by Internal ECC logic
Reserved for the current and future use
BootS 0
ECC Code for Main area data (2nd)
ECC Code for Spare area data (1st)
FFh(Reserved for the future use)
ECC Code for Main area data (1st)
ECC Code for Main area data (3rd)
ECC Code for Spare area data (2nd)
Free Usage
BI
Managed by Internal ECC logic
Reserved for the future use Managed by Internal ECC logic
Reserved for the current and future use
BootS 1
ECC Code for Main area data (2nd)
ECC Code for Main area data (1st)
ECC Code for Main area data (3rd)
ECC Code for Spare area data (2nd)
ECC Code for Spare area data (1st)
FFh(Reserved for the future use)
Free Usage
BI
Managed by Internal ECC logic
Reserved for the future use Managed by Internal ECC logic
Reserved for the current and future use
DataS
0_0
ECC Code for Main area data (2nd)
ECC Code for Main area data (1st)
ECC Code for Main area data (3rd)
ECC Code for Spare area data (2nd)
ECC Code for Spare area data (1st)
FFh(Reserved for the future use)
Free Usage
BI
Managed by Internal ECC logic
Reserved for the future use Managed by Internal ECC logic
Reserved for the current and future use
DataS
0_1
ECC Code for Main area data (2nd)
ECC Code for Main area data (1st)
ECC Code for Main area data (3rd)
ECC Code for Spare area data (2nd)
ECC Code for Spare area data (1st)
FFh(Reserved for the future use)
Free Usage
- 34 -
OneNAND1Gb(KFG1G16Q2C-xEBx)
FLASH MEMORY
Word
Address
Byte
Address
Buf.
F
E
D
C
B
A
9
8
7
6
5
4
3
2
1
8020h
8021h
8022h
8023h
8024h
8025h
8026h
8027h
8028h
8029h
802Ah
802Bh
802Ch
802Dh
802Eh
802Fh
8030h
8031h
8032h
8033h
8034h
8035h
8036h
8037h
8038h
8039h
803Ah
803Bh
803Ch
803Dh
803Eh
803Fh
8040h
8041h
8042h
8043h
8044h
8045h
8046h
8047h
10040h
10042h
10044h
10046h
10048h
1004Ah
1004Ch
1004Eh
10050h
10052h
10054h
10056h
10058h
1005Ah
1005Ch
1005Eh
10060h
10062h
10064h
10066h
10068h
1006Ah
1006Ch
1006Eh
10070h
10072h
10074h
10076h
10078h
1007Ah
1007Ch
1007Eh
10080h
10082h
10084h
10086h
10088h
1008Ah
1008Ch
1008Eh
BI
Managed by Internal ECC logic
Reserved for the future use
Managed by Internal ECC logic
Reserved for the current and future use
DataS 0_2
ECC Code for Main area data (2nd)
ECC Code for Spare area data (1st)
Reserved for the future use
ECC Code for Main area data (1st)
ECC Code for Main area data (3rd)
ECC Code for Spare area data (2nd)
Free Usage
BI
Managed by Internal ECC logic
Reserved for the future use Managed by Internal ECC logic
Reserved for the current and future use
DataS 0_3
DataS 1_0
DataS 1_1
DataS 1_2
ECC Code for Main area data (2nd)
ECC Code for Main area data (1st)
ECC Code for Main area data (3rd)
ECC Code for Spare area data (2nd)
ECC Code for Spare area data (1st)
Reserved for the future use
Free Usage
BI
Managed by Internal ECC logic
Reserved for the future use Managed by Internal ECC logic
Reserved for the current and future use
ECC Code for Main area data (2nd)
ECC Code for Main area data (1st)
ECC Code for Main area data (3rd)
ECC Code for Spare area data (2nd)
ECC Code for Spare area data (1st)
Reserved for the future use
Free Usage
BI
Managed by Internal ECC logic
Reserved for the future use Managed by Internal ECC logic
Reserved for the current and future use
ECC Code for Main area data (2nd)
ECC Code for Main area data (1st)
ECC Code for Main area data (3rd)
ECC Code for Spare area data (2nd)
ECC Code for Spare area data (1st)
Reserved for the future use
Free Usage
BI
Managed by Internal ECC logic
Reserved for the future use Managed by Internal ECC logic
Reserved for the current and future use
ECC Code for Main area data (2nd)
ECC Code for Main area data (1st)
ECC Code for Main area data (3rd)
ECC Code for Spare area data (2nd)
ECC Code for Spare area data (1st)
Reserved for the future use
Free Usage
- 35 -
OneNAND1Gb(KFG1G16Q2C-xEBx)
FLASH MEMORY
Equivalent to 1word of NAND Flash
Word
Address Address
Byte
Buf.
F
E
D
C
B
A
9
8
7
6
5
4
3
2
1
0
8048h
8049h
804Ah
804Bh
804Ch
804Dh
804Eh
804Fh
10090h
10092h
10094h
10096h
10098h
1009Ah
1009Ch
1009Eh
BI
Managed by Internal ECC logic
Reserved for the future use Managed by Internal ECC logic
Reserved for the current and future use
DataS 1_3
ECC Code for Main area data (2nd)
ECC Code for Spare area data (1st)
Reserved for the future use
ECC Code for Main area data (1st)
ECC Code for Main area data (3rd)
ECC Code for Spare area data (2nd)
Free Usage
NOTE :
- BI: Bad block Information
>Host can use complete spare area except BI and ECC code area. For example,
Host can write data to Spare area buffer except for the area controlled by ECC logic at program operation.
>In case of ’with ECC’ mode, OneNAND automatically generates ECC code for both main and spare data of memory during program operation,
but does not update ECC code to spare bufferRAM during load operation.
>When loading/programming spare area, spare area BufferRAM address(BSA) and BufferRAM sector count(BSC) is chosen via Start buffer register
as it is.
- 36 -
OneNAND1Gb(KFG1G16Q2C-xEBx)
FLASH MEMORY
2.8 Registers
Section 2.8 of this specification provides information about the OneNAND registers.
2.8.1 Register Address Map
This map describes the register addresses, register name, register description, and host accessibility.
Address
(word order)
Address
(byte order)
Host
Access
Name
Description
Manufacturer identification
F000h
F001h
F002h
F003h
F004h
1E000h
1E002h
1E004h
1E006h
1E008h
Manufacturer ID
Device ID
R
R
R
R
R
Device identification
N/A
Version ID
Data Buffer size
Boot Buffer size
Data buffer size
Boot buffer size
Amount of
buffers
F005h
1E00Ah
R
Amount of data/boot buffers
F006h
F007h~F0FFh
F100h
1E00Ch
1E00Eh~1E1FEh
1E200h
Technology
Reserved
R
-
Info about technology
Reserved for user
NAND Flash Block Address
N/A
Start address 1
Start address 2
Start address 3
R/W
-
F101h
1E202h
F102h
1E204h
R/W
Destination Block address for Copy back program
Destination Page & Sector address for Copy
back program
F103h
1E206h
Start address 4
R/W
F104h
F105h
1E208h
1E20Ah
Start address 5
Start address 6
Start address 7
Start address 8
Reserved
R/W
Number of Page in Synchronous Burst Block Read
-
N/A
F106h
1E20Ch
-
R/W
-
N/A
F107h
1E20Eh
NAND Flash Page & Sector address
Reserved for user
F108h~F1FFh
1E210h~1E3FEh
Buffer Number for the page data transfer to/from the mem-
ory and the start Buffer Address
The meaning is with which buffer to start and how many
buffers to use for the data transfer
F200h
1E400h
Start Buffer
R/W
F201h~F207h
F208h~F21Fh
F220h
1E402h~1E40Eh
1E410h~1E43Eh
1E440h
Reserved
Reserved
Command
-
-
Reserved for user
Reserved for vendor specific purposes
Host control and memory operation commands
R/W
System
Configuration 1
F221h
F222h
1E442h
1E444h
R, R/W
-
memory and Host Interface Configuration
N/A
System
Configuration 2
F223h~F22Fh
F230h~F23Fh
F240h
1E446h~1E45Eh
1E460h~1E47Eh
1E480h
Reserved
Reserved
-
Reserved for user
-
R
Reserved for vendor specific purposes
Controller Status and result of memory operation
Memory Command Completion Interrupt Status
Reserved for user
Controller Status
Interrupt
F241h
1E482h
R/W
-
F242h~F24Bh
1E484h~1E496h
Reserved
Start
Block Address
F24Ch
1E498h
R/W
Start memory block address in Write Protection mode
- 37 -
OneNAND1Gb(KFG1G16Q2C-xEBx)
FLASH MEMORY
Address
(word order)
Address
(byte order)
Host
Access
Name
Description
F24Dh
F24Eh
1E49Ah
1E49Ch
Reserved
-
R
-
Reserved for user
Write Protection
Status
Current memory Write Protection status
(unlocked/locked/tight-locked)
F24Fh~FEFFh
FF00h
1E49Eh~1FDFEh
1FE00h
Reserved
Reserved for user
ECC Status
Register
R
ECC status of sector
ECC Result of
main area data
ECC error position of Main area data error for first selected
Sector
FF01h
FF02h
FF03h
FF04h
FF05h
FF06h
FF07h
1FE02h
1FE04h
1FE06h
1FE08h
1FE0Ah
1FE0Ch
1FE0Eh
R
R
R
R
R
R
R
ECC Result of
spare area data
ECC error position of Spare area data error for first
selected Sector
ECC Result of
main area data
ECC error position of Main area data error for second
selected Sector
ECC Result of
spare area data
ECC error position of Spare area data error for second
selected Sector
ECC Result of
main area data
ECC error position of Main area data error for third
selected Sector
ECC Result of
spare area data
ECC error position of Spare area data error for third
selected Sector
ECC Result of
main area data
ECC error position of Main area data error for fourth
selected Sector
ECC Result of
spare area data
ECC error position of Spare area data error for fourth
selected Sector
FF08h
1FE10h
R
-
FF09h~FFFFh
1FE12h~1FFFEh
Reserved
Reserved for vendor specific purposes
2.8.2 Manufacturer ID Register F000h (R)
This Read register describes the manufacturer's identification.
Samsung Electronics Company manufacturer's ID is 00ECh.
F000h, default = 00ECh
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
ManufID
- 38 -
OneNAND1Gb(KFG1G16Q2C-xEBx)
FLASH MEMORY
2.8.3 Device ID Register F001h (R)
This Read register describes the device.
F001h, see table for default.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
DeviceID
Device Identification
Register information
DeviceID [1:0] Vcc
Description
00 = 1.8V, 01/10/11 = reserved
0 = Muxed, 1 = Demuxed
0 = Single, 1 = DDP
DeviceID [2] Muxed/Demuxed
DeviceID [3] Single/DDP
DeviceID [7:4] Density
0000 = 128Mb, 0001 = 256Mb, 0010 = 512Mb, 0011 = 1Gb, 0100 = 2Gb, 0101=4Gb
0 = Bottom Boot
DeviceID [8] Bottom Boot
Device ID Default
Device
DeviceID[15:0]
KFG1G16Q2C
0034h
- 39 -
OneNAND1Gb(KFG1G16Q2C-xEBx)
FLASH MEMORY
2.8.4 Version ID Register F002h
This Register is reserved for internal use.
2.8.5 Data Buffer Size Register F003h (R)
This Read register describes the size of the Data Buffer.
F003h, default = 0800h
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
DataBufSize
Data Buffer Size Information
Register information
Description
Total data buffer size in Words equal to 2 buffers of 1024 Words each
(2 x 1024 = 211) in the memory interface
DataBufSize
- 40 -
OneNAND1Gb(KFG1G16Q2C-xEBx)
FLASH MEMORY
2.8.6 Boot Buffer Size Register F004h (R)
This Read register describes the size of the Boot Buffer.
F004h, default = 0200h
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
BootBufSize
Register Information
Description
Total boot buffer size in Words equal to 1 buffer of 512 Words
(1 x 512 = 29) in the memory interface
BootBufSize
2.8.7 Number of Buffers Register F005h (R)
This Read register describes the number of each Buffer.
F005h, default = 0201h
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
DataBufAmount
BootBufAmount
Number of Buffers Information
Register Information
DataBufAmount
Description
The number of data buffers = 2 (2N, N=1)
The number of boot buffers = 1 (2N, N=0)
BootBufAmount
2.8.8 Technology Register F006h (R)
This Read register describes the internal NAND array technology.
F006h, default = 0000h
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Tech
Technology Information
Technology
Register Setting
0000h
NAND SLC
NAND MLC
0001h
Reserved
0002h ~ FFFFh
- 41 -
OneNAND1Gb(KFG1G16Q2C-xEBx)
FLASH MEMORY
2.8.9 Start Address1 Register F100h (R/W)
This Read/Write register describes the NAND Flash block address which will be loaded, programmed, or erased.
F100h, default = 0000h
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reserved(000000)
FBA
Device
Number of Block
FBA
1Gb
1024
FBA[9:0]
Start Address1 Information
Register Information
FBA
Description
NAND Flash Block Address
2.8.10 Start Address2 Register F101h (R/W)
This register is reserved for future use.
- 42 -
OneNAND1Gb(KFG1G16Q2C-xEBx)
FLASH MEMORY
2.8.11 Start Address3 Register F102h (R/W)
This Read/Write register describes the NAND Flash destination block address which will be copy back programmed. Also, this register indi-
cates the block address for the first page to be read in Cache Read Operation.
F102h, default = 0000h
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reserved(000000)
FCBA
Device
Number of Block
FBA
1Gb
1024
FCBA[9:0]
Start Address3 Information
Register Information
Description
NAND Flash Copy Back Block Address &
Block Address for the first page to be read in Cache Read Operation
FCBA
2.8.12 Start Address4 Register F103h (R/W)
This Read/Write register describes the NAND Flash destination page address in a block and the NAND Flash destination sector address in a
page for copy back programming. Also, this register describes the first page and sector address to be loaded in Cache Read Operation.
F103h, default = 0000h
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
FCSA1)
Reserved(00000000)
FCPA
NOTE :
1) In case of ’Cache Read Operation’, FCSA has to be set to 00.
Start Address4 Information
Item
Description
Default Value
Range
NAND Flash Copy Back Page Address &
First Page Address of Cache Read
000000 ~ 111111,
6 bits for 64 pages
FCPA
000000
NAND Flash Copy Back Sector Address &
First Sector Address of Cache Read
00 ~ 11,
2 bits for 4 sectors
FCSA
00
- 43 -
OneNAND1Gb(KFG1G16Q2C-xEBx)
FLASH MEMORY
2.8.13 Start Address5 Register F104h (R/W)
This Read/Write register describes the number of page in Synchronous Burst Block Read.
F104h, default = 0000h
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reserved(0000000000)
FPC
Flash Page Count (FPC) Information
FPC
Number of Page
64 page
3 page
000000 (Default)
000011
000100
4 page
..
..
111111
63 page
NOTE :
Synchronous Burst Block Read are NOT able to be perforformed with 1 or 2pages.
2.8.14 Start Address6 Register F105h
This register is reserved for future use.
2.8.15 Start Address7 Register F106h
This register is reserved for future use.
2.8.16 Start Address8 Register F107h (R/W)
This Read/Write register describes the NAND Flash start page address in a block for a page load, copy back program, or program operation
and the NAND Flash start sector address in a page for a load, copy back program, or program operation.
F107h, default = 0000h
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
FSA1)
Reserved (00000000)
FPA
NOTE :
1) In case of ’ Synchronous Burst Block Read’, ’Cache Read Operation’, FSA has to be set to 00.
Start Address8 Information
Item
Description
Default Value
Range
000000 ~ 111111,
6 bits for 64 pages
FPA
NAND Flash Page Address
000000
00 ~ 11,
2 bits for 4 sectors
FSA
NAND Flash Sector Address
00
- 44 -
OneNAND1Gb(KFG1G16Q2C-xEBx)
FLASH MEMORY
2.8.17 Start Buffer Register F200h (R/W)
This Read/Write register describes the BufferRAM Sector Count (BSC) and BufferRAM Sector Address (BSA).
The BufferRAM Sector Count (BSC) field specifies the number of sectors to be loaded, programmed, or copy back programmed. At 00 value
(the default value), the number of sector is "4". If the internal RAM buffer reaches its maximum value of 11, it will count up to 0 value to meet
the BSC value. For example, if BSA = 1101, BSC = 00, then the selected BufferRAM will count up from '1101 → 1110 → 1111 → 1100'.
The BufferRAM Sector Address (BSA) is the sector 0~3 address in the internal BootRAM and DataRAM where data is placed.
F200h, default = 0000h
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reserved(0000)
BSA
Reserved(000000)
BSC
NOTE :
In case of ’Cache Read’, BSA has to be set to 1000, and BSC has to be set to 00.
In case of ’Synchronous Burst Block Read’, BSA has to be set to 1000 or 1100, and BSC has to be set to 00.
Start Address8 Information
Item
Description
Selection bit between BootRAM and DataRAM
BSA[3]
BSA[2]
Selection bit between DataRAM0 and DataRAM1
Selection bit between Sector0 and Sector1 in the internal BootRAM
Selection bit between Sector0 to Sector3 in the internal DataRAM
BSA[1:0]
Spare area data
16B
Main area data
512B
BSA
0000
0001
BootRAM 0
BootRAM 1
Sector: (512 + 16) Byte
BootRAM
DataRAM 0_0
DataRAM 0_1
DataRAM 0_2
DataRAM 0_3
1000
1001
1010
1011
DataRAM0
DataRAM1
DataRAM 1_0
DataRAM 1_1
DataRAM 1_2
DataRAM 1_3
1100
1101
1110
1111
BSC
01
Number of Sectors
1 sector
10
2 sector
11
3 sector
00
4 sector
- 45 -
OneNAND1Gb(KFG1G16Q2C-xEBx)
FLASH MEMORY
2.8.18 Command Register F220h (R/W)
Command can be issued by two following methods, and user may select one way or the other to issue appropriate command;
1. Write command into Command Register when INT is at ready state. INT will automatically turn to busy state as command is issued. Once
the desired operation is completed, INT will go back ready state.
2. Write 0000h to INT bit of Interrupt Status Register, and then write command into Command Register. Once the desired operation is com-
pleted, INT will go back to ready state.
(00F0h and 00F3h may be accepted during busy state of some operations. Refer to the rightmost column of the command register table
below.)
F220h, default = 0000h
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Command
Acceptable
command
CMD
Operation
during busy
0000h
0013h
0080h
001Ah
001Bh
0023h
002Ah
002Ch
0027h
0071h
000Eh
000Ch
000Ah
0094h
0095h
00B0h
0030h
00F0h
00F3h
0065h
Load single/multiple sector data unit into buffer
Load single/multiple spare sector into buffer
00F0h, 00F3h
00F0h, 00F3h
00F0h, 00F3h
00F0h, 00F3h
00F0h, 00F3h
00F0h, 00F3h
00F0h, 00F3h
00F0h, 00F3h
00F0h, 00F3h
00F0h, 00F3h
00F0h, 00F3h
00F0h, 00F3h
00F0h, 00F3h
00F0h, 00F3h
00F0h, 00F3h
00F0h, 00F3h
00F0h, 00F3h
-
Program single/multiple sector data unit from buffer1)
Program single/multiple spare data unit from buffer
Copy back Program operation
Unlock NAND array a block
Lock NAND array a block
Lock-tight NAND array a block
All Block Unlock 2)
Erase Verify Read
Cache Read
Finish Cache Read
Synchronous Burst Block Read
Block Erase
Multi-Block Erase
Erase Suspend
Erase Resume
Reset NAND Flash Core
Reset OneNAND 3)
OTP Access
-
00F0h, 00F3h
NOTE :
1) 0080h programs both main and spare area, while 001Ah programs only spare area. Refer to chapter 5.9 for NOP limits in issuing these commands. When using
0080h and 001Ah command, Read-only part in spare area must be masked by FF. (Refer to chapter 2.7.2)
2) If any blocks are changed to locked-tight state, the all block unlock command will fail. In order to use all block unlock command again, a cold reset is needed.
3) ’Reset OneNAND’(=Hot reset) command makes the registers and NAND Flash core into default state.
- 46 -
OneNAND1Gb(KFG1G16Q2C-xEBx)
FLASH MEMORY
2.8.18.1 Two Methods to Clear Interrupt Register in Command Input
To clear Interrupt Register in command input, user may select one from either following methods.
First method is to turn INT to low by manually writing 0000h to INT bit of Interrupt Register. 1)
Second method is input command while INT is high, and the device will automatically turn INT to low.1)
(Second method is equivalent with method used in general NAND Flash)
User may choose the desirable method to clear Interrupt Register.
Method 1: Manually set INT=0 before writing command into Command Register: Manual INT Mode
(1) Clear Interrupt Register (F241h) by writing 0000h into INT bit of Interrupt Register. This operation will make INT pin turn low. 1)
(2) Write command into Command Register. This will make the device to perform the designated operation.
(3) INT pin will turn back to high once the operation is completed. 1)
INT pin1)
INT bit
Write command into
Command Register
Write 0 into
INT bit of
INT will automatically turn to high
when designated operation is completed.
Interrupt Register
NOTE 1) INT pin polarity is based on ’IOBE=1 and INT pol=1 (default)’ setting
Method 2: Write command into Command Register at INT ready state: Auto INT Mode
(1) Write command into Command Register. This will automatically turn INT from high to low. 1)
(2) INT pin will turn back to high once the operation is completed. 1)
INT pin1)
INT bit
INT will automatically
turn to Busy State
Write command into
Command Register
INT will automatically turn back to ready state
when designated operation in completed.
NOTE 1) INT pin polarity is based on ’IOBE=1 and INT pol=1 (default)’ setting
- 47 -
OneNAND1Gb(KFG1G16Q2C-xEBx)
FLASH MEMORY
2.8.19 System Configuration 1 Register F221h (R, R/W)
This Read/Write register describes the system configuration.
F221h, default =40C0h
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
R/W
R/W
R
RDY
pol
INT
pol
RDY Reserv
Conf ed
RM
BRWL
BL
ECC
IOBE
HF
WM
BWPS
Read Mode (RM)
RM
Read Mode
0
1
Asynchronous read(default)
Synchronous read
Read Mode Information[15]
Item
Definition
Description
Selects between asynchronous read mode and
synchronous read mode
RM
Read Mode
Burst Read Write Latency (BRWL)
BRWL
Latency Cycles (Read/Write)
under 40MHz
(HF=0)
40MHz~66MHz
(HF=0)
over 66MHz
(HF=1)
000~010
011
Reserved
3(up to 40MHz. min)
3(N/A)
3(N/A)
4(N/A)
5(N/A)
6(min.)
7
100 (default)
101
4
5
6
7
4(min.)
5
6
7
110
111
* Default value of BRWL and HF value is BRWL=4, HF=0.
For host frequency over 66MHz, BRWL should be 6 or 7 while HF is 1.
For host frequency range of 40MHz~66MHz, BRWL should be set to 4~7 while HF is 0.
For host frequency under 40MHz, BRWL should be set to 3~7 while HF is 0.
Burst Read Write Latency (BRWL) Information[14:12]
Item
Definition
Description
Burst Read Latency /
Burst Write Latency
Specifies the access latency in the burst
read / write transfer for the initial access
BRWL
- 48 -
OneNAND1Gb(KFG1G16Q2C-xEBx)
FLASH MEMORY
Burst Length (BL)
Hosts must follow burst length set by BL when reading data in synchronous burst read.
BL
000
Burst Length(Main)
Burst Length(Spare)
Continuous(default)
4 words
001
010
8 words
011
16 words
100
32 words
N/A
N/A
101
1K words (Block Read Only)
110~111
Reserved
NOTE :
1) For normal synchronous burst read, setting BL=000 (continuous) will read 1K words depending on the number of clocks. In using Synchronous Burst Block
Read, setting BL=000 (continuous) will read the amount of data in a block set by number of page register.
2) Even in using Synchronous Burst Block Read, it is possible to use above burst length by setting BL register by following the above table.
Burst Length (BL) Information[11:9]
Item
Definition
Description
Specifies the size of the burst length during a synchronous
linear burst read and wrap around. And also burst length during a
synchronous linear burst write
BL
Burst Length
Error Correction Code (ECC) Information[8]
Item
Definition
Error Correction Code Operation
Description
0 = with correction (default)
1 = without correction (bypassed)
ECC
RDY Polarity (RDYpol) Information[7]
Item
Definition
Description
1 = high for ready (default)
0 = low for ready
RDYpol
RDY signal polarity
INT Polarity (INTpol) Information[6]
INTpol
INT bit of Interrupt Status Register
INT Pin output
0 (busy)
1 (ready)
0 (busy)
1 (ready)
High
Low
Low
High
0
1 (default)
- 49 -
OneNAND1Gb(KFG1G16Q2C-xEBx)
FLASH MEMORY
I/O Buffer Enable (IOBE)
IOBE is the I/O Buffer Enable for the INT and RDY signals. At startup, INT and RDY outputs are High-Z. Bits 6 and 7 become valid after
IOBE is set to "1". IOBE can be reset by a Cold Reset or by writing "0" to bit 5 of System Configuration1 Register.
I/O Buffer Enable Information[5]
Item
Definition
Description
I/O Buffer Enable for INT and
RDY signals
0 = disable (default)
1 = enable
IOBE
RDY Configuration (RDY conf)
RDY Configuration Information[4]
Item
Definition
Description
0=active one clock before valid data(default)
1=active with valid data
RDY conf
RDY configuration
HF Enable (HF)
HF
0
Description
HF Disable (default, 66Mhz and under)
HF Enable (over 66MHz)
1
HF Information[2]
Item
Definition
Description
Selects between HF Disable and
HF Enable
HF
High Frequency
- 50 -
OneNAND1Gb(KFG1G16Q2C-xEBx)
FLASH MEMORY
Write Mode (WM)
WM
0
Write Mode
Asynchronous Write(default)
Synchronous Write
1
Write Mode Information[1]
Item
Definition
Description
Selects between asynchronous Write Mode and
synchronousWrite Mode
WM
Write Mode
MRS(Mode Register Setting) Description
RM
0
WM
0
Mode Description
Asynch Read & Asynch Write (Default)
1
0
Sync Read & Asynch Write
Sync Read & Synch Write
1
1
Reserved 1)
Other Case
NOTE :
1) Operation not guaranteed for cases not defined in above table.
Boot Buffer Write Protect Status(BWPS)
Boot Buffer Write Protect Status Information[0]
Item
Definition
Description
0=locked(fixed)
BWPS
Boot Buffer Write Protect Status
- 51 -
OneNAND1Gb(KFG1G16Q2C-xEBx)
FLASH MEMORY
2.8.20 System Configuration 2 Register F222h
This register is reserved for future use.
2.8.21 Controller Status Register F240h (R)
This Read register shows the overall internal status of the OneNAND and the controller.
F240h, default = 0000h
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reserved
(0)
TO
(0)
OTPBL
OnGo Lock Load Prog Erase Error Sus
RSTB OTPL
Reserved(0000)
OnGo
This bit shows the overall internal status of the OneNAND device.
OnGo Information[15]
Item
Definition
Description
0 = ready
1 = busy
OnGo
Internal Device Status
Lock
This bit shows whether the host is loading data from the NAND Flash array into the locked BootRAM or whether the host is performing a pro-
gram/erase of a locked block of the NAND Flash array.
Lock Information[14]
Lock
Locked/Unlocked Check Result
0
1
Unlocked
Locked
Load
This bit shows the Load Operation status.
Load Information[13]
Item
Definition
Description
0 = ready (default)
1 = busy or error (see controller status output modes)
Load
Load Operation status
- 52 -
OneNAND1Gb(KFG1G16Q2C-xEBx)
FLASH MEMORY
Program
This bit shows the Program Operation status.
Program Information[12]
Item
Definition
Description
0 = ready (default)
1 = busy or error (see controller status output modes)
Prog
Program Operation status
Erase
This bit shows the Erase Operation status.
Erase Information[11]
Item
Definition
Description
0 = ready (default)
1 = busy or error (see controller status output modes)
Erase
Erase Operation status
Error
This bit shows the overall Error status, including Load Reset, Program Reset, and Erase Reset status.
Error Information[10]
Sector/Page Load/Program/CopyBack Program
Error
and Invalid Command Input
0
1
Pass
Fail
Erase Suspend (Sus)
This bit shows the Erase Suspend status.
Sus Information[9]
Sus
Erase Suspend Status
0
Erase Resume(Default)
Erase Suspend, Program Ongoing(Susp.), Load Ongoing(Susp.),
Program Fail(Susp.), Load Fail(Susp.), Invalid Command(Susp.)
1
- 53 -
OneNAND1Gb(KFG1G16Q2C-xEBx)
FLASH MEMORY
Reset / Busy (RSTB)
This bit shows the Reset Operation status.
RSTB Information[7]
Item
Definition
Description
0 = ready (default)
1 = busy (see controller status output modes)
RSTB
Reset Operation Status
OTP Lock Status (OTPL)
This bit shows whether the OTP block is locked or unlocked. Locking the OTP has the effect of a 'write-protect' to guard against accidental re-
programming of data stored in the OTP block.
The OTPL status bit is automatically updated at power-on.
OTP Lock Information[6]
OTPL
OTP Locked/Unlocked Status
OTP Block Unlock Status(Default)
0
1
OTP Block Lock Status(Disable OTP Program/Erase)
1st Block OTP Lock Status (OTPBL
)
This bit shows whether the 1st Block OTP is locked or unlocked.
Locking the 1st Block OTP has the effect of a 'Program/Erase protect' to guard against accidental re-programming of data stored in the 1st
block.
The OTPBL status bit is automatically updated at power-on.
OTP Lock Information[5]
OTPBL
1st Block OTP Locked/Unlocked Status
1st Block OTP Unlock Status(Default)
0
1
1st Block OTPLock Status(Disable 1st Block OTP Program/Erase)
Time Out (TO)
This bit determines if there is a time out for load, program, copy back program, and erase operations. It is fixed at 'no time out'.
TO Information[0]
Item
Definition
Description
TO
Time Out
0 = no time out
- 54 -
OneNAND1Gb(KFG1G16Q2C-xEBx)
FLASH MEMORY
Controller Status Register Output Modes
Controller Status Register [15:0]
[15]
[14]
[13]
[12]
[11]
[10]
[9]
[8]
[7]
[6]
[5]
[4:1]
[0]
TO
Mode
Reserved
(0)
OTPL
(note4) (note5)
OTPBL
Reserved
(0)
OnGo Lock Load Prog Erase Error Sus
RSTB
Load / Cache Read
1
0
1
0
0
0
0
0
0
0/1
0/1
0000
0
6)
Ongoing
Program Ongoing
Erase Ongoing
Reset Ongoing
1
1
1
0
0
0
0
0
0
1
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
1
0/1
0/1
0/1
0/1
0/1
0/1
0000
0000
0000
0
0
0
Multi-Block Erase
Ongoing
1
1
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0/1
0/1
0/1
0/1
0000
0000
0
0
Erase Verify Read
Ongoing
6)
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0/1
0/1
0/1
0/1
0/1
0/1
0000
0000
0000
0
0
0
Load / Cache Read OK
Program OK
Erase OK
Erase Verify Read
0
0
0
0
0
0
0
0
0
0/1
0/1
0000
0
3)
OK
1)
0
0
0
1
0
0
0
0
0
0
1
0
0
1
0
0
1
0
0
0
0
0
1
0
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0000
0000
0000
0000
0000
0
0
0
0
0
Load Fail
Program Fail
Erase Fail
Cache Read Fail
3)
Erase Verify Read Fail
2)
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
0
0
0
0
1
1
1
1
0
1
0
0
0
0
0
0
1
0
0
0
0
0
1
0
0
0
0
1
0
1
0
0
0
1
0
0
1
0
0
1
1
0
1
0
1
0
0
0
0
0
1
1
0
1
0
0
0
1
1
1
1
1
0
1
1
1
1
0
1
1
1
1
1
1
0
0
1
1
1
1
0
0
0
1
0
0
0
0
0
0
1
1
1
1
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0/1
0/1
0/1
0/1
0/1
0/1
0/1
1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
1
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Load Reset
Program Reset
Erase Reset
Erase Suspend
Program Lock
Erase Lock
Load Lock(Buffer Lock)
OTP Program Fail(Lock)
OTP Program Fail
OTP Erase Fail
0
0
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
Program Ongoing(Susp.)
Load Ongoing(Susp.)
Program Fail(Susp.)
Load Fail(Susp.)
Invalid Command
Invalid Command(Susp.)
NOTE :
1) ERm and/or ERs bits in ECC status register at Load Fail case is 10. (2bits error - uncorrectable)
If 2 bit error occurs during Synchronous Burst Block Read Operation, Load Fail mode will be shown.
2) ERm and ERs bits in ECC status register at Load Reset case are 00. (No error)
3) Multi Block Erase status should be checked by Erase Verify Read operation.
4) "1" for OTP Block Lock, "0" for OTP Block Unlock.
5) "1" for 1st Block OTP Lock, "0" for 1st Block OTP Unlock.
6) During Cache Read Operation, Load/Cache Read Ongoing mode will be shown at the INT high after ’Cache Read’ Command.
Load/Cache Read OK mode will be shown only at the completion of ’Finish Cache Read’ Command.
- 55 -
OneNAND1Gb(KFG1G16Q2C-xEBx)
FLASH MEMORY
2.8.22 Interrupt Status Register F241h (R/W)
This Read/Write register shows status of the OneNAND interrupts.
F241h, defaults = 8080h after Cold Reset; 8010h after Warm/Hot Reset
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
INT
Reserved(0000000)
RI
WI
EI
RSTI
Reserved(0000)
Interrupt (INT)
This is the master interrupt bit. The INT bit is wired directly to the INT pin on the chip. Upon writing '0' to the INT bit, the INT pin goes low if
INTpol is high and goes high if INTpol is low.
INT Interrupt [15]
Default State
Valid
State
Interrupt
Function
Status
Conditions
Cold
Warm/hot
1
1
0
off
One or more of RI, WI, RSTI and EI is set to ’1’, or
0065h, 0023h, 0071h, 002Ah, 0027h and 002Ch
commands are completed.
sets itself to ’1’
clears to ’0’
Pending
0→1
’0’ is written to this bit,
Cold/Warm/Hot reset is being performed, or
command is written to Command Register in INT
auto mode
off
1→0
Read Interrupt (RI)
This is the Read interrupt bit.
RI Interrupt [7]
Status
Default State
Valid
State
Interrupt
Function
Conditions
Cold
Warm/hot
1
0
0
off
At the completion of an Load Operation
(0000h, 000Eh, 000Ch, 000Ah, 0013h,
Load Data into Buffer, or boot is done)
sets itself to ’1’
0→1
Pending
’0’ is written to this bit,
Cold/Warm/Hot reset is being performed, or
command is written to Command Register in INT
auto mode
clears to ’0’
1→0
off
- 56 -
OneNAND1Gb(KFG1G16Q2C-xEBx)
FLASH MEMORY
Write Interrupt (WI)
This is the Write interrupt bit.
WI Interrupt [6]
Default State
Valid
State
Interrupt
Function
Status
Conditions
Cold
Warm/hot
0
0
0
off
At the completion of an Program Operation
(0080h, 001Ah, 001Bh)
sets itself to ’1’
clears to ’0’
0→1
Pending
’0’ is written to this bit,
Cold/Warm/Hot reset is being performed, or com-
mand is written to Command Register in INT auto
mode
off
1→0
Erase Interrupt (EI)
This is the Erase interrupt bit.
EI Interrupt [5]
Status
Default State
Valid
State
Interrupt
Function
Conditions
Cold
Warm/hot
0
0
0
off
At the completion of an Erase Operation
(0094h, 0095h, 0030h)
sets itself to ’1’
0→1
Pending
’0’ is written to this bit,
Cold/Warm/Hot reset is being performed, or com-
mand is written to Command Register in INT auto
mode
clears to ’0’
off
1→0
Reset Interrupt (RSTI)
This is the Reset interrupt bit.
RSTI Interrupt [4]
Status
Default State
Valid
State
Interrupt
Function
Conditions
Cold
Warm/hot
0
1
0
off
At the completion of an Reset Operation
(00B0h, 00F0h, 00F3h or
sets itself to ’1’
Pending
0→1
warm reset is released)
’0’ is written to this bit, or
clears to ’0’
command is written to Command Register in INT
auto mode
off
1→0
- 57 -
OneNAND1Gb(KFG1G16Q2C-xEBx)
FLASH MEMORY
2.8.23 Start Block Address Register F24Ch (R/W)
This Read/Write register shows the NAND Flash block address in the Write Protection mode. Setting this register precedes a 'Lock Block'
command, 'Unlock Block' command, or ’Lock-Tight' Command.
F24Ch, default = 0000h
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reserved(000000)
SBA
Device
Number of Block
SBA
1Gb
1024
[9:0]
SBA Information[9:0]
Item
Definition
Description
Precedes Lock Block, Unlock Block, or Lock-Tight commands
SBA
Start Block Address
2.8.24 End Block Address Register F24Dh
This register is reserved for future use.
2.8.25 NAND Flash Write Protection Status Register F24Eh (R)
This Read register shows the Write Protection Status of the NAND Flash memory array.
To read the write protection status, FBA has to be set before reading the register.
F24Eh, default = 0002h
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reserved(0000000000000)
US
LS
LTS
Write Protection Status Information[2:0]
Item
Definition
Unlocked Status
Description
US
1 = current NAND Flash block is unlocked
1 = current NAND Flash block is locked
LS
Locked Status
Or First Block of NAND Flash Array is Locked to be OTP
LTS
Locked-Tight Status
1 = current NAND Flash block is locked-tight
- 58 -
OneNAND1Gb(KFG1G16Q2C-xEBx)
FLASH MEMORY
2.8.26 ECC Status Register FF00h (R)
This Read register shows the Error Correction Status. The OneNAND can detect 1- or 2-bit errors and correct 1-bit errors. 3-bit or more error
detection and correction is not supported.
ECC can be performed on the NAND Flash main and spare memory areas. The ECC status register can also show the number of errors in a
sector as a result of an ECC check in during a load operation. ECC status bits are also updated during a boot loading operation.
ECC registers will be reset when another command is issued.
FF00h, default = 0000h
15
14
ERm3
13
12
11
10
9
8
7
6
5
4
3
2
1
0
ERs01)
ERs3
ERm2
ERs2
ERm1
ERs1
ERm0
NOTE :
1) After Synchronous Block Burst Read operation, DQ[0] shows accmulated 1bit error.
Error Status
ERm, ERs
ECC Status
00
01
10
11
No Error
1 bit error(correctable)
2 bit error (uncorrectable)
Reserved
ECC Information[15:0]
Item
Definition
Description
Status of errors in the 1st selected sector of the main BufferRAM
as a result of an ECC check during a load operation.
Also updated during a Bootload operation.
1st selected sector of
the main BufferRAM
ERm0
Status of errors in the 2nd selected sector of the main BufferRAM
as a result of an ECC check during a load operation.
Also updated during a Bootload operation.
2nd selected sector of
the main BufferRAM
ERm1
ERm2
ERm3
ERs0
ERs1
ERs2
ERs3
Status of errors in the 3rd selected sector of the main BufferRAM
as a result of an ECC check during a load operation.
Also updated during a Bootload operation.
3rd selected sector of
the main BufferRAM
Status of errors in the 4th selected sector of the main BufferRAM
as a result of an ECC check during a load operation.
Also updated during a Bootload operation.
4th selected sector of
the main BufferRAM
Status of errors in the 1st selected sector of the spare BufferRAM
as a result of an ECC check during a load operation.
Also updated during a Bootload operation.
1st selected sector of
the spare BufferRAM
Status of errors in the 2nd selected sector of the spare BufferRAM
as a result of an ECC check during a load operation.
Also updated during a Bootload operation.
2nd selected sector of
the spare BufferRAM
Status of errors in the 3rd selected sector of the spare BufferRAM
as a result of an ECC check during a load operation.
Also updated during a Bootload operation.
3rd selected sector of
the spare BufferRAM
Status of errors in the 4th selected sector of the spare BufferRAM
as a result of an ECC check during a load operation.
Also updated during a Bootload operation.
4th selected sector of
the spare BufferRAM
- 59 -
OneNAND1Gb(KFG1G16Q2C-xEBx)
FLASH MEMORY
st
2.8.27 ECC Result of 1 Selected Sector, Main Area Data Register FF01h (R)
This Read register shows the Error Correction result for the 1st selected sector of the main area data. ECCposWord0 is the error position
address in the Main Area data of 256 words. ECCposIO0 is the error position address which selects 1 of 16 DQs. ECCposWord0 and
ECCposIO0 are also updated at boot loading.
FF01h, default = 0000h
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reserved(0000)
ECCposWord0
ECCposIO0
st
2.8.28 ECC Result of 1 Selected Sector, Spare Area Data Register FF02h (R)
This Read register shows the Error Correction result for the 1st selected sector of the spare area data. ECClogSector0 is the error position
address for 1.5 words of 2nd and 3rd words in the spare area. ECCposIO0 is the error position address which selects 1 of 16 DQs.
ECClogSector0 and ECCposIO0 are also updated at boot loading.
FF02h, default = 0000h
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reserved(0000000000)
ECClogSector0
ECCposIO0
nd
2.8.29 ECC Result of 2 Selected Sector, Main Area Data Register FF03h (R)
This Read register shows the Error Correction result for the 2nd selected sector of the main area data. ECCposWord1 is the error position
address in the Main Area data of 256 words. ECCposIO1 is the error position address which selects 1 of 16 DQs. ECCposWord1 and
ECCposIO1 are also updated at boot loading.
FF03h, default = 0000h
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reserved(0000)
ECCposWord1
ECCposIO1
nd
2.8.30 ECC Result of 2 Selected Sector, Spare Area Data Register FF04h (R)
This Read register shows the Error Correction result for the 2nd selected sector of the spare area data. ECClogSector1 is the error position
address for 1.5 words of 2nd and 3rd words in the spare area. ECCposIO1 is the error position address which selects 1 of 16 DQs.
ECClogSector1 and ECCposIO1 are also updated at boot loading.
FF04h, default = 0000h
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reserved(0000000000)
ECClogSector1
ECCposIO1
- 60 -
OneNAND1Gb(KFG1G16Q2C-xEBx)
FLASH MEMORY
rd
2.8.31 ECC Result of 3 Selected Sector, Main Area Data Register FF05h (R)
This Read register shows the Error Correction result for the 3rd selected sector of the main area data. ECCposWord2 is the error position
address in the Main Area data of 256 words. ECCposIO2 is the error position address which selects 1 of 16 DQs. ECCposWord2 and
ECCposIO2 are also updated at boot loading.
FF05h, default = 0000h
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reserved(0000)
ECCposWord2
ECCposIO2
rd
2.8.32 ECC Result of 3 Selected Sector, Spare Area Data Register FF06h (R)
This Read register shows the Error Correction result for the 3rd selected sector of the spare area data. ECClogSector2 is the error position
address for 1.5 words of 2nd and 3rd words in the spare area. ECCposIO2 is the error position address which selects 1 of 16 DQs.
ECClogSector2 and ECCposIO2 are also updated at boot loading.
FF06h, default = 0000h
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reserved(0000000000)
ECClogSector2
ECCposIO2
th
2.8.33 ECC Result of 4 Selected Sector, Main Area Data Register FF07h (R)
This Read register shows the Error Correction result for the 4th selected sector of the main area data. ECCposWord3 is the error position
address in the Main Area data of 256 words. ECCposIO3 is the error position address which selects 1 of 16 DQs. ECCposWord3 and
ECCposIO3 are also updated at boot loading.
FF07h, default = 0000h
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reserved(0000)
ECCposWord3
ECCposIO3
th
2.8.34 ECC Result of 4 Selected Sector, Spare Area Data Register FF08h (R)
This Read register shows the Error Correction result for the 4th selected sector of the spare area data. ECClogSector3 is the error position
address for 1.5 words of 2nd and 3rd words in the spare area. ECCposIO3 is the error position address which selects 1 of 16 DQs.
ECClogSector3 and ECCposIO3 are also updated at boot loading.
FF08h, default = 0000h
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reserved(0000000000)
ECClogSector3
ECCposIO3
- 61 -
OneNAND1Gb(KFG1G16Q2C-xEBx)
FLASH MEMORY
ECC Log Sector
ECClogSector0~ECClogSector3 indicates the error position in the 2nd word and LSB of 3rd word in the spare area.
Refer to note 2 in chapter 2.7.2
ECClogSector Information [5:4]
ECClogSector
Error Position
2nd word
00
01
3rd word
10, 11
Reserved
- 62 -
OneNAND1Gb(KFG1G16Q2C-xEBx)
3.0 DEVICE OPERATION
FLASH MEMORY
This section of the datasheet discusses the operation of the OneNAND device. It is followed by AC/DC Characteristics and Timing Diagrams
which may be consulted for further information.
The OneNAND supports a limited command-based interface in addition to a register-based interface for performing operations on the
device.
3.1 Command Based Operation
The command-based interface is active in the boot partition. Commands can only be written with a boot area address. Boot area data is only
returned if no command has been issued prior to the read.
The entire address range, except for the boot area, can be used for the data buffer. All commands are written to the boot partition. Writes out-
side the boot partition are treated as normal writes to the buffers or registers.
The command consists of one or more cycles depending on the command. After completion of the command the device starts its execution.
Writing incorrect information including address and data to the boot partition or writing an improper command will terminate the previous com-
mand sequence and make the device enter the ready status.
The defined valid command sequences are stated in Command Sequences Table.
Command based operations are mainly used when OneNAND is used as Booting device, and all command based operations only supports
asynchronous reads and writes.
Command Sequences
Command Definition
Cycles
1st cycle
2nd cycle
BP1)
00F0h
BP
Add
Data
Add
Reset OneNAND
1
BP
Load Data into Buffer2)
2
2
0000h3)
XXXXh4)
Data
Data
Add
00E0h
BP
Read Identification Data 5)
Data
0090h
NOTE :
1) BP(Boot Partition) : BootRAM Area [0000h ~ 01FFh, 8000h ~ 800Fh].
2) Load Data into Buffer operation is available within a block(128KB)
3) Load 2KB unit into DataRAM0. Current Start address(FPA) is automatically incremented by 2KB unit after the load.
4) 0000h -> Data is Manufacturer ID
0001h -> Data is Device ID
0002h -> Current Block Write Protection Status for mono chip
5) WE toggling can terminate ’Read Identification Data’ operation.
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3.1.1 Reset OneNAND Command
The Reset command is given by writing 00F0h to the boot partition address. Reset will return all default values into the device.
3.1.2 Load Data Into Buffer Command
Load Data into Buffer command is a two-cycle command. Two sequential designated command activates this operation. Sequentially writing
00E0h and 0000h to the boot partition [0000h~01FFh, 8000h~800Fh] will load one page to DataRAM0. This operation refers to FBA and FPA.
FSA, BSA, and BSC are not considered.
At the end of this operation, FPA will be automatically increased by 1. So continuous issue of this command will sequentially load data in next
page to DataRAM0. This page address increment is restricted within a block.
The default value of FBA and FPA is 0. Therefore, initial issue of this command after power on will load the first page of memory, which is
usually boot code.
3.1.3 Read Identification Data Command
The Read Identification Data command consists of two cycles. It gives out the devices identification data according to the given address. The
first cycle is 0090h to the boot partition address and second cycle is read from the addresses specified in Identification Data Description
Table.
Identification Data Description
Address
0000h
Data Out
Manufacturer ID (00ECh)
Device ID1)
0001h
Current Block Write Protection Status 2)
0002h
NOTE :
1) Refer to Device ID Register (Chapter 2.8.3)
2)To read the write protection status, FBA has to be set before issuing this command.
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3.2 Device Bus Operation
The device bus operations are shown in the table below.
Operation
Standby
CE
H
OE
X
WE
X
ADD0~15
DQ0~15
High-Z
High-Z
Data In
RP
H
CLK
X
AVD
X
X
X
Warm Reset
X
X
X
L
X
X
Asynchronous Write
L
H
L
Add. In
H
L
X
Asynchronous Read
Load Initial Burst Read
Burst Read
L
L
L
L
H
L
H
H
H
Add. In
Add. In
X
Data Out
X
H
H
H
L
or L
Burst Data
Out
X
Terminate Burst Read
Cycle
H
X
X
X
H
X
X
X
High-Z
High-Z
H
L
X
X
X
X
Terminate Burst Read
Cycle via RP
Terminate Current Burst
Read Cycle and Start
New Burst Read Cycle
H
H
H
H
L
Add In
Add. In
X
High-Z
X
H
H
H
Load Initial Burst Write
Burst Write
L
L
Burst Data
In
X
X
Terminate Burst Write
Cycle
H
X
X
X
X
X
X
X
High-Z
High-Z
H
L
X
X
X
X
Terminate Burst Write
Cycle via RP
Terminate Current Burst
Write Cycle and Start
New Burst Write Cycle
H
L
Add In
High-Z
H
NOTE :
L=VIL (Low), H=VIH (High), X=Don’t Care.
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3.3 Reset Mode Operation
The One NAND has 4 reset modes: Cold/Warm/Hot Reset, and NAND Flash Array Reset. Section 3.3 discusses the operation of these reset
modes.
The Register Reset Table shows the which registers are affected by the various types or Reset operations.
Internal Register Reset Table
Hot
Reset
(BP-
Warm
Reset
(RP)
Hot
Reset
(00F3h)
NANDFlash
Core Reset
(00F0h)
Cold
Reset
Internal Registers
Default
F0h)
F000h Manufacturer ID Register (R)
00ECh
(Note
(Note
0800h
0200h
0201h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
40C0h
0000h
-
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
F001h Device ID Register (R): OneNAND
F002h Version ID Register (R)
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
F003h Data Buffer size Register (R)
N/A
N/A
F004h Boot Buffer size Register (R)
N/A
N/A
F005h Amount of Buffers Register (R)
N/A
N/A
F006h Technology Register (R)
N/A
N/A
F100h Start Address1 Register (R/W): FBA
F101h Start Address2 Register (R/W): Reserved
F102h Start Address3 Register (R/W): FCBA
F103h Start Address4 Register (R/W): FCPA, FCSA
F104h Start Address5 Register (R/W): FPC
F107h Start Address8 Register (R/W): FPA, FSA
F200h Start Buffer Register (R/W): BSA, BSC
F220h Command Register (R/W)
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
40C0h
0000h
8080h
0000h
N/A
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
(Note1a)
0000h
8010h
0000h
N/A
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
(Note1a)
0000h
8010h
N/A
F221h System Configuration 1 Register (R/W)
F240h Controller Status Register (R) (Note 1b) (Note 5)
F241h Interrupt Status Register (R/W)
F24Ch Start Block Address (R/W) : SBA
0000h
N/A
F24Dh End Block Address: N/A
N/A
F24Eh NAND Flash Write Protection Status (R)
FF00h ECC Status Register (R) (Note2)
0002h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0002h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0002h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
N/A
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
FF01h ECC Result of Sector 0 Main area data Register(R)
FF02h ECC Result of Sector 0 Spare area data Register (R)
FF03h ECC Result of Sector 1 Main area data Register(R)
FF04h ECC Result of Sector 1 Spare area data Register (R)
FF05h ECC Result of Sector 2 Main area data Register(R)
FF06h ECC Result of Sector 2 Spare area data Register (R)
FF07h ECC Result of Sector 3 Main area data Register(R)
FF08h ECC Result of Sector 3 Spare area data Register (R)
NOTE :
1a) RDYpol, RDY conf, INTpol, IOBE are reset by Cold reset. The other bits are reset by cold/warm/hot reset.
1b) The other bits except OTP and OTP are reset by cold/warm/hot reset.
L
BL
2) ECC Status Register & ECC Result Registers are reset when any command is issued.
3) Refer to Device ID Register F001h.
4) Refer to Version ID Register F002h.
5) Resetting during IDLE state, this is valid. But resetting during BUSY state, refer to Chapter 2.8.21.
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3.3.1 Cold Reset Mode Operation
See Timing Diagram 6.15
At system power-up, the voltage detector in the device detects the rising edge of Vcc and releases an internal power-up reset signal. This trig-
gers bootcode loading. Bootcode loading means that the boot loader in the device copies designated sized data (1KB) from the beginning of
memory into the BootRAM. This sequence is the Cold Reset of OneNAND.
The POR(Power On Reset) triggering level is typically 1.5V. Boot code copy operation activates typically 500us(max. 2ms) after POR.
Therefore, the system power should reach 1.7V within 400us from the POR triggering level for bootcode data to be valid.
It takes typically 500us(max. 2ms) to copy 1KB of bootcode. Upon completion of loading into the BootRAM, it is available to be read by the
host. The INT pin is not available until after IOBE = 1 and IOBE bit can be changed by host.
3.3.2 Warm Reset Mode Operation
See Timing Diagrams 6.16
A Warm Reset means that the host resets the device by using the RP pin. When the a RP low is issued, the device logic stops all current oper-
ations and executes internal reset operation and resets current NAND Flash core operation synchronized with the
falling edge of RP.
During an Internal Reset Operation, the device initializes internal registers and makes output signals go to default status.
The BufferRAM data is kept unchanged after Warm/Hot reset operations.
The device guarantees the logic reset operation in case RP pulse is longer than tRP min(200ns).
The device may reset if tRP < tRP min(200ns), but this is not guaranteed.
Warm reset will abort the current NAND Flash core operation. During a warm reset, the content of memory cells being altered is no longer
valid as the data will be partially programmed or erased.
Warm reset has no effect on contents of BootRAM and DataRAM.
3.3.3 Hot Reset Mode Operation
See Timing Diagram 6.17
A Hot Reset means that the host resets the device by Reset command. The reset command can be either Command based or Register
Based. Upon receiving the Reset command, the device logic stops all current operation and executes an internal reset operation and resets
the current NAND Flash core operation.
During an Internal Reset Operation, the device initializes internal registers and makes output signals go to default status. The BufferRAM data
is kept unchanged after Warm/Hot reset operations.
Hot reset has no effect on contents of BootRAM and DataRAM.
3.3.4 NAND Flash Core Reset Mode Operation
See Timing Diagram 6.18
The Host can reset the NAND Flash Core operation by issuing a NAND Flash Core reset command. NAND Flash core reset will abort the cur-
rent NAND Flash core operation. During a NAND Flash core reset, the content of memory cells being altered is no longer valid as the data will
be partially programmed or erased.
NAND Flash Core Reset has an effect on neither contents of BootRAM and DataRAM nor register values.
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3.4 Write Protection Operation
The OneNAND can be write-protected to prevent re-programming or erasure of data.
The areas of write-protection are the BootRAM, and the NAND Flash Array.
3.4.1 BootRAM Write Protection Operation
At system power-up, voltage detector in the device detects the rising edge of Vcc and releases the internal power-up reset signal which trig-
gers bootcode loading. And the designated size data(1KB) is copied from the first page of the first block in the NAND flash array to the
BootRAM.
After the bootcode loading is completed, the BootRAM is always locked to protect the boot code from the accidental write.
3.4.2 NAND Flash Array Write Protection Operation
The device has both hardware and software write protection of the NAND Flash array.
Hardware Write Protection Operation
The hardware write protection operation is implemented by executing a Cold or Warm Reset. On power up, the NAND Flash Array is in its
default, locked state. The entire NAND Flash array goes to a locked state after a Cold or Warm Reset.
Software Write Protection Operation
The software write protection operation is implemented by writing a Lock command (002Ah) or a Lock-tight command (002Ch) to command
register (F220h).
Lock (002Ah) and Lock-tight (002Ch) commands write protects the block defined in the Start Block Address Register F24Ch.
3.4.3 NAND Array Write Protection States
There are three lock states in the NAND Array: unlocked, locked, and locked-tight.
OneNAND1Gb supports lock/unlock/lock-tight by one block, and All Block Unlock at once. If any blocks are changed to locked-tight state, the
all block unlock command will fail. In order to use all block unlock command again, a cold reset is needed.
Write Protection Status
The current block Write Protection status can be read in NAND Flash Write Protection Status Register(F24Eh). There are three bits - US, LS,
LTS -, which are not cleared by hot reset. These Write Protection status registers are updated when FBA is set, and when Write Protection
command is entered.
The followings summarize locking status.
example)
In default, [2:0] values are 010.
-> If host executes unlock block operation, then [2:0] values turn to 100.
-> If host executes lock-tight block operation, then [2:0] values turn to 001.
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3.4.3.1 Unlocked NAND Array Write Protection State
An Unlocked block can be programmed or erased. The status of an unlocked block can be changed to locked or locked-tight using the appro-
priate software command. (locked-tight state can be achieved via lock-tight command which follows lock command)
Only one block can be released from lock state to unlock state with Unlock command and addresses. The unlocked block can be changed
with new lock command. Therefore, each block has its own lock/unlock/lock-tight state.
If any blocks are changed to locked-tight state, the all block unlock command will fail. In order to use all block unlock command again, a cold
reset is needed.
Unlocked
Unlock Command Sequence:
Start block address+Unlock block command (0023h)
Unlocked
All Block Unlock Command Sequence:
Start block address(000h)+All Block Unlock command (0027h)
NOTE :
Even though SBA is fixed to 000h, Unlock will be done for all block.
3.4.3.2 Locked NAND Array Write Protection State
A Locked block cannot be programmed or erased. All blocks default to a locked state following a Cold or Warm Reset. Unlocked blocks can be
changed to locked using the Lock block command. The status of a locked block can be changed to unlocked or
locked-tight using the appropriate software command.
Locked
Lock Command Sequence:
Start block address+Lock block command (002Ah)
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3.4.3.3 Locked-tight NAND Array Write Protection State
A block that is in a locked-tight state can only be changed to locked state after a Cold or Warm Reset. Unlock and Lock command sequences
will not affect its state. This is an added level of write protection security. If any blocks are changed to locked-tight state, the all block unlock
command will fail. In order to use all block unlock command again, a cold reset is needed.
A block must first be set to a locked state before it can be changed to locked-tight using the Lock-tight command.
Locked-tight
Lock-Tight Command Sequence:
Start block address+Lock-tight block command (002Ch)
3.4.4 NAND Flash Array Write Protection State Diagram
unlock
RP pin: High
&
Start block address (000h)
+All Block Unlock Command
RP pin: High
&
Start block address
Lock block Command
or
Lock
unlock
Lock
RP pin: High
&
Start block address
+Unlock block Command
Cold reset or
Warm reset
Power On
Lock
RP pin: High
&
Start block address
Cold reset or
Warm reset
+Lock-tight block Command
Lock
Lock-tight
Lock
*NOTE : If the 1st Block is set to be OTP, Block 0 will always be Lock Status
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Data Protection Operation Flow Diagram
Start
Write ’SBA’ of Flash
Add: F24Ch DQ=SBA
Write 0 to interrupt register1)
Add: F241h DQ=0000h
Write ’lock/unlock/lock-tight’
Command
Add: F220h
DQ=002Ah/0023h/002Ch
Wait for INT register
low to high transition
Add: F241h DQ[15]=INT
Read Controller
Status Register
Add: F240h DQ[10]=0(pass)
Write ’FBA’ of Flash
Add: F100h DQ=FBA
Read Write Protection Register
Add: F24Eh DQ[2:0]=US,LS,LTS
Lock/Unlock/Lock-Tight
completed
NOTE : 1) ’Write 0 to interrupt register’ step may be ignored when using INT auto mode. Refer to chapter 2.8.18.1
* Samsung strongly recommends to follow the above flow chart
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All Block Unlock Flow Diagram
Start
Write ’SBA’ of Flash
Add: F24Ch DQ=SBA(000h)
Write 0 to interrupt register1)
Add: F241h DQ=0000h
Write ’All Block Unlock’
Command
Add: F220h
DQ=0027h
Wait for INT register
low to high transition
Add: F241h DQ[15]=INT
Read Controller
Status Register
Add: F240h DQ[10]=0(pass)
Write ’FBA’ of Flash
Add: F100h DQ=FBA
Read Write Protection Register
Add: F24Eh DQ[2:0]=US,LS,LTS
Unlock All Block
completed
NOTE : 1) ’Write 0 to interrupt register’ step may be ignored when using INT auto mode. Refer to chapter 2.8.18.1
* Samsung strongly recommends to follow the above flow chart
** If any blocks are changed to locked-tight state, the all block unlock command will fail.
In order to use all block unlock command again, a cold reset is needed.
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3.5 Data Protection During Power Down Operation
See Timing Diagram 6.19
The device is designed to offer protection from any involuntary program/erase during power-transitions.
RP pin which provides hardware protection is recommended to be kept at VIL before Vcc drops to 1.5V.
3.6 Load Operation
See Timing Diagrams 6.12
The Load operation is initiated by setting up the start address from which the data is to be loaded. The Load command is issued in order to ini-
tiate the load.
During a Load operation, the device:
-Transfers the data from NAND Flash array into the BufferRAM
-ECC is checked and any detected and corrected error is reported in the status response as well as
any unrecoverable error.
Once the BufferRAM has been filled, an interrupt is issued to the host so that the contents of the BufferRAM can be read. The read from the
BufferRAM can be an asynchronous read mode or synchronous read mode. The status information related to load operation can be checked
by the host if required.
The device has a dual data buffer memory architecture (DataRAM0, DataRAM1), each 2KB in size. Each DataRAM buffer has 4
Sectors. The device is capable of independent and simultaneous data-read operation from one data buffer and data-load operation to the
other data buffer. Refer to the information for more details in section 3.12.1, "Read-While-Load Operation".
Load Operation Flow Chart Diagram
Write ’Load’ Command
Start
Add: F220h
DQ=0000h or 0013h
Write ’FBA’ of Flash
Add: F100h DQ=FBA
Wait for INT register
low to high transition
Write ’FPA, FSA’ of Flash
Add: F241h DQ[15]=INT
Add: F107h DQ=FPA, FSA
Read Controller
Status Register
Write ’BSA, BSC’ of DataRAM
Add: F200h DQ=BSA, BSC
Add: F240h DQ[10]=Error
Write 0 to interrupt register1)
Add: F241h DQ=0000h
NO
DQ[10]=0?
YES
Map Out
Host reads data from
DataRAM
Read completed
NOTE :
1) ’Write 0 to interrupt register’ step may be ignored when using INT auto mode. Refer to chapter 2.8.18.1
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3.7 Read Operation
See Timing Diagrams 6.1, 6.2, 6.5, 6.6, 6.7 and 6.8
The device has two read modes; Asynchronous Read and Synchronous Burst Read.
The initial state machine automatically sets the device into the Asynchronous Read Mode (RM=0) to prevent the spurious altering of memory
content upon device power up or after a Hardware reset. No commands are required to retrieve data in Asynchronous Read Mode.
The Synchronous Read Mode is enabled by setting RM bit of System Configuration1 Register (F221h) to Synchronous Read Mode (RM=1).
See Section 2.8.19 for more information about System Configuration1 Register.
3.7.1 Asynchronous Read Mode Operation (RM=0, WM=0)
See Timing Diagrams 6.5, 6.6, 6.7 and 6.8
In an Asynchronous Read Mode, data is output with respect to a logic input, AVD.
Output data will appear on DQ15-DQ0 when a valid address is asserted on A15-A0 while driving AVD and CE to VIL. WE is held at VIH. The
function of the AVD signal is to latch the valid address.
Address access time from AVD low (tAA) is equal to the delay from valid addresses to valid output data.
The Chip Enable access time (tCE) is equal to the delay from the falling edge of CE to valid data at the outputs.
The Output Enable access time (tOE) is the delay from the falling edge of OE to valid data at the output.
3.7.2 Synchronous Read Mode Operation (RM=1, WM=X)
See Timing Diagrams 6.1 and 6.2
In a Synchronous Read Mode, data is output with respect to a clock input.
The device is capable of a continuous linear burst operation and a fixed-length linear burst operation of a preset length. Burst address
sequences for continuous and fixed-length burst operations are shown in the table below.
Burst Address Sequences
Burst Address Sequence(Decimal)
Start
Addr.
Continuous Burst
0-1-2-3-4-5-6-..-0-1...
1-2-3-4-5-6-7-..-1-2...
2-3-4-5-6-7-8-..-2-3...
4-word Burst
0-1-2-3-0...
1-2-3-0-1...
2-3-0-1-2...
8-word Burst
16-word Burst
32-word Burst
0
1
2
0-1-2-3-4-5-6-7-0...
1-2-3-4-5-6-7-0-1...
2-3-4-5-6-7-0-1-2...
0-1-2-3-4-....-13-14-15-0...
1-2-3-4-5-....-14-15-0-1...
2-3-4-5-6-....-15-0-1-2...
0-1-2-3-4-....-29-30-31-0...
1-2-3-4-5-....-30-31-0-1...
2-3-4-5-6-....-31-0-1-2...
Wrap
around
.
.
.
.
.
.
.
.
.
.
.
.
In the burst mode, the initial word will be output asynchronously, regardless of BRWL. While the following words will be determined by BRWL
value.
The latency is determined by the host based on the BRWL bit setting in the System Configuration 1 Register. The default BRWL is 4 latency
cycles. At clock frequencies of 40MHz or lower, latency cycles can be reduced to 3. BRWL can be set up to 7 latency cycles.
The BRWL registers can be read during a burst read mode by using the AVD signal with an address.
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3.7.2.1 Continuous Linear Burst Read Operation
See Timing Diagram 6.2
First Clock Cycle
The initial word is output at tIAA after the rising edge of the first CLK cycle. The RDY output indicates the initial word is ready to the system by
pulsing high. If the device is accessed synchronously while it is set to Asynchronous Read Mode, the first data can still be read out.
Subsequent Clock Cycles
Subsequent words are output (Burst Access Time from Valid Clock to Output) tBA after the rising edge of each successive clock cycle, which
automatically increments the internal address counter.
Terminating Burst Read
The device will continue to output sequential burst data until the system asserts CE high, or RP low, wrapping around until it reaches the des-
ignated address (see Section 2.7.3 for address map information). Alternately, a Cold/Warm/Hot Reset, or a WE low pulse will terminate the
burst read operation.
Synchronous Read Boundary
Division
Add.map(word order)
0000h~01FFh
0200h~05FFh
0600h~09FFh
0A00h~7FFFh
8000H~800Fh
8010h~802Fh
8030h~804Fh
8050h~8FFFh
9000h~EFFFh
F000h~FFFFh
BootRAM Main(0.5Kw)
BufferRAM0 Main(1Kw)
BufferRAM1 Main(1Kw)
Reserved Main
Not Support
Not Support
BootRAM Spare(16w)
BufferRAM0 Spare(32w)
BufferRAM1 Spare(32w)
Reserved Spare
Not Support
Not Support
Not Support
Reserved Register
Register(4Kw)
* Reserved area is not available on Synchronous read
3.7.2.2 4-, 8-, 16-, 32-Word Linear Burst Read Operation
See Timing Diagram 6.1
An alternate Burst Read Mode enables a fixed number of words to be read from consecutive address.
The device supports a burst read from consecutive addresses of 4-, 8-, 16-, and 32-words with a linear-wrap around. When the last word in
the burst has been reached, assert CE and OE high to terminate the operation.
In this mode, the start address for the burst read can be any address of the address map with one exception. The device does not support a
32-word linear burst read on the spare area of the BufferRAM.
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3.7.2.3 Programmable Burst Read Latency Operation
See Timing Diagrams 6.1 and 6.2
Upon power up, the number of initial clock cycles from Valid Address (AVD) to initial data defaults to four clocks.
The number of clock cycles (n) which are inserted after the clock which is latching the address. The host can read the first data with the
(n+1)th rising edge.
The number of total initial access cycles is programmable from three to seven cycles. After the number of programmed burst clock cycles is
reached, the rising edge of the next clock cycle triggers the next burst data.
Four Clock Burst Read Latency (BRWL=4 case)
Rising edge of the clock cycle following last read latency
triggers next burst data
CE
CLK
-1
0
1
2
3
4
AVD
tBA
Valid
Address
A0:
A15
DQ0:
DQ15
D6
D7
D0
D1
D2
D3
D7
D0
tIAA
tRDYS
OE
Hi-Z
Hi-Z
tRDYA
RDY
*NOTE :
BRWL=4, HF=0 is recommended for 40MHz~66MHz. For frequency over 66MHz, BRWL should be 6 or 7 while HF=1.
Also, for frequency under 40MHz, BRWL can be reduced to 3, and HF=0.
3.7.3 Handshaking Operation
The handshaking feature allows the host system to simply monitor the RDY signal from the device to determine when the initial word of burst
data is ready to be read.
To set the number of initial cycles for optimal burst mode, the host should use the programmable burst read latency configuration (see Section
2.8.19, "System Configuration1 Register").
The rising edge of RDY which is derived at one cycle prior of data fetch clock indicates the initial word of valid burst data.
3.7.4 Output Disable Mode Operation
When the CE or OE input is at VIH, output from the device is disabled.
The outputs are placed in the high impedance state.
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3.8 Cache Read Operation (RM=X, WM=X)
A Normal Load Operation(0000h) consists of sequential operation of ’sensing from NAND Flash Array to Page Buffer’ and ’transferring from
Page Buffer to DataRAM’.
Cache Read is a method of improving the data read throughput performance of the device by allowing new data to be transferred from the
NAND Flash Array memory into a Page Buffer while the previous data that was requested is transferred from the Page Buffer to the DataRAM.
This method is called Transfer-While Sensing Operation.
This ability to simultaneously sense a new page shortens the read cycle resulting in performance increase to 108Mbytes/second.
Cache Read Mode is designed to continuously read massive data from random address at a high speed.
The characteristics of Cache read is as follows;
-Before entering ’First Cache Read Command(000Eh)’, address of two pages which will be read will be set on address registers. The register
information follows on next line.
-Register used for first page is Copy-back registers (FCBA, FCPA and FCSA). and the registers used for addressing second page and follow-
ing cache read are normal address registers(FBA, FPA and FSA). At Cache Read Operation, FCSA and FSA must be set to "00".
-BSA setting is only required once at ’First Cache Read’ cycle. From the following cycles, BSA will be automatically switched to select
DataRAM0 and DataRAM1 alternately.
-BSC must be fixed as "00"
-To eliminate performance degradation during Ready state(INT high state) due to register setting time, setting registers (FBA, FPA and FSA)
during busy state(INT low state) is possible from third address setting onwards.
-Inputting other commands, which is not related to Cache Read, between ’First Cache Read Command’ and ’Finish Cache Read Command’
will fail the Cache Read operation.
-In case of performing Cache Read at INT auto mode, INT low setting is not necessary. INT will automatically go to low when Cache Read
command is issued.
Transfer-While Sensing Operation
NAND Flash
Array
Selected Page
1) Sensing
1) Transfer
2) Read
Page Buffer
DataRAM
Host
A Cache-Read flow chart is on the following page.
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Cache Read Flow Chart
Start
Yes
Done with
(n-1)th command issue?
Write ‘FCBA’ of Flash
Add: F102h DQ=FCBA
Wait for INT high State
Add: F241h DQ[15]=INT
No
Write ‘FCPA, FCSA2)’ of Flash
Add: F103h DQ=FCPA, FCSA
Write ‘FBA’ of Flash3)
Add: F100h DQ=FBA
Read Controller Status
Register
Write ‘BSA1), BSC2)’ of Flash
Add: F200h DQ=BSA, BSC
3)
Write ‘FPA, FSA2)’ of Flash
Add: F240h DQ[10]=Error
Add: F107h DQ=FPA, FSA
No
DQ[10]=0?
Yes
Write ‘FBA’ of Flash
Add: F100h DQ=FBA
Wait for INT high State
Add: F241h DQ[15]=INT
Write 0 to Interrupt register4)
Add: F241h DQ=0000h
Write ‘FPA, FSA2)’ of Flash
Add: F107h DQ=FPA, FSA
Read Controller Status
Register
Add: F240h DQ[10]=Error
Write ‘Finish Cache Read
Command’ @ Final Read
Add: F220h DQ=000Ch
Write 0 to Interrupt register4)
Add: F241h DQ=0000h
No
DQ[10]=0?
Yes
Host reads data from
DataRAM6)
Write 0 to Interrupt register4)
Add: F241h DQ=0000h
Write ‘ Cache Read’ Command
Add: F220h DQ=000Eh
Wait for INT high State
Add: F241h DQ[15]=INT
Write ‘ Cache Read’ Command
Add: F220h DQ=000Eh
Read Controller Status
Register Add: F240h
DQ[15]=Ongo & DQ[13]=Load
Read Controller Status
Register
Host reads data from
DataRAM5)
Add: F240h DQ[10]=Error
No
DQ[15]=1 & DQ[13]=1 ?
Yes
No
DQ[10]=0?
Yes
Host reads data from
DataRAM
END
Map out
NOTE :
1) In case of first cycle cache read, BSA must be set to 1000 or 1100, and from second cycle cache read,
BSA will automatically be switched between DataRAM0 and DataRAM1.
2) BSC, FSA and FCSA must be set to "00".
3) These steps can also be set during INT=High, before next ’Cache Read Command’
4) ’Write 0 to interrupt register’ step may be ignored when using INT auto mode. Refer to chapter 2.8.18.1
5) When host reads data from DataRAM, host should start from the DataRAM of the first set BSA, and then next DataRAM alternately, as the number of Cache
Read.
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Cache Read Diagram
≈
≈
≈
≈
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3.9 Synchronous Burst Block Read Operation (RM=1,WM=X)
See Timing Diagram 6.3 and 6.4
OneNAND is internally composed of two DataRAMs and NAND Flash Array. And for host to read data from NAND Cell Array, load operation
which moves data from NAND Cell Array to DataRAM is required. After this load operation, host may use various read mode, such as
synchronous burst read or asynchronous read, to read data from OneNAND.
But these types of read mode require issuing of address and Load Command for each page, and CPU had the burden of calculating address
to be read. To solve this burden, Synchronous Burst Block Read Mode is introduced, which enables host to read the data of succeeding page
with CLK toggle, after initial address setting and command input. This Synchronous Burst Block Read is intended to transfer continuous mas-
sive data in NAND Flash Array at high speed, and it sequentially reads out data only from Main Area, where large sized data is stored.
The addresses set for Synchronous Burst Block Read is Start Page Address(FPA), Number of Page(FPC) and BSA. Note that the number of
page set by FPC should not exceed the block boundary, since page wrap-around is not supported. And from the start page address to desired
number of page, Synchronous Burst Block Read will output data by CLK toggle and CE enable/disable. FPC must be set from 3pages to
64pages. (Refer to 2.8.13)
The Host can access OneNAND during Synchronous Burst Block Read in between every 1-page of read cycle. When host accesses Dat-
aRAMs, the address of DataRAMs must be a multiple of 4 in order to prevent from data corruption. In doing this, INT pin or bit is used as indi-
cator signal. Thus, before host reads 1-page data from DataRAM, host must confirm INT pin or bit return low to high, and then enable CE to
read 1-page of data. And when host read operation for this 1-page is done, INT will automatically turn low. Note that INT auto mode is a man-
datory option for Synchronous Burst Block Read, and WE must always be set high throughout this opeartion.
Therefore, the steps are as follows;
1. Host will deassert CE of OneNAND after checking the indicator(INT pin / bit) turn low.
2. And then assert the CE of other device to perform another operation.
3. Then disable this other device by deasserting CE when desired operation is done.
4. Once the host confirms the INT pin or bit of OneNAND turn low to high, host may read the data of following page by asserting CE(refer to
synchronous burst block read operation timing).
Note that return of INT pin to high implies the internal load operation from NAND Flash Array to DataRAM is complete. Also, even when the
host is NOT accessing other device, this assert/deassert of CE step is neccessary.
Note that return of INT pin to high implies the internal load operation from NAND Flash Array to DataRAM is complete. Also, when the host is
not accessing other device, this assert/deassert of CE step is neccessary.
To read data from this loaded 1 page, same 4, 8, 16, 32, continuous (1K word) linear burst read operation of synchronous burst read may be
utilized.
In conclusion, by supporting indicator signal such as INT pin or bit, host may access other device without terminating continuous linear syn-
chronous burst block read, while using continuous linear burst read mode as synchronous block read within 1 block between every (n) page
and (n+1) page. (refer to synchronous burst block read boundary)
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3.9.1 Burst Address Sequence During Synchronous Burst Block Read Mode
In a Synchronous Burst Block Read, data is output with respect to a clock input.
OneNAND is capable of a continuous linear burst operation within one block size and a fixed-length linear burst operation of a preset length.
Note that only INT pin is valid indicator signal for continuous linear burst read operation but both INT pin and bit are valid for a fixed-length lin-
ear burst operation.
Same as the normal burst mode, the initial word will be output asynchronously, regardless of BRWL While the following words will be deter-
mined by BRWL value.
The latency is determined by the host based on the BRWL bit setting in the System Configuration 1 Register. The default BRWL is 4 latency
cycles. At clock frequencies of 40MHz or lower, latency cycles can be reduced to 3, at frequency range from 40MHz to 66MHz, latency cycle
should be over 4. And at 83MHz frequency, BRWL should be set to 6. BRWL can be set up to 7 latency cycles.
The BRWL registers can be read during a burst read mode by using the AVD signal with an address.
3.9.2 Continuous Linear Burst Read Operation During Synchronous Burst Block Read Mode
First Clock Cycle
The initial word is output at tIAA after the rising edge of the first CLK cycle. The RDY output indicates the initial word is ready to the system by
pulsing high. If the device is accessed synchronously while it is set to Asynchronous Read Mode, the first data can still be read out.
Subsequent Clock Cycles
Subsequent words are output (Burst Access Time from Valid Clock to Output) tBA after the rising edge of each successive clock cycle, which
automatically increments the internal address counter.
Terminating Synchronous Burst Block Read
The device will continue to output sequential burst data until the system resets (Cold/Warm/Hot Reset), wrapping around until it reaches the
designated address (see Section 3.9.1 for burst address sequence). Asserting WE low is prohibited during Synchronous Burst Block Read
operation.
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Synchronous Burst Block Read Boundary
Read Sequence for Single Plane Device
note that only main area data is read.
Page 0
.
.
.
Not supported
Page 63
Main Area
Spare Area
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3.9.3 4-, 8-, 16-, 32-, 1K- Word Linear Burst Read Operation During Synchronous Burst Block Read Mode
Same as normal linear burst read, synchronous burst block read enables a fixed number of words to be read from consecutive address.
The device supports a burst read from consecutive addresses of 4-, 8-, 16-, 32- and 1K-words with no wrap.
(note that wrap-around is not supported in Synchronous Burst Block Read)
3.9.4 Programmable Burst Read Latency Operation During Synchronous Burst Block Read Mode
Synchronous burst block read mode have progrmmable burst read latency just same manner as normal synchronous burst read mode.
Upon power up, the number of initial clock cycles from Valid Address (AVD) to initial data defaults to four clocks.
The number of clock cycles (n) which are inserted after the clock which is latching the address. The host can read the first data with the
(n+1)th rising edge.
The number of total initial access cycles is programmable from three to seven cycles. After the number of programmed burst clock cycles is
reached, the rising edge of the next clock cycle triggers the next burst data.
Four Clock Burst Read Latency (default condition)
Rising edge of the clock cycle following last read latency
triggers next burst data
CE
CLK
-1
0
1
2
3
4
AVD
tBA
Valid
Address
A0:
A15
DQ0:
DQ15
D6
D7
D0
D1
D2
D3
D7
D0
tIAA
tRDYS
OE
Hi-Z
Hi-Z
tRDYA
RDY
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3.9.5 Handshaking Operation During Synchronous Burst Block Read Mode
The handshaking feature allows the host system to simply monitor the RDY signal from the device to determine when the initial word of burst
data is ready to be read.
To set the number of initial cycles for optimal burst mode, the host should use the programmable burst read latency configuration (see Section
2.8.19, "System Configuration1 Register").
The rising edge of RDY which is derived at one cycle prior of data fetch clock indicates the initial word of valid burst data.
Synchronous Burst Block Read Operation Flow Chart
Start
Wait for INT register or PIN3)
Write ’FBA’ of Flash
Wait for INT register or PIN3)
high to low transition
high to low transition
Add: F100h DQ=FBA
Add: F241h DQ[15]=INT
Add: F241h DQ[15]=INT
Write ’FPA, FSA’ of Flash
Add: F107h DQ=FPA, FSA1)
Host may operate
another device while
Host may operate
another device while
CE of OneNAND is disabled5)
Write ’FPC’ of Flash
Add: F104h DQ=FPC
CE of OneNAND is disabled5)
Wait for INT register or PIN3)
low to high transition
Write ’BSA*, ’BSC’ of Flash1)
Add: F200h DQ=BSA, BSC
Wait for INT register or PIN3)
low to high transition
Add: F241h DQ[15]=INT
Add: F241h DQ[15]=INT
Write 0 to INT register or PIN2)3)
Add: F241h DQ=0000h
Host reads data from
DataRAM 14)
Host reads data from
DataRAM 04)
Write Synchronous Burst
Block Read Command
NO
Finished reading
final page set by FPC?
NO
Finished reading
final page set by FPC?
Add=F220h DQ=000Ah
YES
Wait for INT register or PIN3)
low to high transition
YES
Read Controller
Status Register
Add: F241h DQ[15]=INT
Add: F240h DQ[10]=1(Error)
Host reads data from
DataRAM 04)
NO
DQ[10]=0?
YES
Synchronous Burst Block
Read Fail
Synchronous Burst Block
Read Completed
NOTE :
1) These registers must be set as BSA=1000, BSC=00 and FSA=00.
2) INT auto mode is mandatory for Synchronous Burst Block Read Operation.
3) For the continuous synchronous burst block read, only INT PIN is availabe. For the other fixed number of words linear burst block read, both INT register and
INT pin are avilable.
4) While reading data from DataRAM, all normal synchronous burst read mode is supported for the main area.
5) At this time, host should disable the CE of OneNAND in order to operate another device. Even if host does not operate another device, CE should be disabled
during INT low.
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3.10 Synchronous Write(RM=1, WM=1)
See Timing Diagram 6.10
Burst mode operations enable high-speed synchronous read and write operations. Burst operations consist of a multi-clock sequence that
must be performed in an ordered fashion. After CE goes low, the address to access is latched on the next rising edge of clk that ADV is low.
During this first clock rising edge, WE indicates whether the operation is going to be a read (WE = high) or write (WE = low). The size of a
burst can be specified in the BL as either a fixed length or continuous. Fixed-length bursts consist of 4, 8, 16, and 32 words. Continuous burst
write has the ability to start at a specified address and burst within the designated DataRAM. The latency count stored in the BRWL defines
the number of clock cycles that elapse before the initial data value is transferred between the processor and OneNAND device.
The RDY output will be asserted as soon as a burst is initiated, and will be de-asserted to indicate when data is to be transferred into (or out
of) the memory. The processor can access other devices without incurring the timing penalty of the initial latency for a new burst by suspend-
ing burst mode. Bursts are suspended by stopping clk. clk can be stopped high or low. Note that the RDY output will continue to be active, and
as a result no other devices should directly share the RDY connection to the controller.
To continue the burst sequence, clk is restarted after valid data is available on the bus.
Same as the normal burst mode, the latency is determined by the host based on the BRWL bit setting in the System Configuration 1 Register.
The default BRWL is 4 latency cycles. At clock frequencies of 40MHz or lower, latency cycles can be reduced to 3, at frequency range from
40MHz to 66MHz, latency cycle should be over 4. And at 83MHz frequency, BRWL should be set to 6. BRWL can be set up to 7 latency
cycles.
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3.11 Program Operation
See Timing Diagram 6.13
The Program operation is used to program data from the on-chip BufferRAMs into the NAND FLASH memory array.
The device has two 2KB data buffers, each 1 Page (2KB + 64B) in size. Each page has 4 sectors of 512B each main area and 16B spare area.
The device can be programmed in units of 1~4 sectors.
The architecture of the DataRAMs permits a simultaneous data-write operation from the Host to one of data buffers and a program operation
from the other data buffer to the NAND Flash Array memory. Refer to Section 3.12.2, "Write While Program Operation", for more information.
Addressing for program operation
Within a block, the pages must be programmed consecutively from the LSB (least significant bit) page of the block to MSB (most significant
bit) pages of the block. Random page address programming is prohibited
(64)
(64)
Page 63
Page 31
Page 63
Page 31
:
:
(1)
:
(32)
:
(3)
(2)
(1)
Page 2
Page 1
Page 0
(3)
(32)
(2)
Page 2
Page 1
Page 0
Data register
Data register
From the LSB page to MSB page
DATA IN: Data (1)
Data (64)
Ex.) Random page program (Prohibition)
DATA IN: Data (1)
Data (64)
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Program Operation Flow Diagram
Write 0 to interrupt register2)
Start
Add: F241h DQ=0000h
Write Data into DataRAM1)
ADD: DP DQ=Data-in
Write ’Program’ Command
Add: F220h
DQ=0080h or 001Ah
NO
Data Input
Completed?
Wait for INT register
low to high transition
YES
Add: F241h DQ[15]=INT
Write ’FBA’ of Flash
Add: F100h DQ=FBA
Read Interrupt register
Add: F241h DQ[6]=WI
Write ’FPA, FSA’ of Flash
Add: F107h DQ=FPA, FSA
Read Controller
Status Register ‘Lock’ bit high
NO
DQ[6]=1?
YES
Add: F240h DQ[14]=Lock
Write ’BSA, BSC’ of DataRAM
Add: F200h DQ=BSA, BSC
Read Controller
Status Register
Add: F240h DQ[10]=Error
Program Lock Error
DQ[10]=0?
YES
NO
Program completed
Program Error
: If program operation results in an error, map out
the block including the page in error and copy the
target data to another block.
*
NOTE :
1) Data input could be done anywhere between "Start" and "Write Program Command".
2) ’Write 0 to interrupt register’ step may be ignored when using INT auto mode. Refer to chapter 2.8.18.1 .
During the execution of the Internal Program Routine, the host is not required to provide any further controls or timings. Furthermore, all com-
mands, except a Reset command, will be ignored. A reset during a program operation will cause data corruption at the corresponding location.
If a program error is detected at the completion of the Internal Program Routine, map out the block, including the page in error, and copy the
target data to another block. An error is signaled if DQ10 = "1" of Controller Status Register(F240h) .
Data input from the Host to the DataRAM can be done at any time during the Internal Program Routine after "Start" but before the "Write Pro-
gram Command" is written.
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3.12 Copy-Back Program Operation
The Copy-Back program is configured to quickly rewrite data stored in one page without utilizing memory other than OneNAND. Since the
time-consuming cycles of serial access and re-loading cycles are removed, the system performance is improved. The benefit is especially
obvious when a portion of block is updated and the rest of the block also need to be copied to the newly assigned free block.
Data from the source page is saved in one of the on-chip DataRAM buffers and then programmed directly into the destination page. The Dat-
aRAM is overwritten the previous data using the Buffer Sector Address (BSA) and Buffer Sector Count (BSC).
The Copy-Back Program Operation does this by performing sequential page-reads without a serial access and executing a copy-program
using the address of the destination page.
Copy-Back Program Operation Flow Chart
Write ’Copy-back Program’
command
Start
Add: F220h DQ=001Bh
Write ’FBA’ of Flash
Add: F100h DQ=FBA
Wait for INT register
low to high transition
Write ’FPA, FSA’ of Flash
Add: F107h DQ=FPA, FSA
Add: F241h DQ[15]=INT
Read Controller
Status Register
Write ’FCBA’ of Flash
Add: F102h DQ=FCBA
Add: F240h DQ[10]=Error
Write ’FCPA, FCSA’ of Flash
Add: F103h DQ=FCPA, FCSA
DQ[10]=0?
YES
NO
Write ’BSA, BSC’ of DataRAM
Add: F200h DQ=BSA, BSC1)
Copy back completed
Copy back Error
Write 0 to interrupt register
Add: F241h DQ=0000h
: If program operation results in an error, map out
the block including the page in error and copy the
target data to another block.
*
NOTE :
1) Selected DataRAM by BSA & BSC is used for Copy back operation, so previous data is overwritten.
2) FBA, FPA and FSA should be input prior to FCBA, FCPA and FCSA.
3) ’Write 0 to interrupt register’ step may be ignored when using INT auto mode. Refer to chapter 2.8.18.1
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The Copy-Back steps shown in the flow chart are:
• Data is read from the NAND Array using Flash Block Address (FBA), Flash Page Address (FPA) and
Flash Sector Address (FSA). FBA, FPA, and FSA identify the source address to read data from NAND Flash array.
• The BufferRAM Sector Count (BSC) and BufferRAM Sector Address (BSA) identifies how many sectors
and the location of the sectors in DataRAM that are used.
• The destination address in the NAND Array is written using the Flash Copy-Back Block Address (FCBA),
Flash Copy-Back Page Address (FCPA), and Flash Copy-Back Sector Address (FCSA).
• The Copy-Back Program command is issued to start programming.
• Upon completion of copy-back programming to the destination page address, the Host checks the status
to see if the operation was successfully completed. If there was an error, map out the block including the
page in error and copy the target data to another block.
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3.12.1 Copy-Back Program Operation with Random Data Input
The Copy-Back Program Operation with Random Data Input in OneNAND consists of 2 phase, Load data into DataRAM, Modify data and pro-
gram into designated page. Data from the source page is saved in one of the on-chip DataRAM buffers and modified by the host, then pro-
grammed into the destination page.
As shown in the flow chart, data modification is possible upon completion of load operation. ECC is also available at the end of load operation.
Therefore, using hardware ECC of OneNAND, accumulation of 1 bit error can be avoided.
Copy-Back Program Operation with Random Data Input will be effectively utilized at modifying certain bit, byte, word, or sector of source page
to destination page while it is being copied.
Copy-Back Program Operation with Random Data Input Flow Chart
NO
Map Out
DQ[10]=0?
Start
YES
Write ’FBA’ of Flash
Add: F100h DQ=FBA
Random Data Input
Add: Random Address in
Selected DataRAM
DQ=Data
Write ’FPA, FSA’ of Flash
Add: F107h DQ=FPA, FSA
DQ[10]=0?
NO
Write ‘FBA’ of Flash
Add: F100h DQ=FBA
YES
Write ’BSA, BSC’ of DataRAM
Add: F200h DQ=BSA, BSC
Copy back Error
Copy back completed
Write ‘FPA, FSA’ of Flash
Add: F107h DQ=FPA, FSA
Write 0 to interrupt register1)
Add: F241h DQ=0000h
Write 0 to interrupt register
Add: F241h DQ=0000h
Write ’Load’ Command
Add: F220h
DQ=0000h or 0013h
Write ‘Program’ Command
Add: F220h
DQ=0080h or 001Ah
Wait for INT register
low to high transition
Wait for INT register
low to high transition
Add: F241h DQ[15]=INT
Add: F241h DQ[15]=INT
Read Controller
Status Register
Read Interrupt register
Add: F241h DQ[6]=WI
Add: F240h DQ[10]=Error
Read Controller
Status Register ‘Lock’ bit high
NO
DQ[6]=1?
YES
Add: F240h DQ[14]=Lock
Read Controller
Status Register
Add: F240h DQ[10]=Error
Copy back Program Lock Error
NOTE :
1) ’Write 0 to interrupt register’ step may be ignored when using INT auto mode.
Refer to chapter 2.8.18.1
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3.13 Erase Operation
There are multiple methods for erasing data in the device including Block Erase and Multi-Block Erase.
3.13.1 Block Erase Operation
See Timing Diagram 6.14
The Block Erase Operation is done on a block basis. To erase a block is to write all 1's into the desired memory block by executing the Internal
Erase Routine. All previous data is lost.
Block Erase Operation Flow Chart
Start
Write ‘FBA’ of Flash
Add: F100h DQ=FBA
Write 0 to interrupt register1)
Add: F241h DQ=0000h
Write ‘Erase’ Command
Add: F220h DQ=0094h
Wait for INT register
low to high transition
Add: F241h DQ=[15]=INT
: If erase operation results in an error, map out
the failing block and replace it with another block.
*
Read Interrupt register
Add: F241h DQ[5]=EI
NO
Read Controller
Status Register ‘Lock’ bit high
DQ[5]=1?
YES
Add: F240h DQ[14]=Lock
Read Controller
Status Register
Add: F240h DQ[10]=Error
Erase Lock Error
DQ[10]=0?
YES
NO
Erase completed
Erase Error
NOTE :
1) ’Write 0 to interrupt register’ step may be ignored when using INT auto mode. Refer to chapter 2.8.18.1
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In order to perform the Internal Erase Routine, the following command sequence is necessary.
• The Host sets the block address of the memory location.
• The Erase Command initiates the Internal Erase Routine. During the execution of the Routine, the host is
not required to provide further controls or timings. During the Internal erase routine, all commands, except
the Reset command and Erase Suspend Command, written to the device will be ignored.
A reset during an erase operation will cause data corruption at the corresponding location.
3.13.2 Multi-Block Erase Operation
See Timing Diagram 6.14
Using Multi-Block Erase, the device can be erased up to 64 multiple blocks simultaneously.
Multiple blocks can be erased by issuing a Multi-Block Erase command and writing the block address of the memory location to be erased.
The final Flash Block Address (FBA) and Block Erase command initiate the internal multi block erase routine. During a Multi-Block Erase, the
OnGo bit of the Controller Status Register is set to '1'(busy) from the time that the first block address to be latched is written to the time that
the actual erase operation finishes.
During block address latch sequence, issuing of other commands except Block Erase, and Multi Block Erase at INT=High will abort the current
operation. So to speak, It will cancel the previously latched addresses of Multi Block Erase Operation.
On the other hand, Other command issue at INT=low will be ignored.
A reset during an erase operation will cause data corruption at the address location being operated on during the reset.
Despite a failed block during Multi-Block Erase operation, the device will continue the erase operation until all other specified blocks are
erased.
Erase Suspend Command issue during Multi Block Erase Address latch sequence is prohibited.
Locked Blocks
If there are locked blocks in the specified range, the Multi-Block Erase operation works as the follows.
Case 1: All specified blocks except BA(2) will be erased.
[BA(1)+0095h] + [BA((2), locked))+0095h] + ... + [BA(N-1)+0095h] + [BA(N)+0094h]
Case 2: Multi-Block Erase Operation fails to start if the last Block Erase command is put together with the locked block address until right com-
mand and address input are issued.
[BA(1)+0095h] + [BA(2)+0095h] + ... + [BA(N-1)+0095h] + [BA((N), locked)+0094h]
Case 3: All specified blocks except BA(N) are erased.
[BA(1)+0095h] + [BA(2)+0095h] + ... + [BA(N-1)+0095h] + [BA(N, locked)+0094h] + [BA(N+1)+0094h]
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3.13.3 Multi-Block Erase Verify Read Operation
After a Multi-Block Erase Operation, verify Erase Operation result of each block with Multi-Block Erase Verify Command combined with
address of each block.
If a failed address is identified, it must be managed by firmware.
Multi Block Erase/ Multi Block Erase Verify Read Flow Chart
Write ‘FBA’ of Flash
Add: F100h DQ=FBA
Start
Write ‘FBA’ of Flash
Add: F100h DQ=FBA
Write 0 to interrupt register2)
Add: F241h DQ=0000h
Write 0 to interrupt register
Add: F241h DQ=0000h
Write ‘Block Erase
Command’
Add: F220h DQ=0094h
Write ‘Multi Block Erase’
Command
Read Controller
Status Register
Wait for INT register
low to high transition
Add: F220h DQ=0095h
Add: F240h DQ[10]=Error
Add: F241h DQ[15]=INT
Wait for INT register
low to high transition
NO
DQ[10]=0?
Read Interrupt register
Add: F241h DQ[5]=EI
Add: F241h DQ[15]=INT
YES
Read Interrupt register
Add: F241h DQ[5]=EI
Erase completed
DQ[5]=1?
YES
Read Controller
Status Register
Erase Error
DQ[5]=1?
YES
Add: F240h DQ[10]=0
NO
Final Multi Block
Erase Address?
Read Controller
Status Register
Write ‘FBA’ of Flash
Add: F100h DQ=FBA
YES
Add: F240h DQ[10]=0
Multi Block Erase completed
Write 0 to interrupt register
Add: F241h DQ=0000h
NO
Final Multi Block
Erase?
Multi Block Erase Verify Read
YES
Write ‘Multi Block Erase
Verify Read Command’
Add: F220h DQ=0071h
Read Controller
Status Register ‘Lock’ bit high
NO
NO
Add: F240h DQ[14]=Lock
Wait for INT register
low to high transition
Multi block Erase Lock/
Erase Lock Error
Add: F241h DQ=[15]=INT
NOTE :
1) ’Write 0 to interrupt register’ step may be ignored when using INT auto mode. Refer to chapter 2.8.18.1
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3.13.4 Erase Suspend / Erase Resume Operation
The Erase Suspend/Erase Resume Commands interrupt and restart a Block Erase or Multi-Block Erase operation so that user may perform
another urgent operation on the block that is not being designated by Erase/Multi-Block Erase Operation.
Erase Suspend During a Block Erase Operation
When Erase Suspend command is written during a Block Erase or Multi-Block Erase operation, the device requires a maximum of 500us to
suspend erase operation. Erase Suspend Command issue during Block Address latch sequence is prohibited.
After the erase operation has been suspended, the device is ready for the next operation including a load, program, copy-back program, Lock,
Unlock, Lock-tight, Hot Reset, NAND Flash Core Reset, Command Based Reset, Multi-Block Erase Read Verify, or OTP Access.
The subsequent operation can be to any block that was NOT being erased.
A special case arises pertaining Erase Suspend to the OTP. A Reset command is used to exit from the OTP Access mode. If the Reset-trig-
gered exit from the OTP Access Mode happens during an Erase Suspend Operation, the erase routine could fail. Therefore to exit from the
OTP Access Mode without suspending the erase operation stop, a 'NAND Flash Core Reset' command should be issued.
For the duration of the Erase Suspend period the following commands are not accepted:
• Block Erase/Multi-Block Erase/Erase Suspend
Erase Suspend and Erase Resume Operation Flow Chart
Write 0 to interrupt register3)
Start
Add: F241h DQ=0000h
Write 0 to interrupt register3)
Write ’Erase Resume
Command’
Add: F241h DQ=0000h
Add: F220h DQ=0030h
Write ’Erase Suspend
Command’ 1)
Wait for INT register
low to high transition
Add: F220h DQ=00B0h
Add: F241h DQ=[15]=INT
Wait for INT register
low to high transition for 500us
Check Controller Status Register
in case of Block Erase
Add: F241h DQ=[15]=INT
Another Operation *
Do Multi Block Erase Verify Read
in case of Multi Block Erase
* Another Operation ; Load, Program
Copy-back Program, OTP Access2),
Hot Reset, Flash Reset, CMD Reset,
Multi Block Erase Verify, Lock,
Lock-tight, Unlock
NOTE :
1) Erase Suspend command input is prohibited during Multi Block Erase address latch period.
2) If OTP access mode exit happens with Reset operation during Erase Suspend mode,
Reset operation could hurt the erase operation. So if a user wants to exit from OTP access mode
without the erase operation stop, Reset NAND Flash Core command should be used.
3) ’Write 0 to interrupt register’ step may be ignored when using INT auto mode. Refer to chapter 2.8.18.1
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Erase Resume
When the Erase Resume command is executed, the Block Erase will restart. The Erase Resume operation does not actually resume the
erase, but starts it again from the beginning.
When an Erase Suspend or Erase Resume command is executed, the addresses are in Don't Care state.
For Multi Block Erase, Erase suspend/Resume can be operated after final Erase command (0094h) is issued. Therefore, Erase Resume oper-
ation does not actually resume from the erased block, but resumes the multi block erase from the beginning.
3.14 OTP Operation
One Block of the NAND Flash Array memory is reserved as a One-Time Programmable Block memory area.
Also, 1st Block of NAND Flash Array can be used as OTP.
The OTP block can be read, programmed and locked using the same operations as any other NAND Flash Array memory block.
OTP block cannot be erased.
OTP block is fully-guaranteed to be a valid block.
Entering the OTP Block
The OTP block is separately accessible from the rest of the NAND Flash Array by using the OTP Access command instead of the Flash Block
Address (FBA).
Exiting the OTP Block
To exit the OTP Access Mode, a Cold-, Warm-, Hot-, or NAND Flash Core Reset operation is performed.
Exiting the OTP Block during an Erase Operation
If the Reset-triggered exit from the OTP Access Mode happens during an Erase Suspend Operation, the erase routine could fail. Therefore to
exit from the OTP Access Mode without suspending the erase operation stop, a 'NAND Flash Core Reset' command should be issued.
The OTP Block Page Assignments
OTP area is one block size (128KB+4KB, 64 Pages) and is divided into two areas. The 50-page User Area is available as an OTP storage
area. The 14-page Manufacturer Area is programmed by the manufacturer prior to shipping the device to the user.
OTP Block Page Allocation Information
Area
User
Page
Use
0 ~ 49 (50 pages)
50 ~ 63 (14 pages)
Designated as user area
Used by the device manufacturer
Manufacturer
Three Possible OTP Lock Sequence (Refer to Chapter 3.14.3~3.14.5 for more information)
Since OTP Block and 1st Block OTP can be locked only by programming into 8th word of sector0, page0 of the spare memory area of OTP,
OTP Block and 1st Block OTP lock sequence is restricted into three following cases.
Note that user should be careful, because locking OTP Block before locking 1st Block OTP will disable locking 1st Block OTP.
1. OTP Block Lock Only :
Once the OTP Block is locked, 1st Block OTP Lock is impossible.
2. 1st Block OTP Lock, and then Lock OTP Block afterwards :
Locking 1st Block OTP does not lock the OTP block, so that OTP Block Lock can be performed thereafter.
3. OTP Block Lock and 1st Block OTP Lock simultaneously:
This simultaneous operation can be done by programming into 8th word of sector0, page0 of the spare memory area of OTP.
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OTP Block Area Structure
Page:2KB+64B
Sector(main area):512B
Manufacturer Area :
14pages
Sector(spare area):16B
page 50 to page 63
One Block:
64pages
128KB+4KB
User Area :
50pages
page 0 to page 49
1st Block OTP Area Structure
Page:2KB+64B
Sector(main area):512B
One Block:
64pages
Sector(spare area):16B
128KB+4KB
User Area :
64pages
page 0 to page 63
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3.14.1 OTP Block Load Operation
An OTP Block Load Operation accesses the OTP area and transfers identified content from the OTP to the DataRAM on-chip buffer,
thus making the OTP contents available to the Host.
The OTP area is a separate part of the NAND Flash Array memory. It is accessed by issuing OTP Access command(65h) instead of
a Flash Block Address (FBA) command.
After being accessed with the OTP Access Command, the contents of OTP memory area are loaded using the same operations
as a normal load operation to the NAND Flash Array memory (see section 3.6 for more information).
To exit the OTP access mode following an OTP Block Load Operation, a Cold-, Warm-, Hot-, or NAND Flash Core Reset operation is per-
formed.
OTP Block Read Operation Flow Chart
Start
Write 0 to interrupt register2)
Add: F241h DQ=0000h
Write ’FBA’ of Flash1)
Add: F100h DQ=FBA
Write 0 to interrupt register2)
Add: F241h DQ=0000h
Write ’Load’ Command
Add: F220h
DQ=0000h or 0013h
Write ’OTP Access’ Command
Add: F220h DQ=0065h
Wait for INT register
low to high transition
Add: F241h DQ[15]=INT
Wait for INT register
low to high transition
Add: F241h DQ[15]=INT
Host reads data from
DataRAM
Write ’FPA, FSA’ of Flash
Add: F107h DQ=FPA, FSA
OTP Reading completed
Write ’BSA, BSC’ of DataRAM
Add: F200h DQ=BSA, BSC
Do Cold/Warm/Hot
/NAND Flash Core Reset
OTP Exit
NOTE :
1) FBA(NAND Flash Block Address) could be omitted or any address.
2) ’Write 0 to interrupt register’ step may be ignored when using INT auto mode. Refer to chapter 2.8.18.1
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3.14.2 OTP Block Program Operation
An OTP Block Program Operation accesses the OTP area and programs content from the DataRAM on-chip buffer to the designated page(s)
of the OTP.
A memory location in the OTP area can be programmed only one time (no erase operation permitted).
The OTP area is programmed using the same sequence as normal program operation after being accessed by the command (see section 3.8
for more information).
Programming the OTP Area
• Issue the OTP Access Command
• Write data into the DataRAM (data can be input at anytime between the "Start" and "Write Program" commands
• Issue a Flash Block Address (FBA) which is unlocked area address of NAND Flash Array address map.
• Issue a Write Program command to program the data from the DataRAM into the OTP
• When the OTP Block programming is complete,
do a Cold-, Warm-, Hot-, NAND Flash Core Reset to exit the OTP Access mode.
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OTP Block Program Operation Flow Chart
Write ’FBA’ of Flash
Start
Add: F100h DQ=FBA3)
Write ’FBA’ of Flash1)
Add: F100h DQ=FBA
Write ’FPA, FSA’ of Flash
Add: F107h DQ=FPA, FSA
Write 0 to interrupt register4)
Add: F241h DQ=0000h
Write ’BSA, BSC’ of DataRAM
Add: F200h DQ=BSA, BSC
Write ’OTP Access’ Command
Add: F220h DQ=0065h
Write 0 to interrupt register4)
Add: F241h DQ=0000h
Wait for INT register
low to high transition
Write Program command
Add: F220h
Add: F241h DQ[15]=INT
DQ=0080h or 001Ah
Automatically
checked
Write Data into DataRAM2)
Add: DP DQ=Data-in
Automatically
updated
NO
OTPL=0?
YES
Update Controller
Status Register
NO
Data Input
Completed?
Wait for INT register
low to high transition
Add: F240h
DQ[14]=1(Lock), DQ[10]=1(Error)
Add: F241h DQ[15]=INT
Wait for INT register
low to high transition
Read Controller
Status Register
Add: F241h DQ[15]=INT
Add: F240h DQ[10]=0(Pass)
Read Controller
Status Register
OTP Programming completed
Add: F240h DQ[10]=1(Error)
Do Cold/Warm/Hot
/NAND Flash Core reset
Do Cold/Warm/Hot
/NAND Flash Core reset
OTP Exit
OTP Exit
NOTE :
1) FBA(NAND Flash Block Address) could be omitted or any address.
2) Data input could be done anywhere between "Start" and "Write Program Command".
3) FBA should point the unlocked area address among NAND Flash Array address map.
4) ’Write 0 to interrupt register’ step may be ignored when using INT auto mode. Refer to chapter 2.8.18.1
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3.14.3 OTP Block Lock Operation
Even though the OTP area can only be programmed once without erase capability, it can be locked when the device starts up to prevent any
changes from being made.
Unlike the main area of the NAND Flash Array memory, once the OTP block is locked, it cannot be unlocked, for locking bit for both
blocks lies in the same word of OTP area.
Therefore, if OTP Block is locked prior to 1st Block OTP lock, 1st Block OTP cannot be locked.
Locking the OTP
Programming to the OTP area can be prevented by locking the OTP area. Locking the OTP area is accomplished by programming XXFCh to
8th word of sector0 in page0 spare area in the OTP block.
At device power-up, this word location is checked and if XXFCh is found, the OTPL bit of the Controller Status Register is set to "1", indicating
the OTP is locked. When the Program Operation finds that the status of the OTP is locked, the device updates the Error Bit of the Controller
Status Register as "1" (fail).
OTP Lock Operation Steps
• Issue the OTP Access Command
• Fill data to be programmed into DataRAM (data can be input at anytime between the "Start" and "Write Program" commands)
• Write 'XXFCh' data into the 8th word of sector0 in page0 spare area of the DataRAM.
• Issue a Flash Block Address (FBA) which is unlocked area address of NAND Flash Array address map.
• Issue a Program command to program the data from the DataRAM into the OTP
• When the OTP lock is complete, do a Cold Reset to exit the OTP Access mode and update OTP lock bit[6].
• OTP lock bit[6] of the Controller Status Register will be set to "1" and the OTP will be locked.
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OTP Block Lock Operation Flow Chart
Write ’FBA’ of Flash
Start
Add: F100h DQ=FBA3)
Write ’FBA’ of Flash1)
Add: F100h DQ=FBA
Write ’FPA, FSA’ of Flash
Add: F107h DQ=0000h
Write 0 to interrupt register4)
Add: F241h DQ=0000h
Write ’BSA, BSC’ of DataRAM
Add: F200h DQ=0801h/0C01h
Write ’OTP Access’ Command
Add: F220h DQ=0065h
Write 0 to interrupt register4)
Add: F241h DQ=0000h
Wait for INT register
low to high transition
Write Program command
Add: F220h
DQ=0080h or 001Ah
Add: F241h DQ[15]=INT
Write Data into DataRAM2)
Wait for INT register
low to high transition
Add: 8th Word
in sector0/spare/page0
DQ=XXFCh
Add: F241h DQ[15]=INT
Do Cold reset
Automatically
updated
Update Controller
Status Register
Add: F240h
DQ[6]=1(OTPL)
OTP lock completed
NOTE :
1) FBA(NAND Flash Block Address) could be omitted or any address.
2) Data input could be done anywhere between "Start" and "Write Program Command".
3) FBA should point the unlocked area address among NAND Flash Array address map.
4) ’Write 0 to interrupt register’ step may be ignored when using INT auto mode. Refer to chapter 2.8.18.1
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3.14.4 1st Block OTP Lock Operation
1st Block could be used as OTP, for secured booting operation.
1st Block OTP can be accessed just as any other NAND Flash Array Blocks before it is locked, however, once 1st Block is locked to be OTP,
1st Block OTP cannot be erased or programmed.
Note that OTP Block can be locked freely after locking 1st Block OTP.
Locking the 1st Block OTP
Programming to the 1st Block OTP area can be prevented by locking the OTP area. Locking the OTP area is accomplished by
programming XXF3h to 8th word of sector0 in page0 spare area in the OTP block.
At device power-up, this word location is checked and if XXF3h is found, the OTPBL bit of the Controller Status Register is set to "1", indicating
the 1st Block is locked. When the Program Operation finds that the status of the 1st Block is locked, the device updates the Error Bit of the
Controller Status Register as "1" (fail).
1st Block OTP Lock Operation Steps
• Issue the OTP Access Command
• Fill data to be programmed into DataRAM (data can be input at anytime between the "Start" and "Write Program" commands)
• Write 'XXF3h' data into the 8th word of sector0 in page0 spare area of the DataRAM.
• Issue a Flash Block Address (FBA) which is unlocked area address of NAND Flash Array address map.
• Issue a Program command to program the data from the DataRAM into the OTP
• When the 1st Block OTP lock is complete, do a Cold Reset to exit the OTP Access mode
and update 1st Block OTP lock bit[5].
• 1st Block OTP lock bit[5] of the Controller Status Register will be set to "1" and the 1st Block will be locked.
Even though the OTP area can only be programmed once without erase capability, it can be locked when the device starts up to prevent any
changes from being made.
Unlike other remaining main area of the NAND Flash Array memory, once the 1st block OTP is locked, it cannot be unlocked.
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1st Block OTP Lock Operation Flow Chart
Write ’FBA’ of Flash
Start
Add: F100h DQ=FBA3)
Write ’FBA’ of Flash1)
Add: F100h DQ=FBA
Write ’FPA, FSA’ of Flash
Add: F107h DQ=0000h
Write 0 to interrupt register4)
Add: F241h DQ=0000h
Write ’BSA, BSC’ of DataRAM
Add: F200h DQ=0801h/0C01h
Write ’OTP Access’ Command
Add: F220h DQ=0065h
Write 0 to interrupt register4)
Add: F241h DQ=0000h
Wait for INT register
low to high transition
Write Program command
Add: F220h
DQ=0080h or 001Ah
Add: F241h DQ[15]=INT
Write Data into DataRAM2)
Wait for INT register
low to high transition
Add: 8th Word
in sector0/spare/page0
DQ=XXF3h
Add: F241h DQ[15]=INT
Do Cold reset
Automatically
updated
Update Controller
Status Register
Add: F240h
DQ[5]=1(OTPBL
)
1st Block OTP lock completed
NOTE :
1) FBA(NAND Flash Block Address) could be omitted or any address.
2) Data input could be done anywhere between "Start" and "Write Program Command".
3) FBA should point the unlocked area address among NAND Flash Array address map.
4) ’Write 0 to interrupt register’ step may be ignored when using INT auto mode. Refer to chapter 2.8.18.1
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3.14.5 OTP and 1st Block OTP Lock Operation
OTP and 1st Block can be locked simultaneously, for locking bit lies in the same word of OTP area.
1st Block OTP can be accessed just as any other NAND Flash Array Blocks before it is locked, however, once 1st Block is locked to be OTP,
1st Block OTP cannot be erased or programmed. Also, OTP area can only be programmed once without erase capability, it can be locked
when the device starts up to prevent any changes from being made.
Locking the OTP and 1st Block OTP
Programming to the OTP area and 1st Block OTP area can be prevented by locking the OTP area. Locking the OTP area is accomplished by
programming XXF0h to 8th word of sector0 in page0 spare area in the OTP block.
At device power-up, this word location is checked and if XXF0h is found, the OTPL and OTPBL bit of the Controller Status Register is set to "1",
indicating the OTP and 1st Block is locked. When the Program Operation finds that the status of the OTP and 1st Block is locked, the device
updates the Error Bit of the Controller Status Register as "1" (fail).
OTP and 1st Block OTP simultaneous Lock Operation Steps
• Issue the OTP Access Command
• Fill data to be programmed into DataRAM (data can be input at anytime between the "Start" and
"Write Program" commands)
• Write 'XXF0h' data into the 8th word of sector0 in page0 spare area of the DataRAM.
• Issue a Flash Block Address (FBA) which is unlocked area address of NAND Flash Array address map.
• Issue a Program command to program the data from the DataRAM into the OTP
• When the 1st Block OTP lock is complete, do a Cold Reset to exit the OTP Access mode
and update 1st Block OTP lock bit[5] and OTP lock bit[6].
• 1st Block OTP lock bit[5] and OTP lock bit[6] of the Controller Status Register will be set to "1" and
the OTP and 1st Block will be locked.
Even though the OTP area can only be programmed once without erase capability, it can be locked when the device starts up to prevent any
changes from being made.
Unlike other remaining main area of the NAND Flash Array memory, once the OTP block and the 1st block OTP are locked, it cannot be
unlocked.
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OTP and 1st Block OTP Lock Operation Flow Chart
Write ’FBA’ of Flash
Start
Add: F100h DQ=FBA3)
Write ’FBA’ of Flash1)
Add: F100h DQ=FBA
Write ’FPA, FSA’ of Flash
Add: F107h DQ=0000h
Write 0 to interrupt register4)
Add: F241h DQ=0000h
Write ’BSA, BSC’ of DataRAM
Add: F200h DQ=0801h/0C01h
Write ’OTP Access’ Command
Add: F220h DQ=0065h
Write 0 to interrupt register4)
Add: F241h DQ=0000h
Wait for INT register
low to high transition
Write Program command
Add: F220h
DQ=0080h or 001Ah
Add: F241h DQ[15]=INT
Write Data into DataRAM2)
Wait for INT register
low to high transition
Add: 8th Word
in sector0/spare/page0
DQ=XXF0h
Add: F241h DQ[15]=INT
Do Cold reset
Automatically
updated
Update Controller
Status Register
Add: F240h
DQ[6]=1(OTPL)
DQ[5]=1(OTPBL
)
OTP and 1st Block OTP lock completed
NOTE :
1) FBA(NAND Flash Block Address) could be omitted or any address.
2) Data input could be done anywhere between "Start" and "Write Program Command".
3) FBA should point the unlocked area address among NAND Flash Array address map.
4) ’Write 0 to interrupt register’ step may be ignored when using INT auto mode. Refer to chapter 2.8.18.1
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3.15 Dual Operations
The device has independent dual data buffers on-chip (except during the Boot Load period) that enables higher performance read and pro-
gram operation.
3.15.1 Read-While-Load Operation
This operation accelerates the read performance of the device by enabling data to be read out by the host from one DataRAM buffer while the
other DataRAM buffer is being loaded with data from the NAND Flash Array memory.
1) Data Load
2) Data Read
Data
Buffer0
Page A
3) Data Load
Data
Buffer1
Page B
2) Data Load
3) Data Read
The dual data buffer architecture provides the capability of executing a data-read operation from one of DataRAM buffers during a simulta-
neous data-load operation from Flash to the other buffer. Simultaneous load and read operation to same data buffer is prohibited. See sec-
tions 3.6 and 3.7 for more information on Load and Read Operations.
If host sets FBA, FSA, or FPA while loading into designated page, it will fail the internal load operation. Address registers should not be
updated until internal operation is completed.
3.15.2 Write-While-Program Operation
This operation accelerates the programming performance of the device by enabling data to be written by the host into one DataRAM buffer
while the NAND Flash Array memory is being programmed with data from the other DataRAM buffer.
1) Data Write
2) Program
Data
Page A
Buffer0
3) Data Write
Data
Buffer1
Page B
3) Program
2) Data Write
The dual data buffer architecture provides the capability of executing a data-write operation to one of DataRAM buffers during simultaneous
data-program operation to Flash from the other buffer. Simultaneous program and write operation to same data buffer is prohibited. See sec-
tions 3.8 for more information on Program Operation.
If host sets FBA, FSA, or FPA while programming into designated page, it will fail the internal program operation. Address registers should not
be updated until internal operation is completed.
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Read While Load Diagram
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Write While Program Diagram
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3.16 ECC Operation
The OneNAND device has on-chip ECC with the capability of detecting 2 bit errors and correcting 1-bit errors in the NAND Flash Array mem-
ory main and spare areas.
As the device transfers data from a BufferRAM to the NAND Flash Array memory Page Buffer for Program Operation, the device initiates a
background operation which generates an Error Correction Code (ECC) of 24bits for each sector main area data and 10bits for 2nd and 3rd
word data of each sector spare area.
During a Load operation from the NAND Flash Array memory Page, the on-chip ECC engine generates a new ECC. The 'Load ECC result' is
compared to the originally 'Program ECC' thus detecting the number and position of errors. Single-bit error is corrected.
ECC is updated by the device automatically. After a Load Operation, the Host can determine whether there was error by reading the 'ECC Sta-
tus Register' (refer to section 2.8.26).
Error types are divided into 'no error', '1bit correctable error', and '2bit error uncorrectable error'.
OneNAND supports 2bit EDC even though 2bit error seldom or never occurs. Hence, it is not recommended for Host to read 'ECC Status Reg-
ister' for checking ECC error because the built-in Error Correction Logic of OneNAND automatically corrects ECC error.
When the device reads the NAND Flash Array memory main and spare area data with an ECC operation, the device doesn't place the newly
generated ECC for main and spare area into the buffer. Instead it places the ECC which was generated and written during the program oper-
ation into the buffer.
An ECC operation is also done during the Boot Loading operation.
3.16.1 ECC Bypass Operation
In an ECC bypass operation, the device does not generate ECC as a background operation. The result does not indicate error position (refer
to the ECC Result Table).
In a Program Operation the ECC code to NAND Flash Array memory spare area is not updated.
During a Load operation, the on-chip ECC engine does not generate a new ECC internally. Also the ECC Status & Result to Registers are
invalid. The error is not corrected and detected by itself, so that ECC bypass operation is not recommended for host.
ECC bypass operation is set by the 9bit of System Configuration 1 Register (see section 2.8.19)
ECC Code and ECC Result by ECC Operation
Program operation
Load operation
Operation
ECC Code Update to NAND
Flash Array Spare Area
ECC Code at BufferRAM Spare
Area
ECC Status & Result Update
to Registers
1bit Error
Pre-written ECC code(1) loaded
Pre-written code(1) loaded
ECC operation
ECC bypass
Update
Update
Invalid
Correct
Not update
Not correct
NOTE :
1) Pre-written ECC code : ECC code which is previously written to NAND Flash Spare Area in program operation.
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OneNAND1Gb(KFG1G16Q2C-xEBx)
FLASH MEMORY
3.17 Invalid Block Operation
Invalid blocks are defined as blocks in the device's NAND Flash Array memory that contain one or more invalid bits whose reliability is not
guaranteed by Samsung.
The information regarding the invalid block(s) is called the Invalid Block Information. Devices with invalid block(s) have the same quality level
as devices with all valid blocks and have the same AC and DC characteristics.
An invalid block(s) does not affect the performance of valid block(s) because it is isolated from the bit line and the common source line by a
select transistor.
The system design must be able to mask out the invalid block(s) via address mapping. The 1st block, which is placed on 00h block address, is
always fully guaranteed to be a valid block.
Due to invalid marking, during load operation for indentifying invalid block, a load error may occur.
3.17.1 Invalid Block Identification Table Operation
A system must be able to recognize invalid block(s) based on the original invalid block information and create an invalid block table.
Invalid blocks are identified by erasing all address locations in the NAND Flash Array memory except locations where the invalid block(s) infor-
mation is written prior to shipping.
An invalid block(s) status is defined by the 1st word in the spare area. Samsung makes sure that either the 1st or 2nd page of every invalid
block has non-FFFFh data at the 1st word of sector0.
Since the invalid block information is also erasable in most cases, it is impossible to recover the information once it has been erased. Any
intentional erase of the original invalid block information is prohibited.
The following suggested flow chart can be used to create an Invalid Block Table.
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OneNAND1Gb(KFG1G16Q2C-xEBx)
FLASH MEMORY
Invalid Block Table Creation Flow Chart
Start
Set Block Address = 0
Increment Block Address
Check "FFFFh" at the 1st word of sector 0
of spare area in 1st and 2nd page
*
No
No
Check
Create (or update)
Invalid Block(s) Table
"FFFFh" ?
Yes
Last Block ?
Yes
End
3.17.2 Invalid Block Replacement Operation
Within its life time, additional invalid blocks may develop with NAND Flash Array memory. Refer to the device's qualification report for the
actual data.
The following possible failure modes should be considered to implement a highly reliable system.
In the case of a status read failure after erase or program, a block replacement should be done. Because program status failure
during a page program does not affect the data of the other pages in the same block, a block replacement can be executed with a page-sized
buffer by finding an erased empty block and reprogramming the current target data and copying the rest of the replaced block.
Block Failure Modes and Countermeasures
Failure Mode
Detection and Countermeasure sequence
Status Read after Erase --> Block Replacement
Erase Failure
Program Failure
Status Read after Program --> Block Replacement
Error Correction by ECC mode of the device
Single Bit Failure in Load Operation
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OneNAND1Gb(KFG1G16Q2C-xEBx)
FLASH MEMORY
Referring to the diagram for further illustration, when an error happens in the nth page of block 'A' during program operation, copy the data in
the 1st ~ (n-1)th page to the same location of block 'B' via data buffer0.
Then copy the nth page data of block 'A' in the data buffer1 to the nth page of block 'B' or any free block. Do not further erase or program block
'A' but instead complete the operation by creating an 'Invalid Block Table' or other appropriate scheme.
Block Replacement Operation Sequence
1st
1
{
(n-1)th
nth
an error occurs.
Data Buffer0 of the device
(page)
1
Data Buffer1 of the device
Block B
(assuming the nth page data is maintained)
1st
2
{
(n-1)th
nth
(page)
- 112 -
OneNAND1Gb(KFG1G16Q2C-xEBx)
FLASH MEMORY
4.0 DC CHARACTERISTICS
4.1 Absolute Maximum Ratings
Parameter
Symbol
Rating
Unit
Vcc
Voltage on any pin relative to VSS
All Pins
Vcc
-0.5 to + 2.45
-0.5 to + 2.45
-30 to +125
-65 to +150
5
V
VIN
Temperature Under Bias
Storage Temperature
Extended
Tbias
Tstg
°C
°C
Short Circuit Output Current
IOS
mA
TA (Extended Temp.)
TA (Industrial Temp.)
-30 to +85
-40 to +85
Recommended Operating Temperature
°C
NOTE :
1) Minimum DC voltage is -0.5V on Input/ Output pins. During transitions, this level should not fall to POR level(typ. 1.5V).
Maximum DC voltage may overshoot to Vcc+2.0V for periods <20ns.
2) Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to the conditions
detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
4.2 Operating Conditions
Voltage reference to GND
KFG1G16Q2C
Parameter
Symbol
Unit
Min
1.7
0
Typ.
1.8
0
Max
1.95
0
VCC-core / Vcc
VCC- IO / Vccq
VSS
V
V
Supply Voltage
NOTE :
1) Vcc-Core (or Vcc) should reach the operating voltage level prior to or at the same time as Vcc-IO (or Vccq).
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OneNAND1Gb(KFG1G16Q2C-xEBx)
FLASH MEMORY
4.3 DC Characteristics
RMS Value
Unit
Parameter
Symbol
Test Conditions
Min
Typ
Max
Input Leakage Current
Output Leakage Current
ILI
VIN=VSS to VCC, VCC=VCCmax
- 1.0
-
+ 1.0
µA
µA
VOUT=VSS to VCC, VCC=VCCmax,
CE or OE=VIH(Note 1)
ILO
- 1.0
-
-
+ 1.0
15
Active Asynchronous Read Current
(Note 2)
ICC1
CE=VIL, OE=VIH
8
mA
66MHz
83MHz
1MHz
-
-
-
-
-
-
15
20
3
25
30
4
mA
mA
mA
mA
mA
mA
Active Burst Read Current (Note 2)
Active Burst Write Current (Note 2)
ICC2R
CE=VIL, OE=VIH, WE=VIH
66MHz
83MHz
1MHz
15
20
3
25
30
4
ICC2W
ICC3
CE=VIL, OE=VIH, WE=VIL
CE=VIL, OE=VIH
Active Asynchronous Write Current
(Note 2)
-
8
15
mA
Active Load Current (Note 3)
Active Program Current (Note 3)
Active Erase Current (Note 3)
Multi Block Erase Current (Note 3)
Standby Current
ICC4
ICC5
ICC6
ICC7
ISB
CE=VIL, OE=VIH, WE=VIH
CE=VIL, OE=VIH, WE=VIH
CE=VIL, OE=VIH, WE=VIH
CE=VIL, OE=VIH, WE=VIH, 64blocks
CE= RP=VCC ± 0.2V
-
-
30
25
20
20
10
-
40
mA
mA
mA
mA
µA
V
-
30
-
25
-
25
-
50
Input Low Voltage
VIL
-0.5
0.4
Input High Voltage (Note 4)
Output Low Voltage
VIH
-
VCCq-0.4
-
-
VCCq+0.4
V
VOL
VOH
IOL = 100 µA ,VCC=VCCmin , VCCq=VCCqmin
IOH = -100 µA , VCC=VCCmin , VCCq=VCCqmin
-
0.2
-
V
Output High Voltage
VCCq-0.1
-
V
NOTE :
1) CE should be VIH for RDY. IOBE should be ’0’ for INT.
2) I active for Host access
CC
3) I active for Internal operation. (without host access)
CC
4) Vccq is equivalent to Vcc-IO.
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OneNAND1Gb(KFG1G16Q2C-xEBx)
FLASH MEMORY
5.0 AC CHARACTERISTICS
5.1 AC Test Conditions
Parameter
Value (66MHz)
0V to VCC
3ns
Value (83MHz)
0V to VCC
2ns
Input Pulse Levels
CLK
Input Rise and Fall Times
other inputs
5ns
2ns
VCC/2
VCC/2
Input and Output Timing Levels
Output Load
CL = 30pF
CL = 30pF
Device
Under
Test
VCC
Input & Output
VCC/2
VCC/2
Test Point
* CL = 30pF including scope
and Jig capacitance
0V
Input Pulse and Test Point
Output Load
5.2 Device Capacitance
CAPACITANCE(TA = 25 °C, VCC = 1.8V, f = 1.0MHz)
KFG1G16Q2C
Unit
Item
Input Capacitance
Symbol
Test Condition
Min
Max
10
CIN1
CIN2
COUT
CINT
VIN=0V
-
-
-
-
pF
pF
pF
pF
Control Pin Capacitance
Output Capacitance
INT Capacitance
10
VIN=0V
VOUT=0V
VOUT=0V
10
10
NOTE :
Capacitance is periodically sampled and not 100% tested.
5.3 Valid Block Characteristics
Parameter
Symbol
Min
Typ.
Max
1024
Unit
Blocks
Valid Block Number
NVB
1004
-
NOTE :
1) The device may include invalid blocks when first shipped. Additional invalid blocks may develop while being used. The number of valid blocks is presented with
both cases of invalid blocks considered. Invalid blocks are defined as blocks that contain one or more bad bits. Do not erase or program factory-marked bad
blocks.
2) The 1st block, which is placed on 00h block address, is guaranteed to be a valid block up to 1K program/erase cycles with 1bit/512Byte ECC.
- 115 -
OneNAND1Gb(KFG1G16Q2C-xEBx)
FLASH MEMORY
5.4 AC Characteristics for Synchronous Burst Read
See Timing Diagrams 6.1, 6.2 and 6.3.
66MHz
83MHz
Parameter
Symbol
Unit
Min
1
Max
66
-
Min
1
Max
83
-
Clock
CLK
tCLK
tIAA
MHz
ns
Clock Cycle
15
-
12
-
Initial Access Time
70
70
ns
Burst Access Time Valid Clock to Output
Delay
tBA
-
11
-
9
ns
AVD Setup Time to CLK
tAVDS
tAVDH
tACS
tACH
tBDH
tOE
5
2
5
6
3
-
-
-
4
2
4
6
2
-
-
-
ns
ns
ns
ns
ns
ns
ns
AVD Hold Time from CLK
Address Setup Time to CLK
Address Hold Time from CLK
Data Hold Time from Next Clock Cycle
Output Enable to Data
-
-
-
-
-
-
20
20
20
20
1)
CE Disable to Output & RDY High Z
-
-
tCEZ
1)
OE Disable to Output High Z
CE Setup Time to CLK
CLK High or Low Time
-
15
-
-
4.5
5
15
-
ns
ns
ns
ns
ns
ns
ns
tOEZ
tCES
6
tCLKH/L
tCLK/3
-
-
CLK 2) to RDY valid
tRDYO
-
-
11
11
-
-
9
CLK to RDY Setup Time
RDY Setup Time to CLK
CE low to RDY valid
tRDYA
tRDYS
tCER
-
9
4
-
3
-
15
-
15
NOTE :
1) If OE is disabled at the same time or before CE is disabled, the output will go to high-z by tOEZ.
If CE is disabled at the same time or before OE is disabled, the output will go to high-z by tCEZ.
If CE and OE are disabled at the same time, the output will go to high-z by tOEZ.
2) It is the following clock of address fetch clock.
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OneNAND1Gb(KFG1G16Q2C-xEBx)
FLASH MEMORY
5.5 AC Characteristics for Asynchronous Read
See Timing Diagrams 6.5, 6.6, 6.7 and 6.8.
KFG1G16Q2C
Parameter
Access Time from CE Low
Symbol
Unit
Max
Min
tCE
tAA
-
-
76
76
76
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
Asynchronous Access Time from AVD Low
Asynchronous Access Time from address valid
Read Cycle Time
tACC
tRC
-
76
12
7
6
-
AVD Low Time
tAVDP
tAAVDS
tAAVDH
tOE
-
Address Setup to rising edge of AVD
Address Hold from rising edge of AVD
Output Enable to Output Valid
-
-
20
20
CE Disable to Output & RDY High Z1)
tCEZ
tOEZ
-
OE Disable to Output High Z1)
CE Low to RDY Valid
-
-
15
15
-
ns
ns
ns
tCER
tWEA
WE Disable to AVD Enable
15
NOTE :
1) If OE is disabled at the same time or before CE is disabled, the output will go to high-z by tOEZ.
If CE is disabled at the same time or before OE is disabled, the output will go to high-z by tCEZ.
If CE and OE are disabled at the same time, the output will go to high-z by tOEZ.
These parameters are not 100% tested.
5.6 AC Characteristics for Warm Reset (RP), Hot Reset and NAND Flash Core Reset
Parameter
Symbol
Min
Max
Unit
tReady1
(BootRAM)
RP & Reset Command Latch to BootRAM Access
µs
-
5
tReady2
(NAND Flash Array)
RP & Reset Command Latch(During Load Routines) to INT High (Note1)
RP & Reset Command Latch(During Program Routines) to INT High (Note1)
RP & Reset Command Latch(During Erase Routines) to INT High (Note1)
-
-
-
10
20
µs
µs
µs
tReady2
(NAND Flash Array)
tReady2
(NAND Flash Array)
500
tReady2
(NAND Flash Array)
RP & Reset Command Latch(NOT During Internal Routines) to INT High (Note1)
µs
-
10
-
tRP
RP Pulse Width (Note2)
ns
200
NOTE :
1) These parameters are tested based on INT bit of interrupt register. Because the time on INT pin is related to the pull-up and pull-down resistor value.
2) The device may reset if tRP < tRP min(200ns), but this is not guaranteed.
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OneNAND1Gb(KFG1G16Q2C-xEBx)
FLASH MEMORY
5.7 AC Characteristics for Asynchronous Write
See Timing Diagrams 6.9.
Parameter
Symbol
Min
70
0
Max
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tWC
tAWES
tAH
WE Cycle Time
-
-
Address Setup Time
Address Hold Time
Data Setup Time
Data Hold Time
30
25
0
-
tDS
-
tDH
-
CE Setup Time
tCS
0
-
tCH
CE Hold Time
0
-
tWPL
tWPH
tCEZ
WE Pulse Width
WE Pulse Width High
40
30
-
-
-
CE Disable to Output & RDY High Z
20
5.8 AC Characteristics for Burst Write Operation
See Timing Diagrams 6.10 and 6.11.
66MHz
83MHz
Parameter
Symbol
Unit
Min
Max
Min
1
Max
CLK1)
Clock
1
66
-
83
-
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Clock Cycle
AVD Setup to CLK
15
12
4
t
CLK
AVDS
AVDH
5
-
-
t
AVD Hold Time from CLK
Address Setup Time to CLK
Address Hold Time from CLK
Data Setup Time to CLK
Data Hold Time from CLK
WE Setup Time to CLK
WE Hold Time from CLK
CLK High or Low Time
CE high pulse width
2
-
2
-
t
5
-
4
-
tACS
6
-
6
-
tACH
5
-
4
-
t
WDS
2
-
2
-
t
WDH
5
-
4
-
t
WES
WEH
CLKH/L
3
-
3
-
t
tCLK/3
-
5
-
t
10
-
-
10
-
-
tCEHP
CLK to RDY Valid
11
11
-
9
9
-
t
RDYO
CLK to RDY Setup Time
RDY Setup Time to CLK
CE low to RDY valid
-
-
tRDYA
4
-
3
tRDYS
15
-
15
tCER
Clock to CE disable
2
6
-
tCLK - 4.5
2
tCLK - 4.5
tCEH
CE Setup Time to CLK
CE Disable to Output & RDY High Z
-
4.5
-
-
tCES
20
20
tCEZ
NOTE :
1) Target Clock frequency is 83Mhz
- 118 -
OneNAND1Gb(KFG1G16Q2C-xEBx)
FLASH MEMORY
5.9 AC Characteristics for Load/Program/Erase Performance
See Timing Diagrams 6.12, 6.13, and 6.14
Parameter
Symbol
Min
Typ
23
Max
35
Unit
µs
Spare Load time(Note 1, Note2)
tRD1
-
-
-
Sector Load time(Note 1)
Page Load time(Note 1)
tRD2
30
45
µs
Spare Program time(Note 1, Note3)
Sector Program time(Note 1)
tPGM1
205
720
µs
tPGM2
tOTP
tLOCK
tABU
Page Pogram time(Note 1)
OTP Access Time(Note 1)
Lock/Unlock/Lock-tight (Note 1)
All Block Unlock Time (Note 1)
Erase Suspend Time(Note 1)
-
-
-
-
-
-
220
500
500
2
750
700
700
3
µs
ns
ns
µs
µs
ms
ms
tESP
400
1.5
4
500
2
tERS1
tERS2
1 Block
Erase Resume Time(Note 1)
2~64 Blocks
6
Number of Partial Program Cycles in the page (Including main and spare
area)
NOP
-
-
4
cycles
tBERS1
tBERS2
tRD3
1 Block
Block Erase time (Note 1)
-
-
-
1.5
4
2
6
ms
ms
µs
2~64 Blocks
Multi Block Erase Verify Read time(Note 1)
70
100
NOTE :
1) These parameters are tested based on INT bit of interrupt register. Because the time on INT pin is related to the pull-up and pull-down resistor value.
2) Spare Load time is little bit less than Sector Load time.
3) Spare Program time is same as Sector program time.
4) 2/3 sector Load/Program time is between Sector Load/Progrma time and Page Load/Program time.
5.10 AC Characteristics for INT Auto Mode
See Timing Diagrams 6.20
Parameter
Symbol
Min
Max
Unit
Command Input to INT Low
-
200
ns
t
WB
5.11 AC Characteristics for Synchronous Burst Block Read
See Timing Diagrams 6.4
Parameter
Symbol
Typ.
Max
Unit
INT Low Period During Synch Burst Block Read
1
-
us
t
INTL
- 119 -
OneNAND1Gb(KFG1G16Q2C-xEBx)
6.0 TIMING DIAGRAMS
FLASH MEMORY
6.1 8-Word Linear Burst Read Mode with Wrap Around
See AC Characteristics Table 5.4
BRWL=4
tCES
tCLKL
tCLKH
tCLK
CE
tCER
tCEZ
-1
0
1
2
3
4
CLK
tAVDS
tRDYO
AVD
tAVDH
tBDH
D2
tACS
tACH
A0-A15
tBA
D0
DQ0-DQ15
D6
D7
D0
D1
D3
D7
tOEZ
tIAA
tOE
OE
tRDYS
tRDYA
Hi-Z
Hi-Z
RDY
6.2 Continuous Linear Burst Read Mode with Wrap Around
See AC Characteristics Table 5.4
BRWL=4
tCLK
tCES
CE
tCER
tCEZ
-1
0
1
2
3
4
CLK
tAVDS
tRDYO
AVD
tAVDH
tBDH
tACS
A0-A15
tBA
tACH
DQ0-DQ15
Da
Da+1 Da+2 Da+3 Da+4 Da+5
Da+n Da+n+1
tOEZ
tIAA
tOE
OE
tRDYS
Hi-Z
Hi-Z
tRDYA
RDY
- 120 -
OneNAND1Gb(KFG1G16Q2C-xEBx)
FLASH MEMORY
6.3 Synchronous Burst Block Read Operation Timing
See AC Characteristics table 5.4 and 5.7.
- 121 -
OneNAND1Gb(KFG1G16Q2C-xEBx)
FLASH MEMORY
6.4 Synchronous Burst Block Read Timing
See AC Characteristics table 5.11
Case 1 : BL=1K word synchronous burst block read
- 122 -
OneNAND1Gb(KFG1G16Q2C-xEBx)
FLASH MEMORY
Case 2 : Host reads INT bit for Ready/Busy State indicator
≈
≈ ≈ ≈
≈
≈ ≈ ≈
≈
≈
- 123 -
OneNAND1Gb(KFG1G16Q2C-xEBx)
FLASH MEMORY
6.5 Asynchronous Read (VA Transition Before AVD Low)
See AC Characteristics Table 5.5
VIL
CLK
CE
tCEZ
tAVDP
AVD
tOE
OE
WE
tCE
tOEZ
DQ0-DQ15
Valid RD
tAAVDH
A0-A15
VA
Hi-Z
Hi-Z
RDY
NOTE :
VA=Valid Read Address, RD=Read Data.
6.6 Asynchronous Read (VA Transition After AVD Low)
See AC Characteristics Table 5.5
VIL
CLK
CE
tCEZ
tAA
tAVDP
AVD
tOE
OE
tWEA
WE
tOEZ
DQ0-DQ15
Valid RD
tAAVDH
A0-A15
VA
Hi-Z
Hi-Z
RDY
NOTE :
VA=Valid Read Address, RD=Read Data.
- 124 -
OneNAND1Gb(KFG1G16Q2C-xEBx)
FLASH MEMORY
6.7 Asynchronous Read (VA and AVD Transition After CE Low)
See AC Characteristics Table 5.5
VIL
CLK
CE
tCEZ
tAVDP
AVD
tAAVDS
tOE
OE
tWEA
WE
tOEZ
DQ0-DQ15
Valid RD
tAAVDH
tACC
A0-A15
VA
Hi-Z
Hi-Z
RDY
NOTE :
VA=Valid Read Address, RD=Read Data.
6.8 Asynchronous Read (AVD is tied to CE)
See AC Characteristics Table 5.5
VIL
CLK
tRC
CE
tCEZ
tOE
OE
WE
DQ0-DQ15
A0-A15
tCE
tOEZ
Valid RD
tACC
VA
Hi-Z
Hi-Z
RDY
NOTE :
VA=Valid Read Address, RD=Read Data.
- 125 -
OneNAND1Gb(KFG1G16Q2C-xEBx)
FLASH MEMORY
6.9 Asynchronous Write
See AC Characteristics Table 5.7
VIL
CLK
tCS
tCH
tCS
CE
tWPL
tWPH
WE
tWC
OE
RP
tAH
A0-A15
VA
VA
tDS
tDH
tAWES
DQ0-
DQ15
Valid WD
Valid WD
Hi-Z
Hi-Z
RDY
NOTE :
VA=Valid Read Address, WD=Write Data
- 126 -
OneNAND1Gb(KFG1G16Q2C-xEBx)
FLASH MEMORY
6.10 8-Word Linear Burst Write Mode
See AC Characteristics Table 5.8
BRWL = 4
tCEH tCEZ
tCES
tCLK
tCLKH
tCLKL
CE
tCER
-1
0
1
2
3
4
CLK
AVD
tRDYO
tAVDS
tAVDH
tACS
tACH
A0~
A15
tWDS
D1
tWDH
DQ0~
DQ15
D0
D2
D3
D4
D5
D7
OE
tWES
WE
tWEH
tRDYA
Hi-Z
Hi-Z
RDY
tRDYS
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OneNAND1Gb(KFG1G16Q2C-xEBx)
FLASH MEMORY
6.11 Start Initial Burst Write Operation
See AC Characteristics Table 5.8
BRWL = 4
BRWL = 4
tCEHP
tCES
tCLK
tCLKH tCLKL
tCEH
CE
tCER
tCEZ
-1
0
1
2
3
4
CLK
AVD
tRDYO
tAVDS
tAVDH
tACS
tACH
A0~
A15
tWDS tWDH
D0
DQ0~
DQ15
D0
OE
tWES
WE
tWEH
tRDYS
tRDYA
Hi-Z
RDY
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OneNAND1Gb(KFG1G16Q2C-xEBx)
FLASH MEMORY
6.12 Load Operation Timing
See AC Characteristics Tables 5.7 and 5.9
Load Command Sequence
Read Data
tAH
tAWES
A0:A15
AA
CA
BA
BA
DQ0-DQ15
Da
Da+1
LMA
LCD
tDS
tCH
tCS
tDH
CE
OE
WE
tCH
tWPL
tWPH
tRD1 or tRD2
tCS
tWC
VIL
CLK
INT
NOTE :
1) AA = Address of address register
CA = Address of command register
LCD = Load Command
LMA = Address of memory to be loaded
BA = Address of BufferRAM to load the data
BD = Program Data
SA = Address of status register
2) “In progress” and “complete” refer to status register
3) Status reads in this figure is asynchronous read, but status read in synchronous mode is also supported.
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OneNAND1Gb(KFG1G16Q2C-xEBx)
FLASH MEMORY
6.13 Program Operation Timing
See AC Characteristics Tables 5.7 and 5.9
Program Command Sequence (last two cycles)
Read Status Data
tAH
tAWES
A0:A15
AA
BA
tCS
CA
tCS
SA
SA
AA*
In
DQ0-DQ15
Complete
PMB
PMA
tCH
BD
tCH
PCD
Progress
tDH
tDS
CE
OE
WE
tCH
tWPL
tWPH
tCS
tPGM1 or tPGM2
tWC
VIL
CLK
INT
NOTE :
1) AA = Address of address register
CA = Address of command register
PCD = Program Command
PMA = Address of memory to be programmed
BA = Address of BufferRAM to load the data
BD = Program Data
SA = Address of status register
AA* = Address of Start Address1 Register(for Flash Block Address)
PMB = DFS & FBA(Flash Block address) of memory to be programmed next time
2) “In progress” and “complete” refer to status register
3) Status reads in this figure is asynchronous read, but status read in synchronous mode is also supported.
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OneNAND1Gb(KFG1G16Q2C-xEBx)
FLASH MEMORY
6.14 Block Erase Operation Timing
See AC Characteristics Tables 5.7 and 5.9
Erase Command Sequence (last two cycles)
Read Status Data
tAWES
tAH
AA*
A0:A15
DQ0-DQ15
CE
AA
CA
SA
SA
In
PMB
Complete
EMA
tCH
ECD
tDS
Progress
tCS
tDH
tCH
OE
tWPL
WE
tWPH
tBERS1
tCS
tWC
VIL
CLK
INT
NOTE :
1) AA = Address of address register
CA = Address of command register
ECD = Erase Command
EMA = Address of memory to be erased
SA = Address of status register
AA* = Address of Start Address1 Register(for Flash Block Address)
PMB = DFS & FBA(Flash Block address) of memory to be programmed next time
2) “In progress” and “complete” refer to status register
3) Status reads in this figure is asynchronous read, but status read in synchronous mode is also supported.
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OneNAND1Gb(KFG1G16Q2C-xEBx)
FLASH MEMORY
6.15 Cold Reset Timing
POR triggering level
System Power
1)
Bootcode - copy done
Idle
OneNAND
Operation
Sleep
Bootcode copy
2)
RP
High-Z
INT
3)
INT bit
0 (default)
1
IOBE bit
0 (default)
1 (default)
1
INTpol bit
NOTE :
1) Bootcode copy operation starts 400us later than POR activation.
The system power should reach 1.7V after POR triggering level(typ. 1.5V) within 400us for valid boot code data.
2) 1K bytes Bootcode copy takes typically 500us(max. 2ms) from sector0 and sector1/page0/block0 of NAND Flash array to BootRAM.
Host can read Bootcode in BootRAM(1K bytes) after Bootcode copy completion.
3) INT register goes ‘Low’ to ‘High’ on the condition of ‘Bootcode-copy done’ and RP rising edge.
If RP goes ‘Low’ to ‘High’ before ‘Bootcode-copy done’, INT register goes to ‘Low’ to ‘High’ as soon as ‘Bootcode-copy done’
- 132 -
OneNAND1Gb(KFG1G16Q2C-xEBx)
FLASH MEMORY
6.16 Warm Reset Timing
See AC Characteristics Table 5.6
CE, OE
RP
tRP
tReady1
High-Z
High-Z
RDY
tReady2
INT
bit
Operation
Status
1)
2)
3)
4)
1)
Idle
Reset Ongoing
BootRAM Access
INT Bit Polling
Idle
NOTE :
1) The status which can accept any register based operation(Load, Program, Erase command, etc).
2) The status where reset is ongoing.
3) The status allows only BootRAM(BL1) read operation for Boot Sequence.(refer to 7.2.2 Boot Sequence)
4) To read BL2 of Boot Sequence, Host should wait INT until becomes ready. and then, Host can issue load command.
(refer to 7.2.2 Boot Sequence, 7.1 Methods of Determing Interrupt status)
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OneNAND1Gb(KFG1G16Q2C-xEBx)
FLASH MEMORY
6.17 Hot Reset Timing
See AC Characteristics Table 5.6
AVD
BP(Note 3)
or F220h
A0~A15
00F0h
DQ0~DQ15
or 00F3h4)
CE
OE
WE
tReady2
INT
bit
High-Z
RDY
OneNAND
Idle
Operation or Idle
Operation
OneNAND reset
NOTE :
1) Internal reset operation means that the device initializes internal registers and makes output signals go to default status and bufferRAM data are kept
unchanged after Warm/Hot reset operations.
2) Reset command : Command based reset or Register based reset
3) BP(Boot Partition): BootRAM area [0000h~01FFh, 8000h~800Fh]
4) 00F0h for BP, and 00F3h for F220h
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OneNAND1Gb(KFG1G16Q2C-xEBx)
FLASH MEMORY
6.18 NAND Flash Core Reset Timing
See AC Characteristics Table 5.6
AVD
F220h
A0~A15
DQ0~DQ15
CE
00F0h
OE
WE
tReady2
INT
bit
High-Z
RDY
OneNAND
Operation
Idle
Operation or Idle
NAND Flash Core reset
6.19 Data Protection Timing During Power Down
The device is designed to offer protection from any involuntary program/erase during power-transitions. RP pin provides hardware protection
and is recomended to be kept at VIL before Vcc drops to 1.5V
typ. 1.5V
VCC
0V
RP
INT
OneNAND
Operation
OneNAND Logic Reset & NAND Array Write Protected
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OneNAND1Gb(KFG1G16Q2C-xEBx)
FLASH MEMORY
6.20 INT auto mode
See AC Characteristics Table 5.10
tWB
INT pin
INT bit
INT will automatically
turn to Busy State
Write command into
Command Register
INT will automatically turn back to ready state
when designated operation is completed.
WE
DQ
. . .
. . . . . . . . . .
CMD
NOTE :
INT pin polarity is based on ’IOBE=1 and INT pol=1 (default)’ setting
- 136 -
OneNAND1Gb(KFG1G16Q2C-xEBx)
FLASH MEMORY
7.0 TECHNICAL AND APPLICATION NOTES
From time-to-time supplemental technical information and application notes pertaining to the design and operation of the device in a system
are included in this section. Contact your Samsung Representative to determine if additional notes are available.
7.1 Methods of Determining Interrupt Status
There are two methods of determining Interrupt Status on the OneNAND. Using the INT pin or monitoring the Interrupt Status Register Bit.
The OneNAND INT pin is an output pin function used to notify the Host when a command has been completed. In ’Cache Read’, ’Synchro-
nous Burst Block Read’, INT pin notifies that only trasferring from DataRAM to page buffer is completed. This provides a hardware method of
signaling the completion of a program, erase, or load operation.
In its normal state, the INT pin is high if the INT polarity bit is default. In case of normal INT mode, before a command is written to the com-
mand register, the INT bit must be written to '0' so the INT pin transitions to a low state indicating start of the operation. In case of ’INT auto
mode’, INT bit is written to ’0’ automatically right after command issued. Upon completion of the command operation by the OneNAND’s inter-
nal controller, INT returns to a high state.
INT pin is a DQ-type output allowing two INT outputs to be Or-tied together. Refer to section 2.8 for additional information about INT. At previ-
ous 1Gb OneNAND, INT pin operates as an open-drain type. But at current 1Gb B-die OneNAND, INT pin operates as a DQ-type which has
faster responsiveness than open drain type. Although DQ-type INT pin is connected to pull-up resistor, DQ-type INT pin will not be affected by
the resistor.
INT can be implemented by tying INT to a host GPIO or by continuous polling of the Interrupt status register.
INT Type (Mono)
General Operation
DQ type
- 137 -
OneNAND1Gb(KFG1G16Q2C-xEBx)
FLASH MEMORY
7.1.1 The INT Pin to a Host General Purpose I/O
INT can be tied to a Host GPIO to detect the rising edge of INT, signaling the end of a command operation.
COMMAND
INT
This can be configured to operate either synchronously or asynchronously as shown in the diagrams below.
Synchronous Mode Using the INT Pin
When operating synchronously, INT is tied directly to a Host GPIO. RDY could be conneceted as one of following guides.
Host
CE
OneNAND
Host
CE
OneNAND
CE
CE
AVD
CLK
RDY
OE
AVD
CLK
RDY
OE
CLK
RDY(WAIT)
OE
CLK
OE
GPIO
INT
GPIO
INT
Handshaking Mode
Non-Handshaking Mode
Asynchronous Mode Using the INT Pin
When configured to operate in an asynchronous mode, CE and AVD of the OneNAND are tied to CE of the Host. CLK is tied to the Host Vss
(Ground). RDY is NOT connected. OE of the OneNAND and Host are tied together and INT is tied to a GPIO.
Host
CE
OneNAND
CE
AVD
CLK
RDY
OE
Vss
OE
GPIO
INT
- 138 -
OneNAND1Gb(KFG1G16Q2C-xEBx)
FLASH MEMORY
7.1.2 Polling the Interrupt Register Status Bit
An alternate method of determining the end of an operation is to continuously monitor the Interrupt Status Register Bit instead of using the INT
pin.
When using interrupt register instead of INT pin, INT pin is recommended to float to avoid power consumption at IOBE=0(disable).
Command
INT
This can be configured in either a synchronous mode or an asynchronous mode.
Synchronous Mode Using Interrupt Status Register Bit Polling
When operating synchronously, CE and AVD of the OneNAND are tied to CE of the Host, CLK, OE, and DQ pins on the host and OneNAND
are tied together. RDY could be connected as one of following guides.
Host
CE
OneNAND
Host
CE
OneNAND
CE
CE
AVD
CLK
RDY
OE
AVD
CLK
RDY
OE
CLK
RDY(WAIT)
OE
CLK
OE
DQ
DQ
DQ
DQ
Handshaking Mode
Non-Handshaking Mode
Asynchronous Mode Using Interrupt Status Register Bit Polling
When configured to operate in an asynchronous mode, CE and AVD of the OneNAND are tied to CE of the Host. CLK is tied to the Host Vss
(Ground). RDY is NOT connected. OE and DQ of the OneNAND and Host are tied together.
Host
CE
OneNAND
CE
AVD
CLK
RDY
OE
Vss
N.C
OE
DQ
DQ
- 139 -
OneNAND1Gb(KFG1G16Q2C-xEBx)
FLASH MEMORY
7.2 Boot Sequence
One of the best features OneNAND has is that it can be a booting device itself since it contains an internally built-in boot loader despite the
fact that its core architecture is based on NAND Flash. Thus, OneNAND does not make any additional booting device necessary for a system,
which imposes extra cost or area overhead on the overall system.
As the system power is turned on, the boot code originally stored in NAND Flash Array is moved to BootRAM automatically and then fetched
by CPU through the same interface as SRAM’s or NOR Flash’s if the size of the boot code is less than 1KB. If its size is larger than 1KB and
less than or equal to 3KB, only 1KB of it can be moved to BootRAM automatically and fetched by CPU, and the rest of it can be loaded into
one of the DataRAMs whose size is 2KB by Load Command and CPU can take it from the DataRAM after finishing the code-fetching job for
BootRAM. If its size is larger than 3KB, the 1KB portion of it can be moved to BootRAM automatically and fetched by CPU, and its remaining
part can be moved to DRAM through two DataRAMs using dual buffering and taken by CPU to reduce CPU fetch time.
A typical boot scheme usually used to boot the system with OneNAND is explained at Partition of NAND Flash Array and OneNAND Boot
Sequence. In this boot scheme, boot code is comprised of BL1, where BL stands for Boot Loader, BL2, and BL3. Moreover, the size of the
boot code is larger than 3KB (the 3rd case above). BL1 is called primary boot loader in other words. Here is the table of detailed explanations
about the function of each boot loader in this specific boot scheme.
7.2.1 Boot Loaders in OneNAND
Boot Loaders in OneNAND
Boot Loader
BL1
Description
Moves BL2 from NAND Flash Array to DRAM through two DataRAMs using dual buffering
Moves OS image (or BL3 optionally) from NAND Flash Array to DRAM through two DataRams using dual buffering
Moves or writes the image through USB interface
BL2
BL3 (Optional)
NAND Flash Array of OneNAND is divided into the partitions as described at Partition of NAND Flash Array to show where each component of
code is located and how much portion of the overall NAND Flash Array each one occupies. In addition, the boot sequence is listed below and
depicted at Boot Sequence.
7.2.2 Boot Sequence
Boot Sequence :
1. Power is on
BL1 is loaded into BootRAM
2. BL1 is executed in BootRAM
BL2 is loaded into DRAM through two DataRams using dual buffering by BL1
3. BL2 is executed in DRAM
OS image is loaded into DRAM through two DataRams using dual buffering by BL2
4. OS is running
- 140 -
OneNAND1Gb(KFG1G16Q2C-xEBx)
FLASH MEMORY
Block 1023
Reservoir
Partition 6
Partition 5
Sector 0 Sector 1 Sector 2 Sector 3
File System
Page 63
Page 62
Block 162
:
:
Os Image
BL3
Partition 4
Partition 3
Block 2
Block 1
Block 0
Page 2
Page 1
Page 0
NBBLL11
BL2
BL1
Partition of NAND Flash array
Reservoir
File System
step 3
Data Ram 1
Os Image
Data Ram 0
Os Image
BL 2
Boot Ram(BL 1)
BL1
BL2
step 2
step 1
NAND Flash Array
Internal BufferRAM
OneNAND
DRAM
NOTE :
Step 2 and Step 3 can be copied into DRAM through two DataRAMs using dual buffering
OneNAND Boot Sequence
- 141 -
OneNAND1Gb(KFG1G16Q2C-xEBx)
8.0 PACKAGE DIMENSIONS
FLASH MEMORY
#A1 INDEX
A
10.00±0.10
0.10 MAX
10.00±0.10
0.80x9=7.20
(Datum A)
B
6
5
4
3
2 1
#A1
A
(Datum B)
B
0.80
C
D
E
F
G
H
3.60
0.32±0.05
0.9±0.10
BOTTOM VIEW
TOP VIEW
63-
∅ 0.45±0.05
∅
0.20
M A B
1Gb product (KFG1G16Q2C)
- 142 -
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