KFG2816U1M-DEB [SAMSUNG]
OneNAND SPECIFICATION; OneNAND闪存规格型号: | KFG2816U1M-DEB |
厂家: | SAMSUNG |
描述: | OneNAND SPECIFICATION |
文件: | 总87页 (文件大小:1176K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
OneNAND128
FLASH MEMORY
OneNAND SPECIFICATION
Product
Part No.
VCC(core & IO)
1.8V(1.7V~1.95V)
2.65V(2.4V~2.9V)
3.3V(2.7V~3.6V)
Temperature
Extended
Extended
Industrial
PKG
KFG2816Q1M-DEB
KFG2816D1M-DEB
KFG2816U1M-DIB
67FBGA(LF)/48TSOP1
67FBGA(LF)/48TSOP1
67FBGA(LF)/48TSOP1
OneNAND128
Version: Ver. 1.0
Date: June 15th, 2005
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OneNAND128
FLASH MEMORY
INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS,
AND IS SUBJECT TO CHANGE WITHOUT NOTICE.
NOTHING IN THIS DOCUMENT SHALL BE CONSTRUED AS GRANTING ANY LICENSE,
EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE,
TO ANY INTELLECTUAL PROPERTY RIGHTS IN SAMSUNG PRODUCTS OR TECHNOLOGY. ALL
INFORMATION IN THIS DOCUMENT IS PROVIDED
ON AS "AS IS" BASIS WITHOUT GUARANTEE OR WARRANTY OF ANY KIND.
1. For updates or additional information about Samsung products, contact your nearest Samsung office.
2. Samsung products are not intended for use in life support, critical care, medical, safety equipment, or similar
applications where Product failure could result in loss of life or personal or physical harm, or any military or
defense application, or any governmental procurement to which special terms or provisions may apply.
OneNAND™‚ is a trademark of Samsung Electronics Company, Ltd. Other names and brands may be claimed as the property of their
rightful owners.
Copyright © 2005, Samsung Electronics Company, Ltd
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OneNAND128
FLASH MEMORY
Document Title
OneNAND
Revision History
Revision No. History
Draft Date
Remark
0.0
1. Initial Issue.
Sep. 9, 2004
Advance
0.1
1. Corrected the errata
Oct. 28, 2004
Advance
2. Revised Cold Reset
3. Added TSOP1 Package Information
4. Revised FBGA package type
5. Added 67FBGA Package Information
6. Revised typical tOTP, tLOCK from 300us to 600us
7. Revised max tOTP, tLOCK from 600us to 1000us
8. Deleted Lock All Block, Lock-Tight All Block Operation
9. Added Endurance and Data Retention
10. Revised Load Data into Buffer Operation Sequence
11. Revised Warm Reset
12. Revised Programmable Burst Read Latency Timing Diagram
13. Revised Multi Block Erase Flow Chart
14. Revised Extended Operating Temperature
1.0
1. Added Copyright Notice in the beginning
2. Corrected Errata
Jun. 15, 2005
3. Updated Icc2, Icc4, Icc5, Icc6 and ISB
4. Revised INT pin description
5. Added OTP erase case NOTE
6. Revised case definitions of Interrupt Status Register
7. Added a NOTE to Command register
8. Added ECClogSector Information table
9. Removed ’data unit based data handling’ from description of Device
Operation
10. Revised description on Warm/Hot/NAND Flash Core Reset
11. Revised Warm Reset Timing
12. Revised description for 4-, 8-, 16-, 32-Word Linear Burst Mode
13. Revised OTP operation description
14. Added note for OTPL in Internal Register Reset
15. Removed all block lock default case after cold or warm reset
16. Added explanation for each prohibited case in protect mode
17. Revised the case of writing other commands during Multi Block Erase
routine
18. Added note for Erase Suspend/Resume
19. Added supplemental explanation for ECC Operation
20. Removed classification of ECC error from ECC Operation
21. Removed redundant sentance from ECC Bypass Operation
22. Added technical note for Boot Sequence
23. Added technical note for INT pin connection guide
24. Excluded tOEH from Asynchronous Read Table
25. Revised Asycnchronous Read timing diagram for CE don’t care mode
26. Revised Asynchronous Write timing diagram for CE don’t care mode
27. Revised Load operation timing diagram for CE don’t care mode
The attached datasheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right
to change the specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions about device. If you have
any questions, please contact the SAMSUNG branch office near you.
3
OneNAND128
FLASH MEMORY
1. FEATURES
♦ Architecture
• Design Technology: 0.12µm
• Voltage Supply
- 1.8V device(KFG2816Q1M) : 1.7V~1.95V
- 2.65V device(KFG2816D1M) : 2.4V~2.9V
- 3.3V device(KFG2816U1M) : 2.7V~3.6V
• Organization
- Host Interface:16bit
• Internal BufferRAM(3K Bytes)
- 1KB for BootRAM, 2KB for DataRAM
• NAND Array
- Page Size : (1K+32)bytes
- Block Size : (64K+2K)bytes
♦ Performance
• Host Interface type
- Synchronous Burst Read
: Clock Frequency: up to 54MHz
: Linear Burst - 4 , 8 , 16 , 32 words with wrap-around
: Continuous Sequential Burst(512 words)
- Asynchronous Random Read
: Access time of 76ns
- Asynchronous Random Write
• Programmable Read latency
• Multiple Sector Read
- Read multiple sectors by Sector Count Register(up to 2 sectors)
• Multiple Reset
- Cold Reset / Warm Reset / Hot Reset / NAND Flash Reset
• Power dissipation (typical values, CL=30pF)
- Standby current : 10uA@1.8V device, 15uA@2.65V/3.3V device
- Synchronous Burst Read current(54MHz) : 12mA@1.8V device, 20mA@2.65V/3.3V device
- Load current : 20mA@1.8V device, 20mA@2.65V/3.3V device
- Program current: 20mA@1.8V device, 20mA@2.65V/3.3V device
- Erase current: 15mA@1.8V device, 18mA@2.65V/3.3V device
• Reliable CMOS Floating-Gate Technology
- Endurance : 100K Program/Erase Cycles
- Data Retention : 10 Years
♦ Hardware Features
• Voltage detector generating internal reset signal from Vcc
• Hardware reset input (RP)
• Data Protection
- Write Protection mode for BootRAM
- Write Protection mode for NAND Flash Array
- Write protection during power-up
- Write protection during power-down
• User-controlled One Time Programmable(OTP) area
• Internal 2bit EDC / 1bit ECC
• Internal Bootloader supports Booting Solution in system
♦ Software Features
• Handshaking Feature
- INT pin: Indicates Ready / Busy of OneNAND
- Polling method: Provides a software method of detecting the Ready / Busy status of OneNAND
• Detailed chip information by ID register
♦ Packaging
• Package
- 67ball, 7mm x 9mm x max 1.0mmt , 0.8mm ball pitch FBGA
- 48 TSOP 1, 12mm x 20mm, 0.5mm pitch
4
OneNAND128
FLASH MEMORY
2. GENERAL DESCRIPTION
OneNAND is a single-die chip with standard NOR Flash interface using NAND Flash Array. This device is comprised of logic and
NAND Flash Array and 3KB internal BufferRAM. 1KB BootRAM is used for reserving bootcode, and 2KB DataRAM is used for buff-
ering data. The operating clock frequency is up to 54MHz. This device is X16 interface with Host, and has the speed of ~76ns random
access time. Actually, it is accessible with minimum 4clock latency(host-driven clock for synchronous read), but this device adopts the
appropriate wait cycles by programmable read latency. OneNAND provides the multiple sector read operation by assigning the num-
ber of sectors to be read in the sector counter register. The device includes one block sized OTP(One Time Programmable), which
can be used to increase system security or to provide identification capabilities.
5
OneNAND128
FLASH MEMORY
3. PIN DESCRIPTION
Pin Name
Type
Nameand Description
Host Interface
Address Inputs
A15~A0
I
- Inputs for addresses during operation, which are for addressing
BufferRAM & Register.
Data Inputs/Outputs
- Inputs data during program and commands during all operations, outputs data during memory array/
register read cycles.
DQ15~DQ0
I/O
Data pins float to high-impedance when the chip is deselected or outputs are disabled.
Interrupt
Notifying Host when a command has completed. It is open drain output with internal resistor(~50kohms).
After power-up, it is at hi-z condition. Once IOBE is set to 1, it does not float to hi-z condition even when
the chip is deselected or when outputs are disabled.
INT
O
Ready
RDY
CLK
WE
O
I
Indicates data valid in synchronous read modes and is activated while CE is low
Clock
CLK synchronizes the device to the system bus frequency in synchronous read mode.
The first rising edge of CLK in conjunction with AVD low latches address input.
Write Enable
I
WE controls writes to the bufferRAM and registers. Datas are latched on the WE pulse’s rising edge
Address Valid Detect
Indicates valid address presence on address inputs. During asynchronous read operation, all addresses
are latched on AVD’s rising edge, and during synchronous read operation, all addresses are latched on
CLK’s rising edge while AVD is held low for one clock cycle.
AVD
I
I
> Low : for asynchronous mode, indicates valid address ;for burst mode,
causes starting address to be latched on rising edge on CLK
> High : device ignores address inputs
Reset Pin
RP
CE
When low, RP resets internal operation of OneNAND. RP status is don’t care during power-up
and bootloading.
Chip Enable
I
I
CE-low activates internal control logic, and CE-high deselects the device, places it in standby state,
and places ADD and DQ in Hi-Z
Output Enable
OE
OE-low enables the device’s output data buffers during a read cycle.
Power Supply
VCC-Core/Vcc
Power for OneNAND Core
This is the power supply for OneNAND Core.
Power for OneNAND I/O
VCC-IO/Vccq
This is the power supply for OneNAND I/O
Vcc-IO is internally connected to Vcc-Core, thus should be connected to the same power supply.
VSS
Ground for OneNAND
etc.
Do Not Use
DNU
NC
Leave it disconnected. These pins are used for testing.
No Connection
Lead is not internally connected.
NOTE:
Do not leave power supply(VCC, VSS) disconnected.
6
OneNAND128
FLASH MEMORY
4. PIN CONFIGURATION
4.1 TSOP1
V
N.C
1
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
SS
A15
2
OE
A14
3
DQ15
DQ7
A13
4
A12
5
DQ14
DQ6
A11
6
V
Q
A10
7
CC
DQ13
DQ5
A9
8
A8
9
DQ12
DQ4
WE
10
48-pin TSOP1
Standard Type
12mm x 20mm
0.5mm pitch
V
11
SS
DQ11
DQ3
V
12
CC
INT
13
DQ10
DQ2
AVD
14
RP
15
V
A7
16
SS
DQ9
DQ1
DQ8
DQ0
RDY
CLK
CE
A6
17
A5
18
A4
19
A3
20
A2
21
A1
A0
22
23
24
V
N.C
CC
(TOP VIEW, Facing Down)
TSOP1 OneNAND Chip
48pin, 12mm x 20mm, 0.5mm pitch TSOP1
7
OneNAND128
FLASH MEMORY
4.2 67FBGA
NC
VSS
DQ9
DQ3
DQ5
NC
NC
NC
NC
NC
NC
RP
NC
WE
DQ14
DQ1
DQ11
DQ0
DQ2
AVD
A1
DQ13
NC
NC
VSS
OE
VCC
Core
DQ12
DQ7
DQ8
VCC
IO
DQ4
A12
DQ10
A15
DQ15
DQ6
A9
CLK
A14
CE
NC
A7
NC
A2
A13
A11
A10
A8
NC
INT
A0
A4
NC
A6
NC
NC
NC
A5
A3
NC
NC
RDY
NC
NC
NC
NC
(TOP VIEW, Balls Facing Down)
67ball FBGA OneNAND Chip
67ball, 7.0mm x 9.0mm x max 1.0mmt , 0.8mm ball pitch FBGA
8
OneNAND128
FLASH MEMORY
TERMS, ABBREVIATIONS AND DEFINITIONS
B (capital letter)
W (capital letter)
b (lower-case letter)
ECC
Byte, 8bits
Word, 16bits
Bit
Error Correction Code
Calculated ECC
Written ECC
BufferRAM
BootRAM
ECC which has been calculated during load or program access
ECC which has been stored as data in the NAND Flash Array or in the BufferRAM
On-chip Internal Buffer consisting of BootRAM and DataRAM
A 1KB portion of the BufferRAM reserved for Bootcode buffering
A 2KB portion of the BufferRAM reserved for Data buffering
NAND Flash array which is embedded on OneNAND
DataRAM
Memory
Partial unit of page, of which size is 512B for main area and 16B for spare area data.
It is the minimum Load/Program/Copy-Back program unit while one~two sector operation is
available
Sector
Possible data unit to be read from memory to BufferRAM or to be programmed to memory.
Data unit
-
528B of which 512B is in main area and 16B in spare area
- 1056B of which 1024B is in main area and 32B in spare area
9
OneNAND128
FLASH MEMORY
5. BLOCK DIAGRAM
BufferRAM
BootRAM
DQ15~DQ0
A15~A0
CLK
Bootloader
StateMachine
DataRAM
CE
OE
NAND Flash
Array
WE
RP
Error
Correction
Logic
AVD
INT
Internal Registers
(Address/Command/Configuration
/Status Registers)
OTP
(One Block)
RDY
- Host Interface
- BufferRAM(BootRAM, DataRAM)
- Command and status registers
- State Machine (Bootloader is included)
- Error Correction Logic
- Memory(NAND Flash Array, OTP)
NOTE:
1) At cold reset, bootloader copies boot code(1K byte size) from NAND Flash Array to BootRAM.
Figure 1. Internal Block Diagram
10
OneNAND128
FLASH MEMORY
Main area data
(512B)
Spare area data
(16B)
Page:1KB+32B
BootRAM 0
BootRAM 1
Sector
BootRAM
Sector(main area):512B
DataRAM 0_0
DataRAM 0_1
DataRAM 0
Block:
64pages
64KB+2KB
Sector(spare area):16B
Main area data
(512B)
Spare area data
(16B)
DataRAM 1_0
DataRAM 1_1
DataRAM 1
(BufferRAM)
(NAND array)
Figure 2. BufferRAM and NAND array structure
Spare
area
8W
Spare
area
8W
Main area
256W
Main area
256W
ECCm ECCm ECCm ECCs ECCs
FFh
2nd
(Note3)
Note1 Note1 Note2 Note2 Note2 Note3 Note3 Note3
Note4 Note4
1st
2nd
3rd
1st
LSB
LSB MSB LSB MSB LSB MSB LSB MSB LSB MSB LSB MSB LSB MSB LSB MSB
1st W 2nd 3rd W 4th W 5th W 6th W 7th W 8th W
MSB
W
NOTE:
1) The 1st word of spare area in 1st and 2nd page of every invalid block is reserved for the invalid block information by manufacturer.
Please refer to page 59 about the details.
2) These words are managed by internal ECC logic. So it is recommended that the important data like LSN(Logical Sector Number)
are written.
3) These words are reserved for the future purpose by manufacturer. These words will be dedicated to internal logic.
4) These words are for free usage.
5) The 5th, 6th and 7th words are dedicated to internal ECC logic. So these words are only readable. The other words are program-
mable by command.
6) ECCm 1st, ECCm 2nd, ECCm 3rd: ECC code for Main area data
7) ECCs 1st, ECCs 2nd: ECC code for 2nd and 3rd word of spare area.
Figure 3. Spare area of NAND array assignment
11
OneNAND128
FLASH MEMORY
6. ADDRESS MAP For OneNAND NAND Array (word order)
Page and Sector
Page and Sector
Size
Block
Block Address
Size
Block
Block Address
Address(1)
Address(1)
Block0
Block1
0000h
0001h
0002h
0003h
0004h
0005h
0006h
0007h
0008h
0009h
000Ah
000Bh
000Ch
000Dh
000Eh
000Fh
0010h
0011h
0012h
0013h
0014h
0015h
0016h
0017h
0018h
0019h
001Ah
001Bh
001Ch
001Dh
001Eh
001Fh
0000h~00FDh
0000h~00FDh
0000h~00FDh
0000h~00FDh
0000h~00FDh
0000h~00FDh
0000h~00FDh
0000h~00FDh
0000h~00FDh
0000h~00FDh
0000h~00FDh
0000h~00FDh
0000h~00FDh
0000h~00FDh
0000h~00FDh
0000h~00FDh
0000h~00FDh
0000h~00FDh
0000h~00FDh
0000h~00FDh
0000h~00FDh
0000h~00FDh
0000h~00FDh
0000h~00FDh
0000h~00FDh
0000h~00FDh
0000h~00FDh
0000h~00FDh
0000h~00FDh
0000h~00FDh
0000h~00FDh
0000h~00FDh
64KB
64KB
64KB
64KB
64KB
64KB
64KB
64KB
64KB
64KB
64KB
64KB
64KB
64KB
64KB
64KB
64KB
64KB
64KB
64KB
64KB
64KB
64KB
64KB
64KB
64KB
64KB
64KB
64KB
64KB
64KB
64KB
Block32
Block33
Block34
Block35
Block36
Block37
Block38
Block39
Block40
Block41
Block42
Block43
Block44
Block45
Block46
Block47
Block48
Block49
Block50
Block51
Block52
Block53
Block54
Block55
Block56
Block57
Block58
Block59
Block60
Block61
Block62
Block63
0020h
0021h
0022h
0023h
0024h
0025h
0026h
0027h
0028h
0029h
002Ah
002Bh
002Ch
002Dh
002Eh
002Fh
0030h
0031h
0032h
0033h
0034h
0035h
0036h
0037h
0038h
0039h
003Ah
003Bh
003Ch
003Dh
003Eh
003Fh
0000h~00FDh
0000h~00FDh
0000h~00FDh
0000h~00FDh
0000h~00FDh
0000h~00FDh
0000h~00FDh
0000h~00FDh
0000h~00FDh
0000h~00FDh
0000h~00FDh
0000h~00FDh
0000h~00FDh
0000h~00FDh
0000h~00FDh
0000h~00FDh
0000h~00FDh
0000h~00FDh
0000h~00FDh
0000h~00FDh
0000h~00FDh
0000h~00FDh
0000h~00FDh
0000h~00FDh
0000h~00FDh
0000h~00FDh
0000h~00FDh
0000h~00FDh
0000h~00FDh
0000h~00FDh
0000h~00FDh
0000h~00FDh
64KB
64KB
64KB
64KB
64KB
64KB
64KB
64KB
64KB
64KB
64KB
64KB
64KB
64KB
64KB
64KB
64KB
64KB
64KB
64KB
64KB
64KB
64KB
64KB
64KB
64KB
64KB
64KB
64KB
64KB
64KB
64KB
Block2
Block3
Block4
Block5
Block6
Block7
Block8
Block9
Block10
Block11
Block12
Block13
Block14
Block15
Block16
Block17
Block18
Block19
Block20
Block21
Block22
Block23
Block24
Block25
Block26
Block27
Block28
Block29
Block30
Block31
NOTE 1) The 2nd bit of Page and Sector address register is Don’t care. So the address range is bigger than the real range.
Even though 2nd bit is set to "1", this bit is always considered "0". Please refer to Start Address 8 register.
12
OneNAND128
FLASH MEMORY
Page and Sector
Address(1)
Page and Sector
Size
Block
Block Address
Size
Block
Block Address
Address(1)
Block64
Block65
Block66
Block67
Block68
Block69
Block70
Block71
Block72
Block73
Block74
Block75
Block76
Block77
Block78
Block79
Block80
Block81
Block82
Block83
Block84
Block85
Block86
Block87
Block88
Block89
Block90
Block91
Block92
Block93
Block94
Block95
0040h
0041h
0042h
0043h
0044h
0045h
0046h
0047h
0048h
0049h
004Ah
004Bh
004Ch
004Dh
004Eh
004Fh
0050h
0051h
0052h
0053h
0054h
0055h
0056h
0057h
0058h
0059h
005Ah
005Bh
005Ch
005Dh
005Eh
005Fh
0000h~00FDh
0000h~00FDh
0000h~00FDh
0000h~00FDh
0000h~00FDh
0000h~00FDh
0000h~00FDh
0000h~00FDh
0000h~00FDh
0000h~00FDh
0000h~00FDh
0000h~00FDh
0000h~00FDh
0000h~00FDh
0000h~00FDh
0000h~00FDh
0000h~00FDh
0000h~00FDh
0000h~00FDh
0000h~00FDh
0000h~00FDh
0000h~00FDh
0000h~00FDh
0000h~00FDh
0000h~00FDh
0000h~00FDh
0000h~00FDh
0000h~00FDh
0000h~00FDh
0000h~00FDh
0000h~00FDh
0000h~00FDh
64KB
64KB
64KB
64KB
64KB
64KB
64KB
64KB
64KB
64KB
64KB
64KB
64KB
64KB
64KB
64KB
64KB
64KB
64KB
64KB
64KB
64KB
64KB
64KB
64KB
64KB
64KB
64KB
64KB
64KB
64KB
64KB
Block96
Block97
0060h
0061h
0062h
0063h
0064h
0065h
0066h
0067h
0068h
0069h
006Ah
006Bh
006Ch
006Dh
006Eh
006Fh
0070h
0071h
0072h
0073h
0074h
0075h
0076h
0077h
0078h
0079h
007Ah
007Bh
007Ch
007Dh
007Eh
007Fh
0000h~00FDh
0000h~00FDh
0000h~00FDh
0000h~00FDh
0000h~00FDh
0000h~00FDh
0000h~00FDh
0000h~00FDh
0000h~00FDh
0000h~00FDh
0000h~00FDh
0000h~00FDh
0000h~00FDh
0000h~00FDh
0000h~00FDh
0000h~00FDh
0000h~00FDh
0000h~00FDh
0000h~00FDh
0000h~00FDh
0000h~00FDh
0000h~00FDh
0000h~00FDh
0000h~00FDh
0000h~00FDh
0000h~00FDh
0000h~00FDh
0000h~00FDh
0000h~00FDh
0000h~00FDh
0000h~00FDh
0000h~00FDh
64KB
64KB
64KB
64KB
64KB
64KB
64KB
64KB
64KB
64KB
64KB
64KB
64KB
64KB
64KB
64KB
64KB
64KB
64KB
64KB
64KB
64KB
64KB
64KB
64KB
64KB
64KB
64KB
64KB
64KB
64KB
64KB
Block98
Block99
Block100
Block101
Block102
Block103
Block104
Block105
Block106
Block107
Block108
Block109
Block110
Block111
Block112
Block113
Block114
Block115
Block116
Block117
Block118
Block119
Block120
Block121
Block122
Block123
Block124
Block125
Block126
Block127
NOTE 1) 2nd bit of Page and Sector address is Don’t care. So the address range is bigger than the real range.
Even though 2nd bit is set to "1", this bit is always considered "0". Please refer to Start Address 8 register.
13
OneNAND128
FLASH MEMORY
Page and Sector
Address(1)
Page and Sector
Size
Block
Block Address
Size
Block
Block Address
Address(1)
Block128
Block129
Block130
Block131
Block132
Block133
Block134
Block135
Block136
Block137
Block138
Block139
Block140
Block141
Block142
Block143
Block144
Block145
Block146
Block147
Block148
Block149
Block150
Block151
Block152
Block153
Block154
Block155
Block156
Block157
Block158
Block159
0080h
0081h
0082h
0083h
0084h
0085h
0086h
0087h
0088h
0089h
008Ah
008Bh
008Ch
008Dh
008Eh
008Fh
0090h
0091h
0092h
0093h
0094h
0095h
0096h
0097h
0098h
0099h
009Ah
009Bh
009Ch
009Dh
009Eh
009Fh
0000h~00FDh
0000h~00FDh
0000h~00FDh
0000h~00FDh
0000h~00FDh
0000h~00FDh
0000h~00FDh
0000h~00FDh
0000h~00FDh
0000h~00FDh
0000h~00FDh
0000h~00FDh
0000h~00FDh
0000h~00FDh
0000h~00FDh
0000h~00FDh
0000h~00FDh
0000h~00FDh
0000h~00FDh
0000h~00FDh
0000h~00FDh
0000h~00FDh
0000h~00FDh
0000h~00FDh
0000h~00FDh
0000h~00FDh
0000h~00FDh
0000h~00FDh
0000h~00FDh
0000h~00FDh
0000h~00FDh
0000h~00FDh
64KB
64KB
64KB
64KB
64KB
64KB
64KB
64KB
64KB
64KB
64KB
64KB
64KB
64KB
64KB
64KB
64KB
64KB
64KB
64KB
64KB
64KB
64KB
64KB
64KB
64KB
64KB
64KB
64KB
64KB
64KB
64KB
Block160
Block161
Block162
Block163
Block164
Block165
Block166
Block167
Block168
Block169
Block170
Block171
Block172
Block173
Block174
Block175
Block176
Block177
Block178
Block179
Block180
Block181
Block182
Block183
Block184
Block185
Block186
Block187
Block188
Block189
Block190
Block191
00A0h
00A1h
00A2h
00A3h
00A4h
00A5h
00A6h
00A7h
00A8h
00A9h
00AAh
00ABh
00ACh
00ADh
00AEh
00AFh
00B0h
00B1h
00B2h
00B3h
00B4h
00B5h
00B6h
00B7h
00B8h
00B9h
00BAh
00BBh
00BCh
00BDh
00BEh
00BFh
0000h~00FDh
0000h~00FDh
0000h~00FDh
0000h~00FDh
0000h~00FDh
0000h~00FDh
0000h~00FDh
0000h~00FDh
0000h~00FDh
0000h~00FDh
0000h~00FDh
0000h~00FDh
0000h~00FDh
0000h~00FDh
0000h~00FDh
0000h~00FDh
0000h~00FDh
0000h~00FDh
0000h~00FDh
0000h~00FDh
0000h~00FDh
0000h~00FDh
0000h~00FDh
0000h~00FDh
0000h~00FDh
0000h~00FDh
0000h~00FDh
0000h~00FDh
0000h~00FDh
0000h~00FDh
0000h~00FDh
0000h~00FDh
64KB
64KB
64KB
64KB
64KB
64KB
64KB
64KB
64KB
64KB
64KB
64KB
64KB
64KB
64KB
64KB
64KB
64KB
64KB
64KB
64KB
64KB
64KB
64KB
64KB
64KB
64KB
64KB
64KB
64KB
64KB
64KB
NOTE 1) 2nd bit of Page and Sector address is Don’t care. So the address range is bigger than the real range.
Even though 2nd bit is set to "1", this bit is always considered "0". Please refer to Start Address 8 register.
14
OneNAND128
FLASH MEMORY
Page and Sector
Address(1)
Page and Sector
Size
Block
Block Address
Size
Block
Block Address
Address(1)
Block192
Block193
Block194
Block195
Block196
Block197
Block198
Block199
Block200
Block201
Block202
Block203
Block204
Block205
Block206
Block207
Block208
Block209
Block210
Block211
Block212
Block213
Block214
Block215
Block216
Block217
Block218
Block219
Block220
Block221
Block222
Block223
00C0h
00C1h
00C2h
00C3h
00C4h
00C5h
00C6h
00C7h
00C8h
00C9h
00CAh
00CBh
00CCh
00CDh
00CEh
00CFh
00D0h
00D1h
00D2h
00D3h
00D4h
00D5h
00D6h
00D7h
00D8h
00D9h
00DAh
00DBh
00DCh
00DDh
00DEh
00DFh
0000h~00FDh
0000h~00FDh
0000h~00FDh
0000h~00FDh
0000h~00FDh
0000h~00FDh
0000h~00FDh
0000h~00FDh
0000h~00FDh
0000h~00FDh
0000h~00FDh
0000h~00FDh
0000h~00FDh
0000h~00FDh
0000h~00FDh
0000h~00FDh
0000h~00FDh
0000h~00FDh
0000h~00FDh
0000h~00FDh
0000h~00FDh
0000h~00FDh
0000h~00FDh
0000h~00FDh
0000h~00FDh
0000h~00FDh
0000h~00FDh
0000h~00FDh
0000h~00FDh
0000h~00FDh
0000h~00FDh
0000h~00FDh
64KB
64KB
64KB
64KB
64KB
64KB
64KB
64KB
64KB
64KB
64KB
64KB
64KB
64KB
64KB
64KB
64KB
64KB
64KB
64KB
64KB
64KB
64KB
64KB
64KB
64KB
64KB
64KB
64KB
64KB
64KB
64KB
Block224
Block225
Block226
Block227
Block228
Block229
Block230
Block231
Block232
Block233
Block234
Block235
Block236
Block237
Block238
Block239
Block240
Block241
Block242
Block243
Block244
Block245
Block246
Block247
Block248
Block249
Block250
Block251
Block252
Block253
Block254
Block255
00E0h
00E1h
00E2h
00E3h
00E4h
00E5h
00E6h
00E7h
00E8h
00E9h
00EAh
00EBh
00ECh
00EDh
00EEh
00EFh
00F0h
00F1h
00F2h
00F3h
00F4h
00F5h
00F6h
00F7h
00F8h
00F9h
00FAh
00FBh
00FCh
00FDh
00FEh
00FFh
0000h~00FDh
0000h~00FDh
0000h~00FDh
0000h~00FDh
0000h~00FDh
0000h~00FDh
0000h~00FDh
0000h~00FDh
0000h~00FDh
0000h~00FDh
0000h~00FDh
0000h~00FDh
0000h~00FDh
0000h~00FDh
0000h~00FDh
0000h~00FDh
0000h~00FDh
0000h~00FDh
0000h~00FDh
0000h~00FDh
0000h~00FDh
0000h~00FDh
0000h~00FDh
0000h~00FDh
0000h~00FDh
0000h~00FDh
0000h~00FDh
0000h~00FDh
0000h~00FDh
0000h~00FDh
0000h~00FDh
0000h~00FDh
64KB
64KB
64KB
64KB
64KB
64KB
64KB
64KB
64KB
64KB
64KB
64KB
64KB
64KB
64KB
64KB
64KB
64KB
64KB
64KB
64KB
64KB
64KB
64KB
64KB
64KB
64KB
64KB
64KB
64KB
64KB
64KB
NOTE 1) 2nd bit of Page and Sector address is Don’t care. So the address range is bigger than the real range.
Even though 2nd bit is set to "1", this bit is always considered "0". Please refer to Start Address 8 register.
15
OneNAND128
FLASH MEMORY
Detailed information of Address Map (word order)
• BootRAM(Main area)
-0000h~01FFh: 2(sector) x 512byte(NAND main area) = 1KB
0000h~00FFh(512B)
BootM 0
0100h~01FFh(512B)
BootM 1
(sector 0 of page 0)
(sector 1 of page 0)
• DataRAM(Main area)
-0200h~05FFh: 4(sector) x 512byte(NAND main area) = 2KB
0200h~02FFh(512B)
DataM 0_0
0300h~03FFh(512B)
DataM 0_1
0400h~04FFh(512B)
0500h~05FFh(512B)
DataM 1_1
DataM 1_0
(sector 0 of page 0)
(sector 1 of page 0)
(sector 0 of page 1)
(sector 1 of page 1)
• BootRAM(Spare area)
-8000h~800Fh: 2(sector) x 16byte(NAND spare area) = 32B
8000h~8007h(16B)
BootS 0
8008h~800Fh(16B)
BootS 1
(sector 0 of page 0)
(sector 1 of page 0)
• DataRAM(Spare area)
-8010h~802Fh: 4(sector) x 16byte(NAND spare area) = 64B
8010h~8017h(16B)
DataS 0_0
8018h~801Fh(16B)
DataS 0_1
8020h~8027h(16B)
8028h~802Fh(16B)
DataS 1_1
DataS 1_0
(sector 0 of page 0)
(sector 1 of page 0)
(sector 0 of page 1)
(sector 1 of page 1)
*NAND Flash array consists of 1KB page size and 64KB block size.
16
OneNAND128
FLASH MEMORY
Spare area assignment
Equivalent to 1word of NAND Flash
Word
Address Address
Byte
Buf.
F
E
D
C
B
A
9
8
7
6
5
4
3
2
1
0
BootS 0
8000h
8001h
8002h
8003h
8004h
8005h
8006h
8007h
8008h
8009h
800Ah
800Bh
800Ch
800Dh
800Eh
800Fh
8010h
8011h
8012h
8013h
8014h
8015h
8016h
8017h
8018h
8019h
801Ah
801Bh
801Ch
801Dh
801Eh
801Fh
10000h
10002h
10004h
10006h
10008h
1000Ah
1000Ch
1000Eh
10010h
10012h
10014h
10016h
10018h
1001Ah
1001Ch
1001Eh
10020h
10022h
10024h
10026h
10028h
1002Ah
1002Ch
1002Eh
10030h
10032h
10034h
10036h
10038h
1003Ah
1003Ch
1003Eh
BI
Managed by Internal ECC logic
Reserved for the future use
Managed by Internal ECC logic
Reserved for the current and future use
ECC Code for Main area data (2nd)
ECC Code for Spare area data (1st)
FFh(Reserved for the future use)
ECC Code for Main area data (1st)
ECC Code for Main area data (3rd)
ECC Code for Spare area data (2nd)
Free Usage
BI
BootS 1
Managed by Internal ECC logic
Reserved for the future use Managed by Internal ECC logic
Reserved for the current and future use
ECC Code for Main area data (2nd)
ECC Code for Main area data (1st)
ECC Code for Main area data (3rd)
ECC Code for Spare area data (2nd)
ECC Code for Spare area data (1st)
FFh(Reserved for the future use)
Free Usage
BI
DataS
0_0
Managed by Internal ECC logic
Reserved for the future use Managed by Internal ECC logic
Reserved for the current and future use
ECC Code for Main area data (2nd)
ECC Code for Main area data (1st)
ECC Code for Main area data (3rd)
ECC Code for Spare area data (2nd)
ECC Code for Spare area data (1st)
FFh(Reserved for the future use)
Free Usage
BI
DataS
0_1
Managed by Internal ECC logic
Reserved for the future use Managed by Internal ECC logic
Reserved for the current and future use
ECC Code for Main area data (2nd)
ECC Code for Main area data (1st)
ECC Code for Main area data (3rd)
ECC Code for Spare area data (2nd)
ECC Code for Spare area data (1st)
FFh(Reserved for the future use)
Free Usage
17
OneNAND128
FLASH MEMORY
Equivalent to 1word of NAND Flash
Word
Address Address
Byte
Buf.
F
E
D
C
B
A
9
8
7
6
5
4
3
2
1
0
DataS 1_0
8020h
8021h
8022h
8023h
8024h
8025h
8026h
8027h
8028h
8029h
802Ah
802Bh
802Ch
802Dh
802Eh
802Fh
10040h
10042h
10044h
10046h
10048h
1004Ah
1004Ch
1004Eh
10050h
10052h
10054h
10056h
10058h
1005Ah
1005Ch
1005Eh
BI
Managed by Internal ECC logic
Reserved for the future use
Managed by Internal ECC logic
Reserved for the current and future use
ECC Code for Main area data (2nd)
ECC Code for Spare area data (1st)
FFh(Reserved for the future use)
ECC Code for Main area data (1st)
ECC Code for Main area data (3rd)
ECC Code for Spare area data (2nd)
Free Usage
BI
DataS 1_1
Managed by Internal ECC logic
Reserved for the future use Managed by Internal ECC logic
Reserved for the current and future use
ECC Code for Main area data (2nd)
ECC Code for Main area data (1st)
ECC Code for Main area data (3rd)
ECC Code for Spare area data (2nd)
ECC Code for Spare area data (1st)
FFh(Reserved for the future use)
Free Usage
NOTE:
- BI: Invalid block Information
>Host can use complete spare area except BI and ECC code area. For example,
Host can write data to Spare area buffer except for the area controlled by ECC logic at program operation.
>OneNAND automatically generates ECC code for both main and spare data of memory during program operation in case of ’with ECC’ mode ,
but does not update ECC code to spare bufferRAM.
>When loading/programming spare area, spare area BufferRAM address(BSA) and BufferRAM sector count(BSC) is chosen via Start buffer register
as it is.
18
OneNAND128
FLASH MEMORY
7. Detailed address map for registers
Address
(word order)
Address
(byte order)
Host
Access
Name
Description
F000h
F001h
F002h
F003h
F004h
1E000h
1E002h
1E004h
1E006h
1E008h
Manufacturer ID
Device ID
R
R
R
R
R
Manufacturer identification
Device identification
Version identification
Data buffer size
Version ID
Data Buffer size
Boot Buffer size
Boot buffer size
Amount of
buffers
F005h
1E00Ah
R
Amount of data/boot buffers
F006h
F007h~F0FFh
F100h
1E00Ch
1E00Eh~1E1FEh
1E200h
Technology
Reserved
R
Info about technology
-
Reserved for User
Start address 1
Start address 2
Start address 3
R/W
R/W
R/W
NAND Flash Block address
Reserved
F101h
1E202h
F102h
1E204h
Destination Block address for Copy back program
Destination Page & Sector address for Copy
back program
F103h
1E206h
Start address 4
R/W
F104h
F105h
1E208h
1E20Ah
Start address 5
Start address 6
Start address 7
Start address 8
Reserved
-
N/A
-
N/A
F106h
1E20Ch
-
R/W
-
N/A
F107h
1E20Eh
NAND Flash Page & Sector address
Reserved for User
F108h~F1FFh
1E210h~1E3FEh
Number Buffer of for the page data transfer to/from the
memory and the start Buffer Address
The meaning is with which buffer to start and how many
buffers to use for the data transfer
F200h
1E400h
Start Buffer
R/W
F201h~F207h
F208h~F21Fh
F220h
1E402h~1E40Eh
1E410h~1E43Eh
1E440h
Reserved
Reserved
Command
-
-
Reserved for User
Reserved for vendor specific purposes
Host control and memory operation commands
R/W
System
Configuration 1
F221h
F222h
1E442h
1E444h
R, R/W Memory and Host Interface Configuration
System
Configuration 2
-
N/A
F223h~F22Fh
F230h~F23Fh
F240h
1E446h~1E45Eh
1E460h~1E47Eh
1E480h
Reserved
Reserved
-
Reserved for User
-
R
Reserved for vendor specific purposes
Controller Status and result of memory operation
Memory Command Completion Interrupt Status
Reserved for User
Controller Status
Interrupt
F241h
1E482h
R/W
-
F242h~F24Bh
1E484h~1E496h
Reserved
Unlock Start
Block Address
Start memory block address to unlock in Write
Protection mode
F24Ch
F24Dh
1E498h
1E49Ah
R/W
R/W
Unlock End
Block Address
End memory block address to unlock in Write
Protection mode
Write Protection
Status
Current memory Write Protection status
(unlocked/locked/tight-locked)
F24Eh
1E49Ch
R
-
F24Fh~FEFFh
1E49Eh~1FDFEh
Reserved
Reserved for User
19
OneNAND128
FLASH MEMORY
Address
(word order)
Address
(byte order)
Host
Access
Name
Description
ECC Status
Register
FF00h
FF01h
FF02h
FF03h
FF04h
1FE00h
1FE02h
1FE04h
1FE06h
1FE08h
R
R
R
R
ECC status of sector
ECC Result of
main area data
ECC error position of Main area data error for first
selected Sector
ECC Result of
spare area data
ECC error position of Spare area data error for first
selected Sector
ECC Result of
main area data
ECC error position of Main area data error for second
selected Sector
ECC Result of
spare area data
ECC error position of Spare area data error for second
selected Sector
R
-
FF05h~FFFFh
1FE12h~1FF0Ah
Reserved
Reserved for vendor specific purposes
20
OneNAND128
FLASH MEMORY
7. Address Register (word order)
7.1 Manufacturer ID Register (R): F000h, default=00ECh
15
14
13
12
11
10
9
8
7
6
5
5
4
4
3
2
1
0
ManufID
ManufID (Manufacturer ID): manufacturer identification, 00ECh for Samsung Electronics Corp.
7.2 Device ID Register (R): F001h, default=refer to Table1
15
14
13
12
11
10
9
8
7
6
3
2
1
0
DeviceID
DeviceID (Device ID): Device Identification,
Table 1.
Device
DeviceID[15:0]
0004h
KFG2816Q1M
KFG2816D1M
KFG2816U1M
0005h
0005h
7.3 Version ID Register (R): F002h
: N/A
21
OneNAND128
FLASH MEMORY
7.4 Data Buffer size Register(R): F003h, default=0400h
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
DataBufSize
DataBufSize: total data buffer size in words in the memory interface used for shrinks
Equals two buffers of 512 words each(2x512=2N, N=10)
7.5 Boot Buffer size Register (R): F004h, default=0200h
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
BootBufSize
BootBufSize: total boot buffer size in words in the memory interface
(512 words=29, N=9)
7.6 Amount of Buffers Register (R): F005h, default=0201h
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
DataBufAmount
BootBufAmount
DataBufAmount: the amount of data buffer=2(2N, N=1)
BootBufAmount: the amount of boot buffer=1(2N, N=0)
7.7 Technology Register (R): F006h, default=0000h
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Tech
Tech: technology information, what technology is used for the memory
Tech
0000h
Technology
NAND SLC
NAND MLC
Reserved
0001h
0002h-FFFFh
22
OneNAND128
FLASH MEMORY
7.8 Start Address1 Register (R/W): F100h, default=0000h
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reserved(00000000)
FBA
FBA (NAND Flash Block Address): NAND Flash block address which will be read or programmed or erased.
Device
Number of Block
FBA
128Mb
256
FBA[7:0]
7.9 Start Address2 Register (R/W): F101h, default=0000h
15
14
13
12
11
10
9
8
7
6
5
5
4
4
3
3
2
2
1
1
0
0
Reserved(0000000000000000)
7.10 Start Address3 Register (R/W): F102h, default=0000h
15
14
13
12
11
10
9
8
7
6
Reserved(00000000)
FCBA
FCBA (NAND Flash Copy Back Block Address): NAND Flash destination block address which will be copy back programmed.
Device
Number of Block
FBA
128Mb
256
FBA[7:0]
7.11 Start Address4 Register (R/W): F103h, default=0000h
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reserved(00000000)
FCPA
Reserved FCSA
FCPA (NAND Flash Copy Back Page Address): NAND Flash destination page address in a block for copy back program operation.
FCPA(default value) = 000000
FCPA range : 000000~111111, 6bits for 64 pages
FCSA (NAND Flash Copy Back Sector Address): NAND Flash destination sector address in a page for copy back program operation.
FCSA(default value) = 0
FCSA range : 0~1, 1bits for 2 sectors
23
OneNAND128
FLASH MEMORY
7.12 Start Address5 Register: F104h
: N/A
7.13 Start Address6 Register: F105h
: N/A
7.14 Start Address7 Register: F106h
: N/A
7.15 Start Address8 Register (R/W): F107h, default=0000h
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reserved (00000000)
FPA
Reserved FSA
FPA (NAND Flash Page Address): NAND Flash start page address in a block for page read or copy back program or program operation.
FPA(default value)=000000
FPA range: 000000~111111 , 6bits for 64 pages
FSA (Flash Sector Address): NAND Flash start sector address in a page for read or copy back program or program operation.
FSA(default value) = 0
FSA range : 0~1, 1bits for 2 sectors
7.16 Start Buffer Register (R/W): F200h, default=0000h
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reserved(0000)
BSA
Reserved(0000000)
BSC
BSC (BufferRAM Sector Count): this field specifies the number of sectors to be read or programmed or copy back programmed.
Its maximum count is 2 sectors at 0(default value)value.
For a single sector access, it should be programmed as value 1 and it should be programmed as value 0 for two sectors.
However internal RAM buffer reached to 1 value(max. value), it counts up to 0 value to satisfy BSC value.
for example) if BSA=1101, BSC=0, then selected BufferRAM are ’1101->1100’.
BSA (BufferRAM Sector Address): It is the place where data is placed and specifies the sector 0~1 in the internal BootRAM and DataRAM.
BSA[3] is the selection bit between BootRAM and DataRAM.
BSA[2] is the selection bit between DataRAM0 and DataRAM1.
BSA[0] is the selection bit between Sector0 and Sector1 in the internal BootRAM and DataRAM.
While one of BootRAM or DataRAM0 interfaces with memory, the other RAM is inaccessible.
Main area data
Spare area data
BSA
0000
0001
BootRAM 0
BootRAM 1
Sector: (512 + 16)byte
BootRAM
DataRAM0
DataRAM 0_0
DataRAM 0_1
1000
1001
BSC
Number of Sectors
1
0
1 sector
DataRAM 1_0
DataRAM 1_1
1100
1101
DataRAM1
2 sectors
24
OneNAND128
FLASH MEMORY
7.17 Command Register (R/W): F220h, default=0000h
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Command
Command: operation of the memory interface
Acceptable
command
CMD
Operation
during busy
0000h
0013h
0080h
001Ah
001Bh
0023h
002Ah
002Ch
0071h
0094h
0095h
00B0h
0030h
00F0h
00F3h
0065h
Load single/multiple sector data unit into buffer
Load single/multiple spare sector into buffer
00F0h, 00F3h
00F0h, 00F3h
Program single/multiple sector data unit from buffer
Program single/multiple spare area sector from buffer
Copy back program
00F0h, 00F3h
00F0h, 00F3h
00F0h, 00F3h
Unlock NAND array block(s) from start block address to end block address
Lock NAND array block(s) from start block address to end block address
-
-
Lock-tight NAND array block(s) from start block address to end block address
-
Erase Verify Read
Block Erase
00F0h, 00F3h
00F0h, 00F3h
00F0h, 00F3h
00F3h
Multi-Block Erase
Erase Suspend
Erase Resume
00F0h, 00F3h
-
Reset NAND Flash Core
Reset OneNAND 1)
OTP Access
-
00F0h, 00F3h
NOTE:
1)’Reset OneNAND’(=Hot reset) command makes the registers(except RDYpol, INTpol, IOBE, and OTPL bits) and NAND Flash core into default state as
the warm reset(=reset by RP pin).
This R/W register describes the operation of the OneNAND interface.
Note that all commands should be issued right after INT is turned from ready state to busy state. (i.e. right after 0 is written to INT register.) After any
command is issued and the corresponding operation is completed, INT goes back to ready state. (00F0h and 00F3h may be accepted during busy state
of some operations. Refer to the rightmost column of the command register table above.)
25
OneNAND128
FLASH MEMORY
7.18 System Configuration 1 Register (R, R/W): F221h, default=40C0h
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
R
RDY
pol
INT
pol
IOB
E
BW
PS
RM
BRL
BL
ECC
Reserved(0000)
RM (Read Mode): this field specifies the selection between asynchronous read mode and synchronous read mode
RM
0
Read Mode
Asynchronous read(default)
Synchronous read
1
BRL (Burst Read Latency): this field specifies the initial access latency in the burst read transfer.
BRL
000
001
010
011
100
101
110
111
Latency Cycles
8(N/A)
9(N/A)
10(N/A)
3(up to 40MHz)
4(default, min.)
5
6
7
BL (Burst Length): this field specifies the size of burst length during Sync. burst read. Wrap around and linear burst.
BL
000
Burst Length(Main)
Burst Length(Spare)
Continuous(default)
4 words
001
010
8 words
011
16 words
100
32 words
N/A
101~111
Reserved
ECC: Error Correction Operation,
0=with correction(default), 1=without correction(by-passed)
RDYpol: RDY signal polarity
0=low for ready, 1=high for ready((default)
INTpol: INT Pin polarity
0=low for Interrupt pending , 1=high for Interrupt pending (default)
INTpol
INT bit of Interrupt Status Register
INT Pin output
0
1
0
0
1
0
IOBE: I/O buffer enable for INT and RDY signals, INT and RDY outputs are HighZ at power-up, bit 7 and 6 become valid after IOBE is set to1. IOBE can
be reset only by Cold reset or by writing 0 to bit 5 of System Configuration 1 register.
0=disable(default), 1=enable
BWPS: boot buffer write protect status,
0=locked(fixed)
26
OneNAND128
FLASH MEMORY
7.19 System Configuration 2 Register : F222h
: N/A
7.22 Controller Status Register (R): F240h, default=0000h
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
TO
(0)
OnGo Lock
Load
Prog Erase Error
Sus
PRp RSTB OTPL
Reserved(000000)
OnGo: this bit shows the overall internal status of OneNAND
0=ready, 1=busy
Lock: this bit shows whether host loads data from NAND Flash array into locked BootRAM or programs/erases locked block of NAND Flash array.
Lock
Locked/Unlocked Check Result
0
1
Unlocked
Locked
Error (Current Sector/Page Write Result): this bit shows current sector/page Load/Program/Copy Back Program/Erase result of flash memory or whether
host puts invalid command into the device.
Current Sector/Page Load/Program/CopyBack. Program/Erase Result
Error
and Invalid Command Input
0
1
Pass
Fail
Sus (Erase Suspend/Resume):this bit shows the Erase Suspend Status.
Sus
0
Erase Suspend Status
Erase Resume(Default)
Erase Suspend
1
OTPL (OTP Lock Status):this bit shows OTP block is locked or unlocked. OTPL bit is automatically updated at power-on.
OTPL
OTP Locked/Unlocked Status
OTP Block Unlock Status(Default)
0
1
OTP Block Lock Status(Disable OTP Program/Erase)
TO (Time Out): time out for read/program/copy back program/erase
0=no time out(fixed)
Load : this bit shows the Load operation status
0=ready(default), 1=busy or error case, refer to the table 3
Prog (Program Busy) : this bit shows the Program operation status
0=ready(default), 1=busy or error case, refer to the table 3
Erase (Erase Busy) : this bit shows the Erase operation status
0=ready(default), 1=busy or error case, refer to the table 3
RSTB (Reset Busy) : this bit shows the Reset operation status
0=ready(default), 1=busy or error case, refer to the table 3
27
OneNAND128
FLASH MEMORY
Table 3. Controller Status Register output for modes.
Controller Status Register [15:0]
Mode
OnGo Lock
Load
Prog
Erase Error
Sus Reserved(0) RSTB OTPL Reserved(0)
TO
0
Load Ongoing
Program Ongoing
Erase Ongoing
Reset Ongoing
1
1
1
1
0
0
0
0
1
0
0
0
0
1
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0/1
0/1
0/1
0/1
00000
00000
00000
00000
0
0
0
Multi-Block Erase
Ongoing
1
1
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0/1
0/1
00000
00000
0
0
Erase Verify Read
Ongoing
Load OK
Program OK
Erase OK
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0/1
0/1
0/1
00000
00000
00000
0
0
0
Erase Verify Read
OK3)
0
0
0
0
0
0
0
0
0
0/1
00000
0
Load Fail1)
Program Fail
Erase Fail
0
0
0
0
0
0
1
0
0
0
1
0
0
0
1
1
1
1
0
0
0
0
0
0
0
0
0
0/1
0/1
0/1
00000
00000
00000
0
0
0
Erase Verify Read
Fail3)
0
0
0
0
1
1
0
0
0
0/1
00000
0
Load Reset2)
Program Reset
Erase Reset
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
0
1
0
1
0
0
1
0
0
0
0
1
1
0
1
0
1
1
1
0
1
1
1
0
0
0
1
0
0
0
0
0
0
0
0
0
0
1
1
1
0
0
0
0
0/1
0/1
0/1
0/1
0/1
0/1
0/1
00000
00000
00000
00000
00000
00000
00000
0
0
0
0
0
0
0
Erase Suspend
Program Lock
Erase Lock
Load Lock(Buffer Lock)
OTP Program
Fail(Lock)
0
1
0
1
0
1
0
0
0
1
00000
0
OTP Program Fail
OTP Erase Fail
0
0
0
1
0
0
1
0
0
1
1
1
0
0
0
0
0
0
0
00000
00000
0
0
0/1
Program Ongo-
ing(Susp.)
1
0
0
1
1
0
1
0
0
0/1
00000
0
Load Ongoing(Susp.)
Program Fail(Susp.)
Load Fail(Susp.)
1
0
0
0
0
0
0
0
1
0
1
0
0
1
0
0
1
1
1
0
0
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0/1
0/1
0/1
0/1
00000
00000
00000
00000
0
0
0
0
Invalid Command
Invalid Com-
mand(Susp.)
0
0
0
0
1
1
1
0
0
0/1
00000
0
NOTE:
1. ERm and/or ERs bits in ECC status register at Load Fail case is 10. (2bits error - uncorrectable)
2. ERm and ERs bits in ECC status register at Load Reset case are 00. (No error)
3. Multi Block Erase status should be checked by Erase Verify Read operation.
4. OTP Erase does not update the register and the previous value is kept.
28
OneNAND128
FLASH MEMORY
7.23 Interrupt Status Register (R/W): F241h, default=8080h(after Cold reset),8010h(after Warm/Hot reset)
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
INT
Reserved(0000000)
RI
WI
EI
RSTI
Reserved(0000)
Bit
Address
Bit Name
Default State
Cold Warm/Hot
Valid
States
Function
15
INT(interrupt): the master interrupt bit
- Set to ’1’ of itself when one or more of RI, WI, EI and
1
1
0
Interrupt Off
0->1
Interrupt Pending
RSTI is set to ’1’, or Unlock(0023h), Lock(002Ah), Lock-
tight(002Ch), or Erase Verify Read(0071h), or OTP
access(0065h) operation, or "Load Data into Buffer" is
completed.
- Cleared to ’0’ when by writing ’0’ to this bit or by
reset(Cold/Warm/Hot reset).
’0’ in this bit means that INT pin is low status.
(This INT bit is directly wired to the INT pin on the chip.
INT pin goes low upon writing ’0’ to this bit when
INTpol is high and goes high upon writing ’0’ to this
bit when INTpol is low. )
7
6
5
4
RI(Read Interrupt):
1
0
0
0
0
0
0
1
0
Interrupt Off
- Set to ’1’ of itself at the completion of Load Operation
(0000h, 0013h, or boot is done.)
- Cleared to ’0’ when by writing ’0’ to this bit or by reset
(Cold/Warm/Hot reset).
0->1
Interrupt Pending
WI(Write Interrupt):
0
Interrupt Off
- Set to ’1’ of itself at the completion of Program Operation
(0080h, 001Ah, or 001Bh)
- Cleared to ’0’ when by writing ’0’ to this bit or by reset
(Cold/Warm/Hot reset).
0->1
Interrupt Pending
EI(Erase Interrupt):
0
Interrupt Off
- Set to ’1’ of itself at the completion of Erase Operation
(0094h, 0095h, or 0030h)
- Cleared to ’0’ when by writing ’0’ to this bit or by reset
(Cold/Warm/Hot reset).
0->1
Interrupt Pending
RSTI(Reset Interrupt):
0
Interrupt Off
- Set to ’1’ of itself at the completion of Reset Operation
(00B0h, 00F0h, 00F3h, or warm reset is released.)
- Cleared to ’0’ when by writing ’0’ to this bit.
0->1
Interrupt Pending
7.24 Start Block Address (R/W): F24Ch, default=0000h
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reserved(00000000)
SBA
SBA (Lock/Unlock/Lock-tight Start Block Address): Start NAND Flash block address in Write Protection mode, which follows ’Lock block command’ or
’Unlock block command’ or ’Lock-tight command’.
7.25 End Block Address (R/W): F24Dh, default=0000h
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reserved(00000000)
EBA
EBA (Lock/Unlock/Lock-tight End Block Address): End NAND Flash block address in Write Protection mode, which follows ’Lock block command’ or
’Unlock block command’ or ’Lock-tight command’. EBA should be equal to or larger than SBA.
Device
Number of Block
SBA/EBA
128Mb
256
[7:0]
29
OneNAND128
FLASH MEMORY
7.26 NAND Flash Write Protection Status (R): F24Eh, default=0002h
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reserved(0000000000000)
US
LS
LTS
US (Unlocked Status): ’1’ value of this bit specifies that the current block in NAND Flash is unlocked.
LS (Locked Status): ’1’ value of this bit specifies that the current block in NAND Flash is in locked status.
LTS (Lock-tighten Status): ’1’ value of this bit specifies that current block in NAND Flash is lock-tighten.
7.27 ECC Status Register(R): FF00h, default=0000h
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reserved(00000000)
ERm1
ERs1
ERm0
ERs0
ERm (ECC Error for Main area data) & ERs (ECC Error for Spare area data)
: ERm0/1 is for first/second selected sector in main of BufferRAM, ERs0/1 is for first/second selected sector in spare of
BufferRAM.
ERm and ERs show the number of error nits in a sector as a result of ECC check at the load operation.
ERm, ERs
ECC Status
No Error
00
01
10
11
1-bit error(correctable)
2-bit error(uncorrectable)1)
Reserved
NOTE:
1. 3bits or more error detection is not supported.
7.28 ECC Result of first selected Sector Main area data Register (R): FF01h, default=0000h
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reserved(0000)
ECCposWord0
ECCposIO0
7.29 ECC Result of first selected Sector Spare area data Register (R): FF02h, default=0000h
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reserved(0000000000)
ECClogSector0
ECCposIO0
7.30 ECC Result of second selected Sector Main area data Register (R): FF03h, default=0000h
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reserved(0000)
ECCposWord1
ECCposIO1
7.31 ECC Result of second selected Sector Spare area data Register (R): FF04h, default=0000h
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reserved(0000000000)
ECClogSector1
ECCposIO1
NOTE:
1. ECCposWord: ECC error position address that selects one of Main area data(256words)
2. ECCposIO: ECC error position address which selects one of sixteen DQs (DQ 0~DQ 15).
3. ECClogSector: ECC error position address that selects one of the 2nd word and LSB of the 3rd word of spare area. Refer to the below table.
ECClogSector Information [5:4]
ECClogSector
Error Position
2nd word
00
01
3rd word
10, 11
Reserved
4. ECCposWord, ECCposIO and ECClogSector are updated in boot loading operation, too.
30
OneNAND128
FLASH MEMORY
8. Device Operation
The device supports both a limited command based and a register based interface for performing operations on the device, reading
device ID, writing data to buffer etc. The command based interface is active in the boot partition, i.e. commands can only be written
with a boot area address. Boot area data is only returned if no command has been issued prior to the read.
8.1 Command based operation
The entire address range, except for the boot area, can be used for the data buffer. All commands are written to the boot partition. Writes outside the
boot partition are treated as normal writes to the buffers or registers. The command consists of one or more cycles depending on the command. After
completion of the command the device starts its execution. Writing incorrect information which include address and data or writing an improper command
will terminate the previous command sequence and make the device go to the ready status. The defined valid command sequences are stated in Table4.
Table 4. Command Sequences
Command Definition
Cycles
1st cycle
2nd cycle
DP1)
Data
DP
Add
Data
Add
Read Data from Buffer
1
Write Data to Buffer
Reset OneNAND
1
1
2
2
Data
Add
Data
BP2)
Data
Add
00F0h
BP
BP
Load Data into Buffer3)
Read Identification Data 6)
0000h4)
XXXXh5)
Data
Data
Add
00E0h
BP
Data
0090h
NOTE:
1) DP(Data Partition) : DataRAM Area
2) BP(Boot Partition) : BootRAM Area [0000h ~ 01FFh, 8000h ~ 800Fh].
3) Load Data into Buffer operation is available within a block(64KB)
4) Load 1KB unit into DataRAM0. Current Start address(FPA) is automatically incremented by 1KB unit after the load.
5) 0000h -> Data is Manufacturer ID
0001h -> Data is Device ID
0002h -> Current Block Write Protection Status
6) WE toggling can terminate ’Read Identification Data’ operation.
8.1.1 Read Data from Buffer
Buffer can be read by addressing a read to a wanted buffer area
8.1.2 Write Data to Buffer
Buffer can be written by addressing a write to a wanted buffer area
8.1.3 Reset OneNAND
Reset command is given by writing 00F0h to the boot partition address. Reset will return all default values into the device.
8.1.4 Load Data into Buffer
Load Data into Buffer command is a two-cycle command. Two sequential designated command activates this operation. Sequentially writing 00E0h
and 0000h to the boot partition [0000h~01FFh, 8000h~800Fh] will load one page to DataRAM0. This operation refers to FBA and FPA. FSA, BSA, and
BSC are not considered.
At the end of this operation, FPA will be automatically increased by 1. So continuous issue of this command will sequentially load data in next page to
DataRAM0. This page address increment is restricted within a block.
The default value of FBA and FPA is 0. Therefore, initial issue of this command after power on will load the first page of memory, which is usually boot
code.
8.1.5 Read Identification Data
Read Identification Data command consists of two cycles. It gives out the devices identification data according to the given address. The first cycle is
0090h to the boot partition address and second cycle is read from the addresses specified in Table5.
31
OneNAND128
FLASH MEMORY
Table 5. Identification data description
Address
Data Out
0000h
0001h
0002h
Manufacturer ID
Device ID
00ECh
refer to table 1
refer to NAND Flash Write Protection Status Register
Current Block Write Protection Status
8.2 Device Bus Operations
Operation
Standby
CE
OE
X
WE
X
ADD0~15 DQ0~15
RP
H
CLK
X
AVD
X
H
X
X
X
High-Z
High-Z
Warm Reset
X
X
L
X
X
Asynchronous Write
Asynchronous Read
Load Initial Burst Address
Burst Read
L
L
L
L
H
L
H
H
H
Add. In
Add. In
Add. In
X
Data In
Data Out
X
H
H
H
H
L
L
L
H
L
Burst Data
Out
X
Terminate Burst Read
Cycle
H
X
X
X
H
X
X
X
High-Z
High-Z
H
L
X
X
X
X
Terminate Burst Read
Cycle via RP
Terminate Current Burst
Read Cycle and Start
New Burst Read Cycle
H
H
Add In
High-Z
H
Note : L=VIL (Low), H=VIH (High), X=Don’t Care.
32
OneNAND128
FLASH MEMORY
8.3 Reset Mode
Cold Reset
At system power-up, the voltage detector in the device detects the rising edge of Vcc and releases internal power-up reset signal
which triggers bootcode loading. Bootcode loading means that the boot loader in the device copies designated sized data(1KB) from
the beginning of memory to the BootRAM.
POR triggering level
System Power
1)
Bootcode - copy done
OneNAND
Operation
Sleep
Bootcode copy
2)
Idle
RP
High-Z
INT
3)
INT bit
0 (default)
1
IOBE bit
0 (default)
1 (default)
1
INTpol bit
Note: 1) Bootcode copy operation starts 400us later than POR activation.
The system power should reach 1.7V after POR triggering level(typ. 1.5V) within 400us for valid boot code data.
2) 1K bytes Bootcode copy takes 70us(estimated) from sector0 and sector1/page0/block0 of NAND Flash array to BootRAM.
Host can read Bootcode in BootRAM(1K bytes) after Bootcode copy completion.
3) INT register goes ‘Low’ to ‘High’ on the condition of ‘Bootcode-copy done’ and RP rising edge.
If RP goes ‘Low’ to ‘High’ before ‘Bootcode-copy done’, INT register goes to ‘Low’ to ‘High’ as soon as ‘Bootcode-copy done’
Figure 5. Cold Reset Timings
33
OneNAND128
FLASH MEMORY
Warm Reset
Warm reset means that the host resets the device by RP pin, and then the device stops all logic current operation and executes inter-
nal reset operation(Note 1) synchronized with the falling edge of RP and resets current NAND Flash core operation synchronized with
the rising edge of RP. The device logic will not be reset in case RP pulses shorter than 200ns, but the device guarantees the logic
reset operation in case RP pulse is longer than 200ns. NAND Flash core reset will abort current NAND Flash Core operation. The
contents of memory cells being altered are no longer valid as the data will be partially programmed or erased. Warm reset has no
effect on contents of BootRAM and DataRAM.
CE, OE
RP
initiated by RP low
Operation or Idle internal reset operation NAND Flash core reset Idle Operation Operation or Idle
initiated by RP high
MuxOneNAND
Operation
INT
High-Z
High-Z
High-Z
RDY
Figure 6. Warm Reset Timings
34
OneNAND128
FLASH MEMORY
Hot Reset
Hot reset means that the host resets the device by reset command(Note 2), and then the device logic stops all current operation and
executes internal reset operation(Note 1) , and resets current NAND Flash core operation. Hot reset has no effect on contents of
BootRAM and DataRAM.
AVD
BP(Note 3)
or F220h
A0~A15
00F0h
or 00F3h
DQ0~DQ15
CE
WE
INT
High-Z
RDY
OneNAND
Operation
Idle
Operation or Idle
OneNAND reset
Figure 7. Hot Reset Timings
NOTE:
1. Internal reset operation means that the device initializes internal registers and makes output signals go to default status and bufferRAM data are kept
unchanged after Warm/Hot reset operations.
2. Reset command : Command based reset or Register based reset
3. BP(Boot Partition) : BootRAM area[0000h~01FFh, 8000h~800Fh]
35
OneNAND128
FLASH MEMORY
NAND Flash Core Reset
Host can reset NAND Flash Core operation by NAND Flash Core reset command. NAND Flash Core Reset will abort the current
NAND Flash core operation. During a NAND Flash Core Reset, the content of memory cellls being altered is no longer valid as the
data will be partially programmed or erased. NAND Flash Core Reset has an effect on neither contents of BootRAM and DataRAM
nor register values.
AVD
F220h
A0~A15
DQ0~DQ15
CE
00F0h
WE
INT
High-Z
RDY
OneNAND
Operation
Idle
Operation or Idle
NAND Flash Core reset
Figure 8. NAND Flash Core Reset Timings
36
OneNAND128
FLASH MEMORY
Table 6. Internal Register reset
Hot
Reset
(00F3h) (BP-F0)
Hot
Reset
Warm Reset
(RP)
NAND Flash
Reset(00F0h)
Internal Registers
Default Cold Reset
F000h Manufacturer ID Register (R)
00ECh
Note3
-
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
F001h Device ID Register (R)
N/A
F002h Version ID Register (rR)
N/A
N/A
N/A
F003h Data Buffer size Register (R)
0400h
0200h
0201h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
40C0h
0000h
-
N/A
N/A
N/A
F004h Boot Buffer size Register (R)
N/A
N/A
N/A
F005h Amount of Buffers Register (R)
F006h Technology Register (R)
N/A
N/A
N/A
N/A
N/A
N/A
F100h Start Address1 Register (R/W): FBA
F101h Start Address2 Register (R/W): Reserved
F102h Start Address3 Register (R/W): FCBA
F103h Start Address4 Register (R/W): FCPA, FCSA
F107h Start Address8 Register (R/W): FPA, FSA
F200h Start Buffer Register (R/W): BSA, BSC
F220h Command Register (R/W)
0000h
0000h
0000h
0000h
0000h
0000h
0000h
40C0h
0000h
8080h
0000h
0000h
0002h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
O (Note1)
0000h
8010h
0000h
0000h
0002h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
O (Note1)
0000h
8010h
N/A
F221h System Configuration 1 Register (R/W)
F240h Controller Status Register (R)
F241h Interrupt Status Register (R/W)
F24Ch Lock/Unlock Start Block Address (R/W)
F24Dh Lock/Unlock End Block Address (R/W)
F24Eh NAND Flash Write Protection Status (R)
FF00h ECC Status Register (R) (Note2)
0000h
0000h
0002h
0000h
0000h
0000h
0000h
0000h
N/A
N/A
0000h
0000h
0000h
0000h
0000h
ECC Result of Sector 0 Main area data Register(R)
FF02h ECC Result of Sector 0 Spare area data Register (R)
FF01h
ECC Result of Sector 1 Main area data Register(R)
ECC Result of Sector 1 Spare area data Register (R)
FF03h
FF04h
NOTE: 1) RDYpol, INTpol, and IOBE are reset by Cold reset. The other bits are reset by Cold/Warm/Hot reset.
OTPL is not reset but updated by Cold reset.
2) ECC Status Register & ECC Result Registers are reset when any command is issued.
3) Refer to table 1
37
OneNAND128
FLASH MEMORY
Write Protection
Write Protection for BootRAM
At system power-up, the voltage detector in the device detects the rising edge of Vcc and releases the internal power-up reset signal
which triggers bootcode loading. And the designated size data(1KB) is copied from the beginning of the memory to the BootRAM.
After the bootcode loading is completed, the BootRAM is always locked to protect the significant boot code from accidental write.
Write Protection for NAND Flash array
Write Protection Modes
The device offers both hardware and software write protection features for NAND Flash array. The software write protection feature is
used by writing Lock command or Lock-tight command to command register; The 002Ah or 002Ch command is written into F220h
register. The partial write protection feature is also permitted by writing Partial Lock(002Ah) and Partial Lock-Tight(002Ch) command
with the start address and the end address to F24Ch and F24Dh registers. The hardware write protection feature is used by executing
cold or warm reset. The default state is locked, and all NAND Flash array goes to locked state after cold or warm reset.
Write Protection Commands
Individual or consecutive instant secured block protects code and data by allowing any block to be locked or lock-tighten. The write
protection scheme offers two levels of protection. The first allows software-only control of write protection(useful for frequently
changed data blocks), while the second requires hardware interaction before locking can be changed(protects infrequently changed
code blocks).
The following summarize the locking functionality.
> All blocks power-up in a locked state. Unlock command can unlock these blocks with the start and end block address.
> Partial Lock-Tight command makes the part of locked block(s) to be lock-tightened by writing the start and end block address. And
lock-tightened state can be returned to lock state only when cold or warm reset is asserted.
> Only one individual area can be lock-tightened by Partial Lock-tight command; i.e lock-tightening multi area is not available.
> Lock-tightened blocks offer the user an additional level of write protection beyond that of a regular locked block. Lock-tightened
block can’t have it’s state changed by software, it can be changed by warm reset or cold reset.
> Unlock start or end block address is reflected immediately to the device only when Unlock command is issued, and NAND Flash
write protection status register is also updated at that time.
> Unlocked blocks can be programmed or erased.
> Only one area can be released from lock state to unlock state with Unlock command and addresses. This unlocked area can be
changed with new Unlock command; when new Unlock command is issued, last unlocked area is locked again and new area is
unlocked.
> Partial Lock command makes the part of unlocked block(s) to be locked with the start and end block address.
> Only one area can be locked with Partial Lock command and address. This locked area can be changed with new Partial Lock com-
mand; when new Partial Lock command is issued, last unlocked area is locked again and new area is unlocked.
Write Protection Status
The block current Write Protection status can be read in NAND Flash Write Protection Status Register(F24Eh). There are three bits -
US, LS, LTS -, which are not cleared by hot reset. These Write Protection status registers are updated when Write Protection com-
mand is entered.
The followings summarize locking status.
example)
In default, [2:0] values are 010.
-> If host executes unlock block operation, then [2:0] values turn to 100.
-> If host executes lock-tight block operation, then [2:0] values turn to 001.
38
OneNAND128
FLASH MEMORY
Locked
> Command Sequence :
Start block address+End block address+Lock block command
(002Ah)
> All blocks default to be locked after Cold reset or Warm reset
> Unlocked blocks can be locked by using the Lock block
command and a lock block’s status can be changed to
unlock or lock-tight using the appropriate software commands
Unlocked
> Command Sequence :
Start block address+End block address+Unlock block command
(0023h)
> Unlocked block can be programmed or erased
> An unlocked block’s status can be changed to the locked or
lock-tighten state using the appropriate software command
> Only one sequential area can be released to unlock state from
lock state ; Unlocking multi individual area is not available
Lock-tighten
> Command Sequence :
Start block address+End block address+Lock-tight block command
(002Ch)
:> Lock-tighten blocks offer the user an additional level of write
protection beyond that of a regular lock block. A block that
is lock-tighten cannot have its state change by software,
only by Cold or Warm reset.
> Only locked blocks can be lock-tighten by Lock-tight command.
> Lock-tighten blocks revert to the locked state at Cold or Warm
reset
> Lock-tighten area does not change with any command;
when new unlock command is issued including the lock-tighten
area, new unlocked command is ignored.
Figure 9. Operations of NAND Flash Write Protection
39
OneNAND128
FLASH MEMORY
SBA, EBA
+Partial Lock
Command
SBA, EBA
+Partial Lock-tight
Command
SBA, EBA
+Unlock
Command
SBA, EBA
+Partial Lock
Command
Lock
Unlock
Lock
Lock
Lock
Unlock
Lock
Unlock
Unlock
Lock
Changed
with new
SBA, EBA
Changed
with new
SBA, EBA
SBA, EBA
+Unlock
Command
SBA, EBA
+Partial Lock-tight
Command
SBA, EBA
+Partial Lock-tight
Command
Lock-tight
Lock-tight
Power On
Lock
Lock
Lock
Sustained
with last
SBA, EBA
Lock-tight
Lock
Unlock
Note ; The below cases are prohibited in write protection modes.
Even though these cases happen, Error bit of Controller Status Register(F240h)is not updated.
Case1. Unlock
Lock-tight
SBA
If this case happens, the command is ignored and last status is sustained.
EBA
Lock
Case2. Lock
Lock-tight
SBA
If this case happens, the command is ignored and last status is sustained.
EBA
Unlock
Case3. Lock-tight
Lock
SBA
If this case happens, the selected area changes to be lock-tight.
EBA
Unlock
Figure 10. State diagram of NAND Flash Write Protection
40
OneNAND128
FLASH MEMORY
Load Operation
The load operation is initiated by setting up the start address from which the data is to be loaded. The load command is issued in
order to initiate the load. The device transfers the data from NAND Flash array into the BufferRAM. The ECC is checked and any
detected and corrected error is reported in the status response as well as any unrecoverable error. When the BufferRAM has been
filled an interrupt is issued to the host in order to read the contents of the BufferRAM. The read from the BufferRAM consist of asyn-
chronous read mode or synchronous read mode. The status information related to the BufferRAM fill operation can be checked by
the host if required.
The device provides dual data buffer memory architecture. The device is capable of data-read operation from one data buffer and
data-load operation to the other data buffer simultaneously. Refer to the information for more details in "Read while Load operation".
Write ’Load’ Command
Start
Add: F220h
DQ=0000h or 0013h
Write ’FBA’ of Flash
Add: F100h DQ=FBA
Wait for INT register
low to high transition
Write ’FPA, FSA’ of Flash
Add: F107h DQ=FPA, FSA
Add: F241h DQ[15]=INT
Read Controller
Status Register
Write ’BSA, BSC’ of DataRAM
Add: F200h DQ=BSA, BSC
Add: F240h DQ[10]=Error
Write 0 to interrupt register
Add: F241h DQ=0000h
NO
DQ[10]=0?
YES
Map Out
Host reads data from
DataRAM
Read completed
Figure 11. Load operation flow-chart
41
OneNAND128
FLASH MEMORY
Read Operation
The device has two read configurations ; Asynchronous read and Synchronous burst read.
The initial state machine makes the device to be automatically entered into asynchronous read mode to prevent the memory content
from spurious altering upon device power up or after a hardware reset. No commands are required to retrieve data in asynchronous
mode. The synchronous mode will be enabled by setting RM bit of System configuration1 register to Synchronous read mode.
Asynchronous Read Mode (RM = 0)
For the asynchronous read mode a valid address should be asserted on A0-A15, while driving AVD and CE to VIL. WE should
remain at VIH . The data will appear on DQ15-DQ0. Address access time (tAA) is equal to the delay from valid addresses to valid out-
put data. The chip enable access time(tCE) is the delay from the falling edge of CE to valid data at the outputs. The output enable
access time(tOE) is the delay from the falling edge of OE to valid data at the output.
Synchronous (Burst) Read Mode (RM = 1)
The device is capable of continuous linear burst operation and linear burst operation of a preset length. For the burst mode, the initial
word(tIAA) is output asynchronously regardless of BRL bit in System Configuration 1 register. But the host should determine BRL bit
of System configuration 1 register for the subsequent words of each burst access. The registers also can be read during burst read
mode by using AVD signal with a address. To initiate the synchronous read again, a new address during CE and AVD low toggle is
needed after the host has completed status reads or the device has completed the program or erase operation.
Continuous Linear Burst Read
The initial word(tIAA) is output asynchronously regardless of BRL bit in System Configuration 1 register. Subsequent words are output
tBA after the rising edge of each successive clock cycle, which automatically increments the internal address counter. The RDY output
indicates this condition to the system by pulsing low. The device will continue to output sequential burst data, wrapping around after it
reaches the designated location(See Figure 12 for address map information) until the system asserts CE high, RP low or AVD low in
conjunction with a new address. The cold/warm/hot reset or asserting CE high or WE low pulse terminate the burst read operation.
If the device is accessed synchronously while it is set to asynchronous read mode, it is possible to read out the first data without prob-
lems.
Division
Add.map(word order)
0000h~01FFh
0200h~03FFh
0400h~05FFh
0600h~7FFFh
8000h~800Fh
8010h~801Fh
8020h~802Fh
8030h~8FFFh
9000h~EFFFh
F000h~FFFFh
BootM(0.5Kw)
BufM 0(0.5Kw)
BufM 1(0.5Kw)
Reserved Main
BootS(16w)
Buffer0
Not Support
Not Support
Buffer1
N/A Reg.
Not Support
Buffer0
Buffer1
N/A Reg.
Reg.
BufS 0(16w)
BufS 1(16w)
Reserved Spare
Reserved Reg.
Register(4Kw)
* Reserved area is not available on Synchronous read
Figure 12. The boundary of synchronous read
42
OneNAND128
FLASH MEMORY
4-, 8-,16-, 32- Word Linear Burst Read
As well as the Continuous Linear Burst Mode, there are four(4 & 8 & 16 & 32 word) (Note1) linear wrap-around mode, in which a fixed
number of words are read from consecutive addresses. When the last word in the burst mode is reached, assert /CE and /OE high to
terminate the operation. In these modes, the start address for burst read can be any address of address map.
(Note 1) 32 word linear burst read isn’t available on spare area BufferRAM
Table 7. Burst Address Sequences
Burst Address Sequence(Decimal)
Start
Addr.
Continuous Burst
0-1-2-3-4-5-6...
1-2-3-4-5-6-7...
2-3-4-5-6-7-8...
4-word Burst
0-1-2-3-0...
1-2-3-0-1...
2-3-0-1-2...
8-word Burst
16-word Burst
32-word Burst
0
1
2
0-1-2-3-4-5-6-7-0...
1-2-3-4-5-6-7-0-1...
2-3-4-5-6-7-0-1-2...
0-1-2-3-4-....-13-14-15-0...
1-2-3-4-5-....-14-15-0-1...
2-3-4-5-6-....-15-0-1-2...
0-1-2-3-4-....-29-30-31-0...
1-2-3-4-5-....-30-31-0-1...
2-3-4-5-6-....-31-0-1-2...
Wrap
around
.
.
.
.
.
.
.
.
.
.
.
.
Programmable Burst Read Latency
The programmable burst read latency feature indicates to the device the number of additional clock cycles that must elapse after
AVD is driven active before data will be available. Upon power up, the number of total initial access cycles defaults to four clocks. The
number of total initial access cycles is programmable from three to seven cycles.
Rising edge of the clock cycle following last read latency
triggers next burst data
CE
CLK
5
6
-1
0
1
2
3
4
AVD
tBA
Valid
A0:
A15
Address
DQ0:
DQ15
D6
D7
D0
D1
D2
D3
D7
D0
tIAA
tRDYS
OE
Hi-Z
tRDYA
Hi-Z
RDY
Figure 13. Example of 4 clock Burst Read Latency
Handshaking
The handshaking feature allows the host system to simply monitor the RDY signal from the device to determine when the initial word
of burst data is ready to be read. To set the number of initial cycle for optimal burst mode, the host should use the programmable
burst read latency configuration.(See "System Configuration1 Register" for details.) The rising edge of RDY which is derived from 1
clock ahead of data fetch clock indicates the initial word of valid burst data.
Output Disable Mode
When the CE or OE input is at VIH , output from the device is disabled. The outputs are placed in the high impedance state.
43
OneNAND128
FLASH MEMORY
Program Operation
The device can be programmed in data unit. Programming is writing 0's into the memory array by executing the internal program rou-
tine. In order to perform the Internal Program Routine, command sequence is necessary. First, host sets the address of the Buffer-
RAM and the memory location and loads the data to be programmed into the BufferRAM. Second, program command initiates the
internal program routine. During the execution of the Routine, the host is not required to provide further controls or timings. During the
Internal Program Routine, commands except reset command written to the device will be ignored. Note that a reset during a program
operation will cause data corruption at the corresponding location.
The device provides dual data buffer memory architecture. The device is capable of data-write operation from host to one of data buff-
ers during program operation from anther data buffer to Flash simultaneously. Refer to the information for more details in "Read while
Load operation".
Write 0 to interrupt register
Start
Add: F241h DQ=0000h
Write Data into DataRAM1)
Write ’Program’ Command
ADD: DP DQ=Data-in
Add: F220h
DQ=0080h or 001Ah
NO
Data Input
Completed?
Wait for INT register
low to high transition
YES
Add: F241h DQ[15]=INT
Write ’FBA’ of Flash
Add: F100h DQ=FBA
Read Controller
Status Register
Write ’FPA, FSA’ of Flash
Add: F107h DQ=FPA, FSA
Add: F240h DQ[10]=Error
Write ’BSA, BSC’ of DataRAM
Add: F200h DQ=BSA, BSC
DQ[10]=0?
YES
NO
Program completed
Program Error
: If program operation results in an error, map out
the block including the page in error and copy the
target data to another block.
*
Note 1) Data input could be done anywhere between "Start" and "Write Program Command".
Figure 14. Program operation flow-chart
44
OneNAND128
FLASH MEMORY
Addressing for program operation
Within a block, the pages must be programmed consecutively from the LSB (least significant bit) page of the block to MSB (most sig-
nificant bit) pages of the block. Random page address programming is prohibited.
(64)
(64)
Page 63
Page 31
Page 63
Page 31
:
:
(1)
:
(32)
:
(3)
(2)
(1)
Page 2
Page 1
Page 0
(3)
(32)
(2)
Page 2
Page 1
Page 0
Data register
Data register
From the LSB page to MSB page
DATA IN: Data (1)
Data (64)
Ex.) Random page program (Prohibition)
DATA IN: Data (1)
Data (64)
45
OneNAND128
FLASH MEMORY
Copy-back Program Operation
The copy-back program is configured to quickly and efficiently rewrite data stored in one page by sector unit(1/2 sector) without utiliz-
ing an external memory. Since the time-consuming cycles of serial access and re-loading cycles are removed, the system perfor-
mance is improved. The benefit is especially obvious when a portion of a block is updated and the rest of the block also need to be
copied to the newly assigned free block. The operation for performing a copy-back program is a sequential execution of page-read
without serial access and copying-program with the address of destination page.
Write ’Copy-back Program’
command
Start
Add: F220h DQ=001Bh
Write ’FBA’ of Flash
Add: F100h DQ=FBA
Wait for INT register
low to high transition
Write ’FPA, FSA’ of Flash
Add: F107h DQ=FPA, FSA
Add: F241h DQ[15]=INT
Read Controller
Status Register
Write ’FCBA’ of Flash
Add: F102h DQ=FCBA
Add: F240h DQ[10]=Error
Write ’FCPA, FCSA’ of Flash
Add: F103h DQ=FCPA, FCSA
DQ[10]=0?
YES
NO
Write ’BSA, BSC’ of DataRAM
Add: F200h DQ=BSA, BSC1)
Copy back completed
Copy back Error
Write 0 to interrupt register
Add: F241h DQ=0000h
: If program operation results in an error, map out
the block including the page in error and copy the
target data to another block.
*
Note 1) Selected DataRAM by BSA & BSC is used for Copy back operation, so previous data is overwritten.
Figure 15. Copy back program operation flow-chart
46
OneNAND128
FLASH MEMORY
Copy-Back Program Operation with Random Data Input
The Copy-Back Program Operation with Random Data Input in OneNAND consists of 2 phase, Load data into DataRAM, Modify data
and program into designated page. Data from the source page is saved in one of the on-chip DataRAM buffers and modified by the
host, then programmed into the destination page.
As shown in the flow chart, data modification is possible upon completion of load operation. ECC is also available at the end of load
operation. Therefore, using hardware ECC of OneNAND, accumulation of 1 bit error can be avoided.
Copy-Back Program Operation with Random Data Input will be effectively utilized at modifying certain bit, byte, word, or sector of
source page to destination page while it is being copied.
Start
NO
DQ[10]=0?
YES
Map Out
Write ’FBA’ of Flash
Add: F100h DQ=FBA
Random Data Input
Write ’FPA, FSA’ of Flash
Add: F107h DQ=FPA, FSA
Add: Random Address in
Selected DataRAM
DQ=Data
Write ’BSA, BSC’ of DataRAM
Add: F200h DQ=BSA, BSC
Write ’FBA’ of Flash
Add: F100h DQ=FBA
Write 0 to interrupt register
Add: F241h DQ=0000h
Write ’FPA, FSA’ of Flash
Add: F107h DQ=FPA, FSA
Write ’Load’ Command
Write 0 to interrupt register
Add: F241h DQ=0000h
Add: F220h
DQ=0000h or 0013h
Write ’Program’ Command
Wait for INT register
low to high transition
Add: F220h
DQ=0080h or 001Ah
Add: F241h DQ[15]=INT
Wait for INT register
low to high transition
Read Controller
Status Register
Add: F241h DQ[15]=INT
Add: F240h DQ[10]=Error
Read Controller
Status Register
Add: F240h DQ[10]=Error
DQ[10]=0?
YES
NO
Copy back Error
Copy back completed
Figure 16. Copy-Back Program Operation with Random Data Input Flow Chart
47
OneNAND128
FLASH MEMORY
Erase Operation
The device can be erased in block unit. To erase a block is to write 1′s into the desired memory block by executing the Internal Erase
Routine. In order to perform the Internal Erase Routine, command sequence is necessary. First, host sets the block address of the
memory location. Second, erase command initiates the internal erase routine. During the execution of the Routine, the host is not
required to provide further controls or timings.
During the Internal erase routine, commands except reset and erase suspend command written to the device will be ignored.
Note that a reset during a erase operation will cause data corruption at the corresponding location.
Start
Write ’FBA’ of Flash
Add: F100h DQ=FBA
Write 0 to interrupt register
Add: F241h DQ=0000h
Write ’Erase’ Command
Add: F220h DQ=0094h
Wait for INT register
low to high transition
Add: F241h DQ=[15]=INT
Read Controller
Status Register
Add: F240h DQ[10]=Error
DQ[10]=0?
YES
NO
Erase completed
Erase Error
Figure 17. Erase operation flow-chart
48
OneNAND128
FLASH MEMORY
Multi Block Erase and Multi Block Erase Verify Read Operation
The device can be simultaneously erased in multi blocks unit, too. The block address of the memory location and Multi Block Erase
command may be repeated for erasing multi blocks. The final block address and Block Erase command initiate the internal multi
block erase routine. During Multi Block Erase routine, if the command except Multi Block Erase command is written before Block
Erase command is issued, Multi Block Erase operation will be aborted. Erase Suspend command is allowed only when INT is Low
after Block Erase command is issued.
Pass/fail status of each block in Multi Block Erase operation can be read by writing each block address and Multi Block Erase Verify
Read command. But the information of the failed address has to be managed by the firmware. After Block Erase operation, the pass/
fail status can be read with Multi Block Erase Verify Read command, too.
Note that a reset during a erase operation will cause data corruption at the corresponding location.
Read Controller
Status Register
Write ’FBA’ of Flash
Add: F100h DQ=FBA
Start
Add: F240h DQ[10]=Error
Write ’FBA’ of Flash
Add: F100h DQ=FBA
Write 0 to interrupt register
Add: F241h DQ=0000h
DQ[10]=0?
Write 0 to interrupt register
Add: F241h DQ=0000h
NO
Write ’Block Erase
Command’
YES
Add: F220h DQ=0094h
Erase completed
Write ’Multi Block Erase’
Command
Wait for INT register
low to high transition
Add: F220h DQ=0095h
Erase Error
Add: F241h DQ=[15]=INT
NO
Wait for INT register
low to high transition
Final Multi Block
Erase Address?
Write ’FBA’ of Flash
Add: F100h DQ=FBA
Add: F241h DQ=[15]=INT
YES
Multi Block Erase completed
NO
Final Multi Block
Erase?
Write 0 to interrupt register
Add: F241h DQ=0000h
Multi Block Erase Verify Read
YES
Write ’Multi Block Erase
Verify Read Command’
Add: F220h DQ=0071h
Wait for INT register
low to high transition
Add: F241h DQ=[15]=INT
Figure 18. Multi Block Erase operation flow-chart
NOTE:
1. If there are the locked blocks in the specified range, the operation works as the follows.
Case 1. [BA(1)+0095h] + [BA(2, locked)+0095h] + ... + [BA(N-1)+0095h] + [BA(N)+0094h] = All specified blocks except BA(2) are erased.
Case 2. [BA(1)+0095h] + [BA(2)+0095h] + ... + [BA(N-1)+0095h] + [BA(N, locked)+0094h] = If the last command, Block Erase command, is put
together with the locked block address, Multi Block Erase operation doesn’t start and is suspended until right command and address input.
Case 3. [BA(1)+0095h] + [BA(2)+0095h] + ... + [BA(N-1)+0095h] + [BA(N, locked)+0094h] + [BA(N+1)+0094h]= All specified blocks except BA(N) are
erased.
2. The OnGo bit of Controller Status register is set to ’1’(busy) from the time of writing the 1st block address to be latched until the actual erase has fin-
ished.
3. Even though the failed blocked happen during multi block erase operation, the device continues the erase operation until other specified blocks are
erased.
49
OneNAND128
FLASH MEMORY
Erase Suspend / Resume
Erase Suspend command interrupts Block Erase and Multi Block Erase to load or program data in a block that is not being erased.
When Erase Suspend command is written during Block Erase and Multi Block Erase operation, the device requires a maximum of
500us to suspend erase operation. After the erase operation has been suspended, the device is available for loading or programming
data in a block that is not being erased. For the erase suspend period, Block Erase, Multi Block Erase and Erase Suspend com-
mands are not accepted.
When Erase Resume command is executed, Block Erase and Multi Block Erase operation will resume. The Erase Resume operation
does not actually resume the erase, but starts it again from the beginning. When Erase Suspend and Erase Resume command is
executed, the addresses are in Don’t Care state.
Write 0 to interrupt register
Add: F241h DQ=0000h
Start
Write 0 to interrupt register
Add: F241h DQ=0000h
Write ’Erase Resume
Command’
Add: F220h DQ=0030h
Write ’Erase Suspend
Command’1)
Wait for INT register
low to high transition
Add: F220h DQ=00B0h
Add: F241h DQ=[15]=INT
Wait for INT register
low to high transition for 500us
Check Controller Status Register
in case of Block Erase
Add: F241h DQ=[15]=INT
Do Multi Block Erase Verify Read
in case of Multi Block Erase
Another Operation *
* Another Operation ; Load, Program
Copy-back Program, OTP Access2),
Hot Reset, Flash Reset, CMD Reset,
Multi Block Erase Verify, Lock,
Lock-tight, Unlock
Note 1) Erase Suspend command input is prohibited during Multi Block Erase address latch period.
2) If OTP access mode exit happens with Reset operation during Erase Suspend mode,
Reset operation could hurt the erase operation. So if a user wants to exit from OTP access mode
without the erase operation stop, Reset NAND Flash Core command should be used.
Figure 19. Erase Suspend and Resume operation flow-chart
50
OneNAND128
FLASH MEMORY
OTP Operation
The device supports one block sized OTP area, which can be read, programmed and locked with the same sequence as normal
operation. But this OTP block could not be erased. This block is separated from NAND Flash Array, so it could be accessed by OTP
Access command instead of FBA. If user wants to exit from OTP access mode, Cold, Warm and Hot Reset operation should be done.
But if OTP access mode exit happens with Reset operation during Erase Suspend mode, Reset operation could hurt the erase oper-
ation. So if user wants to exit from OTP access mode without the erase operation stop, ’Reset NAND Flash Core’ command should
be used.
OTP area is one block size(64KB, 64pages) and is divided by two areas. The first area from page 0 to page 19, total 20pages, is
assigned for user and the second area from page 20 to page 63, total 44pages, are occupied for the device manufacturer. The sec-
ond area is programmed prior to shipping, so this area could not be used by user.
This block is fully guaranteed to be a valid block.
OTP Block Page Allocation Information
Area
User
Page
Use
0 ~ 19 (20 pages)
20 ~ 63 (44 pages)
Designated as user area
Used by the device manufacturer
Manufacturer
Page:1KB+32B
Sector(main area):512B
One Block:
64pages
Sector(spare area):16B
64KB+2KB
Manufacturer Area :
20pages
page 20 to page 63
User Area :
20pages
page 0 to page 19
Figure 20. OTP area structure and assignment
51
OneNAND128
FLASH MEMORY
OTP Load(OTP Access+Load NAND)
OTP area is separated from NAND Flash Array, so it is accessed by OTP Access command instead of FBA. The content of OTP
could be loaded with the same sequence as normal load operation after being accessed by the command. If user wants to exit from
OTP access mode, Cold, Warm, Hot, and NAND Flash Core Reset operation should be done.
Write 0 to interrupt register
Add: F241h DQ=0000h
Start
Write ’FBA’ of Flash1)
Add: F100h DQ=FBA
Write ’Load’ Command
Add: F220h
DQ=0000h or 0013h
Write 0 to interrupt register
Add: F241h DQ=0000h
Wait for INT register
low to high transition
Write ’OTP Access’ Command
Add: F220h DQ=0065h
Add: F241h DQ[15]=INT
Host reads data from
DataRAM
Wait for INT register
low to high transition
Add: F241h DQ[15]=INT
OTP Load completed
Write ’FPA, FSA’ of Flash1)
Add: F107h DQ=FPA, FSA
Do Cold/Warm/Hot
/NAND Flash Core reset
Write ’BSA, BSC’ of DataRAM
Add: F200h DQ=BSA, BSC
OTP Exit
Note 1) FBA(NAND Flash Block Address) could be omitted or any address.
Figure 21. OTP Load operation flow-chart
52
OneNAND128
FLASH MEMORY
OTP Programming(OTP Access+Program NAND)
OTP area could be programmed with the same sequence as normal program operation after being accessed by the command. To
avoid the accidental write, FBA should point the unlocked area address among NAND Flash Array address map even though OTP
area is separated from NAND Flash Array.
Write ’FBA’ of Flash
Start
Add: F100h DQ=FBA3)
Write ’FBA’ of Flash1)
Write ’FPA, FSA’ of Flash
Add: F100h DQ=FBA
Add: F107h DQ=FPA, FSA
Write 0 to interrupt register
Add: F241h DQ=0000h
Write ’BSA, BSC’ of DataRAM
Add: F200h DQ=BSA, BSC
Write ’OTP Access’ Command
Add: F220h DQ=0065h
Write 0 to interrupt register
Add: F241h DQ=0000h
Wait for INT register
low to high transition
Write Program command
Add: F220h
Add: F241h DQ[15]=INT
DQ=0080h or 001Ah
Automatically
checked
Write Data into DataRAM2)
Add: DP DQ=Data-in
Automatically
updated
NO
OTPL=0?
YES
NO
Update Controller
Status Register
Data Input
Completed?
Wait for INT register
low to high transition
Add: F240h
DQ[14]=1(Lock), DQ[10]=1(Error)
Add: F241h DQ[15]=INT
Wait for INT register
low to high transition
Read Controller
Status Register
Add: F241h DQ[15]=INT
Add: F240h DQ[10]=0(Pass)
Read Controller
Status Register
OTP Programming completed
Add: F240h DQ[10]=1(Error)
Do Cold/Warm/Hot
/NAND Flash Core reset
Do Cold/Warm/Hot
/NAND Flash Core reset
OTP Exit
OTP Exit
Note 1) FBA(NAND Flash Block Address) could be omitted or any address.
2) Data input could be done anywhere between "Start" and "Write Program Command".
3) FBA should point the unlocked area address among NAND Flash Array address map.
Figure 22. OTP program operation flow-chart
53
OneNAND128
FLASH MEMORY
OTP Lock(OTP Access+Lock OTP)
OTP area could be locked by programming XXXCh to 8th word in sector0 of page0 to prevent the program operation. At the device
power-up, the device automatically checks this word and updates OTPL bit of Controller Status register as "1"(lock). If the program
operation happens in OTP locked status, the device updates Error bit of Controller Status register as "1"(fail).
Write ’FBA’ of Flash
Start
Add: F100h DQ=FBA3)
Write ’FBA’ of Flash1)
Write ’FPA, FSA’ of Flash
Add: F100h DQ=FBA
Add: F107h DQ=0000h
Write 0 to interrupt register
Add: F241h DQ=0000h
Write ’BSA, BSC’ of DataRAM
Add: F200h DQ=0001h
Write ’OTP Access’ Command
Add: F220h DQ=0065h
Write 0 to interrupt register
Add: F241h DQ=0000h
Wait for INT register
low to high transition
Write Program command
Add: F220h
DQ=0080h or 001Ah
Add: F241h DQ[15]=INT
Write Data into DataRAM2)
Wait for INT register
low to high transition
Add: 8th Word
in spare0/sector0/page0
DQ=XXXCh
Add: F241h DQ[15]=INT
Do Cold reset
Automatically
updated
Update Controller
Status Register
Add: F240h
DQ[6]=1(OTPL)
OTP lock completed
Note 1) FBA(NAND Flash Block Address) could be omitted or any address.
2) Data input could be done anywhere between "Start" and "Write Program Command".
3) FBA should point the unlocked area address among NADND Flash Array address map.
Figure 23. OTP lock operation flow-chart
54
OneNAND128
FLASH MEMORY
55
OneNAND128
FLASH MEMORY
56
OneNAND128
FLASH MEMORY
ECC Operation
While the device transfers data from BufferRAM to NAND Flash Array Page Buffer for Program Operation, the device hiddenly gener-
ates ECC(24bits for main area data and 10bits for 2nd and 3rd word data of each sector spare area) and while Load operation, hid-
denly generates ECC and detects error number and position and corrects 1bit error. ECC is updated by the device automatically.
After Load Operation, host can know whether there is error or not by reading ’ECC Status Register’(refer to ECC Status Register
Table). In addition, OneNAND supports 2bit EDC even though it is little probable that 2bit error occurs. Hence, it is not recommeded
that Host reads ’ECC Status Register’ for checking ECC error because the built-in Error Correction Logic of OneNAND finds out and
corrects ECC error.
When the device loads NAND Flash Array main and sprea area data with ECC operation, the device does not place the newly gener-
ated ECC for main and spare area into the buffer but places ECC which was generated and written in program operation into the
buffer.
Ecc operation is done during the boot loading operation.
ECC Bypass Operation
ECC bypass operation is set by 9th bit of System Configuration 1 register. In ECC Bypass operation, the device neither generates
ECC result which indicates error position nor updates ECC code to NAND Flash arrary spare area in program operation(refer to ECC
Result Register Tables). During Load operation, the on-chip ECC engine does not generate a new ECC internally and the values of
ECC Status and Result Registers are invalid. Hence, in ECC Bypass operation, the error cannot be detected and corrected by
OneNAND itself. ECC Bypass operation is not recommended to host.
Table 8. ECC Code & Result Status by ECC operation mode
Program operation
Load operation
Operation
ECC Code Update to NAND ECC Code at BufferRAM Spare ECC Status & Result Update
1bit Error
Flash Array Spare Area
Area
to Registers
Pre-written ECC code(1) loaded
Pre-written code loaded
ECC operation
ECC bypass
Update
Update
Correct
Not update
Invalid
Not correct
NOTE:
1. Pre-written ECC code : ECC code which is previously written to NAND Flash Spare Area in program operation.
57
OneNAND128
FLASH MEMORY
Data Protection during Power Down
The device is designed to offer protection from any involuntary program/erase during power-transitions. An internal voltage detector
disables all functions whenever Vcc is below about 1.3V. RP pin provides hardware protection and is recommended to be kept at VIL
before power-down.
VCC
typ. 1.3V
0V
RP
INT
NAND Write
Protected
OneNAND
Operation
Idle
One NAND Reset
Figure 24. Data Protection during Power Down
58
OneNAND128
FLASH MEMORY
Technical Notes
Invalid Block(s)
Invalid blocks are defined as blocks that contain one or more invalid bits whose reliability is not guaranteed by Samsung. The infor-
mation regarding the invalid block(s) is so called as the invalid block information. Devices with invalid block(s) have the same quality
level as devices with all valid blocks and have the same AC and DC characteristics. An invalid block(s) does not affect the perfor-
mance of valid block(s) because it is isolated from the bit line and the common source line by a select transistor. The system design
must be able to mask out the invalid block(s) via address mapping. The 1st block, which is placed on 00h block address, is fully guar-
anteed to be a valid block.
Identifying Invalid Block(s)
All device locations are erased(FFFFh) except locations where the invalid block(s) information is written prior to shipping. The invalid
block(s) status is defined by the 1st word in the spare area. Samsung makes sure that either the 1st or 2nd page of every invalid
block has non-FFFFh data at the 1st word of sector0. Since the invalid block information is also erasable in most cases, it is impos-
sible to recover the information once it has been erased. Therefore, the system must be able to recognize the invalid block(s) based
on the original invalid block information and create the invalid block table via the following suggested flow chart(Figure 24). Any
intentional erasure of the original invalid block information is prohibited.
Start
Set Block Address = 0
Increment Block Address
Check "FFFFh" at the sector0 1st word
of the 1st and 2nd page in the block
*
No
Check "
Create (or update)
Invalid Block(s) Table
FFFFh" ?
Yes
No
Last Block ?
Yes
End
Figure 25. Flow chart to create invalid block table.
59
OneNAND128
FLASH MEMORY
Technical Notes (Continued)
Error in write or load operation
Within its life time, additional invalid blocks may develop with the device. Refer to the qualification report for the actual data.The fol-
lowing possible failure modes should be considered to implement a highly reliable system. In the case of status read failure after
erase or program, block replacement should be done. Because program status fail during a page program does not affect the data of
the other pages in the same block, block replacement can be executed with a page-sized buffer by finding an erased empty block and
reprogramming the current target data and copying the rest of the replaced block.
Failure Mode
Erase Failure
Detection and Countermeasure sequence
Status Read after Erase --> Block Replacement
Status Read after Program --> Block Replacement
Error Correction by ECC mode of the device
Write
Load
Program Failure
Single Bit Failure
Block Replacement
Block A
1st
1
{
(n-1)th
nth
an error occurs.
Data Buffer0 of the device
(page)
1
Data Buffer1 of the device
Block B
(assuming maintain the nth page data)
1st
2
{
(n-1)th
nth
(page)
When an error happens in the nth page of the Block ’A’ during program operation.
* Step1
Then, copy the data in the 1st ~ (n-1)th page to the same location of the Block ’B’ via data buffer0.
* Step2
Copy the nth page data of the Block ’A’ in the data buffer1 to the nth page of another free block. (Block ’B’)
Do not further erase or program Block ’A’ by creating an ’invalid Block’ table or other appropriate scheme.
60
OneNAND128
FLASH MEMORY
Technical Notes (Continued)
Boot Sequence
One of the best features OneNAND has is that it can be a booting device itself since it contains an internally built-in boot loader
despite the fact that its core architecture is based on NAND Flash. Thus, OneNAND does not make any additional booting device
necessary for a system, which imposes extra cost or area overhead on the overall system.
As the system power is turned on, the boot code originally stored in NAND Flash Arrary is moved to BootRAM automatically and then
fetched by CPU through the same interface as SRAM’s or NOR Flash’s if the size of the boot code is less than 1KB. If its size is larger
than 1KB and less than or equal to 2KB, only 1KB of it can be moved to BootRAM automatically and fetched by CPU, and the rest of
it can be loaded into one of the DataRAMs whose size is 1KB by Load Command and CPU can take it from the DataRAM after finish-
ing the code-fetching job for BootRAM. If its size is larger than 2KB, the 1KB portion of it can be moved to BootRAM automatically
and fetched by CPU, and its remaining part can be moved to DRAM through two DataRAMs using dual buffering and taken by CPU
to reduce CPU fetch time.
A typical boot scheme usually used to boot the system with OneNAND is explained at Figure 26 and Figure 27. In this boot scheme,
boot code is comprised of BL1, where BL stands for Boot Loader, BL2, and BL3. Moreover, the size of the boot code is larger than
2KB (the 3rd case above). BL1 is called primary boot loader in other words. Here is the table of detailed explanations about the func-
tion of each boot loader in this specific boot scheme.
Boot Loaders in OneNAND
Boot Loader
BL1
Description
Moves BL2 from NAND Flash Array to DRAM through two DataRAMs using dual buffering
Moves OS image (or BL3 optionally) from NAND Flash Array to DRAM through two DataRams using dual buffering
Moves or writes the image through USB interface
BL2
BL3 (Optional)
NAND Flash Array of OneNAND is divided into the partitions as described at Figure 26 to show where each component of code is
located and how much portion of the overall NAND Flash Array each one occupies. In addition, the boot sequence is listed below and
depicted at Figure 27.
Boot Sequence :
1. Power is on
BL1 is loaded into BootRAM
2. BL1 is executed in BootRAM
BL2 is loaded into DRAM through two DataRams using dual buffering by BL1
3. BL2 is executed in DRAM
OS image is loaded into DRAM through two DataRams using dual buffering by BL2
4. OS is running
61
OneNAND128
FLASH MEMORY
Technical Notes (Continued)
Block 512
Reservoir
Partition 6
Partition 5
Sector 0 Sector 1
File System
Page 63
Page 62
Block 162
Os Image
Block 2
:
:
Partition 4
Partition 3
Page 2
Page 1
Page 0
BL3
Block 1
NBBLL11
BL2
BL1
Block 0
Figure 26. Partition of NAND Flash array
Reservoir
File System
Os Image
3
Data Ram 1
Data Ram 0
Os Image
BL 2
Boot Ram(BL 1)
BL1
BL2
2
1
NAND Flash Array
Internal BufferRAM
OneNAND
DRAM
NOTE:
and
can be copied into DRAM through two DataRAMs using dual buffering
3
2
Figure 27. OneNAND Boot Sequence
62
OneNAND128
FLASH MEMORY
Technical Notes (Continued)
Methods of Determining Interrupt Status
There are two methods of determining Interrupt Status on the OneNAND. Using the INT pin or monitoring the Interrupt Status Regis-
ter Bit.
The OneNAND INT pin is an output pin function used to notify the Host when a command has been completed. This provides a hard-
ware method of signaling the completion of a program, erase, or load operation.
In its normal state, the INT pin is high if the INT polarity bit is default. Before a command is written to the command register, the INT
bit must be written to '0' so the INT pin transitions to a low state indicating start of the operation. Upon completion of the command
operation by the OneNAND’s internal controller, INT returns to a high state.
INT is an open drain output allowing multiple INT outputs to be Or-tied together. INT does not float to a hi-Z condition when the chip is
deselected or when outputs are disabled. Refer to section 2.8 for additional information about INT.
INT can be implemented by tying INT to a host GPIO or by continuous polling of the Interrupt status register.
The INT Pin to a Host General Purpose I/O
INT can be tied to a Host GPIO to detect the rising edge of INT, signaling the end of a command operation.
COMMAND
INT
This can be configured to operate either synchronously or asynchronously as shown in the diagrams below.
63
OneNAND128
FLASH MEMORY
Technical Notes (Continued)
Synchronous Mode Using the INT Pin
When operating synchronously, INT is tied directly to a Host GPIO.
Host
OneNAND
CE
AVD
CLK
RDY
OE
CE
AVD
CLK
RDY
OE
GPIO
INT
Asynchronous Mode Using the INT Pin
When configured to operate in an asynchronous mode, /CE and /AVD of the OneNAND are tied to /CE of the Host. CLK is tied to the
Host Vss (Ground). /RDY is tied to a no-connect. /OE of the OneNAND and Host are tied together and INT is tied to a GPIO.
Host
CE
OneNAND
CE
AVD
CLK
RDY
OE
Vss
N.C
OE
GPIO
INT
Polling the Interrupt Register Status Bit
An alternate method of determining the end of an operation is to continuously monitor the Interrupt Status Register Bit instead of
using the INT pin.
Command
INT
This can be configured in either a synchronous mode or an asynchronous mode.
64
OneNAND128
FLASH MEMORY
Technical Notes (Continued)
Synchronous Mode Using Interrupt Status Register Bit Polling
When operating synchronously, /CE, /AVD, CLK, /RDY, /OE, and DQ pins on the host and OneNAND are tied together.
Host
CE
OneNAND
CE
AVD
CLK
RDY
OE
AVD
CLK
RDY
OE
DQ
DQ
Asynchronous Mode Using Interrupt Status Register Bit Polling
When configured to operate in an asynchronous mode, /CE and /AVD of the OneNAND are tied to /CE of the Host. CLK is tied to the
Host Vss (Ground). /RDY is tied to a no-connect. /OE and DQ of the OneNAND and Host are tied together.
Host
CE
OneNAND
CE
AVD
CLK
RDY
OE
Vss
N.C
OE
DQ
DQ
65
OneNAND128
FLASH MEMORY
Technical Notes (Continued)
Determing Rp Value
Because the pull-up resistor value is related to tr(INT), an appropriate value can be obtained by the following reference charts.
INT pol = ’High’
Internal Vcc
Rp
~50k ohm
INT
Ready Vcc
VOH
VOL
Vss
Busy State
tf
tr
@ Vcc = 1.8V, Ta = 25°C , CL = 30pF
5.420
2.431
1.75
2.142
0.045
Ibusy
0.18
1.788
0.06
0.09
0.7727
1.345
0.089
0.036
3.77
tr[us]
0.000
3.77
1K
3.77
10K
3.77
20K
3.77
3.77
40K
tf[ns]
30K
Open(100K)
50K
Rp(ohm)
66
OneNAND128
FLASH MEMORY
Technical Notes (Continued)
INT pol = ’Low’
Internal Vcc
INT
Rp
~50k ohm
tf
tr
Ready
Vcc
VOH
Busy State
Vss
VOL
@ Vcc = 1.8V, Ta = 25°C , CL = 30pF
4.05
1.84
1.75
1.623
0.045
Ibusy
0.18
1.356
0.06
0.09
1.02
0.586
0.067
0.036
6.49
tf[us]
0.000
6.49
6.49
10K
6.49
20K
6.49
6.49
40K
tr[ns]
30K
Open(100K)
1K
50K
Rp(ohm)
67
OneNAND128
FLASH MEMORY
ABSOLUTE MAXIMUM RATINGS
Rating
Parameter
Symbol
Unit
V
KFG2816Q1M
-0.5 to + 2.45
-0.5 to + 2.45
-30 to +125
-
KFG2816D1M
-0.6 to + 4.6
-0.6 to + 4.6
-30 to +125
-
KFG2816U1M
-0.6 to + 4.6
-0.6 to + 4.6
-30 to +125
-40 to +125
-65 to +150
5
Vcc
Vcc
VIN
Voltage on any pin relative
to VSS
All Pins
Extended
Industrial
Temperature Under Bias
Tbias
°C
Storage Temperature
Tstg
IOS
TA
-65 to +150
5
-65 to +150
5
°C
Short Circuit Output Current
mA
Extended
Industrial
-30 to + 85
-
-30 to + 85
-
-30 to + 85
-40 to + 85
Operating Temperature
°C
TA
NOTES:
1. Minimum DC voltage is -0.5V on Input/ Output pins. During transitions, this level should not fall to POR level(typ. 1.5V).
Maximum DC voltage is Vcc+0.6V on input / output pins which, during transitions, may overshoot to Vcc+2.0V for periods <20ns.
2. Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to the conditions
detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
9.2 RECOMMENDED OPERATING CONDITIONS ( Voltage reference to GND )
1.8V Device
2.65V Device
3.3V Device
Parameter
Symbol
Unit
Min
1.7
0
Typ.
Max
1.95
0
Min
2.4
0
Typ.
Max
2.9
0
Min
2.7
0
Typ.
Max
3.6
0
VCC-core
VCC- IO
VSS
V
1.8
0
2.65
0
3.3
0
Supply Voltage
V
NOTES:
1. The system power should reach 1.7V after POR triggering level(typ. 1.5V) within 400us.
2. Vcc-Core should reach the operating voltage level prior to Vcc-IO or at the same time.
68
OneNAND128
FLASH MEMORY
DC CHARACTERISTICS
1.8V device
2.65V device
3.3V device
Parameter
Symbol
Test Conditions
Unit
Min Typ Max Min Typ Max Min Typ Max
Input Leakage Current
ILI
VIN=VSS to VCC, VCC=VCCmax
- 1.0
- 1.0
-
-
+ 1.0 - 1.0
+ 1.0 - 1.0
-
-
+ 1.0 - 1.0
+ 1.0 - 1.0
-
-
+ 1.0 µA
+ 1.0 µA
Output Leakage Cur-
rent
VOUT=VSS to VCC, VCC=VCCmax,
CE or OE=VIH(Note 1)
ILO
Active Asynchronous
Read Current (Note 2)
ICC1
ICC2
CE=VIL, OE=VIH
-
8
15
-
10
20
-
10
20 mA
30 mA
54MHz
CE=VIL, OE=VIH
1MHz
-
-
12
3
20
4
-
-
20
4
30
6
-
-
20
4
Active Burst Read Cur-
rent (Note 2)
6
mA
Active Write Current
(Note 2)
ICC3
ICC4
ICC5
ICC6
CE=VIL, OE=VIH
-
-
-
-
8
15
25
25
-
-
-
10
20
20
18
20
30
30
25
-
-
-
-
10
20
20
18
20 mA
30 mA
30 mA
25 mA
Active Load Current
(Note 3)
CE=VIL, OE=VIH, WE=VIH,
VIN=VIH or VIL
20
20
15
Active Program Cur-
rent (Note 3)
CE=VIL, OE=VIH, WE=VIH,
VIN=VIH or VIL
Erase/Multi Block
Erase Current (Note 3)
CE=VIL, OE=VIH, WE=VIH,
VIN=VIH or VIL, 64blocks
20
50
-
-
Standby Current
Input Low Voltage
ISB
VIL
CE= RP=VCC ± 0.2V
-
10
-
15
-
50
-
15
-
50
µA
-
-0.5
0.4 -0.5
0.4
0
0.8
V
VCCq-
0.4
VCCq VCCq-
+0.4 0.4
VCCq
+0.4
0.7*V
CCq
Input High Voltage
Output Low Voltage
Output High Voltage
VIH
VOL
VOH
-
-
-
-
-
-
-
-
-
-
VCCq
V
V
V
IOL = 100 µA , VCC=VCCmin ,
VCCq=VCCqmin
0.22*
Vccq
-
0.2
-
-
0.2
-
-
IOH = -100 µA , VCC=VCCmin ,
VCCq=VCCqmin
VCCq-
0.1
VCCq-
0.4
0.8*V
CCq
-
1. CE should be VIH for RDY. IOBE should be ’0’ for INT.
2. Icc active for Host access
3. ICC active while Internal operation is in progress.
69
OneNAND128
FLASH MEMORY
VALID BLOCK
Parameter
Symbol
Min
Typ.
Max
Unit
Valid Block Number
NVB
251
-
256
Blocks
NOTES:
1. The device may include invalid blocks when first shipped. Additional invalid blocks may develop while being used. The number of valid blocks is pre-
sented with both cases of invalid blocks considered. Invalid blocks are defined as blocks that contain one or more bad bits. Do not erase or program
factory-marked bad blocks.
2. The 1st block, which is placed on 00h block address, is fully guaranteed to be a valid block.
CAPACITANCE(TA = 25 °C, VCC = 1.8V/2.65V/3.3V, f = 1.0MHz)
Item
Symbol
Test Condition
Min
Max
10
Unit
pF
Input Capacitance
CIN1
VIN=0V
-
-
-
Control Pin Capacitance
Output Capacitance
CIN2
10
pF
VIN=0V
COUT
VOUT=0V
10
pF
NOTE : Capacitance is periodically sampled and not 100% tested.
AC TEST CONDITION(VCC = 1.8V/2.65V/3.3V)
Parameter
Value
Input Pulse Levels
0V to VCC
3ns
CLK
Input Rise and Fall Times
other inputs
5ns
Input and Output Timing Levels
Output Load
Vcc/2
CL = 30pF
Device
Under
Test
VCC
Input & Output
VCC/2
VCC/2
Test Point
* CL = 30pF including scope
and Jig capacitance
0V
Input Pulse and Test Point
Output Load
70
OneNAND128
FLASH MEMORY
Synchronous Burst Read
KFG2816X1M
Parameter
Symbol
Unit
Min
Max
Clock
CLK
tCLK
tIAA
1
54
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Clock Cycle
18.5
-
Initial Access Time(at 54MHz)
Burst Access Time Valid Clock to Output Delay
AVD Setup Time to CLK
AVD Hold Time from CLK
Address Setup Time to CLK
Address Hold Time from CLK
Data Hold Time from Next Clock Cycle
Output Enable to Data
-
-
76
tBA
14.5
tAVDS
tAVDH
tACS
tACH
tBDH
tOE
7
7
7
7
4
-
-
-
-
-
-
20
20
1)
CE Disable to Output High Z
-
tCEZ
1)
OE Disable to Output High Z
CE Setup Time to CLK
CLK High or Low Time
-
17
-
ns
ns
ns
ns
ns
ns
ns
tOEZ
tCES
7
tCLKH/L
tCLK/3
-
CLK 2) to RDY valid
CLK to RDY Setup Time
RDY Setup Time to CLK
CE low to RDY valid
Note
tRDYO
-
-
14.5
14.5
-
tRDYA
tRDYS
tCER
4
-
15
1. If OE is disabled at the same time or before CE is disabled, the output will go to high-z by tOEZ(max. 17ns).
If CE is disabled at the same time or before OE is disabled, the output will go to high-z by tCEZ(max. 20ns).
If CE and OE are disabled at the same time, the output will go to high-z by tOEZ(max. 17ns).
These parameters are not 100% tested.
2. It is the following clock of address fetch clock.
71
OneNAND128
FLASH MEMORY
SWITCHING WAVEFORMS
5 cycles for initial access shown.
BRL=4
tCLK
tCES
tCLKL
tCLKH
CE
tCER
tCEZ
CLK
tAVDS
tRDYO
AVD
tAVDH
tBDH
tACS
tACH
A0-A15
tBA
D0
DQ0-DQ15
D6
D7
D0
D1
D2
D3
D7
tOEZ
tIAA
tOE
OE
tRDYS
tRDYA
Hi-Z
Hi-Z
RDY
Figure 28. 8 Word Linear Burst Mode with Wrap Around
5 cycles for initial access shown.
BRL=4
tCLK
tCES
CE
tCER
tCEZ
CLK
tAVDS
tRDYO
AVD
A0-A15
tAVDH
tBDH
tACS
tBA
tACH
Da+n+1
tOEZ
DQ0-DQ15
Da
Da+1 Da+2 Da+3 Da+4 Da+5
Da+n
tIAA
tOE
OE
tRDYS
Hi-Z
tRDYA
Hi-Z
RDY
Figure 29. Continuous Linear Burst Mode with Wrap Around
NOTE: In order to avoid a bus conflict the OE signal is enabled on the next rising edge after AVD is going high.
72
OneNAND128
FLASH MEMORY
Asynchronous Read
KFG2816X1M
Parameter
Symbol
Unit
Min
Max
76
76
76
-
Access Time from CE Low
tCE
tAA
-
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Asynchronous Access Time from AVD Low
Asynchronous Access Time from address valid
Read Cycle Time
tACC
tRC
-
76
12
7
7
-
AVD Low Time
tAVDP
tAAVDS
tAAVDH
tOE
-
Address Setup to rising edge of AVD
Address Hold from rising edge of AVD
Output Enable to Output Valid
CE Setup to AVD falling edge
-
-
20
-
tCA
0
-
CE Disable to Output & RDY High Z1)
tCEZ
tOEZ
20
OE Disable to Output & RDY High Z1)
-
17
ns
NOTE:
1. If OE is disabled at the same time or before CE is disabled, the output will go to high-z by tOEZ(max. 17ns).
If CE is disabled at the same time or before OE is disabled, the output will go to high-z by tCEZ(max. 20ns).
If CE and OE are disabled at the same time, the output will go to high-z by tOEZ(max. 17ns).
These parameters are not 100% tested.
SWITCHING WAVEFORMS
Case 1 : Valid Address and AVD Transition occur before CE is driven to Low
VIL
CLK
CE
tCEZ
tAVDP
AVD
tOE
OE
WE
tCE
tOEZ
DQ0-DQ15
A0-A15
Valid RD
tAAVDH
VA
Hi-Z
RDY
Hi-Z
NOTE: VA=Valid Read Address, RD=Read Data.
Figure 30. Asynchronous Read Mode(AVD toggling)
73
OneNAND128
FLASH MEMORY
Case 2 : AVD Transition occurs after CE is driven to Low and Valid Address Transition occurs before AVD is driven to Low
VIL
CLK
CE
tCEZ
tAA
tAVDP
AVD
OE
tOE
tWEA
WE
tOEZ
DQ0-DQ15
Valid RD
tAAVDH
A0-A15
VA
RDY
Hi-Z
Hi-Z
NOTE: VA=Valid Read Address, RD=Read Data.
Figure 31. Asynchronous Read Mode(AVD toggling)
Case 3 : AVD Transition occur after CE is driven to Low and Valid Address Transition occurs after AVD is driven to Low
VIL
CLK
CE
tCEZ
tAVDP
AVD
tAAVDS
tOE
OE
tWEA
WE
tOEZ
DQ0-DQ15
Valid RD
tAAVDH
tACC
A0-A15
VA
Hi-Z
RDY
Hi-Z
NOTE: VA=Valid Read Address, RD=Read Data.
Figure 32. Asynchronous Read Mode(AVD toggling)
74
OneNAND128
FLASH MEMORY
Case 4 : AVD is tied to CE
VIL
CLK
tRC
CE
OE
tCEZ
tOE
WE
DQ0-DQ15
A0-A15
tCE
tOEZ
Valid RD
tACC
VA
Hi-Z
Hi-Z
RDY
NOTE: VA=Valid Read Address, RD=Read Data.
Figure 33. Asynchronous Read Mode(AVD tied to CE)
75
OneNAND128
FLASH MEMORY
AC CHARACTERISTICS
Asynchronous write operation
KFG2816X1M
Parameter
Symbol
Unit
Min
70
12
7
Typ
Max
WE Cycle Time
tWC
tAVDP
tAAVDS
tAWES
tAAVDH
tAH
-
-
-
-
-
-
ns
ns
ns
AVD low pulse width
Address Setup to rising edge of AVD
Address Setup to falling edge of WE
Address Hold to rising edge of AVD
Address Hold to rising edge of WE
Data Setup to rising edge of WE
Data Hold from rising edge of WE
CE Setup to falling edge of WE
0
7
-
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
10
10
4
tDS
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
tDH
tCS
0
AVD toggled
AVD tied to CE
tCH1
0
CE Hold from rising edge of WE
CE Hold from rising edge of WE
WE Pulse Width
tCH2
10
40
30
15
15
tWPL
tWPH
tVLWH
tWEA
WE Pulse Width High
AVD Disable to WE Disable
WE Disable to AVD Enable
76
OneNAND128
FLASH MEMORY
Case 1 : AVD is toggled every write cycle
VIL
CLK
tCS
tCH1
CE
tCS
tCH1
tAVDP
AVD
tWEA
tVLWH
tWPL
tWPH
WE
tWC
OE
tAAVDS
tAAVDH
VA
A0-A15
VA
tDS
tDH
DQ0-DQ15
RDY
Valid WD
Valid WD
Hi-Z
Hi-Z
NOTE: VA=Valid Read Address, WD=Write Data.
Figure 34. Latched Asynchronous Write Mode(AVD toggling)
77
OneNAND128
FLASH MEMORY
Case 2 : AVD is synchronized with CE
VIL
CLK
tCS
tCH2
tCS
CE
tCH2
AVD
tWPL
tWPH
WE
tWC
OE
tAH
tAWES
A0-A15
VA
VA
tDS
tDH
DQ0-DQ15
Valid WD
Valid WD
RDY
Hi-Z
Hi-Z
NOTE: VA=Valid Read Address, WD=Write Data.
Figure 35. Asynchronous Write Mode(AVD toggling)
78
OneNAND128
FLASH MEMORY
Case 3 : AVD is tied to CE
VIL
CLK
tCS
tCH2
tCS
CE or AVD
tCH2
tWPL
tWPH
WE
OE
tWC
tAH
tAWES
A0-A15
VA
VA
tDS
tDH
DQ0-DQ15
RDY
Valid WD
Valid WD
Hi-Z
Hi-Z
NOTE: VA=Valid Read Address, WD=Write Data.
Figure 36. Asynchronous Write Mode(AVD tied to CE)
79
OneNAND128
FLASH MEMORY
Reset
KFG2816X1M
Unit
Parameter
Symbol
Min
Max
10
20
500
10
-
RP & Reset Command Latch(During Load Routines) to INT High (Note)
RP & Reset Command Latch(During Program Routines) to INT High (Note)
RP & Reset Command Latch(During Erase Routines) to INT High (Note)
RP & Reset Command Latch(NOT During Internal Routines) to Read Mode (Note)
INT High to Read Mode (Note)
tRST
tRST
tRST
tRST
tReady
tRP
µs
µs
µs
µs
ns
ns
-
-
-
-
200
200
RP Pulse Width
-
NOTE: These parameters are tested based on INT bit of interrupt register. Because the time on INT pin is related to the pull-up and
pull-down resistor value. Please refer to page 66 and 67.
SWITCHING WAVEFORMS
Warm Reset
CE, OE
RP
tRP
tRST
tReady
INT bit
Hot Reset
AVD
Ai
BP or F220h
00F0h
or 00F3h
DQi
CE
OE
WE
tReady
tRST
INT bit
Figure 37. Reset Timing
80
OneNAND128
FLASH MEMORY
Performance
Parameter
Symbol
tRD1
Min
Typ
35
Max
45
Unit
µs
Sector Load time(Note 1)
-
-
-
-
-
-
-
-
Page Load time(Note 1)
tRD2
50
75
µs
Sector Program time(Note 1)
Page Program time(Note 1)
OTP Access Time(Note 1)
Lock/Unlock/Lock-tight Time(Note 1)
Erase Suspend Time(Note 1)
tPGM1
tPGM2
tOTP
µs
320
350
600
600
400
2
720
750
1000
1000
500
3
µs
ns
ns
µs
tLOCK
tESP
1 Block
tERS1
tERS2
ms
ms
Erase Resume Time(Note 1)
2~64 Blocks
4
5
Number of Partial Program Cycles in the sector
(Including main and spare area)
NOP
-
-
2
cycles
1 Block
2~64 Blocks
tBERS1
tBERS2
tRD3
-
-
-
2
4
3
5
ms
ms
µs
Block Erase time (Note 1)
Multi BlocK Erase Verify Read time(Note 1)
115
135
NOTES:
1. These parameters are tested based on INT bit of interrupt register. Because the time on INT pin is related to the pull-up and pull-
down resistor value. Please refer to page 66 and 67.
81
OneNAND128
FLASH MEMORY
SWITCHING WAVEFORMS
Load Operations
Read Command Sequence
Read Data
tVLWH
tAVDP
AVD
tWEA
tAAVDH
tAAVDS
A0:A15
AA
CA
SA
BA
DQ0-DQ15
Complete
Da
RMA
RCD
tDS
tDH
CE
OE
WE
tCH1
tWPL
tWPH
tRD
tCS
tWC
VIL
CLK
INT
bit
Figure 38. Load Operation Timing
NOTES:
1. AA = Address of address register
CA = Address of command register
LCD = Load Command
LMA = Address of memory to be loaded
BA = Address of BufferRAM to load the data
BD = Program Data
SA = Address of status register
2. “In progress” and “complete” refer to status register
3. Status reads in this figure is asynchronous read, but status read in synchronous mode is also supported.
82
OneNAND128
FLASH MEMORY
SWITCHING WAVEFORMS
Program Operations
Program Command Sequence (last two cycles)
Read Status Data
tVLWH
tAVDP
tWEA
AVD
tAAVDS
tAAVDH
A0:A15
AA
BA
CA
SA
SA
In
DQ0-DQ15
Complete
Progress
PMA
BD
PCD
tDH
tDS
CE
OE
WE
tCH
tWPL
tWPH
tCS
tPGM
tWC
VIL
CLK
INT
Figure 39. Program Operation Timing
NOTES:
1. AA = Address of address register
CA = Address of command register
PCD = Program Command
PMA = Address of memory to be programmed
BA = Address of BufferRAM to load the data
BD = Program Data
SA = Address of status register
2. “In progress” and “complete” refer to status register
3. Status reads in this figure is asynchronous read, but status read in synchronous mode is also supported.
83
OneNAND128
FLASH MEMORY
SWITCHING WAVEFORMS
Erase Operation
Erase Command Sequence (last two cycles)
Read Status Data
tVLWH
tWEA
tAVDP
AVD
tAAVDH
tAAVDS
A0:A15
DQ0-DQ15
CE
AA
CA
SA
SA
In
Complete
Progress
EMA
ECD
tDS
tDH
tCH
OE
tWPL
WE
tWPH
tBERS
tCS
tWC
VIL
CLK
INT
Figure 40. Block Erase Operations
NOTES:
1. AA = Address of address register
CA = Address of command register
ECD = Erase Command
EMA = Address of memory to be erased
SA = Address of status register
2. “In progress” and “complete” refer to status register
3. Status reads in this figure is asynchronous read, but status read in synchronous mode is also supported.
84
OneNAND128
FLASH MEMORY
OneNAND128 PACKAGE DIMENSIONS
67-FBGA-7.00x9.00
Units:millimeters
7.00±0.10
A
0.80x7=5.60
2.800
#A1 INDEX
0.10 MAX
7.00±0.10
0.80
(Datum A)
B
6
5
4
3
2
1
#A1
A
(Datum B)
B
C
D
E
F
G
H
0.32±0.05
0.90±0.10
BOTTOM VIEW
TOP VIEW
67-
∅ 0.45±0.05
∅
0.20
M A B
85
OneNAND128
FLASH MEMORY
PACKAGE DIMENSIONS
48-PIN LEAD/LEAD FREE PLASTIC THIN SMALL OUT-LINE PACKAGE TYPE(I)
48 - TSOP1 - 1220F
Unit :mm/Inch
20.00±0.20
0.787±0.008
#1
#48
#24
#25
1.00±0.05
0.039±0.002
0.05
0.002
MIN
1.20
0.047
MAX
18.40±0.10
0.724±0.004
0~8°
0.45~0.75
0.018~0.030
0.50
0.020
(
)
86
OneNAND128
FLASH MEMORY
ORDERING INFORMATION
K F G 28 1 6 X 1 M - X X B
Samsung
OneNAND Memory
Product Line desinator
B : Include Bad Block
D : Daisy Sample
Device Type
G : Single Chip
Operating Temperature Range
E = Extended Temp. (-30 °C to 85 °C)
I = Industrial Temp. (-40 °C to 85 °C)
Package
Density
D : FBGA(Lead Free)
P : TSOP(Lead Free)
28 : 128Mb
Organization
x16 Organization
Version
M : 1st Generation
Operating Voltage Range
Q : 1.8V(1.7 V to 1.95V)
D : 2.65V(2.4V to 2.9V)
U : 3.3V(2.7 V to 3.6V)
Page Architecture
1 : 1KB Page
87
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