KM23C16000DT-10 [SAMSUNG]
MASK ROM, 2MX8, 100ns, CMOS, PDSO44, 0.400 INCH, TSOP2-44;型号: | KM23C16000DT-10 |
厂家: | SAMSUNG |
描述: | MASK ROM, 2MX8, 100ns, CMOS, PDSO44, 0.400 INCH, TSOP2-44 有原始数据的样本ROM 光电二极管 |
文件: | 总3页 (文件大小:51K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
Preliminary
CMOS MASK ROM
KM23C16000D(E)T
16M-Bit (2Mx8 /1Mx16) CMOS MASK ROM
FEATURES
GENERAL DESCRIPTION
· Switchable organization
2,097,152 x 8(byte mode)
1,048,576 x 16(word mode)
· Fast access time : 100ns(Max.)
· Supply voltage : single +5V
· Current consumption
Operating : 70mA(Max.)
Standby : 50mA(Max.)
· Fully static operation
The KM23C16000D(E)T is a fully static mask programmable
ROM fabricated using silicon gate CMOS process technology,
and is organized either as 2,097,152x8 bit(byte mode) or as
1,048,576x16 bit(word mode) depending on BHE voltage
level.(See mode selection table)
This device operates with a 5V single power supply, and all
inputs and outputs are TTL compatible.
Because of its asynchronous operation, it requires no external
clock assuring extremely easy operation.
· All inputs and outputs TTL compatible
· Three state outputs
· Package
It is suitable for use in program memory of microprocessor, and
data memory, character generator.
-. KM23C16000D(E)T : 44-TSOP2-400
The KM23C16000D(E)T is packaged in a 44-TSOP2.
PRODUCT INFORMATION
FUNCTIONAL BLOCK DIAGRAM
Operating
Temp Range
Vcc Range
(Typical)
Speed
(ns)
Product
A19
X
MEMORY CELL
MATRIX
(1,048,576x16/
2,097,152x8)
KM23C16000DT
KM23C16000DET
0°C~70°C
BUFFERS
AND
DECODER
5.0V
100
.
.
.
.
.
.
.
.
-20°C~85°C
PIN CONFIGURATION
Y
SENSE AMP.
BUFFERS
AND
DECODER
DATA OUT
BUFFERS
A0
N.C
1
N.C
44
43
42
41
40
39
A-1
A18
2
3
A19
A8
A17
A7
.
.
.
4
A9
A6
A5
A4
A3
A10
A11
5
CE
OE
Q0/Q8
Q7/Q15
6
CONTROL
LOGIC
7
38 A12
37 A13
BHE
8
A14
36
A2
A1
9
A15
35
10
11
A0
A16
34
33
TSOP2
CE 12
BHE
Pin Name
A0 - A19
Pin Function
Address Inputs
Data Outputs
VSS
13
32 VSS
OE 14
Q15/A-1
31
30
Q7
Q0
15
Q0 - Q14
Q8
Q1
Q9
16
29 Q14
28 Q6
Output 15(Word mode)/
LSB Address(Byte mode)
Q15 /A-1
17
18
Q13
Q5
27
26
25
24
23
Q2 19
BHE
CE
Word/Byte selection
Chip Enable
Q10 20
Q12
Q4
Q3
21
22
Q11
OE
Output Enable
Power ( +5V)
Ground
VCC
VCC
VSS
N.C
KM23C16000D(E)T
No Connection
Preliminary
CMOS MASK ROM
KM23C16000D(E)T
ABSOLUTE MAXIMUM RATINGS
Item
Symbol
VIN
Rating
-0.3 to +7.0
-10 to +85
-55 to +150
0 to +70
Unit
Remark
Voltage on Any Pin Relative to VSS
Temperature Under Bias
Storage Temperature
V
-
TBIAS
TSTG
°C
°C
°C
°C
-
-
KM23C16000DT
KM23C16000DET
Operating Temperature
TA
-20 to +85
NOTE : Permanent device damage may occur if "ABSOLUTE MAXIMUM RATINGS" are exceeded. Functional operation should be restricted to teh
conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extenedd periods may
affect device reliability.
RECOMMENDED OPERATING CONDITIONS (Voltage reference to VSS)
Item
Supply Voltage
Symbol
Min
4.5
0
Typ
5.0
0
Max
5.5
0
Unit
V
VCC
Supply Voltage
VSS
V
DC CHARACTERISTICS
Parameter
Symbol
Test Conditions
Min
Max
Unit
Operating Current
ICC
ISB1
ISB2
ILI
CE=OE=VIL, all outputs open
CE=VIH, all outputs open
CE=VCC, all outputs open
VIN=0 to VCC
-
70
mA
mA
mA
mA
mA
V
Standby Current(TTL)
-
-
1
50
Standby Current(CMOS)
Input Leakage Current
Output Leakage Current
Input High Voltage, All Inputs
Input Low Voltage, All Inputs
Output High Voltage Level
Output Low Voltage Level
-
10
ILO
VOUT=0 to VCC
-
10
VIH
VIL
2.2
-0.3
2.4
-
VCC+0.3
0.8
-
V
VOH
VOL
IOH=-400mA
V
IOL=2.1mA
0.4
V
NOTE : Minimum DC Voltage(VIL) is -0.3V an input pins. During transitions, this level may undershoot to -2.0V for periods <20ns.
Maximum DC voltage on input pins(VIH) is VCC+0.3V which, during transitions, may overshoot to VCC+2.0V for periods <20ns.
MODE SELECTION
CE
OE
BHE
X
Q15/A-1
Mode
Data
High-Z
Power
H
X
X
X
Standby
Operating
Operating
Standby
Active
L
H
X
High-Z
H
Output
Q0~Q15 : Dout
Active
L
L
Q0~Q7 : Dout
Q8~Q14 : Hi-Z
L
Input
Operating
Active
CAPACITANCE(TA=25°C, f=1.0MHz)
Item
Output Capacitance
Input Capacitance
Symbol
Test Conditions
VOUT=0V
MIN
Max
12
Unit
pF
COUT
CIN
-
-
VIN=0V
12
pF
NOTE : Capacitance is periodically sampled and not 100% tested.
Preliminary
CMOS MASK ROM
KM23C16000D(E)T
AC CHARACTERISTICS (VCC=5V±10%, unless otherwise noted.)
TEST CONDITIONS
Item
Value
Input Pulse Levels
0.6V to 2.4V
10ns
Input Rise and Fall Times
Input and Output timing Levels
0.8V and 2.0V
Output Loads
1 TTL Gate and CL=100pF
READ CYCLE
KM23C16000D(E)T-10 KM23C16000D(E)T-12 KM23C16000D(E)T-15
Item
Symbol
Unit
Min
Max
Min
Max
Min
Max
Read Cycle Time
tRC
tACE
tAA
100
120
150
ns
ns
ns
ns
Chip Enable Access Time
Address Access Time
Output Enable Access Time
100
100
50
120
120
60
150
150
70
tOE
Output or Chip Disable to
Output High-Z
tDF
tOH
20
20
30
ns
ns
Output Hold from Address Change
0
0
0
TIMING DIAGRAM
READ
ADD
ADD2
ADD1
A0~A19
A-1(*1)
tRC
tDF(*3)
tACE
CE
OE
tOE
tAA
tOH
DOUT
D0~D7
VALID DATA
VALID DATA
D8~D15(*2)
NOTES :
*1. Byte Mode only. A-1 is Least Significant Bit Address.(BHE = VIL)
*2. Word Mode only.(BHE = VIH)
*3. tDF is defined as the time at which the outputs achieve the open circuit condition and is not referenced to VOH or VOL level.
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