KM23C8000DG-10 [SAMSUNG]
MASK ROM, 1MX8, 100ns, CMOS, PDSO32, 0.525 INCH, SOP-32;型号: | KM23C8000DG-10 |
厂家: | SAMSUNG |
描述: | MASK ROM, 1MX8, 100ns, CMOS, PDSO32, 0.525 INCH, SOP-32 有原始数据的样本ROM 光电二极管 内存集成电路 |
文件: | 总4页 (文件大小:88K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
KM23C8000D(G)
CMOS MASK ROM
8M-Bit (1Mx8) CMOS MASK ROM
FEATURES
GENERAL DESCRIPTION
· 1,048,576 x 8 bit organization
· Fast access time : 100ns(Max.)
· Supply voltage : single +5V
· Current consumption
Operating : 50mA(Max.)
Standby : 50mA(Max.)
· Fully static operation
· All inputs and outputs TTL compatible
· Three state outputs
The KM23C8000D(G) is a fully static mask programmable
ROM organized 1,048,576 x 8 bit. It is fabricated using silicon
gate CMOS process technology.
This device operates with a 5V single power supply, and all
inputs and outputs are TTL compatible.
Because of its asynchronous operation, it requires no external
clock assuring extremely easy operation.
It is suitable for use in program memory of microprocessor, and
data memory, character generator.
· Package
The KM23C8000D is packaged in
KM23C8000DG in a 32-SOP.
a 32-DIP and the
-. KM23C8000D : 32-DIP-600
-. KM23C8000DG : 32-SOP-525
FUNCTIONAL BLOCK DIAGRAM
PIN CONFIGURATION
A19
A16
A15
A12
A7
1
2
VCC
A18
A17
A14
A13
A8
32
31
30
29
28
27
26
25
24
23
21
21
20
19
18
17
X
A19
MEMORY CELL
MATRIX
BUFFERS
AND
.
.
.
.
.
.
.
.
3
(1,048,576x8)
DECODER
4
5
A6
6
Y
A5
A9
DIP
&
SOP
7
SENSE AMP.
BUFFERS
BUFFERS
AND
A4
A11
8
A3
DECODER
OE
A10
CE
Q7
Q6
Q5
Q4
Q3
9
A0
A2
10
11
12
13
14
15
16
A1
. . .
A0
Q0
Q1
Q2
VSS
CE
OE
Q0
Q7
CONTROL
LOGIC
Pin Name
A0 - A19
Q0 - Q7
CE
Pin Function
Address Inputs
KM23C8000D(G)
Data Outputs
Chip Enable
Output Enable
Power (+5V)
Ground
OE
VCC
VSS
KM23C8000D(G)
CMOS MASK ROM
ABSOLUTE MAXIMUM RATINGS
Item
Symbol
VIN
Rating
Unit
Voltage on Any Pin Relative to VSS
Temperature Under Bias
Storage Temperature
-0.3 to +7.0
-10 to +85
-55 to +150
V
TBIAS
TSTG
°C
°C
NOTE : Permanent device damage may occur if "ABSOLUTE MAXIMUM RATINGS" are exceeded. Functional operation should be restricted to the
conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may
affect device reliability.
RECOMMENDED OPERATING CONDITIONS(Voltage reference to VSS, TA=0 to 70°C)
Item
Supply Voltage
Symbol
Min
4.5
0
Typ
5.0
0
Max
5.5
0
Unit
V
VCC
Supply Voltage
VSS
V
DC CHARACTERISTICS
Min
Max
Parameter
Operating Current
Symbol
Test Conditions
Unit
ICC
ISB1
ISB2
ILI
CE=OE=VIL, all outputs open
CE=VIH, all outputs open
CE=VCC, all outputs open
VIN=0 to VCC
-
50
mA
mA
mA
mA
mA
V
Standby Current(TTL)
-
-
1
50
Standby Current(CMOS)
Input Leakage Current
Output Leakage Current
Input High Voltage, All Inputs
Input Low Voltage, All Inputs
Output High Voltage Level
Output Low Voltage Level
-
10
ILO
VOUT=0 to VCC
-
10
VIH
VIL
2.2
-0.3
2.4
-
VCC+0.3
0.8
V
IOH=-400mA
VOH
VOL
-
V
IOL=2.1mA
0.4
V
NOTE : Minimum DC Voltage(VIL) is -0.3V an input pins. During transitions, this level may undershoot to -2.0V for periods <20ns.
Maximum DC voltage on input pins(VIH) is VCC+0.3V which, during transitions, may overshoot to VCC+2.0V for periods <20ns.
MODE SELECTION
CE
OE
X
Mode
Data
High-Z
High-Z
Dout
Power
Standby
Active
H
Standby
Operating
Operating
H
L
L
Active
CAPACITANCE(TA=25°C, f=1.0MHz)
Item
Output Capacitance
Input Capacitance
Symbol
Test Conditions
VOUT=0V
Min
Max
12
Unit
COUT
CIN
-
-
pF
pF
VIN=0V
12
NOTE : Capacitance is periodically sampled and not 100% tested.
KM23C8000D(G)
CMOS MASK ROM
AC CHARACTERISTICS(TA=0°C to +70°C, VCC=5.0V±10%, unless otherwise noted.)
TEST CONDITIONS
Item
Value
0.6V to 2.4V
Input Pulse Levels
Input Rise and Fall Times
Input and Output timing Levels
Output Loads
10ns
0.8V and 2.0V
1 TTL Gate and CL=100pF
READ CYCLE
Item
KM23C8000D(G)-10
KM23C8000D(G)-12
KM23C8000D(G)-15
Symbol
Unit
Min
Max
Min
Max
Min
Max
Read Cycle Time
tRC
tACE
tAA
100
120
150
ns
ns
ns
ns
Chip Enable Access Time
Address Access Time
Output Enable Access Time
100
100
50
120
120
60
150
150
70
tOE
Output or Chip Disable to
Output High-Z
tDF
tOH
20
20
30
ns
ns
Output Hold from Address Change
0
0
0
TIMING DIAGRAM
READ
ADD2
ADD1
ADD
tRC
tDF(Note)
tACE
CE
tAA
tOE
OE
tOH
DOUT
VALID DATA
VALID DATA
NOTE : tDF is defined as the time at which the outputs achieve the open circuit condition and is not referenced to VOH or VOL level.
KM23C8000D(G)
CMOS MASK ROM
PACKAGE DIMENSIONS
(Unit : mm/inch)
+0.10
0.25
32-DIP-600
-0.05
+0.004
0.010
-0.002
#32
#17
13.60±0.20
0.535±0.008
#1
#16
0~15°
3.81±0.20
0.150±0.008
42.31
1.666
MAX
5.08
0.200
MAX
4.191±0.20
1.650±0.008
3.30±0.30
0.46±0.10
0.130±0.012
0.018±0.004
1.52±0.10
0.060±0.004
0.38
0.015
2.54
0.100
1.91
0.075
MIN
(
)
32-SOP-525
0~8°
#32
#17
14.12±0.30 11.43±0.20
0.556±0.012 0.450±0.008
0.80±0.20
0.031±0.008
#1
#16
+0.10
-0.05
0.20
+0.004
0.008
-0.002
2.74±0.20
0.108±0.008
20.87
0.822
MAX
3.00
0.118
20.47±0.20
0.806±0.008
MAX
0.10 MAX
0.004 MAX
+0.100
0.41
0.05
0.002
-0.050
1.27
0.050
MIN
0.71
)
+0.004
-0.002
(
0.016
0.028
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