KM23S32005DTY-15 [SAMSUNG]
MASK ROM, 2MX16, 150ns, CMOS, PDSO48, 12 X 18 MM, TSOP1-48;型号: | KM23S32005DTY-15 |
厂家: | SAMSUNG |
描述: | MASK ROM, 2MX16, 150ns, CMOS, PDSO48, 12 X 18 MM, TSOP1-48 有原始数据的样本ROM 光电二极管 |
文件: | 总6页 (文件大小:97K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
KM23V32005D(E)TY/KM23S32005D(E)TY
CMOS MASK ROM
32M-Bit (4Mx8 /2Mx16) CMOS MASK ROM
FEATURES
GENERAL DESCRIPTION
The KM23V32005D(E)TY and KM23S32005D(E)TY are fully
static mask programmable ROM fabricated using silicon gate
CMOS process technology, and is organized either as
4,194,304 x8 bit(byte mode) or as 2,097,152x16 bit(word mode)
depending on BHE voltage level.(See mode selection table)
This device includes page read mode function, page read mode
allows 8 words (or 16 bytes) of data to read fast in the same
page, CE and A3 ~ A20 should not be changed.
· Switchable organization
4,194,304x8(byte mode)
2,097,152x16(word mode)
· Fast access time
Random Access Time/Page Access Time
3.3V/3.0V Operation : 100/30ns(Max.)
2.5V Operation : 150/50ns(Max.)
· 8 words/ 16 bytes page access
· Supply voltage
KM23V32005D(E)TY : single +3.0V/ single +3.3V
KM23S32005D(E)TY : single +2.5V
· Current consumption
This device operates with low power supply, and all inputs and
outputs are TTL compatible.
Because of its asynchronous operation, it requires no external
clock assuring extremely easy operation.
Operating : 60mA(Max.)
Standby : 30mA(Max.)
· Fully static operation
· All inputs and outputs TTL compatible
· Three state outputs
· Package
It is suitable for use in program memory of microprocessor, and
data memory, character generator.
The KM23V32005D(E)TY and KM23S32005D(E)TY are pack-
aged in a 48-TSOP1.
-. KM23V(S)32005D(E)TY : 48-TSOP1-1218
FUNCTIONAL BLOCK DIAGRAM
Pin Name
A0 - A2
Pin Function
Page Address Inputs
A20
X
MEMORY CELL
MATRIX
BUFFERS
AND
.
.
.
.
.
.
.
.
(2,097,152x16/
4,194,304x8)
A3 - A20
Q0 - Q14
Address Inputs
Data Outputs
DECODER
Output 15(Word mode)/
LSB Address(Byte mode)
Q15 /A-1
Y
SENSE AMP.
BUFFERS
AND
BHE
CE
Word/Byte selection
Chip Enable
Output Enable
Power
DATA OUT
BUFFERS
DECODER
A3
A0~A2
A-1
OE
.
.
.
VCC
VSS
Ground
CE
Q0/Q8
Q7/Q15
CONTROL
LOGIC
OE
BHE
KM23V32005D(E)TY/KM23S32005D(E)TY
CMOS MASK ROM
PRODUCTMINFORMATION
Operating
Temp Range
VCC Range
(Typical)
Speed(ns)
tAA/tPA
Product
KM23V32005BTY
3.3V/3.0V
2.5V
100/30ns
150/50ns
100/30ns
150/50ns
0°C ~ 70°C
KM23S32005BTY
KM23V32005BETY
KM23S32005BETY
3.3V/3.0V
2.5V
-20°C ~ 85°C
PIN CONFIGURATION
BHE
A16
A15
A14
A13
A12
A11
A10
A9
1
2
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
VSS
VSS
Q15/A-1
Q7
Q14
Q6
Q13
Q5
Q12
Q4
VCC
VCC
VSS
Q11
Q3
3
4
5
6
7
8
9
A8
A19
VSS
10
11
12
A20 13
A18 14
A17 15
A7 16
A6 17
A5
A4
A3
A2 21
A1 22
A0 23
CE 24
TSOP I
Q10
Q2
18
19
20
Q9
Q1
Q8
Q0
OE
VSS
VSS
KM23V32005D(E)TY
KM23S32005D(E)TY
ABSOLUTE MAXIMUM RATINGS
Item
Symbol
Rating
Unit
Remark
Voltage on Any Pin Relative to
VIN
-0.3 to+4.5
-10 to+85
-55 to+150
V
-
-
-
Temperature Under Bias
Storage Temperature
TBIAS
TSTG
°C
°C
KM23V32005DTY
KM23S32005DTY
0 to+70
°C
°C
Operating Temperature
TA
KM23V32005DETY
KM23S32005DETY
-20 to+85
NOTE : Permanent device damage may occur if "ABSOLUTE MAXIMUM RATINGS" are exceeded. Functional operation should be restricted to the con-
ditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may
affect device reliability.
KM23V32005D(E)TY/KM23S32005D(E)TY
CMOS MASK ROM
RECOMMENDED OPERATING CONDITIONS(Voltage reference to VSS)
Item
Min
2.7/3.0
2.3
Symbol
Typ
3.0/3.3
2.5
Max
3.3/3.6
2.7
Unit
V
Supply Voltage
VCC
V
Supply Voltage
VSS
0
0
0
V
DC CHARACTERISTICS
Min
Max
60
Parameter
Symbol
Test Conditions
Unit
mA
mA
mA
mA
mA
mA
mA
mA
mA
V
VCC=3.3V±0.3V
-
CE=OE=VIL,
all outputs open
Operating Current
ICC
VCC=3.0V±0.3V
VCC=2.5V±0.2V
-
50
-
40
KM23V32005D(E)TY
KM23S32005D(E)TY
KM23V32005D(E)TY
KM23S32005D(E)TY
ILI
-
500
100
30
Standby Current(TTL)
ISB1
ISB2
CE=VIH, all outputs open
CE=VCC, all outputs open
-
-
Standby Current(CMOS)
-
5
Input Leakage Current
VIN=0 to VCC
-
10
Output Leakage Current
Input High Voltage, All Inputs
ILO
VOUT=0 to VCC
-
10
VIH
2.0
-0.3
-0.3
2.4
2.0
-
VCC+0.3
KM23V32005D(E)TY
KM23S32005D(E)TY
0.6
0.4
-
V
Input Low Voltage, All Inputs
VIL
V
KM23V32005D(E)TY IOH=-400mA
KM23S32005D(E)TY IOH=-400mA
V
Output High Voltage Level
Output Low Voltage Level
VOH
-
V
VOL
IOL=2.1mA
0.4
V
NOTE : Minimum DC Voltage(VIL) is -0.3V an input pins. During transitions, this level may undershoot to -2.0V for periods <20ns.
Maximum DC voltage on input pins(VIH) is VCC+0.3V which, during transitions, may overshoot to VCC+2.0V for periods <20ns.
MODE SELECTION
CE
H
OE
X
BHE
X
Q15/A-1
Mode
Data
High-Z
Power
X
X
Standby
Operating
Operating
Standby
Active
L
H
X
High-Z
H
Output
Q0~Q15 : Dout
Active
L
L
Q0~Q7 : Dout
Q8~Q14 : Hi-Z
L
Input
Operating
Active
CAPACITANCE(TA=25°C, f=1.0MHz)
Item
Output Capacitance
Input Capacitance
Symbol
Test Conditions
VOUT=0V
Min
Max
12
Unit
pF
COUT
CIN
-
-
VIN=0V
12
pF
NOTE : Capacitance is periodically sampled and not 100% tested.
KM23V32005D(E)TY/KM23S32005D(E)TY
CMOS MASK ROM
AC CHARACTERISTICS(VCC=3.3V/3.0V±0.3V, VCC=2.5V±0.2V, unless otherwise noted.)
TEST CONDITIONS
Item
Value
0.45V to 2.4V(at VCC=3.3V/3.0V)
0.4V to 2.2V (at VCC=2.5V)
10ns
Input Pulse Levels
Input Rise and Fall Times
Input and Output timing Levels
Output Loads
1.5V (at VCC=3.3V/3.0V)
1.1V (at VCC=2.5V)
1 TTL Gate and CL=100pF
READ CYCLE
VCC=3.3V/3.0V±0.3V
VCC=2.5V±0.2V
Item
Symbol
Unit
Min
Max
Min
150
Max
Read Cycle Time
tRC
tACE
tAA
100
ns
ns
ns
ns
ns
Chip Enable Access Time
Address Access Time
Page Access Time
100
100
30
150
150
50
tPA
Output Enable Access Time
tOE
30
50
Output or Chip Disable to
Output High-Z
tDF
tOH
20
30
ns
ns
Output Hold from Address Change
0
0
NOTE: Page Address is determined as below
Word mode(BHE=VIH) : A0, A1, A2
Byte mode(BHE=VIL) : A-1, A0, A1, A2
KM23V32005D(E)TY/KM23S32005D(E)TY
CMOS MASK ROM
TIMING DIAGRAM
READ
ADD
ADD1
ADD2
A0~A20
A-1(*1)
tRC
tDF(*3)
tACE
CE
OE
tOE
tAA
tOH
DOUT
D0~D7
VALID DATA
VALID DATA
D8~D15(*2)
PAGE READ
CE
OE
tDF(*3)
ADD
A3~A20
ADD
1 st
2 nd
3 rd
A0,A1,A2
A -1(*1)
tAA
tPA
DOUT
VALID DATA
VALID DATA
VALID DATA
VALID DATA
D0~D7
D8~D15(*2)
NOTES :
*1. Byte Mode only. A-1 is Least Significant Bit Address.(BHE = VIL)
*2. Word Mode only.(BHE = VIH)
*3. tDF is defined as the time at which the outputs achieve the open circuit condition and is not referenced to VOH or VOL level.
KM23V32005D(E)TY/KM23S32005D(E)TY
CMOS MASK ROM
PACKAGE DIMENSIONS
(Unit : mm/inch)
48-TSOP1-1218
18.00±0.20
0.709±0.008
#1
#48
12.40
MAX
0.488
1.00±0.10
0.039±0.004
1.20
0.05
0.002
#25
#24
MIN
MAX
16.40±0.10
0.646±0.004
0.047
0~8°
0.50
0.020
(
)
0.45~0.75
0.018~0.030
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