KM23V32005BG [SAMSUNG]
32M-Bit (4Mx8/2Mx16) COMS MASK ROM; 32M位（ 4Mx8 / 2Mx16 ） COMS MASK ROM
| 型号： | KM23V32005BG |
| 厂家： | 
SAMSUNG |
| 描述： | 32M-Bit (4Mx8/2Mx16) COMS MASK ROM |
| 文件： | 总5页 (文件大小：90K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
KM23V32005BG
CMOS MASK ROM
32M-Bit (4Mx8 /2Mx16) CMOS MASK ROM
FEATURES
GENERAL DESCRIPTION
· Switchable organization
4,194,304x8(byte mode)
2,097,152x16(word mode)
· Fast access time
The KM23V32005BG is a fully static mask programmable ROM
fabricated using silicon gate CMOS process technology, and is
organized either as 4,194,304x8 bit(byte mode) or as
2,097,152x16 bit(word mode) depending on BHE voltage
level.(See mode selection table)
Random Access Time : 100ns(Max.)
Page Access Time
: 30ns(Max.)
This device includes page read mode function, page read mode
allows 8 words(or 16 bytes) of data to read fast in the same
page, CE and A3 ~ A20 should not be changed.
· 8 words / 16 bytes page access
· Supply voltage : single +3.3V
· Current consumption
This device operates with a 3.3V power supply, and all inputs
and outputs are TTL compatible.
Operating : 60mA(Max.)
Standby : 30mA(Max.)
· Fully static operation
· All inputs and outputs TTL compatible
· Three state outputs
Because of its asynchronous operation, it requires no external
clock assuring extremely easy operation.
It is suitable for use in program memory of microprocessor, and
data memory, character generator.
The KM23V32005BG is packaged in a 44-SOP.
· Package
KM23V32005BG : 44-SOP-600
FUNCTIONAL BLOCK DIAGRAM
PIN CONFIGURATION
A20
X
MEMORY CELL
MATRIX
(2,097,152x16/
4,194,304x8)
N.C
A18
A20
A19
A8
1
2
44
43
42
41
40
39
BUFFERS
AND
DECODER
.
.
.
.
.
.
.
.
A17
A7
3
4
A9
A6
A5
A4
A3
A2
A1
A0
A10
A11
5
6
Y
SENSE AMP.
38 A12
37 A13
7
BUFFERS
AND
DECODER
8
DATA OUT
BUFFERS
A14
36
9
A3
A15
35
10
11
A0~A2
A-1
A16
34
33
32
31
30
BHE
VSS
CE 12
.
.
.
SOP
VSS
13
OE 14
Q15/A-1
Q7
CE
Q0
Q8
15
16
17
18
Q0/Q8
Q7/Q15
CONTROL
LOGIC
29 Q14
OE
Q1
Q9
Q6
Q13
Q5
28
27
26
25
24
23
BHE
Q2 19
Q10 20
Q12
Q4
Pin Name
A0 - A2
Pin Function
Page Address Inputs
Q3
21
22
Q11
VCC
A3 - A20
Q0 - Q14
Address Inputs
Data Outputs
KM23V32005BG
Output 15(Word mode)/
LSB Address(Byte mode)
Q15 /A-1
BHE
CE
Word/Byte selection
Chip Enable
OE
Output Enable
Power (3.3V)
Ground
VCC
VSS
N.C
No Connection
KM23V32005BG
CMOS MASK ROM
ABSOLUTE MAXIMUM RATINGS
Item
Voltage on Any Pin Relative to VSS
Temperature Under Bias
Storage Temperature
Symbol
VIN
Rating
Unit
-0.3 to +4.5
-10 to +85
-55 to +150
V
TBIAS
TStg
°C
°C
NOTE : Permanent device damage may occur if "ABSOLUTE MAXIMUM RATINGS" are exceeded. Functional operation should berestricted to the con-
ditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may
affect device reliability.
RECOMMENDED OPERATING CONDITIONS(Voltage reference to VSS, TA=0 to 70°C)
Item
Supply Voltage
Symbol
Min
3.0
0
Typ
3.3
0
Max
3.6
0
Unit
V
VCC
Supply Voltage
VSS
V
DC CHARACTERISTICS
Parameter
Symbol
ICC
Test Conditions
CE=OE=VIL, all outputs open
CE=VIH, all outputs open
CE=VCC, all outputs open
VIN=0 to VCC
Min
Max
60
Unit
Operating Current
-
mA
mA
mA
mA
mA
V
Standby Current(TTL)
ISB1
ISB2
ILI
500
30
Standby Current(CMOS)
Input Leakage Current
Output Leakage Current
Input High Voltage, All Inputs
Input Low Voltage, All Inputs
Output High Voltage Level
Output Low Voltage Level
-
-
10
ILO
VOUT=0 to VCC
10
VIH
2.0
-0.3
2.4
-
VCC+0.3
0.6
VIL
V
IOH=-400mA
VOH
VOL
-
V
IOL=2.1mA
0.4
V
NOTE : Minimum DC Voltage(VIL) is -0.3V an input pins. During transitions, this level may undershoot to -2.0V for periods <20ns.
Maximum DC voltage on input pins(VIH) is VCC+0.3V which, during transitions, may overshoot to VCC+2.0V for periods <20ns.
MODE SELECTION
CE
H
OE
X
BHE
X
Q15/A-1
Mode
Data
High-Z
Power
X
X
Standby
Operating
Operating
Standby
Active
L
H
X
High-Z
H
Output
Q0~Q15 : Dout
Active
L
L
Q0~Q7 : Dout
Q8~Q14 : Hi-Z
L
Input
Operating
Active
CAPACITANCE(TA=25°C, f=1.0MHz)
Item
Output Capacitance
Input Capacitance
Symbol
Test Conditions
VOUT=0V
Min
Max
12
Unit
pF
COUT
CIN
-
-
VIN=0V
12
pF
NOTE : Capacitance is periodically sampled and not 100% tested.
KM23V32005BG
CMOS MASK ROM
AC CHARACTERISTICS(TA=0°C to +70°C, VCC=3.3V±0.3V, unless otherwise noted.)
TEST CONDITIONS
Item
Value
0.45V to 2.4V
10ns
Input Pulse Levels
Input Rise and Fall Times
Input and Output timing Levels
Output Loads
1.5V
1 TTL Gate and CL=100pF
READ CYCLE
Item
KM23V32005BG-10
KM23V32005BG-12
KM23V32005BG-15
Symbol
Unit
Min
Max
Min
Max
Min
Max
Read Cycle Time
tRC
tACE
tAA
100
120
150
ns
ns
ns
ns
ns
Chip Enable Access Time
Address Access Time
100
100
30
120
120
50
150
150
70
Page Address Access Time
Output Enable Access Time
tPA
tOE
30
50
70
Output or Chip Disable to
Output High-Z
tDF
tOH
20
20
30
ns
ns
Output Hold from Address Change
0
0
0
NOTE : Page Address is determined as below.
Word mode(BHE=VIH) ; A0, A1, A2
Byte mode(BHE=VIL) ; A -1, A0, A1, A2
KM23V32005BG
CMOS MASK ROM
TIMING DIAGRAM
READ
ADD
ADD1
ADD2
A0~A20
A-1(*1)
tRC
tDF(*3)
tACE
CE
OE
tOE
tAA
tOH
DOUT
D0~D7
VALID DATA
VALID DATA
D8~D15(*2)
PAGE READ
CE
OE
tDF(*3)
ADD
A3~A20
ADD
1 st
2 nd
3 rd
A0,A1,A2
A -1(*1)
tAA
tPA
DOUT
VALID DATA
VALID DATA
VALID DATA
VALID DATA
D0~D7
D8~D15(*2)
NOTES :
*1.Byte Mode only. A-1 is Least Significant Bit Address.(BHE = VIL)
*2. Word Mode only.(BHE = VIH)
*3. tDF is defined as the time at which the outputs achieve the open circuit condition and is not referenced to VOH or VOL level.
KM23V32005BG
CMOS MASK ROM
PACKAGE DIMENSIONS
(Unit : mm/inch)
44-SOP-600
0~8°
#44
#23
16.04±0.30
12.60±0.20
0.631±0.012 0.496±0.008
0.80±0.20
#1
#22
+0.10
0.20
-0.05
0.031±0.008
0.008+0.004
-0.002
2.80±0.20
0.110±0.008
28.95
1.140
MAX
3.10
0.122
28.50±0.20
1.122±0.008
MAX
0.10 MAX
0.004 MAX
0.40 +0.100
0.05
0.002
-0.050
1.27
0.050
MIN
0.915
0.036
+0.004
-0.002
(
)
0.016
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