KM29W8000IT [SAMSUNG]
Flash, 1MX8, 45ns, PDSO40, 0.400 INCH, 0.80 MM PITCH, PLASTIC, TSOP2-44/40;
| 型号： | KM29W8000IT |
| 厂家： | 
SAMSUNG |
| 描述： | Flash, 1MX8, 45ns, PDSO40, 0.400 INCH, 0.80 MM PITCH, PLASTIC, TSOP2-44/40 光电二极管 内存集成电路 |
| 文件： | 总25页 (文件大小：446K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
KM29W8000T, KM29W8000IT
FLASH MEMORY
Document Title
1M x 8 bit NAND Flash Memory
Revision History
Revision No.
History
Draft Date
Remark
0.0
1.0
Data Sheet 1997
April 10th 1997
April 10th 1998
Advance
Data Sheet 1998
Preliminary
1. Changed tBERS parameter : 5ms(Typ.) ® 2ms(Typ.)
10ms(Max.) ® 4ms(Max.)
2. Changed tPROG parameter : 1.5ms(Max.) ® 1.0ms(Max.)
1.1
July 14th 1998
Final
Data sheet 1998
1. Cjanged DC and Operating Characteristics
Vcc=2.7V~3.6V
Vcc=3.6V~5.5V
Typ Max
Parameter
Unit
Typ
Max
Burst Read
10 ® 5
10 ® 5
10 ® 5
20 ® 10 15 ® 10 30 ® 20
20 ® 10 15 ® 10 30 ® 20
20 ® 10 15 ® 10 30 ® 20
Operating
Current
mA
Program
Eraase
Stand-by Current (CMOS) 5 ® 10
50
10
-
100 ® 50
10 ® ±10
10 ® ±10
mA
Input Leakage Current
Output Leakage Current
-
-
10 ® ±10
10 ® ±10
-
1.2
April 10th 1999
Final
Data Sheet 1999
1) Added CE dont’ care mode during the data-loading and reading
The attached datasheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right
to change the specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions about device. If you have
any questions, please contact the SAMSUNG branch office near you.
1
KM29W8000T, KM29W8000IT
1M x 8 Bit NAND Flash Memory
FEATURES
FLASH MEMORY
GENERAL DESCRIPTION
The KM29W8000 is a 1M(1,048,576)x8bit NAND Flash Mem-
ory with a spare 32K(32,768)x8bit. Its NAND cell provides the
most cost-effective solution for the solid state mass storage
market. A program operation programs the 264-byte page in
typically 250ms and an erase operation can be performed in
typically 2ms on a 4K-byte block.
Data in the page can be read out at 80ns cycle time per byte.
The I/O pins serve as the ports for address and data input/out-
put as well as command inputs. The on-chip write controller
automates all program and erase system functions, including
pulse repetition, where required, and internal verify and margin-
ing of data. Even the write-intensive systems can take advan-
tage of the KM29W8000 extended reliability of 1,000,000
program/erase cycles by providing either ECC(Error Correction
Code) or real time mapping-out algorithm. These algorithms
have been implemented in many mass storage applications
and also the spare 8bytes of a page combined with the other
256 bytes can be utilized by system-level ECC.
· Voltage supply : 2.7V ~ 5.5V
· Organization
- Memory Cell Array : (1M + 32K)bit x 8bit
- Data Register
: (256 + 8)bit x8bit
· Automatic Program and Erase(Typical)
- Page Program : (256 + 8)Byte in 250ms
- Block Erase : (4K + 128)Byte in 2ms
- Status Register
· 264-Byte Page Read Operation
- Random Access
: 10ms(Max.)
- Serial Page Access : 80ns(Min.)
· System Performance Enhancement
- Ready/ Busy Status Output
· Command/Address/Data Multiplexed I/O port
· Hardware Data Protection
- Program/Erase Lockout During Power Transitions
· Reliable CMOS Floating-Gate Technology
- Endurance : 1M Program/Erase Cycles
- Data Retention : 10 years
· Command Register Operation
The KM29W8000 is an optimum solution for large nonvolatile
storage application such as solid state storage, digital voice
recorder, digital still camera and other portable applications
requiring nonvolatility.
· 44(40) - Lead TSOP Type II (400mil / 0.8 mm pitch)
PIN CONFIGURATION
PIN DESCRIPTION
Pin Name
I/O0~I/O7
CLE
ALE
Pin Function
Data Inputs/Outputs
VSS
CLE
ALE
WE
WP
N.C
N.C
N.C
N.C
N.C
1
2
3
4
5
6
7
8
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
VCC
CE
RE
R/B
GND
N.C
N.C
N.C
N.C
N.C
Command Latch Enable
Address Latch Enable
Chip Enable
CE
9
10
11
12
13
14
15
16
17
18
19
20
21
22
RE
Read Enable
WE
Write Enable
N.C
N.C
N.C
N.C
N.C
I/O0
I/O1
I/O2
I/O3
VSS
N.C
N.C
N.C
N.C
N.C
I/O7
I/O6
I/O5
I/O4
VCC
WP
Write Protect
GND
R/B
Ground Input
Ready/Busy output
Power(2.7V ~ 5.5V)
Ground
VCC
VSS
N.C
No Connection
44(40) TSOP (II)
STANDARD TYPE
NOTE : Connect all VCC and VSS pins of each device to power supply outputs.
Do NOT leave VCC or VSS disconnected.
2
KM29W8000T, KM29W8000IT
FLASH MEMORY
Figure 1. FUNCTIONAL BLOCK DIAGRAM
vCC
vSS
X-Buffers
A8 - A19
Latches
& Decoders
8M + 256K Bit
NAND Flash
ARRAY
Y-Buffers
A0 - A7
Latches
& Decoders
(256 + 8)Byte x 4096
Page Register & S/A
Y-Gating
Command
Command
Register
vCC
vSS
I/O Buffers & Latches
Global Buffers
CE
RE
WE
Control Logic
& High Voltage
Generator
I/00
Output
Driver
I/07
CLE ALE WP
Figure 2. ARRAY ORGANIZATION
1 Block(=16 Row)
(4K + 128)Byte
1 Page = 264 Byte
1 Block = 264 B x 16 Pages
= (4K + 128) Bytes
1 Device = 264B x 16Pages x 256 Blocks
= 8.6 Mbits
8M : 4K Row
(=256 Block)
8 bit
256B Column
8B Column
I/O0 ~ I/O7
Page Register
256 Byte
8 Byte
I/O0
A0
I/O1
A1
I/O2
A2
I/O3
A3
I/O4
I/O5
A5
I/O6
A6
I/O7
A7
1st Cycle
2nd Cycle
3rd Cycle
A4
A12
*X
Column Address
Row Address
(Page Address)
A8
A9
A10
A18
A11
A19
A13
*X
A14
*X
A15
*X
A16
A17
NOTE : A12 to A19 : Block Address
* : X can be VIL or VIH.
3
KM29W8000T, KM29W8000IT
FLASH MEMORY
PRODUCT INTRODUCTION
The KM29W8000 is an 8.6Mbit(8,650,752 bit) memory organized as 4096 rows by 264 columns. Spare eight columns are located
from column address of 256 to 263. A 264-byte data register is connected to memory cell arrays accommodating data transfer
between the I/O buffers and memory during page read and page program operations. The memory array is made up of 16 cells that
are serially connected to form a NAND structure. Each of the 16 cells resides in a different page. A block consists of the 16 pages
formed by one NAND structures, totaling 2,112 NAND structures of 16 cells. The array organization is shown in Figure 2. The pro-
gram and read operations are executed on a page basis, while the erase operation is executed on block basis. The memory array
consists of 256 separately or grouped erasable 4K-byte blocks. It indicates that the bit by bit erase operation is prohibited on the
KM29W8000.
The KM29W8000 has addresses multiplexed into 8 I/O¢s. This scheme dramatically reduces pin counts and allows systems
upgrades to future densities by maintaining consistency in system board design. Command, address and data are all written through
I/O¢s by bringing WE to low while CE is low. Data is latched on the rising edge of WE. Command Latch Enable(CLE) and Address
Latch Enable(ALE) are used to multiplex command and address respectively, via the I/O pins. All commands require one bus cycle
except for Block Erase command which requires two cycles : a cycle for erase-setup and another for erase-execution after block
address loading. The 2M byte physical space requires 21 addresses, thereby requiring three cycles for byte-level addressing : col-
umn address, low row address and high row address, in that order. Page Read and Page Program need the same three address
cycles following the required command input. In Block Erase operation, however, only the two row address cycles are used.
Device operations are selected by writing specific commands into the command register. Table 1 defines the specific commands of
the KM29W8000.
Table 1. COMMAND SETS
Function
Sequential Data Input
Read 1
1st. Cycle
80h
2nd. Cycle
Acceptable Command during Busy
-
00h
-
Read 2
50h
-
Read ID
90h
-
Reset
FFh
-
O
O
Page Program
Block Erase
Read Status
10h
-
D0h
-
60h
70h
4
KM29W8000T, KM29W8000IT
FLASH MEMORY
PIN DESCRIPTION
Command Latch Enable(CLE)
The CLE input controls the path activation for commands sent to the command register. When active high, commands are latched
into the command register through the I/O ports on the rising edge of the WE signal.
Address Latch Enable(ALE)
The ALE input controls the path activation for address and input data to the internal address/data register.
Addresses are latched on the rising edge of WE with ALE high, and input data is latched when ALE is low.
Chip Enable(CE)
The CE input is the device selection control. When CE goes high during a read operation the device is returned to standby mode.
However, when the devices is in the busy state during program or erase, CE high is ignored, and does not return the device to
standby mode.
Write Enable(WE)
The WE input controls writes to the I/O port. Commands, address and data are latched on the rising edge of the WE pulse.
Read Enable(RE)
The RE input is the serial data-out control, and when active drives the data onto the I/O bus. Data is valid tREA after the falling edge
of RE which also increments the internal column address counter by one.
I/O Port : I/O0 ~ I/O7
The I/O pins are used to input command, address and data, and to output data during read operations. The I/O pins float to high-z
when the chip is deselected or when the outputs are disabled.
Write Protect(WP)
The WP pin provides inadvertent write/erase protection during power transitions. The internal high voltage generator is reset when
the WP pin is active low.
Ready/Busy(R/B)
The R/B output indicates the status of the device operation. When low, it indicates that a program, erase or random read operation is
in process and returns to high state upon completion. It is an open drain output and does not float to high-z condition when the chip is
deselected or when outputs are disabled.
5
KM29W8000T, KM29W8000IT
FLASH MEMORY
ABSOLUTE MAXIMUM RATINGS
Parameter
Symbol
Rating
Unit
Voltage on any pin relative to VSS
VIN
-0.6 to +7.0
-10 to +125
-40 to +125
-65 to +150
5
V
KM29W8000T
Temperature Under Bias
TBIAS
°C
KM29W8000IT
Storage Temperature
Short Circuit Output Current
NOTE :
TSTG
IOS
°C
mA
1. Minimum DC voltage is -0.3V on input/output pins. During transitions, this level may undershoot to -2.0V for periods <30ns.
Maximum DC voltage on input/output pins is VCC+0.3V which, during transitions, may overshoot to VCC+2.0V for periods <20ns.
2. Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to the conditions
as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
RECOMMENDED OPERATING CONDITIONS
(Voltage reference to GND, KM29W8000T:TA=0 to 70°C, KM29W8000IT:TA=-40 to 85°C)
Parameter
Supply Voltage
Supply Voltage
Symbol
VCC
Min
2.7
0
Typ.
Max
5.5
0
Unit
V
-
VSS
0
V
DC AND OPERATING CHARACTERISTICS(Recommended operating conditions otherwise noted.)
Vcc = 2.7V ~ 3.6V
Vcc = 3.6V ~ 5.5V
Parameter
Symbol
Test Conditions
Unit
Min
Typ
5
Max
10
Min Typ
Max
20
Burst Read Cycle
Program
ICC1
ICC2
tcycle=80ns,CE=VIL, IOUT=0mA
-
-
-
-
-
10
10
Operat-
ing
Current
5
10
10
mA
Erase
ICC3
ISB1
ISB2
ILI
-
CE=VIH, WP=0V/VCC
CE=VCC-0.2, WP=0V/VCC
VIN=0 to 5.5V
VOUT=0 to 5.5V
-
-
5
-
10
1
-
-
-
-
-
10
-
20
Stand-by Current(TTL)
-
-
1
50
Stand-by Current(CMOS)
Input Leakage Current
10
-
50
10
-
-
±10
±10
±10
±10
VCC+0.5
0.8
-
mA
Output Leakage Current
Input High Voltage, All inputs
Input Low Voltage, All inputs
Output High Voltage Level
Output Low Voltage Level
Output Low Current(R/B)
ILO
-
-
-
VIH
VIL
2.4
-0.3
2.4
-
-
VCC+0.3 2.4
-
-
-
0.6
-
-0.3
2.4
-
-
V
VOH
VOL
IOH=-400mA
-
-
IOL=2.1mA
-
0.4
-
-
0.4
-
IOL(R/B) VOL=0.4V
8
10
8
10
mA
6
KM29W8000T, KM29W8000IT
FLASH MEMORY
VALID BLOCK
Parameter
Symbol
Min
Typ.
Max
Unit
Valid Block Number
NVB
251
-
256
Blocks
NOTE :
1. The KM29W8000 may include invalid blocks. Invalid blocks are defined as blocks that contain one or more bad bits. Do not try to access these invalid
blocks for program and erase. During its lifetime of 10 years and/or 1million program/erase cycles,the minimum number of valid blocks are guaran-
teed though its initial number could be reduced. (Refer to the attached technical notes)
2. The 1st block, which is placed on 00h block address, is guaranteed to be a valid block
AC TEST CONDITION
(KM29W8000T:TA=0 to 70°C, KM29W8000IT:TA=-40 to 85°C, VCC=2.7V ~ 5.5V unless otherwise noted)
Value
Parameter
Vcc = 2.7V ~ 3.6V
Vcc = 3.6V ~ 5.5V
Input Pulse Levels
0.4V to 2.6V
0.4V to 2.6V
Input Rise and Fall Times
Input and Output Timing Levels
5ns
0.8V and 2.0V
1TTL GATE & CL=50pF(3.0V+/-10%)
1TTL GATE & CL=100pF(3.0V~3.6V)
Output Load
1 TTL GATE and CL = 100pF
CAPACITANCE(TA=25°C, VCC=5.0V, f=1.0MHz)
Item
Symbol
Test Condition
VIL=0V
Min
Max
10
Unit
Input/Output Capacitance
Input Capacitance
CI/O
-
-
pF
pF
CIN
VIN=0V
10
NOTE : Capacitance is periodically sampled and not 100% tested.
MODE SELECTION
CLE
H
L
ALE
CE
L
WE
RE
H
WP
Mode
L
X
Command Input
Read Mode
Write Mode
H
L
H
X
Address Input(3clock)
Command Input
H
L
L
L
H
H
H
L
H
H
Address Input(3clock)
L
L
L
H
H
Data Input
L
L
L
H
H
X
X
X
X
X
Sequential Read & Data Output
During Read(Busy)
During Program(Busy)
During Erase(Busy)
Write Protect
L
L
L
H
X
X
X
X
X
X
X
X
X
X
H
H
X
X
H
L
X
X(1)
X
(2)
X
Stand-by
0V/VCC
NOTE : 1. X can be VIL or VIH
2. WP should be biased to CMOS high or CMOS low for standby.
Program/Erase Characteristics
Parameter
Symbol
Min
Typ
0.25
-
Max
1.0
10
Unit
ms
Program Time
tPROG
Nop
-
-
-
Number of Partial Program Cycles in the Same Page
Block Erase Time
cycles
ms
tBERS
2
4
7
KM29W8000T, KM29W8000IT
FLASH MEMORY
AC Timing Characteristics for Command / Address / Data Input
Parameter
Symbol
tCLS
tCLH
tCS
Min
20
40
20
40
40
20
40
30
20
80
20
Max
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
CLE Set-up Time
CLE Hold Time
CE Setup Time
CE Hold Time
-
-
-
-
-
-
-
-
-
-
-
tCH
WE Pulse Width
ALE Setup Time
ALE Hold Time
Data Setup Time
Data Hold Time
Write Cycle Time
tWP
tALS
tALH
tDS
tDH
tWC
WE High Hold Time
tWH
AC Characteristics for Operation
Parameter
Data Transfer from Cell to Register
ALE to RE Delay
Symbol
tR
Min
Max
Unit
-
150
200
200
20
-
10
ms
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tAR
-
-
ALE to RE Delay( ID Read )
CE to RE Delay( ID Read )
Ready to RE Low
tAR1
tCR
-
tRR
-
WE High to Busy
tWB
200
-
Read Cycle Time
tRC
80
-
RE Access Time
tREA
tRHZ
tCHZ
tREH
tIR
45
20
30
-
RE High to Output Hi-Z
CE High to Output Hi-Z
RE High Hold Time
5
-
20
0
Output Hi-Z to RE Low
Last RE High to Busy(at sequential read)
-
tRB
-
200
CE High to Ready(in case of interception by at read)(1)
CE High Hold Time(at the last serial read)(3)
RE Low to Status Output
100+tr(R/B)(2)
tCRY
tCEH
tRSTO
tCSTO
tWHR
tRST
-
250
-
-
45
CE Low to Status Output
-
55
WE High to RE Low
50
-
-
Device Resetting Time(Read/Program/Erase)
5/10/500
ms
NOTE : 1. If CE goes high within 30ns after the rising edge of the last RE, R/B will not return to VOL.
2. The time to Ready depends on the value of the pull-up resistor tied R/B pin.
3. To break the sequential read cycle, CE must be held high for longer time than tCEH.
8
KM29W8000T, KM29W8000IT
FLASH MEMORY
NAND Flash Technical Notes
Invalid Block(s)
Invalid blocks are defined as blocks that contain one or more invalid bits whose reliability is not guaranteed by Samsung. Typically,
an invalid block will contain a single bad bit. The information regarding the invalid block(s) is so called as the invalid block informa-
tion. The invalid block information is written to the 1st or the 2nd page of the invalid block(s) with 00h data. Devices with invalid
block(s) have the same quality level or as devices with all valid blocks and have the same AC and DC characteristics. An invalid
block(s) does not affect the performance of valid block(s) because it is isolated from the bit line and the common source line by a
select transistor. The system design must be able to mask out the invalid block(s) via address mapping. The 1st block of the NAND
Flash, however, is fully guaranteed to be a valid block.
Identifying Invalid Block(s)
All device locations are erased(FFh) except locations where the invalid block information is written prior to shipping. Since the
invalid block information is also erasable in most cases, it is impossible to recover the information once it has been
erased. Therefore, the system must be able to recognize the invalid block(s) based on the original invalid block
information and create the invalid block table via the following suggested flow chart(Figure 1). Any intentional era-
sure of the original invalid block information is prohibited.
Start
Set Block Address = 0
Increment Block Address
Check "FFH" on the 1st and 2nd page
No
*
Create (or update)
Invalid Block(s) Table
Check "FFH"
?
Yes
No
Last Block
?
Yes
End
Figure 1. Flow chart to create invalid block table.
9
KM29W8000T, KM29W8000IT
FLASH MEMORY
NAND Flash Technical Notes (Continued)
Error in write or read operation
Over its life time, the additional invalid blocks may occur. Through the tight process control and intensive testing, Samsung mini-
mizes the additional block failure rate, which is projected below 0.1% up until 1million program/erase cycles. Refer to the qualification
report for the actual data.The following possible failure modes should be considered to implement a highly reliable system.
Failure Mode
Detection and Countermeasure sequence
Erase Failure
Status Read after Erase --> Block Replacement
Status Read after Program --> Block Replacement
Read back ( Verify after Program) --> Block Replacement
or ECC Correction
Write
Read
Program Failure
Single Bit Failure
Verify ECC -> Block Replacement or ECC Correction
: Error Correcting Code --> Hamming Code etc.
Example) 1bit correction & 2bit detection
ECC
Program Flow Chart
If ECC is used, this verification
operation is not needed.
Start
Write 00H
Write 80H
Write Address
Wait for tR Time
Write Address
Write Data
Write 10H
*
No
Program Error
Verify Data
Write 70H
Yes
Program Completed
No
SR. 6 = 1 ?
or R/B = 1 ?
: If program operation results in an error, map out
the block including the page in error and copy the
target data to another block.
*
Yes
*
No
Program Error
SR. 0 = 0 ?
Yes
10
KM29W8000T, KM29W8000IT
FLASH MEMORY
NAND Flash Technical Notes (Continued)
Erase Flow Chart
Read Flow Chart
Start
Start
Write 60H
Write 00H
Write Block Address
Write Address
Read Data
Write D0H
Write 70H
ECC Generation
No
No
SR. 6 = 1 ?
or R/B = 1 ?
Reclaim the Error
Verify ECC
Yes
Yes
*
No
Page Read Completed
Erase Error
SR. 0 = 0 ?
*
Block Replacement
Yes
: copy the corrected whole block data to another
block (recommended for high reliability system)
Erase Completed
*
: If erase operation results in an error, map out
the failing block and replace it with another block.
*
Block Replacement
Buffer
memory
error occurs
When the error happens in Block "A", try to write the
data into another Block "B" by reloading from an exter-
nal buffer. Then, prevent further system access to
Block "A"(by creating a "invalid block" table or other
appropriate scheme.)
Block A
Block B
11
KM29W8000T, KM29W8000IT
FLASH MEMORY
System Interface Using CE don’t-care.
For a easier system interface, CE may be inactive during the data-loading or sequential data-reading as shown below. The internal
256byte page registers are utilized as seperate buffers for this operation and the system design gets more flexible. In addition, for
voice or audio applications which use slow cycle time on the order of u-seconds, de-activating CE during the data-loading and read-
ing would provide significant savings in power consumption.
Figure 3. Program Operation with CE don’t-care.
CLE
CE dont’-care
CE
WE
ALE
80H
Start Add.(3Cycle)
Data Input
Data Input
10H
I/O0~7
CE
(Max. 55ns)
tCEA
tCS
tCH
CE
RE
tREA
tWP
WE
I/O0~7
out
Timing requirements : If CE is is exerted high during sequential
data-reading, the falling edge of CE to valid data(tCEA) must
be kept greater than 55ns.
Figure 4. Read Operation with CE don’t-care.
CLE
CE
CE dont’-care
RE
ALE
tR
R/B
WE
Data Output(sequential)
00H
Start Add.(3Cycle)
I/O0~7
12
KM29W8000T, KM29W8000IT
FLASH MEMORY
* Command Latch Cycle
CLE
tCLH
tCH
tCLS
tCS
CE
tWP
WE
tALH
tALS
ALE
tDH
tDS
Command
I/O0~7
* Address Latch Cycle
tCLS
CLE
CE
tCS
tWC
tWC
tWP
tWP
tWP
WE
tWH
tWH
tALH
tALS
ALE
tDH
tDH
tDH
tDS
tDS
tDS
A0~A7
I/O0~7
A16~A19
A8~A15
13
KM29W8000T, KM29W8000IT
FLASH MEMORY
* Input Data Latch Cycle
tCLH
CLE
CE
tCH
tWC
tALS
ALE
tWP
tWP
tWP
WE
tWH
tDH
tDH
tDH
tDS
tDS
tDS
I/O0~7
DIN 255
DIN 0
DIN 1
* Sequential Out Cycle after Read(CLE=L, WE=H, ALE=L)
tRC
CE
tREH
tCHZ*
tREA
tREA
tREA
RE
tRHZ
tRHZ*
I/O0~7
R/B
Dout
Dout
Dout
tRR
NOTES : Transition is measured ±200mV from steady state voltage with load.
This parameter is sampled and not 100% tested.
14
KM29W8000T, KM29W8000IT
FLASH MEMORY
* Status Read Cycle
tCLS
CLE
tCLS
tCLH
tCS
CE
tCH
tWP
WE
tCSTO
tCHZ
tWHR
RE
tDH
tRSTO
tDS
tIR
tRHZ
Status Output
I/O0~7
70H
READ1 OPERATION(READ ONE PAGE)
CLE
tCEH
tCHZ
CE
WE
ALE
RE
tWB
tAR
tCRY
tRHZ
tR
tRC
tRR
A8 ~ A15 A16 ~ A19
Dout N+3
00h
A0 ~ A7
Dout N+1 Dout N+2
Dout 263
tRB
Dout N
I/O0~7
R/B
Column
Address
Page(Row)
Address
Busy
15
KM29W8000T, KM29W8000IT
FLASH MEMORY
READ1 OPERATION(INTERCEPTED BY CE)
CLE
CE
WE
tWB
tCHZ
tAR
ALE
RE
tRC
tR
tRR
Dout N+2 Dout N+3
Dout N
Dout N+1
A8 ~ A15
A16 ~ A19
00h
A0 ~ A7
I/O0~7
R/B
Page(Row)
Address
Column
Address
Busy
READ2 OPERATION(READ ONE PAGE)
CLE
CE
WE
ALE
RE
tR
tWB
tAR
tRR
Dout
255+M+1
Dout
50H
A8 ~ A15 A16 ~ A19
Dout 263
A0 ~ A7
I/O0~7
R/B
255+M
Selected
Row
M Address
8
256
Start
address M
16
KM29W8000T, KM29W8000IT
FLASH MEMORY
SEQUENTIAL ROW READ OPERATION
CLE
CE
WE
ALE
RE
Dout
N
Dout
N+1
Dout
N+2
Dout
0
Dout
1
Dout
2
Dout
263
Dout
263
00H
A0 ~ A7 A8 ~ A15
A16 ~ A19
I/O0~7
R/B
Ready
Busy
Busy
M
M+1
Output
N
Output
PAGE PROGRAM OPERATION
CLE
CE
WE
ALE
RE
tPROG
tWB
Din
263
Din
N
Din
N+1
10H
80H
A0 ~ A7 A8 ~ A15 A16 ~ A19
70H
I/O0
I/O0~7
R/B
Sequential Data
Input Command
1 up to 264 Byte Data
Serial Input
Column
Address
Program
Command
Read Status
Command
Page(Row)
Address
I/O0=0 Successful Program
I/O0=1 Error in Program
17
KM29W8000T, KM29W8000IT
FLASH MEMORY
BLOCK ERASE OPERATION(ERASE ONE BLOCK)
CLE
CE
WE
tBERS
tWB
ALE
RE
60H
A8 ~ A15 A16 ~ A19
70H
DOH
I/O 0
I/O0~7
R/B
Page(Row)
Address
Busy
I/O0=0 Successful Erase
Read Status I/O0=1 Error in Erase
Command
Auto Block Erase Setup Command
Erase Command
18
KM29W8000T, KM29W8000IT
FLASH MEMORY
DEVICE OPERATION
PAGE READ
Upon initial device power up, the device defaults to Read1 mode. This operation is also initiated by writing 00H to the command reg-
ister along with three address cycles. Once the command is latched, it does not need to be written for the following page read opera-
tion. Three types of operations are available : random read, sequential page read and sequential row read.
The random read mode is enabled when the page address is changed. The 264 bytes of data within the selected page are trans-
ferred to the data registers in less than 10ms(tR). The CPU can detect the completion of this data transfer(tR) by analyzing the output
of R/B pin. Once the data in a page is loaded into the registers, they may be read out in 80ns cycle time by sequentially pulsing RE
with CE staying low. High to low transitions of the RE clock output the data starting from the selected column address up to the last
column address(column 264).
After the data of last column address is clocked out, the next page is automatically selected for sequential read.
Waiting 10ms again allows for reading of the page. The sequential row read operation is terminated by bringing CE to high. The way
the Read1 and Read2 commands work is like a pointer set to either the main area or the spare area. The spare area of bytes 256 to
263 may be selectively accessed by writing the Read2 command. Addresses A
0
to A
2
set the starting address of the spare area while
addresses A to A are ignored. Unless the operation is aborted, the page address is automatically incremented for sequential row
3
7
read as in Read1 operation and spare eight bytes of each page may be sequentially read. The Read1 command(00H) is needed to
move the pointer back to the main area. Figures 3 thru 6 show typical sequence and timings for each read operation.
Figure 3. Read1 Operation
CLE
CE
WE
ALE
tR
R/B
RE
00H
Start Add.(3Cycle)
A0 ~ A7 & A8 ~ A19
Data Output(Sequential)
I/O0~7
(00H Command)
Seek Time
Data Field
Spare Field
19
KM29W8000T, KM29W8000IT
FLASH MEMORY
Figure 4. Read2 Operation
CLE
CE
WE
ALE
R/B
Busy(Seek Time)
RE
Data Output(Sequential)
Spare Field
50H
Start Add.(3Cycle)
A0 ~ A2 & A8 ~ A19
I/O0~7
(A3 ~ A7 :
Don¢t Care)
Seek Time
Data Field
Spare Field
Figure 5. Sequential Row Read1 Operation
tR
tR
tR
R/B
I/O0~7
00H
Start Add.(3Cycle)
A0 ~ A7 & A8 ~ A19
Data Output
1st
Data Output
Data Output
2nd
(264 Byte)
Nth
(264 Byte)
(GND=L, 00H Command)
1st
2nd
Nth
Data Field
Spare Field
20
KM29W8000T, KM29W8000IT
FLASH MEMORY
Figure 6. Sequential Row Read2 Operation
tR
tR
tR
R/B
I/O0~7
50H
Start Add.(3Cycle)
A0 ~ A2 & A8 ~ A19
Data Output
1st
Data Output
Data Output
2nd
(8Byte)
Nth
(8Byte)
(A3 ~ A7 :
Don¢t Care)
1st
2nd
Nth
Data Field
Spare Field
PAGE PROGRAM
The device is programmed basically on a page basis. But it also allows multiple partial page programming of a byte or consecutive
bytes up to 264 may be programmed in a single page program cycle. The number of partial page programming operation in the same
page without an intervening erase operation must not exceed ten. The addressing may be done in any random order in a block. A
page program cycle consist of a serial data loading period in which up to 264 bytes of data must be loaded into the device, and non-
volatile programming period in which the loaded data is programmed into the appropriate cell.
The sequential data loading period begins by inputting the Serial Data Input command(80H), followed by the three cycle address
input and then serial data loading. The bytes other than those to be programmed do not need to be loaded.
In order to program the bytes in the spare columns of 256 to 263, the pointer should be set to the spare area by writing the Read 2
command(50H) to the command register. The pointer remains in the spare area unless the Read 1 command(00H) is entered to
retum to the main area. The Page Program confirm command(10H) initiates the programming process. Writing 10H alone without
previously entering the serial data will not initiate the programming process. The internal write controller automatically executes the
algorithms and timings necessary for program and verify, thereby freeing the CPU for other tasks. Once the program process starts,
the Status Register may be read RE and CE low after the Read Status command(70H) is written to it. The CPU can detect the com-
pletion of program cycle by monitoring the R/B output, or the Status bit(I/O6) of the Status Register. Only the Read Status command
and Reset command are valid while programming is in progress. When the Page Program is complete, the Write Status Bit(I/O0) may
be checked(Figure 7). The internal write verify detects only errors for "1"s that are not successfully programmed to "0"s. The com-
mand register remains in Read Status command mode until another valid command is written to the command register.
Figure 7. Program & Read Status Operation
tPROG
R/B
Pass
I/O0~7
80H
Address & Data Input
I/O0
Fail
10H
70H
A0 ~ A7 & A8 ~ A19
264 Byte Data
21
KM29W8000T, KM29W8000IT
FLASH MEMORY
BLOCK ERASE
The Erase operation is done on a block(4K Byte) basis. Block address loading is accomplished in two cycles initiated by an Erase
Setup command(60H). Only address A12 to A19 is valid while A8 to A11 is ignored. The Erase Confirm command(D0H) following the
block address loading initiates the internal erasing process. This two-step sequence of setup followed by execution command
ensures that memory contents are not accidentally erased due to external noises conditions.
At the rising edge of WE after the erase confirm command input, the internal write controller handles erase, erase-verify and pulse
repetition where required. If an erase operation error is detected, the internal verify is halted and erase operation is terminated. When
the erase operation is complete, the Write Status Bit(I/O0) may be checked.
Figure 8 details the sequence.
Figure 8. Block Erase Operation
tBERS
R/B
Pass
I/O0~7
60H
I/O0
Fail
70H
Address Input(2Cycle)
Block Add. : A8 ~ A19
D0H
READ STATUS
The device contains a Status Register which may be read to find out whether program or erase operation is complete, and whether
the program or erase operation is completed successfully. After writing 70H command to the command register, a read cycle outputs
the contents of the Status Register to the I/O pins on the falling edge of CE or RE, whichever occurs last. This two line control allows
the system to poll the progress of each device in multiple memory connections even when R/B pins are common-wired. RE or CE
does not need to be toggled for updated status. Refer to table 2 for specific Status Register definitions. The command register
remains in Status Read mode until further commands are issued to it. Therefore, if the status register is read during a random read
cycle, a read command(00H or 50H) should be given before sequential page read cycle.
Table2. Status Register Definition
SR
Status
Definition
"0" : Successful Program / Erase
I/O0
Program / Erase
"1" : Error in Program / Erase
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
"0"
"0"
"0"
"0"
"0"
Reserved for Future
Use
Device Operation
Write Protect
"0" : Busy
"1" : Ready
"1" : Not Protected
"0" : Protected
22
KM29W8000T, KM29W8000IT
FLASH MEMORY
READ ID
The device contains a product identification mode, initiated by writing 90H to the command register, followed by an address input of
00H. Two read cycles sequentially output the manufacture code(ECH), and the device code (6EH) respectively. The command regis-
ter remains in Read ID mode until further commands are issued to it. Figure 9 shows the operation sequence.
Figure 9. Read ID Operation
CLE
tCR
CE
WE
tAR1
ALE
RE
tREA
I/O0~7
Address. 1 cycle
A0 ~ A7 :"0"
Dout(6EH)
90H
Dout(ECH)
Maker code
Device code
RESET
The device offers a reset feature, executed by writing FFH to the command register. When the device is in Busy state during random
read, program or erase mode, the reset operation will abort these operations. The contents of memory cells being altered are no
longer valid, as the data will be partially programmed or erased. The command register is cleared to wait for the next command, and
the Status Register is cleared to value C0H when WP is high. Refer to table 3 for device status after reset operation. If the device is
already in reset state a new reset command will not be accepted by the command register. The R/B pin transitions to low for tRST
after the Reset command is written. Reset command is not necessary for normal operation. Refer to Figure 10 below.
Figure 10. RESET Operation
tRST
R/B
I/O0~7
FFH
Table3. Device Status
After Power-up
After Reset
Operation Mode
Read 1
Waiting for next command
23
KM29W8000T, KM29W8000IT
FLASH MEMORY
READY/BUSY
The device has a R/B output that provides a hardware method of indicating the completion of a page program, erase and random
read completion. The R/B pin is normally high but transitions to low after program or erase command is written to the command reg-
ister or random read is started after address loading. It returns to high when the internal controller has finished the operation. The pin
is an open-drain driver thereby allowing two or more R/B outputs to be Or-tied. An appropriate pull-up resister is required for proper
operation and the value may be calculated by the following equation.
VCC
Note*
VCC(Max.) - VOL(Max.)
Rp =
=
8mA + SIL
IOL + SIL
R/B
open drain output
where IL is the sum of the input currents of all devices tied to the
R/B pin.
Note* : 5.1V when Vcc=3.6V~5.5V
3.2V when Vcc=2.7V~3.6V
GND
Device
DATA PROTECTION
The device is designed to offer protection from any involuntary program/erase during power-transitions. An internal voltage detector
disables all functions whenever Vcc is below about 2V. WP pin provides hardware protection and is recommended to be kept at VIL
during power-up and power-down as shown in Figure 11. The two step command sequence for program/erase provides additional
software protection.
Figure 11. AC Waveforms for Power Transition
~ 2.5V
~ 2.5V
VCC
WP
High
24
KM29W8000T, KM29W8000IT
FLASH MEMORY
PACKAGE DIMENSIONS
44(40) LEAD PLASTIC THIN SMALL OUT-LINE PACKAGE TYPE(II)
44(40) - TSOP2 - 400F
Unit :mm/Inch
0~8°
0.25
TYP
0.010
#44(40)
#23(21)
0.50
0.020
#1
#22(20)
+0.10
0.15
-0.05
+0.004
-0.002
0.006
18.81
0.741
Max.
18.41±0.10
0.725±0.004
0.10
MAX
0.004
0.805
0.032
0.80
0.35±0.10
0.014±0.004
(
)
0.0315
25
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