KM416RD8C-SK80 [SAMSUNG]
Rambus DRAM, 8MX16, CMOS, PBGA62, CSP, MICRO, BGA-62;
| 型号： | KM416RD8C-SK80 |
| 厂家： | 
SAMSUNG |
| 描述： | Rambus DRAM, 8MX16, CMOS, PBGA62, CSP, MICRO, BGA-62 动态存储器 |
| 文件： | 总64页 (文件大小：3807K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Preliminary
Direct RDRAM
™
KM416RD8C/KM418RD8C
128/144Mbit RDRAM
256K x 16/18 bit x 2*16 Dependent Banks
Direct RDRAMTM
Revision 0.9
April 1999
Rev. 0.9 Apr. 1999
Preliminary
Direct RDRAM
™
KM416RD8C/KM418RD8C
Revision History
Version 0.7 (Nov. 1998) - Target
- First copy.
- Based on the Rambus Datasheet ver. 0.7.
Version 0.9 (April 1999) - Preliminary
- Based on the Rambus Datasheet ver. 0.9.
Rev. 0.9 Apr. 1999
Preliminary
Direct RDRAM
™
KM416RD8C/KM418RD8C
ORDERING INFORMATION
1
2
3
4
5
6
7
8
9
10
KM 4 XX XX XX X X - X X XX
SAMSUNG Memory
Device
Speed
tRAC(Row Access Time)
Organization
Product
Power & Refresh
Package Type
Density
Revision
1. SAMSUNG Memory
7. Package Type
- C : u - BGA(CSP-Forward)
- D : u - BGA(CSP-Reverse)
- W : WL - CSP
2. Device
- 4 : DRAM
- S : u-BGA For Sony
8. Power & Refresh
- Blank : Normal Power Self Refesh(32m/8K, 3.9us)
3. Organization
- 16 : x16 bit
- L
- R
- S
: Low Power Self Refesh(32m/8K, 3.9us)
: Normal Power Self Refesh(32m/16K, 1.9us)
: Low Power Self Refesh(32m/16K, 1.9us)
- 18 : x18 bit
4. Product
9. tRAC(Row Access Time)
- Blank : for Daisy Chain Sample
- RD : Direct RAMBUS DRAM
- G
- K
- M
: 53.3ns
: 45ns
: 40ns
5. Density
- 2 : 2M
- 4 : 4M
- 8 : 8M
- 16 : 16M
- B~D, F, J, L, N~ : Reserved
10. Speed
- DS : for Daisy Chain Sample
- 60 : 600Mbps (300MHz)
- 80 : 800Mbps (400MHz)
6. Revision
- Blank : 1st Gen.
- A
: 2nd Gen.
Rev. 0.9 Apr. 1999
Preliminary
Direct RDRAM
™
KM416RD8C/KM418RD8C
Overview
The Rambus Direct RDRAM™ is a general purpose high-
performance memory device suitable for use in a broad
range of applications including computer memory, graphics,
video, and any other application where high bandwidth and
low latency are required.
â
The 128/144-Mbit Direct Rambus DRAMs (RDRAM ) are
extremely high-speed CMOS DRAMs organized as 8M
words by 16 or 18 bits. The use of Rambus Signaling Level
(RSL) technology permits 600MHz or 800MHz transfer
rates while using conventional system and board design
technologies. Direct RDRAM devices are capable of
sustained data transfers at 1.25 ns per two bytes (10ns per
sixteen bytes).
Figure 1: Direct RDRAM CSP Package
The architecture of the Direct RDRAMs allows the highest
sustained bandwidth for multiple, simultaneous randomly
addressed memory transactions. The separate control and
data buses with independent row and column control yield
over 95% bus efficiency. The Direct RDRAM's thirty-two
banks support up to four simultaneous transactions.
The 128/144-Mbit Direct RDRAMs are offered in a CSP
horizontal package suitable for desktop as well as low-
profile add-in card and mobile applications.
Direct RDRAMs operate from a 2.5 volt supply.
System oriented features for mobile, graphics and large
memory systems include power management, byte masking,
and x18 organization. The two data bits in the x18 organiza-
tion are general and can be used for additional storage and
bandwidth or for error correction.
Key Timing Parameters/Part Numbers
Speed
trac (Row
Access
Time) ns
Organization
Part Number
I/O Freq.
MHz
Features
Binning
¨ Highest sustained bandwidth per DRAM device
- 1.6GB/s sustained data transfer rate
- Separate control and data buses for maximized
efficiency
256Kx16x32sa -RG60
600
800
800
600
800
800
600
800
800
600
800
800
53
45
40
53
45
40
53
45
40
53
45
40
KM416RD8C-RbG60
KM416RD8C-RK80
KM416RD8C-RM80
KM416RD8C-ScG60
KM416RD8C-SK80
KM416RD8C-SM80
KM418RD8C-RG60
KM418RD8C-RK80
KM418RD8C-RM80
KM418RD8C-SG60
KM418RD8C-SK80
KM418RD8C-SM80
-RK80
-RM80
- Separate row and column control buses for
easy scheduling and highest performance
- 32 banks: four transactions can take place simul-
taneously at full bandwidth data rates
-SG60
-SK80
-SM80
256Kx18x32s -RG60
¨ Low latency features
- Write buffer to reduce read latency
- 3 precharge mechanisms for controller flexibility
- Interleaved transactions
-RK80
-RM80
-SG60
-SK80
-SM80
¨ Advanced power management:
- Multiple low power states allows flexibility in power
consumption versus time to transition to active state
- Power-down self-refresh
a.The “32s"designation indicates that this RDRAM core is composed of 32
banks which use a "split" bank architecture.
¨ Organization: 1Kbyte pages and 32 banks, x 16/18
- x18 organization allows ECC configurations or
increased storage/bandwidth
b.The “ R"designation indicates that this RDRAM core uses Normal Power
Self Refresh.
- x16 organization for low cost applications
c.The “S"designation indicates that this RDRAM core uses Low Power Self
Refresh.
¨ Uses Rambus Signaling Level (RSL) for up to 800MHz
operation
Page 1
Rev. 0.9 Apr. 1999
Preliminary
KM416RD8C/KM418RD8C
Direct RDRAM™
(the view looking down on the package as it is mounted on
the circuit board).
Pinouts and Definitions
Forward Package
This table shows the pin assignments of the center-bonded-
forward RDRAM package from the top-side of the package
Table 1 : Forward Package (Top View)
Top View
GND
VDD
VDD
GND
12
11
10
9
DQA7
GND
CMD
DQA4
VDD
CFM
GND
CFMN
GNDa
VDDa
RQ5
VDD
RQ6
RQ3
GND
RQ2
DQB0
VDD
DQB4
VDD
DQB7
GND
SIO1
DQA5
DQA2
DQB1
DQB5
8
Chip
7
6
SCK
DQA6
GND
DQA1
VDD
VREF
GND
RQ7
GND
CTM
RQ1
VDD
RQ4
DQB2
GND
RQ0
DQB6
GND
SIO0
5
* DQA8/DQB8 are just used for
144Mb RDRAM. These two pins are
NC(No Connection) in 128Mb
RDRAM.
VCMOS
VCMOS
4
*
*
DQA8
DQA3
DQA0
CTMN
DQB3
DQB8
3
2
GND
VDD
VDD
GND
1
A
B
C
D
E
F
G
H
J
This table shows the pin assignments of the center-bonded-
Reverse RDRAM package from the top-side of the package
(the view looking down on the package as it is mounted on
the circuit board).
Table 2: Reverse Package (Top View)
GND
VDD
VDD
GND
12
11
10
9
*
*
DQA8
DQA3
GND
DQA0
VDD
CTMN
GND
CTM
GND
RQ7
RQ4
VDD
RQ1
RQ0
GND
DQB2
DQB3
GND
DQB8
VCMOS
SIO0
VCMOS
SCK
DQA6
DQA1
VREF
DQB6
8
7
6
CMD
GND
DQA5
VDD
DQA2
GND
CFM
VDDa
GNDa
CFMN
RQ6
VDD
RQ5
RQ2
GND
RQ3
DQB1
VDD
DQB5
VDD
SIO1
GND
5
4
DQA7
DQA4
DQB0
DQB4
DQB7
3
2
GND
VDD
VDD
GND
1
A
B
C
D
E
F
G
H
J
Page 2
Rev. 0.9 Apr. 1999
Preliminary
Direct RDRAM
™
KM416RD8C/KM418RD8C
Table 3: Pin Description
Signal
I/O
Type
# of Pins
Description
a
a
a
SIO1,SIO0
I/O
CMOS
2
Serial input/output. Pins for reading from and writing to the control
registers using a serial access protocol. Also used for power man-
agement.
CMD
SCK
I
I
CMOS
CMOS
1
1
Command input. Pins used in conjunction with SIO0 and SIO1 for
reading from and writing to the control registers. Also used for
power management.
Serial clock input. Clock source used for reading from and writing to
the control registers
V
V
V
10
1
Supply voltage for the RDRAM core and interface logic.
Supply voltage for the RDRAM analog circuitry.
Supply voltage for CMOS input/output pins.
DD
DDa
CMOS
6
GND
9
Ground reference for RDRAM core and interface.
Ground reference for RDRAM analog circuitry.
GNDa
1
b
DQA8..DQA0
I/O
RSL
9
Data byte A. Nine pins which carry a byte of read or write data
between the Channel and the RDRAM. DQA8 is not used by
RDRAMs with a x16 organization.
b
CFM
I
I
RSL
1
1
Clock from master. Interface clock used for receiving RSL signals
from the Channel. Positive polarity.
b
CFMN
RSL
Clock from master. Interface clock used for receiving RSL signals
from the Channel. Negative polarity
V
1
1
Logic threshold reference voltage for RSL signals
REF
b
CTMN
I
RSL
Clock to master. Interface clock used for transmitting RSL signals
to the Channel. Negative polarity.
b
CTM
I
RSL
1
3
5
9
Clock to master. Interface clock used for transmitting RSL signals
to the Channel. Positive polarity.
b
RQ7..RQ5 or
ROW2..ROW0
I
RSL
Row access control. Three pins containing control and address
information for row accesses.
b
RQ4..RQ0 or
COL4..COL0
I
RSL
Column access control. Five pins containing control and address
information for column accesses.
b
DQB8..
DQB0
I/O
RSL
Data byte B. Nine pins which carry a byte of read or write data
between the Channel and the RDRAM. DQB8 is not used by
RDRAMs with a x16 organization.
Total pin count per package
62
a. All CMOS signals are high-true; a high voltage is a logic one and a low voltage is logic zero.
b. All RSL signals are low-true; a low voltage is a logic one and a high voltage is logic zero.
Page 3
Rev. 0.9 Apr. 1999
Preliminary
KM416RD8C/KM418RD8C
Direct RDRAM™
RQ7..RQ5 or
ROW2..ROW0
3
RQ4..RQ0 or
CTM CTMN SCK,CMD SIO0,SIO1 CFM CFMN
COL4..COL0
DQA8..DQA0
DQB8..DQB0
9
2
5
9
2
RCLK
RCLK
1:8 Demux
1:8 Demux
TCLK
RCLK
6
Control Registers
Packet Decode
Packet Decode
COLC
ROWR
11
ROWA
9
COLX
COLM
5
5
5
5
5
5
5
6
8
8
ROP DR BR
AV
R
REFR Power Modes DEVID
XOP DX BX COP DC BC
C
MB MA
M
S
Match
Mux
Match
Match
Write
Buffer
DM
Row Decode
XOP Decode
PREX
PRER
ACT
Mux
Mux
Column Decode & Mask
PREC
RD, WR
DRAM Core
512x64x144
Sense Amp
32x72
32x72
32x72
72
Internal DQB Data Path
72
Internal DQA Data Path
72
Bank 0
Bank 1
Bank 2
72
9
9
9
9
Bank 13
Bank 14
Bank 15
9
9
Bank 16
Bank 17
Bank 18
9
9
9
9
Bank 29
Bank 30
Bank 31
Figure 2: 128/144 Mbit Direct RDRAM Block Diagram
Page 4
Rev. 0.9 Apr. 1999
Preliminary
Direct RDRAM
™
KM416RD8C/KM418RD8C
24-bit ROWA (row-activate) or ROWR (row-operation)
packet.
General Description
Figure 2 is a block diagram of the 128/144 Mbit Direct
RDRAM. It consists of two major blocks: a “ core” block
built from banks and sense amps similar to those found in
other types of DRAM, and a Direct Rambus interface block
which permits an external controller to access this core at up
to 1.6GB/s.
COL Pins: The principle use of these five pins is to
manage the transfer of data between the DQA/DQB pins and
the sense amps of the RDRAM. These pins are de-multi-
plexed into a 23-bit COLC (column-operation) packet and
either a 17-bit COLM (mask) packet or a 17-bit COLX
(extended-operation) packet.
Control Registers: The CMD, SCK, SIO0, and SIO1
pins appear in the upper center of Figure 2. They are used to
write and read a block of control registers. These registers
supply the RDRAM configuration information to a
controller and they select the operating modes of the device.
The nine bit REFR value is used for tracking the last
refreshed row. Most importantly, the five bit DEVID speci-
fies the device address of the RDRAM on the Channel.
ACT Command: An ACT (activate) command from an
ROWA packet causes one of the 512 rows of the selected
bank to be loaded to its associated sense amps (two 256 byte
sense amps for DQA and two for DQB).
PRER Command: A PRER (precharge) command from
an ROWR packet causes the selected bank to release its two
associated sense amps, permitting a different row in that
bank to be activated, or permitting adjacent banks to be acti-
vated.
Clocking: The CTM and CTMN pins (Clock-To-Master)
generate TCLK (Transmit Clock), the internal clock used to
transmit read data. The CFM and CFMN pins (Clock-From-
Master) generate RCLK (Receive Clock), the internal clock
signal used to receive write data and to receive the ROW and
COL pins.
RD Command: The RD (read) command causes one of
the 64 dualocts of one of the sense amps to be transmitted on
the DQA/DQB pins of the Channel.
WR Command: The WR (write) command causes a
dualoct received from the DQA/DQB data pins of the
Channel to be loaded into the write buffer. There is also
space in the write buffer for the BC bank address and C
column address information. The data in the write buffer is
automatically retired (written with optional bytemask) to one
of the 64 dualocts of one of the sense amps during a subse-
quent COP command. A retire can take place during a RD,
WR, or NOCOP to another device, or during a WR or
NOCOP to the same device. The write buffer will not retire
during a RD to the same device. The write buffer reduces the
delay needed for the internal DQA/DQB data path turn-
around.
DQA,DQB Pins: These 18 pins carry read (Q) and write
(D) data across the Channel. They are multiplexed/de-multi-
plexed from/to two 72-bit data paths (running at one-eighth
the data frequency) inside the RDRAM.
Banks: The 16Mbyte core of the RDRAM is divided into
sixteen 0.5Mbyte banks, each organized as 512 rows, with
each row containing 64 dualocts, and each dualoct
containing 16 bytes. A dualoct is the smallest unit of data
that can be addressed.
Sense Amps: The RDRAM contains two sets of 17 sense
amps. Each sense amp consists of 512 bytes of fast storage
(256 for DQA and 256 for DQB) and can hold one-half of
one row of one bank of the RDRAM. The sense amp may
hold any of the 512 half-rows of an associated bank.
However, each sense amp is shared between two adjacent
banks of the RDRAM (except for numbers 0, 15, 16, and
31). This introduces the restriction that adjacent banks may
not be simultaneously accessed.
PREC Precharge: The NOP, RDA and WRA
commands are similar to PREC, RD and WR, except that a
precharge operation is scheduled at the end of the data
transfer. These commands provide a second mechanism for
performing precharge.
PREX Precharge: After a RD command, or after a WR
command with no byte masking (M=0), a COLX packet may
be used to specify an extended operation (XOP). The most
important XOP command is PREX. This command provides
a third mechanism for performing precharge.
RQ Pins: These pins carry control and address informa-
tion. They are broken into two groups. RQ7..RQ5 are also
called ROW2..ROW0, and are used primarily for controlling
row accesses. RQ4..RQ0 are also called COL4..COL0, and
are used primarily for controlling column accesses.
ROW Pins: The principle use of these three pins is to
manage the transfer of data between the banks and the sense
amps of the RDRAM. These pins are de-multiplexed into a
Page 5
Rev. 0.9 Apr. 1999
Preliminary
Direct RDRAM
™
KM416RD8C/KM418RD8C
The AV (ROWA/ROWR packet selection) bit distinguishes
between the two packet types. Both the ROWA and ROWR
packet provide a five bit device address and a five bit bank
address. An ROWA packet uses the remaining bits to
specify a nine bit row address, and the ROWR packet uses
the remaining bits for an eleven bit opcode field. Note the
use of the “ RsvX” notation to reserve bits for future address
field extension.
Packet Format
Figure 3 shows the formats of the ROWA and ROWR
packets on the ROW pins. Table 4 describes the fields which
comprise these packets. DR4T and DR4F bits are encoded to
contain both the DR4 device address bit and a framing bit
which allows the ROWA or ROWR packet to be recognized
by the RDRAM.
Table 4: Field Description for ROWA Packet and ROWR Packet
Description
Field
DR4T,DR4F
DR3..DR0
BR4..BR0
AV
Bits for framing (recognizing) a ROWA or ROWR packet. Also encodes highest device address bit.
Device address for ROWA or ROWR packet.
Bank address for ROWA or ROWR packet. RsvB denotes bits ignored by the RDRAM.
Selects between ROWA packet (AV=1) and ROWR packet (AV=0).
R8..R0
Row address for ROWA packet. RsvR denotes bits reserved for future row address extension.
Opcode field for ROWR packet. Specifies precharge, refresh, and power management functions.
ROP10..ROP0
Figure 3 also shows the formats of the COLC, COLM, and
COLX packets on the COL pins. Table 5 describes the fields
which comprise these packets.
The remaining 17 bits are interpreted as a COLM (M=1) or
COLX (M=0) packet. A COLM packet is used for a COLC
write command which needs bytemask control. The COLM
packet is associated with the COLC packet from a time t
RTR
The COLC packet uses the S (Start) bit for framing. A
COLM or COLX packet is aligned with this COLC packet,
and is also framed by the S bit.
earlier. An COLX packet may be used to specify an indepen-
dent precharge command. It contains a five bit device
address, a five bit bank address, and a five bit opcode. The
COLX packet may also be used to specify some house-
keeping and power management commands. The COLX
packet is framed within a COLC packet but is not otherwise
associated with any other packet.
The 23 bit COLC packet has a five bit device address, a five
bit bank address, a six bit column address, and a four bit
opcode. The COLC packet specifies a read or write
command, as well as some power management commands.
Table 5: Field Description for COLC Packet, COLM Packet, and COLX Packet
Description
Field
S
Bit for framing (recognizing) a COLC packet, and indirectly for framing COLM and COLX packets.
Device address for COLC packet.
DC4..DC0
BC4..BC0
C5..C0
Bank address for COLC packet. RsvB denotes bits reserved for future extension (controller drives 0’s).
Column address for COLC packet. RsvC denotes bits ignored by the RDRAM.
Opcode field for COLC packet. Specifies read, write, precharge, and power management functions.
Selects between COLM packet (M=1) and COLX packet (M=0).
COP3..COP0
M
MA7..MA0
MB7..MB0
DX4..DX0
BX4..BX0
XOP4..XOP0
Bytemask write control bits. 1=write, 0=no-write. MA0 controls the earliest byte on DQA8..0.
Bytemask write control bits. 1=write, 0=no-write. MB0 controls the earliest byte on DQB8..0.
Device address for COLX packet.
Bank address for COLX packet. RsvB denotes bits reserved for future extension (controller drives 0’s).
Opcode field for COLX packet. Specifies precharge, I control, and power management functions.
OL
Page 6
Rev. 0.9 Apr. 1999
Preliminary
Direct RDRAM
™
KM416RD8C/KM418RD8C
T0
T1
T2
T3
T8
T9
T10
T11
CTM/CFM
CTM/CFM
ROW2 DR4T DR2 BR0 BR3 RsvR R8
R5
R4
R3
R2
R1
R0
ROW2 DR4T DR2 BR0 BR3 ROP10 ROP8 ROP5 ROP2
ROW1
ROW0 DR3
DR1 BR1 BR4 RsvR R7
DR0 BR2 RsvB AV=1 R6
ROW1
ROW0 DR3
DR1 BR1 BR4 ROP9 ROP7 ROP4 ROP1
DR0 BR2 RsvB AV=0 ROP6 ROP3 ROP0
DR4F
DR4F
ROWA Packet
ROWR Packet
T0
T1
T2
T3
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15
CTM/CFM
CTM/CFM
ROW2
..ROW0
S=1
RsvC C4
ACT a0
WR b1
PRER c0
DC4
DC3
COL4
COL3
COL2
COL1
COL0
t
PACKET
MSK (b1) PREX d0
C5
C3
COL4
..COL0
DC2 COP1
RsvB BC2 C2
BC4 BC1 C1
DQA8..0
DQB8..0
COP0
COP2
DC1
DC0
COP3 BC3 BC0 C0
COLC Packet
T8
T9
T10
T11
T12
T13
T14
T15
CTM/CFM
CTM/CFM
S=1a MA7 MA5 MA3 MA1
M=1 MA6 MA4 MA2 MA0
MB7 MB4 MB1
S=1b DX4 XOP4 RsvB BX1
M=0 DX3 XOP3 BX4 BX0
DX2 XOP2 BX3
COL4
COL3
COL2
COL1
COL4
COL3
COL2
COL1
COL0
MB6 MB3 MB0
DX1 XOP1 BX2
COL0
MB5 MB2
DX0 XOP0
b
a
The COLX is aligned
The COLM is associated with a
previous COLC, and is aligned
with the present COLC, indicated
by the Start bit (S=1) position.
with the present COLC,
indicated by the Start
bit (S=1) position.
COLM Packet
COLX Packet
Figure 3: Packet Formats
Page 7
Rev. 0.9 Apr. 1999
Preliminary
Direct RDRAM
™
KM416RD8C/KM418RD8C
broadcast operation is indicated when both bits are set.
Field Encoding Summary
Broadcast operation would typically be used for refresh and
power management commands. If the device is selected, the
DM (DeviceMatch) signal is asserted and an ACT or ROP
command is performed.
Table 6 shows how the six device address bits are decoded
for the ROWA and ROWR packets. The DR4T and DR4F
encoding merges a fifth device bit with a framing bit. When
neither bit is asserted, the device is not selected. Note that a
Table 6: Device Field Encodings for ROWA Packet and ROWR Packet
DR4T
DR4F
Device Selection
Device Match signal (DM)
1
0
1
0
1
1
0
0
All devices (broadcast)
One device selected
One device selected
No packet present
DM is set to 1
DM is set to 1 if {DEVID4..DEVID0} == {0,DR3..DR0} else DM is set to 0
DM is set to 1 if {DEVID4..DEVID0} == {1,DR3..DR0} else DM is set to 0
DM is set to 0
Table 7 shows the encodings of the remaining fields of the
ROWA and ROWR packets. An ROWA packet is specified
by asserting the AV bit. This causes the specified row of the
specified bank of this device to be loaded into the associated
sense amps.
row address comes from an internal register REFR, and
REFR is incremented at the largest bank address. The REFP
(refresh-precharge) command is identical to a PRER
command.
The NAPR, NAPRC, PDNR, ATTN, and RLXR commands
are used for managing the power dissipation of the RDRAM
and are described in more detail in “ Power state manage-
ment ” on page 38. The TCEN and TCAL commands are
used to adjust the output driver slew rate and they are
described in more detail in “Current and Temperature
Control” on page 43.
An ROWR packet is specified when AV is not asserted. An
11 bit opcode field encodes a command for one of the banks
of this device. The PRER command causes a bank and its
two associated sense amps to precharge, so another row or
an adjacent bank may be activated. The REFA (refresh-acti-
vate) command is similar to the ACT command, except the
Table 7: ROWA Packet and ROWR Packet Field Encodings
ROP10..ROP0 Field
Command Description
DMa AV
Name
10
9
8
7
6
5
4
3
2:0
0
1
1
1
-
-
-
-
-
-
-
-
-
---
-
No operation.
1
0
0
Row address
ACT
Activate row R8..R0 of bank BR4..BR0 of device and move device to ATTNb.
1
0
1
0
0
0
0
1
0
1
xc
0
x
0
x
x
000 PRER
000 REFA
Precharge bank BR4..BR0 of this device.
Refresh (activate) row REFR8..REFR0 of bank BR4..BR0 of device.
Increment REFR if BR4..BR0 = 1111 (see Figure 50).
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
1
x
x
x
x
x
0
0
0
0
x
x
x
x
x
0
0
0
1
0
0
0
x
x
0
0
0
0
0
0
0
x
x
0
0
0
1
0
0
0
x
x
0
0
0
0
0
1
1
x
x
0
0
0
0
1
0
1
x
x
0
0
0
x
x
x
x
0
1
x
x
0
000 REFP
000 PDNR
000 NAPR
Precharge bank BR4..BR0 of this device after REFA (see Figure 50).
Move this device into the powerdown (PDN) power state (see Figure 47).
Move this device into the nap (NAP) power state (see Figure 47).
000 NAPRC Move this device into the nap (NAP) power state conditionally
000 ATTNb
000 RLXR
001 TCAL
010 TCEN
Move this device into the attention (ATTN) power state (see Figure 45).
Move this device into the standby (STBY) power state (see Figure 46).
Temperature calibrate this device (see Figure 52).
Temperature calibrate/enable this device (see Figure 52).
000 NOROP No operation.
a. The DM (Device Match signal) value is determined by the DR4T,DR4F, DR3..DR0 field of the ROWA and ROWR packets. See Table 6.
b. The ATTN command does not cause a RLX-to-ATTN transition for a broadcast operation (DR4T/DR4F=1/1).
c. An “ x ” entry indicates which commands may be combined. For instance, the three commands PRER/NAPRC/RLXR may be specified in one ROP value (011000111000).
Page 8
Rev. 0.9 Apr. 1999
Preliminary
Direct RDRAM
™
KM416RD8C/KM418RD8C
Table 8 shows the COP field encoding. The device must be
in the ATTN power state in order to receive COLC packets.
The COLC packet is used primarily to specify RD (read) and
WR (write) commands. Retire operations (moving data from
the write buffer to a sense amp) happen automatically. See
Figure 17 for a more detailed description.
The COLC packet can also specify a PREC command,
which precharges a bank and its associated sense amps. The
RDA/WRA commands are equivalent to combining RD/WR
with a PREC. RLXC (relax) performs a power mode transi-
tion. See “ Power State Management ” on page 38.
Table 8: COLC Packet Field Encodings
S
DC4.. DC0
COP3..0 Name
Command Description
(select device)a
0
1
1
1
1
1
1
1
1
1
1
----
-----
-
-
No operation.
/= (DEVID4 ..0)
== (DEVID4 ..0)
== (DEVID4 ..0)
== (DEVID4 ..0)
== (DEVID4 ..0)
== (DEVID4 ..0)
== (DEVID4 ..0)
== (DEVID4 ..0)
== (DEVID4 ..0)
== (DEVID4 ..0)
-----
Retire write buffer of this device.
x000b
x001
x010
x011
x100
x101
x110
x111
1xxx
NOCOP Retire write buffer of this device.
WR
Retire write buffer of this device, then write column C5..C0 of bank BC4..BC0 to write buffer.
RSRV
RD
Reserved, no operation.
Read column C5..C0 of bank BC4..BC0 of this device.
Retire write buffer of this device, then precharge bank BC4..BC0 (see Figure 14).
Same as WR, but precharge bank BC4..BC0 after write buffer (with new data) is retired.
Reserved, no operation.
PREC
WRA
RSRV
RDA
RLXC
Same as RD, but precharge bank BC4..BC0 afterward.
Move this device into the standby (STBY) power state (see Figure 46).
a. “ /= ” means not equal, “ == ” means equal.
b. An “ x ” entry indicates which commands may be combined. For instance, the two commands WR/RLXC may be specified in one COP value (1001).
Table 9 shows the COLM and COLX field encodings. The
M bit is asserted to specify a COLM packet with two 8 bit
bytemask fields MA and MB. If the M bit is not asserted, an
COLX is specified. It has device and bank address fields,
and an opcode field. The primary use of the COLX packet is
to permit an independent PREX (precharge) command to be
specified without consuming control bandwidth on the ROW
pins. It is also used for the CAL(calibrate) and SAM
(sample) current control commands (see “Current and
Temperature Control” on page 43), and for the RLXX power
mode command (see “Power State Management” on page
38).
Table 9: COLM Packet and COLX Packet Field Encodings
DX4 .. DX0
(selects device)
M
XOP4..0
Name
Command Description
1
0
0
0
0
0
0
0
----
-
MSK
MB/MA bytemasks used by WR/WRA.
/= (DEVID4 ..0)
== (DEVID4 ..0)
== (DEVID4 ..0)
== (DEVID4 ..0)
== (DEVID4 ..0)
== (DEVID4 ..0)
== (DEVID4 ..0)
-
-
No operation.
00000
1xxx0a
x10x0
x11x0
xxx10
xxxx1
NOXOP
PREX
CAL
No operation.
Precharge bank BX4..BX0 of this device (see Figure 14).
Calibrate (drive) IOL current for this device (see Figure 51).
Calibrate (drive) and Sample ( update) IOL current for this device (see Figure 51).
Move this device into the standby (STBY) power state (see Figure 46).
Reserved, no operation.
CAL/SAM
RLXX
RSRV
a. An “x” entry indicates which commands may be combined. For instance, the two commands PREX/RLXX may be specified in one XOP value (10010).
Page 9
Rev. 0.9 Apr. 1999
Preliminary
Direct RDRAM
™
KM416RD8C/KM418RD8C
A WR or WRA command will receive a dualoct of write
DQ Packet Timing
data D a time t
later. This time does not need to include
CWD
Figure 4 shows the timing relationship of COLC packets
with D and Q data packets. This document uses a specific
convention for measuring time intervals between packets: all
packets on the ROW and COL pins (ROWA, ROWR,
COLC, COLM, COLX) use the trailing edge of the packet as
a reference point, and all packets on the DQA/DQB pins (D
and Q) use the leading edge of the packet as a reference
point.
the round-trip propagation time of the Channel since the
COLC and D packets are traveling in the same direction.
When a Q packet follows a D packet (shown in the left half
of the figure), a gap (t
between them because the t
-t
) will automatically appear
value is always less than the
CAC CWD
CWD
t
value. There will be no gap between the two COLC
CAC
packets with the WR and RD commands which schedule the
D and Q packets.
An RD or RDA command will transmit a dualoct of read
When a D packet follows a Q packet (shown in the right half
of the figure), no gap is needed between them because the
data Q a time t
later. This time includes one to five
CAC
cycles of round-trip propagation delay on the Channel. The
parameter may be programmed to a one of a range of
t
t
value is less than the t
value. However, , a gap of
CAC
CWD
t
CAC
-t
or greater must be inserted between the COLC
CAC CWD
values ( 8, 9, 10, 11, or 12 t
). The value chosen
CYCLE
packets with the RD WR commands by the controller so the
Q and D packets do not overlap.
depends upon the number of RDRAM devices on the
Channel and the RDRAM timing bin. See Figure 39 for
more information.
T
T1 T2 T3 T T5 T6 T7 T T9 T10 T11 T T13 T14 T15 T T17 T18 T19 T T21 T22 T25 T26 T27 T T29 T30 T31 T T33 T34 T35 T T37 T38 T39 T T41 T42 T43 T T45 T46 T47
4 8 12 16 20 24 28 32 36 40 44
0
CTM/CFM
This gap on the DQA/DQB pins appears automatically
This gap on the COL pins must be inserted by the controller
t
-t
ROW2
..ROW0
CAC CWD
t
-t
CAC CWD
WR d1
W
W
W
W
• • •
t
t
CWD
• • •
CWD
RD b1
COL4
WR a1
RD c1
• • •
..COL0
Q (b1)
Q (c1)
D (d1)
D (a1)
DQA8..0
DQB8..0
• • •
• • •
t
CAC
t
CAC
= 8, 9, 10, 11, or 12 t
CYCLE
Figure 4: Read (Q) and Write (D) Data Packet - Timing for t
CAC
housekeeping command (this case is not shown). The M bit
is not asserted in an COLX packet and causes all 16 bytes of
the previous WR to be written unconditionally. Note that a
RD command will never need a COLM packet, and will
always be able to use the COLX packet option (a read opera-
tion has no need for the byte-write-enable control bits).
COLM Packet to D Packet Mapping
Figure 5 shows a write operation initiated by a WR
command in a COLC packet. If a subset of the 16 bytes of
write data are to be written, then a COLM packet is trans-
mitted on the COL pins a time t
after the COLC packet
RTR
containing the WR command. The M bit of the COLM
packet is set to indicate that it contains the MA and MB
mask fields. Note that this COLM packet is aligned with the
COLC packet which causes the write buffer to be retired.
See Figure 17 for more details.
Figure 5 also shows the mapping between the MA and MB
fields of the COLM packet and bytes of the D packet on the
DQA and DQB pins. Each mask bit controls whether a byte
of data is written (=1) or not written (=0).
If all 16 bytes of the D data packet are to be written, then no
further control information is required. The packet slot that
would have been used by the COLM packet (t
after the
RTR
COLC packet) is available to be used as an COLX packet.
This could be used for a PREX precharge command or for a
Page 10
Rev. 0.9 Apr. 1999
Preliminary
Direct RDRAM
™
KM416RD8C/KM418RD8C
T
T1 T2 T3 T T5 T6 T7 T T9 T10 T11 T T13 T14 T15 T T17 T18 T19 T T21 T22 T23 T T25 T26 T27 T T29 T30 T31 T T33 T34 T35 T T37 T38 T39 T T41 T42 T43 T T45 T46 T47
4 8 12 16 20 24 28 32 36 40 44
0
CTM/CFM
ROW2
ACT a0
PRER a2
ACT b0
..ROW0
t
RTR
COL4
..COL0
WR a1
retire (a1)
MSK (a1)
t
CWD
D (a1)
DQA8..0
DQB8..0
Transaction a: WR
a0 = {Da,Ba,Ra}
a1 = {Da,Ba,Ca1}
a3 = {Da,Ba}
COLM Packet
D Packet
T17
T18
T19
T20
T19
T20
T21
T22
CTM/CFM
CTM/CFM
MA7 MA5 MA3 MA1
COL4
COL3
COL2
COL1
COL0
DB17 DB26 DB35 DB45 DB53 DB62 DB71
DB16 DB25 DB34 DB44 DB52 DB61 DB70
DQB8
DQB7
DB8
DB7
M=1 MA6 MA4 MA2 MA0
MB7 MB4 MB1
MB6 MB3 MB0
MB5 MB2
DQB1
DQB0
DB10 DB19 DB28 DB37 DB46 DB55 DB64
DB9 DB18 DB27 DB36 DB45 DB54 DB63
DB1
DB0
MB0 MB1 MB2 MB3 MB4 MB5 MB6 MB7
DA8 DA17 DA26 DA35 DA45 DA53 DA62 DA71
Each bit of the MB7..MB0 field
controls writing (=1) or no writing
(=0) of the indicated DB bits when
the M bit of the COLM packet is one.
When M=1, the MA and MB
fields control writing of
individual data bytes.
When M=0, all data bytes are
written unconditionally.
DQA8
DQA7
DA16 DA25 DA34 DA44 DA52 DA61 DA70
DA7
DQA1
DQA0
DA10 DA19 DA28 DA37 DA46 DA55 DA64
DA9 DA18 DA27 DA36 DA45 DA54 DA63
DA1
DA0
Each bit of the MA7..MA0 field
controls writing (=1) or no writing
(=0) of the indicated DA bits when
the M bit of the COLM packet is one.
MA0 MA1 MA2 MA3 MA4 MA5 MA6 MA7
Figure 5: Mapping Between COLM Packet and D Packet for WR Command
Page 11
Rev. 0.9 Apr. 1999
Preliminary
Direct RDRAM
™
KM416RD8C/KM418RD8C
Cases RR1 through RR4 show two successive ACT
commands. In case RR1, there is no restriction since the
ACT commands are to different devices. In case RR2, the
ROW-to-ROW Packet Interaction
T
T1 T2 T3
T
T5 T6 T7
T
T9 T10 T11
T
T13 T14 T15 T T17 T18 T19
16
t
restriction applies to the same device with non-adjacent
0
4
8
12
RR
banks. Cases RR3 and RR4 are illegal (as shown) since bank
Ba needs to be precharged. If a PRER to Ba, Ba+1, or Ba-1
CTM/CFM
t
is inserted, t
is t (t
to the PRER command,
RRDELAY
RRDELAY
RC RAS
ROW2
..ROW0
ROPa a0
ROPb b0
and t to the next ACT).
RP
Cases RR5 through RR8 show an ACT command followed
by a PRER command. In cases RR5 and RR6, there are no
restrictions since the commands are to different devices or to
non-adjacent banks of the same device. In cases RR7 and
COL4
..COL0
RR8, the t
before it can be precharged.
restriction means the activated bank must wait
RAS
DQA8..0
DQB8..0
Transaction a: ROPa
Transaction b: ROPb
a0 = {Da,Ba,Ra}
b0= {Db,Bb,Rb}
Cases RR9 through RR12 show a PRER command followed
by an ACT command. In cases RR9 and RR10, there are
essentially no restrictions since the commands are to
different devices or to non-adjacent banks of the same
device. RR10a and RR10b depend upon whether a bracketed
bank (Ba+-1) is precharged or activated. In cases RR11 and
Figure 6: ROW-to-ROW Packet Interaction- Timing
Figure 6 shows two packets on the ROW pins separated by
an interval t
which depends upon the packet
RRDELAY
contents. No other ROW packets are sent to banks
RR12, the same and adjacent banks must all wait t for the
RP
{Ba,Ba+1,Ba-1} between packet “a” and packet “b” unless
sense amp and bank to precharge before being activated.
noted otherwise. Table 10 summarizes the t
for all possible cases.
values
RRDELAY
Table 10: ROW-to-ROW Packet Interaction - Rules
Case # ROPa Da
Ba
Ra
ROPb Db
Bb
Rb
tRRDELAY
Example
RR1
RR2
RR3
RR4
RR5
RR6
RR7
RR8
RR9
RR10
ACT
ACT
ACT
ACT
ACT
ACT
ACT
ACT
Da
Da
Da
Da
Da
Da
Da
Da
Ba
Ba
Ba
Ba
Ba
Ba
Ba
Ba
Ba
Ba
Ba
Ba
Ba
Ba
Ba
Ba
Ba
Ba
Ra
Ra
Ra
Ra
Ra
Ra
Ra
Ra
Ra
Ra
Ra
Ra
Ra
Ra
Ra
Ra
Ra
Ra
ACT
ACT
ACT
ACT
/= Da
xxxx
x..x tPACKET
Figure 11
Figure 11
Figure 10
Figure 10
Figure 11
Figure 11
Figure 10
Figure 15
Figure 12
Figure 12
== Da /= {Ba,Ba+1,Ba-1}
== Da == {Ba+1,Ba-1}
== Da == {Ba}
x..x tRR
x..x tRC - illegal unless PRER to Ba/Ba+1/Ba-1
x..x tRC - illegal unless PRER to Ba/Ba+1/Ba-1
PRER /= Da
xxxx
x..x tPACKET
x..x tPACKET
x..x tRAS
PRER == Da /= {Ba,Ba+1,Ba-1}
PRER == Da == { Ba+1,Ba-1}
PRER == Da == {Ba}
x..x tRAS
PRER Da
PRER Da
ACT
ACT
ACT
ACT
ACT
ACT
/= Da
xxxx
x..x tPACKET
== Da /= {Ba,Ba+-1,Ba+-2} x..x tPACKET
RR10a PRER Da
RR10b PRER Da
== Da == {Ba+2}
== Da == {Ba-2}
== Da == {Ba+1,Ba-1}
== Da == {Ba}
x..x tPACKET/tRP if Ba+1 is precharged/activated.
x..x tPACKET/tRP if Ba-1 is precharged/activated.
RR11
RR12
RR13
RR14
RR15
RR16
PRER Da
PRER Da
PRER Da
PRER Da
PRER Da
PRER Da
x..x tRP
x..x tRP
x..x tPACKET
x..x tPP
Figure 10
Figure 10
Figure 12
Figure 12
Figure 12
Figure 12
PRER /= Da
xxxx
PRER == Da /= {Ba,Ba+1,Ba-1}
PRER == Da == {Ba+1,Ba-1}
PRER == Da == Ba
x..x tPP
x..x tPP
Page 12
Rev. 0.9 Apr. 1999
Preliminary
Direct RDRAM
™
KM416RD8C/KM418RD8C
Cases RC1 through RC5 summarize the rules when the
ROW packet has an ACT command. Figure 15 and
ROW-to-ROW Interaction - contin-
ued
Figure 16 show examples of RC5 - an activation followed by
a read or write. RC4 is an illegal situation, since a read or
write of a precharged banks is being attempted (remember
that for a bank to be activated, adjacent banks must be
precharged). In cases RC1, RC2, and RC3, there is no inter-
action of the ROW and COL packets.
Cases RR13 through RR16 summarize the combinations of
two successive PRER commands. In case RR13 there is no
restriction since two devices are addressed. In RR14, t
PP
applies, since the same device is addressed. In RR15 and
RR16, the same bank or an adjacent bank may be given
repeated PRER commands with only the t restriction.
PP
T
T1 T2 T3 T T5 T6 T7 T8 T9 T10 T11 T T13 T14 T15 T T17 T18 T19 T
4 12 16
0
Two adjacent banks can’t be activate simultaneously. A
precharge command to one bank will thus affect the state of
the adjacent banks (and sense amps). If bank Ba is activate
and a PRER is directed to Ba, then bank Ba will be
precharged along with sense amps Ba-1/Ba and Ba/Ba+1. If
bank Ba+1 is activate and a PRER is directed to Ba, then
bank Ba+1 will be precharged along with sense amps
Ba/Ba+1 and Ba+1/Ba+2. If bank Ba-1 is activate and a
PRER is directed to Ba, then bank Ba-1 will be precharged
along with sense amps Ba/Ba-1 and Ba-1/Ba-2.
CTM/CFM
t
RCDELAY
ROW2
..ROW0
ROPa a0
COL4
..COL0
COPb b1
DQA8..0
DQB8..0
A ROW packet may contain commands other than ACT or
PRER. The REFA and REFP commands are equivalent to
ACT and PRER for interaction analysis purposes. The inter-
action rules of the NAPR, NAPRC, PDNR, RLXR, ATTN,
TCAL, and TCEN commands are discussed in later sections
(see Table 7 for cross-ref).
Transaction a: ROPa
Transaction b: COPb
a0 = {Da,Ba,Ra}
b1= {Db,Bb,Cb1}
Figure 7: ROW-to-COL Packet Interaction- Timing
Cases RC6 through RC8 summarize the rules when the
ROW packet has a PRER command. There is either no inter-
action (RC6 through RC9) or an illegal situation with a read
or write of a precharged bank (RC9).
ROW-to-COL Packet Interaction
Figure 7 shows two packets on the ROW and COL pins.
The COL pins can also schedule a precharge operation with
a RDA, WRA, or PREC command in a COLC packet or a
PREX command in a COLX packet. The constraints of these
precharge operations may be converted to equivalent PRER
command constraints using the rules summarized in
Figure 14.
They must be separated by an interval t
which
RCDELAY
depends upon the packet contents. Table 11 summarizes the
values for all possible cases. Note that if the COL
t
RCDELAY
packet is earlier than the ROW packet, it is considered a
COL-to-ROW packet interaction.
Table 11: ROW-to-COL Packet Interaction - Rules
Case # ROPa Da
Ba
Ra
COPb
NOCOP,RD,retire
Db
/= Da
Bb
Cb1 tRCDELAY
Example
RC1
RC2
RC3
RC4
RC5
RC6
RC7
RC8
RC9
ACT
ACT
ACT
ACT
ACT
Da
Da
Da
Da
Da
Ba
Ba
Ba
Ba
Ba
Ba
Ba
Ba
Ba
Ra
Ra
Ra
Ra
Ra
Ra
Ra
Ra
Ra
xxxx
xxxx
x..x
x..x
0
0
0
NOCOP
== Da
== Da
== Da
== Da
/= Da
RD,retire
RD,retire
RD,retire
NOCOP,RD,retire
NOCOP
/= {Ba,Ba+1,Ba-1} x..x
== {Ba+1,Ba-1}
== Ba
x..x Illegal
x..x tRCD
Figure 15
PRER Da
PRER Da
PRER Da
PRER Da
xxxx
x..x
x..x
0
0
0
== Da
== Da
== Da
xxxx
RD,retire
RD,retire
/= {Ba,Ba+1,Ba-1} x..x
== {Ba+1,Ba-1}
x..x Illegal
Page 13
Rev. 0.9 Apr. 1999
Preliminary
Direct RDRAM
™
KM416RD8C/KM418RD8C
CC2, CC4, and CC5, there is no restriction (t
is
CCDELAY
COL-to-COL Packet Interaction
t
).
CC
In cases CC6 through CC10, COPb is a WR command and
COPc is a RD command. The t value needed
T
T1 T2 T3 T T5 T6 T7 T T9 T10 T11 T T13 T14 T15 T T17 T18 T19
4 8 12 16
0
CCDELAY
between these two packets depends upon the command and
address in the packet with COPa. In particular, in case CC6
when there is WR-WR-RD command sequence directed to
the same device, a gap will be needed between the packets
with COPb and COPc. The gap will need a COLC packet
with a NOCOP command directed to any device in order to
force an automatic retire to take place. Figure 18 (right)
provides a more detailed explanation of this case.
CTM/CFM
ROW2
..ROW0
t
CCDELAY
COL4
..COL0
COPa a1 COPb b1
COPc c1
In case CC10, there is a RD-WR-RD sequence directed to
the same device. If a prior write to the same device is unre-
tired when COPa is issued, then a gap will be needed
between the packets with COPb and COPc as in case CC6.
The gap will need a COLC packet with a NOCOP command
directed to any device in order to force an automatic retire to
take place.
DQA8..0
DQB8..0
Transaction a: COPa
Transaction b: COPb
Transaction c: COPc
a1 = {Da,Ba,Ca1}
b1 = {Db,Bb,Cb1}
c1 = {Dc,Bc,Cc1}
Figure 8: COL-to-COL Packet Interaction- Timing
Figure 8 shows three arbitrary packets on the COL pins.
Packets “b” and “ c” must be separated by an interval
Cases CC7, CC8, and CC9 have no restriction (t
is
CCDELAY
t
).
CC
t
which depends upon the command and address
CCDELAY
For the purposes of analyzing COL-to-ROW interactions,
values in all three packets. Table 12 summarizes the
values for all possible cases.
the PREC, WRA, and RDA commands of the COLC packet
are equivalent to the NOCOP, WR, and RD commands.
These commands also cause a precharge operation PREC to
take place. This precharge may be converted to an equiva-
lent PRER command on the ROW pins using the rules
summarized in Figure 14.
t
CCDELAY
Cases CC1 through CC5 summarize the rules for every situ-
ation other than the case when COPb is a WR command and
COPc is a RD command. In CC3, when a RD command is
followed by a WR command, a gap of t
-t
must be
CAC CWD
inserted between the two COL packets. See Figure 4 for
more explanation of why this gap is needed. For cases CC1,
Table 12: COL-to-COL Packet Interaction - Rules
Case # COPa
Da
Ba
Ca1 COPb
Db
Bb
Cb1 COPc
Dc
Bc
Cc1 tCCDELAY
Example
CC1
CC2
CC3
CC4
CC5
CC6
CC7
CC8
CC9
CC10
xxxx
xxxx
xxxx
xxxx
xxxx
WR
xxxxx x..x x..x NOCOP
xxxxx x..x x..x RD,WR
xxxxx x..x x..x RD
xxxxx x..x x..x RD
xxxxx x..x x..x WR
Db
Db
Db
Db
Db
Db
Db
Db
Db
Db
Bb
Bb
Bb
Bb
Bb
Bb
Bb
Bb
Bb
Bb
Cb1 xxxx
Cb1 NOCOP
Cb1 WR
Cb1 RD
Cb1 WR
Cb1 RD
Cb1 RD
Cb1 RD
Cb1 RD
Cb1 RD
xxxxx x..x
xxxxx x..x
xxxxx x..x
xxxxx x..x
xxxxx x..x
== Db x..x
x..x tCC
x..x tCC
x..x tCC+tCAC -tCWD
x..x tCC
Figure 4
Figure 15
Figure 16
Figure 18
x..x tCC
== Db
== Db
/= Db
x
x
x
x
x
x..x WR
x..x WR
x..x WR
x..x WR
x..x WR
x..x tRTR
x..x tCC
WR
/= Db
x..x
WR
== Db x..x
== Db x..x
== Db x..x
x..x tCC
NOCOP == Db
RD == Db
x..x tCC
x..x tCC
Page 14
Rev. 0.9 Apr. 1999
Preliminary
Direct RDRAM
™
KM416RD8C/KM418RD8C
Case CR4 is illegal because an already-activated bank is to
be re-activated without being precharged Case CR5 is illegal
because an adjacent bank can’t be activated or precharged
until bank Ba is precharged first.
COL-to-ROW Packet Interaction
T
T1 T2 T3 T T5 T6 T7 T T9 T10 T11 T T13 T14 T15 T T17 T18 T19
4 8 12 16
0
In case CR6, the COLC packet contains a RD command, and
the ROW packet contains a PRER command for the same
CTM/CFM
t
CRDELAY
bank. The t
parameter specifies the required spacing.
RDP
ROW2
..ROW0
ROPb b0
Likewise, in case CR7, the COLC packet causes an auto-
matic retire to take place, and the ROW packet contains a
PRER command for the same bank. The t
specifies the required spacing.
parameter
RTP
COL4
..COL0
COPa a1
Case CR8 is labeled “Hazardous” because a WR command
should always be followed by an automatic retire before a
precharge is scheduled. Figure 19 shows an example of what
can happen when the retire is not able to happen before the
precharge.
DQA8..0
DQB8..0
Transaction a: COPa
Transaction b: ROPb
a1= {Da,Ba,Ca1}
b0= {Db,Bb,Rb}
For the purposes of analyzing COL-to-ROW interactions,
the PREC, WRA, and RDA commands of the COLC packet
are equivalent to the NOCOP, WR, and RD commands.
These commands also cause a precharge operation to take
place. This precharge may converted to an equivalent PRER
command on the ROW pins using the rules summarized in
Figure 14.
Figure 9: COL-to-ROW Packet Interaction- Timing
Figure 9 shows arbitrary packets on the COL and ROW pins.
They must be separated by an interval t which
CRDELAY
depends upon the command and address values in the
packets. Table 13 summarizes the t
possible cases.
value for all
CRDELAY
A ROW packet may contain commands other than ACT or
PRER. The REFA and REFP commands are equivalent to
ACT and PRER for interaction analysis purposes. The inter-
action rules of the NAPR, PDNR, and RLXR commands are
discussed in a later section.
Cases CR1, CR2, CR3, and CR9 show no interaction
between the COL and ROW packets, either because one of
the commands is a NOP or because the packets are directed
to different devices or to non-adjacent banks.
Table 13: COL-to-ROW Packet Interaction - Rules
Db
Example
Case # COPa
Da
Ba
Ca1
ROPb
Bb
Rb
tCRDELAY
CR1
CR2
CR3
CR4
CR5
CR6
CR7
CR8
CR9
NOCOP
RD/WR
RD/WR
RD/WR
RD/WR
RD
Da
Da
Da
Da
Da
Da
Da
Da
Da
Ba
Ba
Ba
Ba
Ba
Ba
Ba
Ba
Ba
Ca1
Ca1
Ca1
Ca1
Ca1
Ca1
Ca1
Ca1
Ca1
x..x
xxxxx
/= Da
xxxx
xxxx
x..x
x..x
0
x..x
0
x..x
== Da
== Da
== Da
== Da
== Da
== Da
xxxxx
/= {Ba,Ba+1,Ba-1} x..x
0
ACT
ACT
PRER
PRER
PRER
NOROP
== {Ba}
x..x
x..x
Illegal
Illegal
tRDP
tRTP
0
== {Ba+1,Ba-1}
== {Ba,Ba+1,Ba-1} x..x
== {Ba,Ba+1,Ba-1} x..x
== {Ba,Ba+1,Ba-1} x..x
Figure 15
Figure 16
Figure 19
retirea
WRb
xxxx
xxxx
x..x
0
a. This is any command which permits the write buffer of device Da to retire (see Table 8). “Ba” is the bank address in the write buffer.
b. This situation is hazardous because the write buffer will be left unretired while the targeted bank is precharged. See Figure 19.
Page 15
Rev. 0.9 Apr. 1999
Preliminary
Direct RDRAM
™
KM416RD8C/KM418RD8C
between ACT commands to the same bank must also satisfy
ROW-to-ROW Examples
the t timing parameter (RR4).
RC
Figure 10 shows examples of some of the ROW-to-ROW
packet spacings from Table 10. A complete sequence of acti-
vate and precharge commands is directed to a bank. The
RR8 and RR12 rules apply to this sequence. In addition to
When a bank is activated, it is necessary for adjacent banks
to remain precharged. As a result, the adjacent banks will
also satisfy parallel timing constraints; in the example, the
RR11 and RR3 rules are analogous to the RR12 and RR4
rules.
satisfying the t
and t timing parameters, the separation
RP
RAS
a0 = {Da,Ba,Ra}
a1 = {Da,Ba+1}
b0 = {Da,Ba+1,Rb}
b0 = {Da,Ba,Rb}
b0 = {Da,Ba+1,Rb}
b0 = {Da,Ba,Rb}
Same Device
Same Device
Same Device
Same Device
Same Device
Adjacent Bank
Adjacent Bank
Same Bank
Adjacent Bank
Same Bank
RR7
RR3
RR4
RR11
RR12
T
T1 T2 T3
T
T5 T6 T7
T
T9 T10 T11
T
T13 T14 T15
T
T17 T18 T19
T
T21 T22 T23
T
T25 T26 T27
T
T29 T30 T31 T T33 T34 T35 T T37 T38 T39 T T41 T42 T43 T T45 T46 T47
32 36 40 44
0
4
8
12
16
20
24
28
CTM/CFM
ROW2
ACT a0
PRER a1
ACT b0
..ROW0
COL4
..COL0
t
t
RAS
RP
DQA8..0
DQB8..0
t
RC
Figure 10: Row Packet Example
Figure 11 shows examples of the ACT-to-ACT (RR1, RR2)
and ACT-to-PRER (RR5, RR6) command spacings from
Table 10. In general, the commands in ROW packets may be
the same or adjacent banks or unless they are a similar
command type (both PRER or both ACT) directed to the
same device.
spaced an interval t
apart unless they are directed to
PACKET
a0 = {Da,Ba,Ra}
Different Device
Same Device
Different Device
Same Device
Any Bank
Non-adjacent Bank RR2
Any Bank RR5
Non-adjacent Bank RR6
RR1
b0 = {Db,Bb,Rb}
c0 = {Da,Bc,Rc}
b0 = {Db,Bb,Rb}
c0 = {Da,Bc,Rc}
T
T1 T2 T3 T T5 T6 T7 T T11 T T13 T14 T15 T T17 T18 T19 T T21 T22 T23 T T27 T T29 T30 T31 T T33 T34 T35 T T39 T T41 T42 T43 T T45 T46 T47
4 8 12 16 20 24 28 32 36 40 44
0
CTM/CFM
ROW2
ACT a0
ACT b0
ACT a0
ACT c0
ACT a0 PRER b0
ACT a0
PRER c0
..ROW0
t
t
t
PACKET
PACKET
PACKET
t
RR
COL4
..COL0
DQA8..0
DQB8..0
Figure 11: Row Packet Example
Page 16
Rev. 0.9 Apr. 1999
Preliminary
Direct RDRAM
™
KM416RD8C/KM418RD8C
Figure 12 shows examples of the PRER-to-PRER (RR13,
RR14) and PRER-to-ACT (RR9, RR10) command spacings
from Table 10. The RR15 and RR16 cases (PRER-to-PRER
to same or adjacent banks) are not shown, but are similar to
RR14. In general, the commands in ROW packets may be
spaced an interval t
apart unless they are directed to
PACKET
the same or adjacent banks or unless they are a similar
command type (both PRER or both ACT) directed to the
same device.
a0 = {Da,Ba,Ra}
Different Device
Same Device
Same Device
Same Device
Different Device
Same Device
Any Bank
Non-adjacent Bank RR14
Adjacent Bank
Same Bank
Any Bank
RR13
b0 = {Db,Bb,Rb}
c0 = {Da,Bc,Rc}
c0 = {Da,Ba,Rc}
RR15
RR16 c0 = {Da,Ba+1Rc}
RR9
b0 = {Db,Bb,Rb}
c0 = {Da,Bc,Rc}
Non-adjacent Bank RR10
T
T1 T2 T3 T T5 T6 T7 T T11 T T13 T14 T15 T T17 T18 T19 T T21 T22 T23 T T27 T T29 T30 T31 T T33 T34 T35 T T39 T T41 T42 T43 T T45 T46 T47
4 8 12 16 20 24 28 32 36 40 44
0
CTM/CFM
ROW2
PRER a0 PRER b0
PRER a0
PRER c0
PRER a0 ACT b0
PRER a0
ACT c0
..ROW0
t
t
PACKET
t
PACKET
PACKET
t
PP
COL4
..COL0
DQA8..0
DQB8..0
Figure 12: Row Packet Examples
and write operations are also performed during the t
RAS,MIN
Row and Column Cycle Description
- t
interval (if more than about four column opera-
RCD,MIN
Activate: A row cycle begins with the activate (ACT) opera-
tion. The activation process is destructive; the act of sensing
the value of a bit in a bank’s storage cell transfers the bit to
the sense amp, but leaves the original bit in the storage cell
with an incorrect value.
tions are performed, this interval must be increased). The
precharge operation requires the interval t
complete.
to
RP,MIN
Adjacent Banks: An RDRAM with an “s” designation
(256Kx32sx16/18) indicates it contains “split banks”. This
means the sense amps are shared between two adjacent
banks. The only exception is that sense amp 0 and sense amp
0, 15, 16, and 31are not shared. When a row in a bank is acti-
vated, the two adjacent sense amps are connected to (associ-
ated with) that bank and are not available for use by the two
adjacent banks. These two adjacent banks must remain
precharged while the selected bank goes through its activate,
restore, read/write, and precharge operations.
Restore: Because the activation process is destructive, a
hidden operation called restore is automatically performed.
The restore operation rewrites the bits in the sense amp back
into the storage cells of the activated row of the bank.
Read/Write: While the restore operation takes place, the
sense amp may be read (RD) and written (WR) using
column operations. If new data is written into the sense amp,
it is automatically forwarded to the storage cells of the bank
so the data in the activated row and the data in the sense amp
remain identical.
For example (referring to the block diagram of Figure 2), if
bank 5 is accessed, sense amp 4/5 and sense amp 5/6 will
both be loaded with one of the 512 rows (with 512 bytes
loaded into each sense amp from the 1Kbyte row - 256 bytes
to the DQA side and 256 bytes to the DQB side). While this
row from bank 5 is being accessed, no rows may be accessed
in banks 4 or 6 because of the sense amp sharing.
Precharge: When both the restore operation and the column
operations are completed, the sense amp and bank are
precharged (PRE). This leaves them in the proper state to
begin another activate operation.
Intervals: The activate operation requires the interval
t
to complete. The hidden restore operation requires
RCD,MIN
the interval t
- t
to complete. Column read
RAS,MIN RCD,MIN
Page 17
Rev. 0.9 Apr. 1999
Preliminary
Direct RDRAM
™
KM416RD8C/KM418RD8C
t
after the ACT command, and a time t before the next
RP
RAS
Precharge Mechanisms
ACT command. This timing will serve as a baseline aginst
which the other precharge mechanisms can be compared.
Figure 13 shows an example of precharge with the ROWR
packet mechanism. The PRER command must occur a time
a0 = {Da,Ba,Ra}
a5 = {Da,Ba}
b0 = {Da,Ba,Rb}
T
T1 T2 T3
T
T5 T6 T7
T
T9 T10 T11
T
T13 T14 T15
T
T17 T18 T19
T
T21 T22 T23
T
T25 T26 T27
T
T29 T30 T31 T T33 T34 T35 T T37 T38 T39 T T41 T42 T43 T T45 T46 T47
32 36 40 44
0
4
8
12
16
20
24
28
CTM/CFM
ROW2
ACT a0
PRER a5
ACT b0
..ROW0
COL4
..COL0
t
t
RAS
RP
DQA8..0
DQB8..0
t
RC
Figure 13: Precharge via PRER Command in ROWR Packet
Figure 14 (top) shows an example of precharge with a RDA
command. A bank is activated with an ROWA packet on the
ROW pins. Then, a series of four dualocts are read with RD
commands in COLC packets on the COL pins. The fourth of
these commands is a RDA, which causes the bank to auto-
matically precharge when the final read has finished. The
timing of this automatic precharge is equivalent to a PRER
command in an ROWR packet on the ROW pins that is
the WR command unless the second COLC contains a RD
command to the same device. This is described in more
detail in Figure 17.
Figure 14 (bottom) shows an example of precharge with a
PREX command in an COLX packet. A bank is activated
with an ROWA packet on the ROW pins. Then, a series of
four dualocts are read with RD commands in COLC packets
on the COL pins. The fourth of these COLC packets
includes an COLX packet with a PREX command. This
causes the bank to precharge with timing equivalent to a
PRER command in an ROWR packet on the ROW pins that
offset a time t
from the COLC packet with the RDA
OFFP
command. The RDA command should be treated as a RD
command in a COLC packet as well as a simultaneous (but
offset) PRER command in an ROWR packet when analyzing
interactions with other packets.
is offset a time t
command.
from the COLX packet with the PREX
OFFP
Figure 14 (middle) shows an example of precharge with a
WRA command. As in the RDA example, a bank is acti-
vated with an ROWA packet on the ROW pins. Then, two
dualocts are written with WR commands in COLC packets
on the COL pins. The second of these commands is a WRA,
which causes the bank to automatically precharge when the
final write has been retired. The timing of this automatic
precharge is equivalent to a PRER command in an ROWR
packet on the ROW pins that is offset a time t
from the
OFFP
COLC packet that causes the automatic retire. The WRA
command should be treated as a WR command in a COLC
packet as well as a simultaneous (but offset) PRER
command in an ROWR packet when analyzing interactions
with other packets. Note that the automatic retire is triggered
by a COLC packet a time t
after the COLC packet with
RTR
Page 18
Rev. 0.9 Apr. 1999
Preliminary
Direct RDRAM
™
KM416RD8C/KM418RD8C
COLC Packet: RDA Precharge Offset
T
T1 T2 T3 T T5 T6 T7 T T9 T10 T11 T T13 T14 T15 T T17 T18 T19 T T21 T22 T23 T T25 T26 T27 T T29 T30 T31 T T33 T34 T35 T T37 T38 T39 T T41 T42 T43 T T45 T46 T47
0
4 8 12 16 20 24 28 32 36 40 44
CTM/CFM
The RDA precharge is equivalent to a PRER command here
ACT a0 PRER a5
ROW2
ACT b0
..ROW0
t
OFFP
COL4
..COL0
RD a1
RD a2
RD a3
RDA a4
Q (a1)
Q (a2)
Q (a3)
Q (a4)
DQA8..0
DQB8..0
Transaction a: RD
a0 = {Da,Ba,Ra}
a1 = {Da,Ba,Ca1}
a3 = {Da,Ba,Ca3}
a2 = {Da,Ba,Ca2}
a4 = {Da,Ba,Ca4}
a5 = {Da,Ba}
COLC Packet: WDA Precharge Offset
T
T1 T2 T3 T T5 T6 T7 T T9 T10 T11 T T13 T14 T15 T T17 T18 T19 T T21 T22 T23 T T25 T26 T27 T T29 T30 T31 T T33 T34 T35 T T37 T38 T39 T T41 T42 T43 T T45 T46 T47
4 8 12 16 20 24 28 32 36 40 44
0
CTM/CFM
The WRA precharge (triggered by the automatic retire) is equivalent to a PRER command here
ROW2
ACT a0
PRER a5
ACT b0
..ROW0
t
t
OFFP
RTR
COL4
..COL0
WR a1
WRA a2 retire (a1) retire (a2)
MSK (a1) MSK (a2)
D (a1)
D (a2)
DQA8..0
DQB8..0
Transaction a: WR
a0 = {Da,Ba,Ra}
a1 = {Da,Ba,Ca1}
a2 = {Da,Ba,Ca2}
a5 = {Da,Ba}
COLX Packet: PREX Precharge Offset
T
T1 T2 T3
T
T5 T6 T7
T
T9 T10 T11
T
T13 T14 T15
T
T17 T18 T19
T
T21 T22 T23
T
T25 T26 T27
T
T29 T30 T31
T
T33 T34 T35
T
T37 T38 T39
T
T41 T42 T43 T T45 T46 T47
44
0
4
8
12
16
20
24
28
32
36
40
CTM/CFM
The PREX precharge command is equivalent to a PRER command here
ACT a0 PRER a5
ROW2
ACT b0
..ROW0
t
OFFP
COL4
..COL0
RD a1
RD a2
RD a3
RD a4
PREX a5
Q (a1)
Q (a2)
Q (a3)
Q (a4)
DQA8..0
DQB8..0
Transaction a: RD
a0 = {Da,Ba,Ra}
a1 = {Da,Ba,Ca1}
a3 = {Da,Ba,Ca3}
a2 = {Da,Ba,Ca2}
a4 = {Da,Ba,Ca4}
a5 = {Da,Ba}
Figure 14: Offsets for Alternate Precharge Mechanisms
Page 19
Rev. 0.9 Apr. 1999
Preliminary
Direct RDRAM
™
KM416RD8C/KM418RD8C
includes the same device and bank address as the a0, a1, and
a2 addresses. The PRER command must occur a time t
Read Transaction - Example
RAS
Figure 15 shows an example of a read transaction. It begins
by activating a bank with an ACT a0 command in an ROWA
or more after the original ACT command (the activation
operation in any DRAM is destructive, and the contents of
the selected row must be restored from the two associated
packet. A time t
later a RD a1 command is issued in a
RCD
COLC packet. Note that the ACT command includes the
device, bank, and row address (abbreviated as a0) while the
RD command includes device, bank, and column address
sense amps of the bank during the t
interval). The PRER
or more after the last
RAS
command must also occur a time t
RDP
RD command. Note that the t
value shown is greater
RDP
(abbreviated as a1). A time t
after the RD command the
than the t
specification in Table 22. This transaction
CAC
RDP,MIN
read data dualoct Q(a1) is returned by the device. Note that
the packets on the ROW and COL pins use the end of the
packet as a timing reference point, while the packets on the
DQA/DQB pins use the beginning of the packet as a timing
reference point.
example reads two dualocts, but there is actually enough
time to read three dualocts before t becomes the limiting
RDP
parameter rather than t
. If four dualocts were read, the
RAS
packet with PRER would need to shift right (be delayed) by
one t (note - this case is not shown).
CYCLE
A time t after the first COLC packet on the COL pins a
Finally, an ACT b0 command is issued in an ROWR packet
on the ROW pins. The second ACT command must occur a
CC
second is issued. It contains a RD a2 command. The a2
address has the same device and bank address as the a1
address (and a0 address), but a different column address. A
time t or more after the first ACT command and a time t
RC
RP
or more after the PRER command. This ensures that the
bank and its associated sense amps are precharged. This
time t
after the second RD command a second read data
CAC
dualoct Q(a2) is returned by the device.
example assumes that the second transaction has the same
device and bank address as the first transaction, but a
different row address. Transaction b may not be started until
transaction a has finished. However, transactions to other
banks or other devices may be issued during transaction a.
Next, a PRER a3 command is issued in an ROWR packet on
the ROW pins. This causes the bank to precharge so that a
different row may be activated in a subsequent transaction or
so that an adjacent bank may be activated. The a3 address
T
T1 T2 T3
T
T5 T6 T7
T
T9 T10 T11
T
T13 T14 T15
T
T17 T18 T19
T
T21 T22 T23
T
T25 T26 T27
T
T29 T30 T31 T T33 T34 T35 T T37 T38 T39 T T41 T42 T43 T T45 T46 T47
32 36 40 44
0
4
8
12
16
20
24
28
CTM/CFM
t
RC
ROW2
ACT a0
PRER a3
ACT b0
..ROW0
t
t
RAS
RP
COL4
RD a1
RD a2
..COL0
t
t
t
RCD
CC
RDP
Q (a1)
Q (a2)
DQA8..0
DQB8..0
t
CAC
t
CAC
Transaction a: RD
Transaction b: xx
a0 = {Da,Ba,Ra}
b0 = {Da,Ba,Rb}
a1 = {Da,Ba,Ca1}
a2 = {Da,Ba,Ca2}
a3 = {Da,Ba}
Figure 15: Read Transaction Example
Page 20
Rev. 0.9 Apr. 1999
Preliminary
Direct RDRAM
™
KM416RD8C/KM418RD8C
the write buffer to retire is delayed, then the COLM packet
(if used) must also be delayed.
Write Transaction - Example
Figure 16 shows an example of a write transaction. It begins
by activating a bank with an ACT a0 command in an ROWA
Next, a PRER a3 command is issued in an ROWR packet on
the ROW pins. This causes the bank to precharge so that a
different row may be activated in a subsequent transaction or
so that an adjacent bank may be activated. The a3 address
includes the same device and bank address as the a0, a1, and
packet. A time t
-t
later a WR a1 command is issued
RCD RTR
in a COLC packet (note that the t
interval is measured to
RCD
the end of the COLC packet with the first retire command).
Note that the ACT command includes the device, bank, and
row address (abbreviated as a0) while the WR command
includes device, bank, and column address (abbreviated as
a2 addresses. The PRER command must occur a time t
RAS
or more after the original ACT command (the activation
operation in any DRAM is destructive, and the contents of
the selected row must be restored from the two associated
a1). A time t
after the WR command the write data
CWD
dualoct D(a1) is issued. Note that the packets on the ROW
and COL pins use the end of the packet as a timing reference
point, while the packets on the DQA/DQB pins use the
beginning of the packet as a timing reference point.
sense amps of the bank during the t
interval).
RAS
A PRER a3 command is issued in an ROWR packet on the
ROW pins. The PRER command must occur a time t or
RTP
more after the last COLC which causes an automatic retire.
A time t after the first COLC packet on the COL pins a
CC
second COLC packet is issued. It contains a WR a2
command. The a2 address has the same device and bank
address as the a1 address (and a0 address), but a different
Finally, an ACT b0 command is issued in an ROWR packet
on the ROW pins. The second ACT command must occur a
time t or more after the first ACT command and a time t
RC
RP
column address. A time t
command a second write data dualoct D(a2) is issued.
after the second WR
or more after the PRER command. This ensures that the
bank and its associated sense amps are precharged. This
CWD
example assumes that the second transaction has the same
device and bank address as the first transaction, but a
different row address. Transaction b may not be started until
transaction a has finished. However, transactions to other
banks or other devices may be issued during transaction a.
A time t after each WR command an optional COLM
RTR
packet MSK (a1) is issued, and at the same time a COLC
packet is issued causing the write buffer to automatically
retire. See Figure 17 for more detail on the write/retire
mechanism. If a COLM packet is not used, all data bytes are
unconditionally written. If the COLC packet which causes
T
T1 T2 T3
T
T5 T6 T7
T
T9 T10 T11
T
T13 T14 T15 T T17 T18 T19 T T21 T22 T23 T T25 T26 T27 T T29 T30 T31 T T33 T34 T35 T T37 T38 T39 T T41 T42 T43 T T45 T46 T47
16 20 24 28 32 36 40 44
0
4
8
12
CTM/CFM
t
RC
ROW2
..ROW0
ACT a0
PRER a3
ACT b0
t
RCD
t
t
RAS
RP
COL4
..COL0
WR a1
WR a2
retire (a1) retire (a2)
MSK (a1) MSK (a2)
t
RTP
t
RTR
t
RTR
D (a1)
D (a2)
DQA8..0
DQB8..0
t
t
CC
CWD
t
CWD
Transaction a: WR
Transaction b: xx
a0 = {Da,Ba,Ra}
b0 = {Da,Ba,Rb}
a1 = {Da,Ba,Ca1}
a2 = {Da,Ba,Ca2}
a3 = {Da,Ba}
Figure 16: Write Transaction Example
Page 21
Rev. 0.9 Apr. 1999
Preliminary
Direct RDRAM
™
KM416RD8C/KM418RD8C
packet which follows a time t
later will retire the write
RTR
Write/Retire - Examples
buffer. The retire will happen automatically unless (1) a
COLC packet is not framed (no COLC packet is present and
the S bit is zero), or (2) the COLC packet contains a RD
command to the same device. If the retire does not take place
The process of writing a dualoct into a sense amp of an
RDRAM bank occurs in two steps. The first step consists of
transporting the write command, write address, and write
data into the write buffer. The second step happens when the
RDRAM automatically retires the write buffer (with an
optional bytemask) into the sense amp. This two-step write
process reduces the natural turn-around delay due to the
internal bidirectional data pins.
at time t
after the original WR command, then the device
RTR
continues to frame COLC packets, looking for the first that
is not a RD directed to itself. A bytemask MSK(a1) may be
supplied in a COLM packet aligned with the COLC that
retires the write buffer at time t
after the WR command.
RTR
Figure 17 (left) shows an example of this two step process.
The first COLC packet contains the WR command and an
address specifying device, bank and column. The write data
The memory controller must be aware of this two-step
write/retire process. Controller performance can be
improved, but only if the controller design accounts for
several side effects.
dualoct follows a time t
later. This information is loaded
CWD
into the write buffer of the specified device. The COLC
T
T1 T2 T3 T T5 T6 T7 T T9 T10 T11 T T13 T14 T1TT1 T2 T3 T T5 T6 T7 T T9 T10 T11 T T13 T14 T15 T T17 T18 T19 T T21 T22 T23
4 8 12
0 4 8 12 16 20
0
CTM/CFM
CTM/CFM
Retire is automatic here unless:
(1) No COLC packet (S=0) or
(2) COLC packet is RD to device Da
This RD gets the old data
This RD gets the new data
ROW2
..ROW0
ROW2
..ROW0
t
t
CAC
CAC
COL4
..COL0
WR a1
COL4
..COL0
WR a1
retire (a1)
MSK (a1)
RD b1
retire (a1)
MSK (a1)
RD c1
t
t
RTR
RTR
D (a1)
Q (b1)
DQA8..0
DQB8..0
D (a1)
Q (
DQA8..0
DQB8..0
t
t
CWD
CWD
Transaction a: WR
a1= {Da,Ba,Ca1}
Transaction a: WR
Transaction b: RD
Transaction c: RD
a1= {Da,Ba,Ca1}
b1= {Da,Ba,Ca1}
c1= {Da,Ba,Ca1}
Figure 17: Normal Retire (left) and Retire/Read Ordering (right)
Figure 17 (right) shows the first of these side effects. The
first COLC packet has a WR command which loads the
address and data into the write buffer. The third COLC
causes an automatic retire of the write buffer to the sense
amp. The second and fourth COLC packets (which bracket
the retire packet) contain RD commands with the same
device, bank and column address as the original WR
command. In other words, the same dualoct address that is
written is read both before and after it is actually retired. The
first RD returns the old dualoct value from the sense amp
before it is overwritten. The second RD returns the new
dualoct value that was just written.
retire operation and MSK(a1) will be delayed by a time
as a result. If the RD command used the same bank
t
PACKET
and column address as the WR command, the old data from
the sense amp would be returned. If many RD commands to
the same device were issued instead of the single one that is
shown, then the retire operation would be held off an arbi-
trarily long time. However, once a RD to another device or a
WR or NOCOP to any device is issued, the retire will take
place. Figure 18 (right) illustrates a situation in which the
controller wants to issue a WR-WR-RD COLC packet
sequence, with all commands addressed to the same device,
but addressed to any combination of banks and columns.
Figure 18 (left) shows the result of performing a RD
command to the same device in the same COLC packet slot
that would normally be used for the retire operation. The
read may be to any bank and column address; all that matters
is that it is to the same device as the WR command. The
Page 22
Rev. 0.9 Apr. 1999
Preliminary
Direct RDRAM
™
KM416RD8C/KM418RD8C
Therefore, it is required in this situation that the controller
issue a NOCOP command in the third COLC packet,
Write/Retire Examples - continued
The RD will prevent a retire of the first WR from automati-
cally happening. But the first dualoct D(a1) in the write
buffer will be overwritten by the second WR dualoct D(b1)
if the RD command is issued in the third COLC packet.
delaying the RD command by a time of t
. This situa-
PACKET
tion is explicitly shown in Table 12 for the cases in which
is equal to t
t
.
RTR
CCDELAY
T
T1 T2 T3
T
T5 T6 T7
T
T9 T10 T11
T
T13 T14 T15
T
T17 T18 T19
T
T2
T T1 T2 T3 T T5 T6 T7 T8 T9 T10 T11 T T13 T14 T15 T T17 T18 T19 T
0 4 12 16 20
0
4
8
12
16
20
CTM/CFM
CTM/CFM
The retire operation for a write can be
held off by a read to the same device
The controller must insert a NOCOP to retire (a1)
to make room for the data (b1) in the write buffer
ROW2
ROW2
..ROW0
..ROW0
t
t
CAC
CAC
COL4
..COL0
COL4
..COL0
WR a1
WR a1
RD b1
retire (a1)
MSK (a1)
WR b1 retire (a1)
MSK (a1)
RD c1
t
+ t
t
RTR
RTR
PACKET
D (a1)
Q
D (b1)
DQA8..0
DQB8..0
DQA8..0
D (a1)
DQB8..0
t
t
CWD
CWD
Transaction a: WR
Transaction b: RD
a1= {Da,Ba,Ca1}
b1= {Da,Bb,Cb1}
Transaction a: WR
Transaction b: WR
Transaction c: RD
a1= {Da,Ba,Ca1}
b1= {Da,Bb,Cb1}
c1= {Da,Bc,Cc1}
Figure 18: Retire Held Off by Read (left) and Controller Forces WWR Gap (right)
Figure 19 shows a possible result when a retire is held off for
a long time (an extended version of Figure 18-left). After a
WR command, a series of six RD commands are issued to
the same device (but to any combination of bank and column
addresses). In the meantime, the bank Ba to which the WR
command was originally directed is precharged, and a
different row Rc is activated. When the retire is automati-
cally performed, it is made to this new row, since the write
buffer only contains the bank and column address, not the
row address. The controller can insure that this doesn’t
happen by never precharging a bank with an unretired write
buffer. Note that in a system with more than one RDRAM,
there will never be more than two RDRAMs with unretired
write buffers. This is because a WR command issued to one
device automatically retires the write buffers of all other
devices written a time t
before or earlier.
RTR
T
T1 T2 T3
T
T5 T6 T7
T
T9 T10 T11
T
T13 T14 T15
T
T17 T18 T19
T
T21 T22 T23
T
T25 T26 T27
T
T29 T30 T31 T T33 T34 T35 T T37 T38 T39 T T41 T42 T43 T T45 T46 T47
32 36 40 44
0
4
8
12
16
20
24
28
CTM/CFM
The retire operation puts the
write data in the new row
t
RC
ROW2
ACT a0
PRER a2
ACT c0
..ROW0
t
t
RAS
RP
COL4
..COL0
WR a1
RD b1
RD b2
RD b3
RD b4
RD b5
RD b6
retire (a1)
MSK (a1)
t
t
RCD
RTR
D (a1)
Q (b1)
Q (b2)
Q (b3)
Q (b4)
Q (b5)
DQA8..0
DQB8..0
t
t
CWD
CAC
WARNING
This sequence is hazardous
and must be used with caution
Transaction a: WR
Transaction b: RD
a0 = {Da,Ba,Ra}
a1 = {Da,Ba,Ca1}
b2 = {Da,Bb,Cb2}
b5 = {Da,Bb,Cb5}
a2 = {Da,Ba}
b3= {Da,Bb,Cb3}
b6 = {Da,Bb,Cb6}
b1 = {Da,Bb,Cb1}
b4 = {Da,Bb,Cb4}
c0 = {Da,Ba,Rc}
Transaction c: WR
Figure 19: Retire Held Off by Reads to Same Device, Write Buffer Retired to New Row
Page 23
Rev. 0.9 Apr. 1999
Preliminary
Direct RDRAM
™
KM416RD8C/KM418RD8C
using the WRA autoprecharge option rather than the PRER
command in an ROWR packet on the ROW pins.
Interleaved Write - Example
Figure 20 shows an example of an interleaved write transac-
tion. Transactions similar to the one presented in Figure 16
are directed to non-adjacent banks of a single RDRAM. This
In this example, the first transaction is directed to device Da
and bank Ba. The next three transactions are directed to the
same device Da, but need to use different, non-adjacent
banks Bb, Bc, Bd so there is no bank conflict. The fifth
transaction could be redirected back to bank Ba without
interference, since the first transaction would have
allows a new transaction to be issued once every t interval
RR
rather than once every t interval (four times more often).
RC
The DQ data pin efficiency is 100% with this sequence.
With two dualocts of data written per transaction, the COL,
DQA, and DQB pins are fully utilized. Banks are precharged
completed by then (t has elapsed). Each transaction may
use any value of row address (Ra, Rb, ..) and column address
(Ca1, Ca2, Cb1, Cb2, ...).
RC
T
T1 T2 T3
T
T5 T6 T7
T
T9 T10 T11
T
T13 T14 T15
T
T17 T18 T19
T
T21 T22 T23
T
T25 T26 T27
T
T29 T30 T31
T
T33 T34 T35 T T37 T38 T39 T T41 T42 T43 T T45 T46 T47
32 36 40 44
0
4
8
12
16
20
24
28
CTM/CFM
Transaction e can use the
same bank as transaction a
t
RC
ROW2
ACT a0
ACT b0
ACT c0
ACT d0
ACT e0
ACT f0
..ROW0
t
t
RCD
WR a1
RR
WR d1
COL4
..COL0
WR z1
WRA z2
WRA a2
WR b1
WRA b2
WR c1
WRA c2
WR d2
WR e1
WR e2
MSK (y1) MSK (y2) MSK (z1) MSK (z2) MSK (a1) MSK (a2) MSK (b1) MSK (b2) MSK (c1) MSK (c2) MSK (d1) MSK (d
t
CWD
D (z2)
D (x2)
D (y1)
D (y2)
D (z1)
D (a1)
D (a2)
D (b1)
D (b2)
D(c1)
D (c2)
D (d1)
DQA8..0
DQB8..0
Transaction y: WR
Transaction z: WR
Transaction a: WR
Transaction b: WR
Transaction c: WR
Transaction d: WR
Transaction e: WR
Transaction f: WR
y0 = {Da,Ba+4,Ry}
z0 = {Da,Ba+6,Rz}
a0 = {Da,Ba,Ra}
b0 = {Da,Ba+2,Rb}
c0 = {Da,Ba+4,Rc}
d0 = {Da,Ba+6,Rd}
e0 = {Da,Ba,Re}
y1 = {Da,Ba+4,Cy1}
z1 = {Da,Ba+6,Cz1}
a1 = {Da,Ba,Ca1}
b1 = {Da,Ba+2,Cb1}
c1 = {Da,Ba+4,Cc1}
d1 = {Da,Ba+6,Cd1}
e1 = {Da,Ba,Ce1}
y2= {Da,Ba+4,Cy2}
z2= {Da,Ba+6,Cz2}
a2= {Da,Ba,Ca2}
b2= {Da,Ba+2,Cb2}
c2= {Da,Ba+4,Cc2}
d2= {Da,Ba+6,Cd2}
e2= {Da,Ba,Ce2}
y3 = {Da,Ba+4}
z3 = {Da,Ba+6}
a3 = {Da,Ba}
b3 = {Da,Ba+2}
c3 = {Da,Ba+4}
d3 = {Da,Ba+6}
e3 = {Da,Ba}
f0 = {Da,Ba+2,Rf}
f1 = {Da,Ba+2,Cf1}
f2= {Da,Ba+2,Cf2}
f3 = {Da,Ba+2}
Figure 20: Interleaved Write Transaction with Two Dualoct Data Length
that bubble cycles need to be inserted by the controller at
read/write boundaries. The DQ data pin efficiency for the
example in Figure 22 is 32/42 or 76%. If there were more
RDRAMs on the Channel, the DQ pin efficiency would
approach 32/34 or 94% for the two-dualoct RRWW
sequence (this case is not shown).
Interleaved Read - Example
Figure 21 shows an example of interleaved read transac-
tions. Transactions similar to the one presented in Figure 15
are directed to non-adjacent banks of a single RDRAM. The
address sequence is identical to the one used in the previous
write example. The DQ data pins efficiency is also 100%.
The only difference with the write example (aside from the
use of the RD command rather than the WR command) is
the use of the PREX command in a COLX packet to
precharge the banks rather than the RDA command. This is
done because the PREX is available for a readtransaction but
is not available for a masked write transaction.
In Figure 22, the first bubble type t
is inserted by the
CBUB1
controller between a RD and WR command on the COL
pins. This bubble accounts for the round-trip propagation
delay that is seen by read data, and is explained in detail in
Figure 4. This bubble appears on the DQA and DQB pins as
t
between a write data dualoct D and read data dualoct
DBUB1
Q. This bubble also appears on the ROW pins as t
.
RBUB1
Interleaved RRWW - Example
Figure 22 shows a steady-state sequence of 2-dualoct
RD/RD/WR/WR.. transactions directed to non-adjacent
banks of a single RDRAM. This is similar to the interleaved
write and read examples in Figure 20 and Figure 21 except
Page 24
Rev. 0.9 Apr. 1999
Preliminary
Direct RDRAM
™
KM416RD8C/KM418RD8C
T
T1 T2 T3 T T5 T6 T7 T T9 T10 T11 T T13 T14 T15 T T17 T18 T19 T T21 T22 T23 T T25 T26 T27 T T29 T30 T31 T T33 T34 T35 T T37 T38 T39 T T41 T42 T43 T T45 T46 T47
4 8 12 16 20 24 28 32 36 40 44
0
CTM/CFM
Transaction e can use the
same bank as transaction a
t
RC
ROW2
ACT a0
ACT b0
ACT c0
ACT d0
ACT e0
ACT f0
..ROW0
t
t
RCD
RD a1
RR
RD d1
COL4
..COL0
RD z1
RD z2
RD a2
PREX z3
RD b1
RD b2
PREX a3
RD c1
RD c2
RDd2
PREX c3
RD e1
Q (c2)
RD e2
PREX d
PREX y3
PREX b3
t
CAC
Q (z2)
Q (x2)
Q (y1)
Q (y2)
Q (z1)
Q (a1)
Q (a2)
Q (b1)
Q (b2)
Q (c1)
Q (d1)
DQA8..0
DQB8..0
Transaction y: RD
Transaction z: RD
Transaction a: RD
Transaction b: RD
Transaction c: RD
Transaction d: RD
Transaction e: RD
Transaction f: RD
y0 = {Da,Ba+4,Ry}
z0 = {Da,Ba+6,Rz}
a0 = {Da,Ba,Ra}
b0 = {Da,Ba+2,Rb}
c0 = {Da,Ba+4,Rc}
d0 = {Da,Ba+6,Rd}
e0 = {Da,Ba,Re}
y1 = {Da,Ba+4,Cy1}
z1 = {Da,Ba+6,Cz1}
a1 = {Da,Ba,Ca1}
b1 = {Da,Ba+2,Cb1}
c1 = {Da,Ba+4,Cc1}
d1 = {Da,Ba+6,Cd1}
e1 = {Da,Ba,Ce1}
y2= {Da,Ba+4,Cy2}
z2= {Da,Ba+6,Cz2}
a2= {Da,Ba,Ca2}
b2= {Da,Ba+2,Cb2}
c2= {Da,Ba+4,Cc2}
d2= {Da,Ba+6,Cd2}
e2= {Da,Ba,Ce2}
y3 = {Da,Ba+4}
z3 = {Da,Ba+6}
a3 = {Da,Ba}
b3 = {Da,Ba+2}
c3 = {Da,Ba+4}
d3 = {Da,Ba+6}
e3 = {Da,Ba}
f0 = {Da,Ba+2,Rf}
f1 = {Da,Ba+2,Cf1}
f2= {Da,Ba+2,Cf2}
f3 = {Da,Ba+2}
Figure 21: Interleaved Read Transaction with Two Dualoct Data Length
The second bubble type t
command) by the controller between a WR and RD
is inserted (as a NOCOP
explained in detail in Figure 18. There would be no bubble if
address c0 and address d0 were directed to different devices.
CBUB2
command on the COL pins when there is a WR-WR-RD
sequence to the same device. This bubble enables write data
to be retired from the write buffer without being lost, and is
This bubble appears on the DQA and DQB pins as t
DBUB2
between a write data dualoct D and read data dualoct Q. This
bubble also appears on the ROW pins as t
.
RBUB2
T
T1 T2 T3
T
T5 T6 T7
T
T9 T10 T11
T
T13 T14 T15
T
T17 T18 T19
T
T21 T22 T23
T
T25 T26 T27
T
T29 T30 T31
T
T33 T34 T35
T
T37 T38 T39
T
T41 T42 T43
T
T45 T46 T47
0
4
8
12
16
20
24
28
32
36
40
44
CTM/CFM
Transaction e can use the
same bank as transaction a
t
RBUB2
t
RBUB1
ACT b0
ROW2
ACT a0
ACT c0
ACT d0
ACT e0
..ROW0
t
CBUB2
t
t
CBUB2
CBUB1
WR b1
COL4
..COL0
RD z1
RD z2
RD a1
RD a2
PREX z3
WRA b2
WR c1
WRA c2
NOCOP NOCOP
MSK (y2) PREX a3 MSK (b1) MSK (b2) MSK (c1) MSK (c2)
RDd0
t
DBUB2
t
t
DBUB1
DBUB1
D (y2)
Q (z1)
Q (z2)
DQA8..0
DQB8..0
Q (a1)
Q (a2)
D (b1)
D (b2)
D (c1)
D (c2)
Transaction y: WR
Transaction z: RD
Transaction a: RD
Transaction b: WR
Transaction c: WR
Transaction d: RD
Transaction e: RD
Transaction f: WR
y0 = {Da,Ba+4,Ry}
z0 = {Da,Ba+6,Rz}
a0 = {Da,Ba,Ra}
b0 = {Da,Ba+2,Rb}
c0 = {Da,Ba+4,Rc}
d0 = {Da,Ba+6,Rd}
e0 = {Da,Ba,Re}
y1 = {Da,Ba+4,Cy1}
z1 = {Da,Ba+6,Cz1}
a1 = {Da,Ba,Ca1}
b1 = {Da,Ba+2,Cb1}
c1 = {Da,Ba+4,Cc1}
d1 = {Da,Ba+6,Cd1}
e1 = {Da,Ba,Ce1}
y2= {Da,Ba+4,Cy2}
z2= {Da,Ba+6,Cz2}
a2= {Da,Ba,Ca2}
b2= {Da,Ba+2,Cb2}
c2= {Da,Ba+4,Cc2}
d2= {Da,Ba+6,Cd2}
e2= {Da,Ba,Ce2}
y3 = {Da,Ba+4}
z3 = {Da,Ba+6}
a3 = {Da,Ba}
b3 = {Da,Ba+2}
c3 = {Da,Ba+4}
d3 = {Da,Ba+6}
e3 = {Da,Ba}
f0 = {Da,Ba+2,Rf}
f1 = {Da,Ba+2,Cf1}
f2= {Da,Ba+2,Cf2}
f3 = {Da,Ba+2}
Figure 22: Interleaved RRWW Sequence with Two Dualoct Data Length
Page 25
Rev. 0.9 Apr. 1999
Preliminary
Direct RDRAM
™
KM416RD8C/KM418RD8C
SCK (serial clock) and CMD (command) are driven by the
controller to all RDRAMs in parallel. SIO0 and SIO1 are
connected (in a daisy chain fashion) from one RDRAM to
the next. In normal operation, the data on SIO0 is repeated
on SIO1, which connects to SIO0 of the next RDRAM (the
data is repeated from SIO1 to SIO0 for a read data packet).
The controller connects to SIO0 of the first RDRAM.
Control Register Transactions
The RDRAM has two CMOS input pins SCK and CMD and
two CMOS input/output pins SIO0 and SIO1. These provide
serial access to a set of control registers in the RDRAM.
These control registers provide configuration information to
the controller during the initialization process. They also
allow an application to select the appropriate operating mode
of the RDRAM.
T20
T36
T52
T68
T4
SCK
1
0
1
0
1
0
1
0
next transaction
00000000...00000000
CMD
1111 0000
00000000...00000000
00000000...00000000
SA
00000000...00000000
1111
SIO0
SIO1
SRQ - SWR command
SD
SD
SINT
SINT
Each packet is repeated
from SIO0 to SIO1
SRQ - SWR command
SA
Figure 23: Serial Write (SWR) Transaction to Control Register
Write and read transactions are each composed of four
packets, as shown in Figure 23 and Figure 24. Each packet
consists of 16 bits, as summarized in Table 16 and Table 17.
The packet bits are sampled on the falling edge of SCK. A
transaction begins with a SRQ (Serial Request) packet. This
packet is framed with a 11110000 pattern on the CMD input
(note that the CMD bits are sampled on both the falling edge
and the rising edge of SCK). The SRQ packet contains the
SOP3..SOP0 (Serial Opcode) field, which selects the trans-
action type. The SDEV5..SDEV0 (Serial Device address)
selects one of the 32 RDRAMs. If SBC (Serial Broadcast) is
set, then all RDRAMs are selected. The SA (Serial Address)
packet contains a 12 bit address for selecting a control
register.
A write transaction has a SD (Serial Data) packet next. This
contains 16 bits of data that is written into the selected
control register. A SINT (Serial Interval) packet is last,
providing some delay for any side-effects to take place. A
read transaction has a SINT packet, then a SD packet. This
provides delay for the selected RDRAM to access the
control register. The SD read data packet travels in the oppo-
site direction (towards the controller) from the other packet
types. The SCK cycle time will accomodate the total delay.
T20
T36
T52
T68
T4
SCK
1
0
1
0
1
0
1
0
next transaction
00000000...00000000 1111
CMD
1111 0000
00000000...00000000
SRQ - SRD command
00000000...00000000
SA
00000000...00000000
addressed RDRAM drives
0/SD15..SD0/0 on SIO0
controller drives
0 on SIO0
SIO0
SIO1
0
0
SD
0
0
SINT
First 3 packets are repeated
from SIO0 to SIO1
non-addressed RDRAMs pass
0/SD15..SD0/0 from SIO1 to SIO0
SD
SRQ - SRD command
SA
SINT
Figure 24: Serial Read (SRD) Transaction Control Register
Page 26
Rev. 0.9 Apr. 1999
Preliminary
Direct RDRAM
™
KM416RD8C/KM418RD8C
Control Register Packets
T4
T20
1
Table 14 summarizes the formats of the four packet types for
control register transactions. Table 15 summarizes the fields
that are used within the packets.
SCK
CMD
SIO0
SIO1
0
1
1111 0000
00000000...00000000
Figure 25 shows the transaction format for the SETR,
CLRR, and SETF commands. These transactions consist of a
single SRQ packet, rather than four packets like the SWR
and SRD commands. The same framing sequence on the
CMD input is used, however. These commands are used
during initialization prior to any control register read or
write transactions.
0
1
0
1
0
SRQ packet - SETR/CLRR/SETF
The packet is repeated
from SIO0 to SIO1
SRQ packet - SETR/CLRR/SETF
Figure 25: SETR, CLRR,SETF Transaction
Table 14: Control Register Packet Formats
SCK
Cycle
SIO0 or
SIO1
SIO0 or
SIO1
SIO0 or
SIO1
SIO0 or
SIO1
SCK
Cycle
SIO0 or
SIO1
SIO0 or
SIO1
SIO0 or
SIO1
SIO0 or
SIO1
for SRQ
for SA
for SINT
for SD
for SRQ
for SA
for SINT
for SD
0
1
2
3
4
5
6
7
rsrv
rsrv
0
0
0
0
0
0
0
0
SD15
SD14
SD13
SD12
SD11
SD10
SD9
8
SOP1
SA7
SA6
SA5
SA4
SA3
SA2
SA1
SA0
0
0
0
0
0
0
0
0
SD7
SD6
SD5
SD4
SD3
SD2
SD1
SD0
rsrv
rsrv
9
SOP0
rsrv
rsrv
10
11
12
13
14
15
SBC
rsrv
rsrv
SDEV4
SDEV3
SDEV2
SDEV1
SDEV0
rsrv
SA11
SA10
SA9
SA8
SDEV5
SOP3
SOP2
SD8
Table 15: Field Description for Control Register Packets
Field
Description
rsrv
Reserved. Should be driven as “0” by controller.
SOP3..SOP0
0000 - SRD. Serial read of control register {SA11..SA0} of RDRAM {SDEV5..SDEV0}.
0001 - SWR. Serial write of control register {SA11..SA0} of RDRAM {SDEV5..SDEV0}.
0010 - SETR. Set Reset bit, all control registers assume their reset values.a 16 tSCYCLE delay until CLRR command.
0100 - SETF. Set fast (normal) clock mode. 4 tSCYCLE delay until next command.
1011 - CLRR. Clear Reset bit, all control registers retain their reset values.a 4 tSCYCLE delay until next command.
1111 - NOP. No serial operation.
0011, 0101-1010, 1100-1110 - RSRV. Reserved encodings.
SDEV5..SDEV0
Serial device. Compared to SDEVID5..SDEVID0 field of INIT control register field to select the RDRAM to which the transac-
tion is directed.
SBC
Serial broadcast. When set, RDRAMs ignore {SDEV5..SDEV0} for RDRAM selection.
Serial address. Selects which control register of the selected RDRAM is read or written.
Serial data. The 16 bits of data written to or read from the selected control register of the selected RDRAM.
SA11..SA0
SD15..SD0
a. The SETR and CLRR commands must always be applied in two successive transactions to RDRAMs; i.e. they may not be used in isolation. This is called “SETR/CLRR Reset”.
Page 27
Rev. 0.9 Apr. 1999
Preliminary
Direct RDRAM
™
KM416RD8C/KM418RD8C
Initialization
At this point, Algorithm InitDev is complete and all
RDRAMs have a unique device address SDEVID5..0 for
control register transactions. Note that the SDEVID address
value of an RDRAM indicates its position in the daisy-
chained CMOS serial pins. This will not necessarily be the
same value as the DEVID register which is used for memory
transactions. The next steps taken by the controller will vary
depending upon the application, so only a rough outline can
be given here.
T0
T16
1
0
1
0
1
0
1
0
SCK
CMD
SIO0
SIO1
1100
00000000...00000000
0000000000000000
=======================================
Algorithm InitDev: Assign SDEVID Device Addresses
The packet is repeated
from SIO0 to SIO1
1.
2.
Issue SIO Reset sequence (see Figure 26).
0000000000000000
Issue one SETR transaction:
• SOP3..SOP0 = 0010 (SETR command)
• SBC = 1 (Broadcast)
• SDEV5..SDEV0 = 000000 (don’t care).
Figure 26: SIO Reset Sequence
3.
4.
Wait 16 SCK cycles.
Initialization refers to the process that a controller must go
through after power is applied to the system or the system is
reset. The controller prepares the RDRAM sub-system for
normal Channel operation by using a sequence of control
register transactions on the serial CMOS pins.
Issue one CLRR transaction:
• SOP3..SOP0 = 0011 (CLRR command)
• SBC = 1 (Broadcast)
• SDEV5..SDEV0 = 000000 (don’t care).
5.
6.
Wait 4 SCK cycles.
The first step in this sequence is to assign unique serial
device addresses to all the RDRAMs. This is done with
Algorithm InitDev, shown in the opposite column. The
controller assumes that there are no more that “N” RDRAMs
on the Channel (the Channel maximum is 32, but some
applications may have a lower limit).
Issue one SETF transaction:
• SOP3..SOP0 = 0100 (SETF command)
• SBC = 1 (Broadcast)
• SDEV5..SDEV0 = 000000 (don’t care).
7.
8.
Wait 4 SCK cycles.
Issue one register write transaction:
• SOP3..SOP0 = 0001 (SWR command)
• SBC = 1 (broadcast)
• SDEV5..SDEV0 = 000000 (don’t care).
• SA11..SA0 = 021 16 (INIT control register).
• SD15..SD0 = 401f 16 (SRP<=0, SDEVID<=3f).
First, the SIO0 and SIO1 pin directionality is established
with the sequence in step 1. The controller then resets all
RDRAMs, using broadcast SETR and CLRR commands
(steps 2,3,4,5) with a delay in between (this is also called
SIO Reset). In step 6, a SETF command establishs the
normal clock frequency. See Figure 25 for the format of
SETR, CLRR, and SETF transactions. In step 7 the SIO0-to-
SIO1 link is broken in all RDRAMs, so the controller is only
talking to the first RDRAM. Also, the SDEVID field is set to
its maximum value. Next, the loop index INDX is initialized
(step 8). In step 9, the SDEVID field is loaded with the
INDX value, and the SRP bit is set so the next RDRAM
becomes accessible. In step 10, the INDX value is incre-
mented, and in step 11, steps 8 and 9 are repeated for the
remaining RDRAMs.
9.
Set INDX5..INDX0 to 00000002. INDX is a counter in the
Controller which acts as a loop index.
10. Issue one register write transaction (SRP<=1, SDEVID<=INDX):
• SOP3..SOP0 = 0001 (SWR command)
• SBC = 0 (non-broadcast)
•SDEV5..SDEV0 = 111111.
• SA11..SA0 = 021 16 (INIT control register).
• SD15..SD0 = {0 2, INDX5, 000001002, INDX4..INDX0}.
11. Increment INDX5..INDX0.
12. Repeat Steps (8) and (9) an additional (N-1) times.
13. tPAUSE delay, then tPDNXA+ tPDNXB delay (to allow DLLs to lock),
then access all banks twice from a precharged state; i.e perform one of
the two following two (broadcast) sequences to each bank of all
RDRAMs:
Finally, it will be necessary for the controller to force a
200ms pause interval to allow the RDRAM core timing
circuits to stabilize. All banks of all RDRAMs must also be
accessed twice. An access is an activate (ACT) and a
precharge (PRE) command. This may be accomplished with
the refresh commands.
a. REFA/REFP, REFA/REFP, REFA/REFP or
a. REFP, REFA/REFP, REFA/REFP
Page 28
Rev. 0.9 Apr. 1999
Preliminary
Direct RDRAM
™
KM416RD8C/KM418RD8C
Initialization (continued)
In essence, the controller must read all the read-only config-
uration registers of all RDRAMs, it must process this infor-
mation, and then it must write all the read-write registers to
place the RDRAMs into the proper operating mode. The
most important of these read-write registers are DEVID (the
device address for memory transactions) and TRDLY
(which sets the delay value for memory read data).
During the initialization process, it is necessary for the
controller to perform 128 current control operations
(3xCAL, 1xCAL/SAM) and one temperature calibrate oper-
ation (TCEN/TCAL) after reset or after powerdown (PDN)
exit.
There are two classes of 128/144Mbit RDRAM. They are
distinguished by the “S28IECO” bit in the SPD. The
behavior of the RDRAM at initialization is slightly different
for the two types:
S28IECO=0: Upon powerup the device enters ATTN state.
The serial operations SETR, CLRR, and SETF are
performed without requiring a SDEVID match of the SBC
bit (broadcast) to be set.
S28IECO=1: Upon powerup the device enters PDN state.
The serial operations SETR, CLRR, and SETF require a
SDEVID match.
See the document detailing the reference initialization proce-
dure for more information on how to handle this in a system.
After the step of equalizing the total read delay of each
RDRAM has been completed (i.e. after the TCDLY0 and
TCDLY1 fields have been written for the final time), a
single final memory read transaction should be made to each
RDRAM in order to ensure that the output pipeline stages
have been cleared.
Page 29
Rev. 0.9 Apr. 1999
Preliminary
Direct RDRAM
™
KM416RD8C/KM418RD8C
SPD Application Note describes additional read-only
configuration registers which are present on Direct RIMMs.
Control Register Summary
Table 16 summarizes the RDRAM control registers. Detail
is provided for each control register in Figure 27 through
Figure 43. Read-only bits which are shaded gray are unused
and return zero. Read-write bits which are shaded gray are
reserved and should always be written with zero. The RIMM
The state of the register fields are potentially affected by the
IO Reset operation or the SETR/CLRR operation. This is
indicated in the text accompanying each register diagram.
Table 16: Control Register Summary
SA11..SA0
Register
Field
read-write/ read-only
Description
02116
INIT
SDEVID
PSX
read-write, 6 bits
read-write, 1 bit
read-write, 1 bit
read-write, 1 bit
read-write, 1 bit
read-write, 1 bit
read-write, 1 bit
read-write, 1 bit
read-write, 1 bit
read-write, 16 bits
read-only, 3 bit
read-only, 1 bit
read-only, 6 bit
read-only, 6 bit
read-only, 1 bit
read-only, 3 bit
read-only, 1 bit
read-only, 6 bit
read-only, 6 bit
read-write, 5 bits
read-write, 4 bits
read-write, 9 bits
read-write, 7 bits
read-write, 2 bits
read-write, 7 bits
read-write, 2 bits
read-write, 5 bits
read-write, 5 bits
read-write, 1 bits
read-write, 13 bits
read-write, 13 bits
read-write, 2 bits
read-write, 2 bits
read-write, 3 bits
Serial device ID. Device address for control register read/write.
Power select exit. PDN/NAP exit with device addr on DQA5..0.
SIO repeater. Used to initialize RDRAM.
SRP
NSR
NAP self-refresh. Enables self-refresh in NAP mode.
PDN self-refresh. Enables self-refresh in PDN mode.
Low power self-refresh. Enables low power self-refresh.
Temperature sensing enable.
PSR
LSR
TEN
TSQ
Temperature sensing output.
DIS
RDRAM disable.
02216
02316
TEST34
CNFGA
TEST34
REFBIT
DBL
Test register. Do not read or write after SIO reset.
Refresh bank bits. Used for multi-bank refresh.
Double. Specifies doubled-bank architecture
MVER
PVER
BYT
Manufacturer version. Manufacturer identification number.
Protocol version. Specifies version of Direct protocol supported.
Byte. Specifies an 8-bit or 9-bit byte size.
02416
CNFGB
DEVTYP
SPT
Device type. Device can be RDRAM or some other device category.
Split-core. Each core half is an individual dependent core.
Core organization. Bank, row, column address field sizes.
Stepping version. Mask version number.
CORG
SVER
DEVID
REFB
REFR
CCA
04016
04116
04216
04316
DEVID
REFB
REFR
CCA
Device ID. Device address for memory read/write.
Refresh bank. Next bank to be refreshed by self-refresh.
Refresh row. Next row to be refreshed by REFA, self-refresh.
Current control A. Controls IOL output current for DQA.
Asymmetry control. Controls asymmetry of VOL/VOH swing for DQA.
Current control B. Controls IOL output current for DQB.
Asymmetry control. Controls asymmetry of VOL/VOH swing for DQB.
NAP exit. Specifies length of NAP exit phase A.
NAP exit. Specifies length of NAP exit phase A + phase B.
DQ select. Selects CMD framing for NAP/PDN exit.
PDN exit. Specifies length of PDN exit phase A.
PDN exit. Specifies length of PDN exit phase A + phase B.
tCAS-C core parameter. Determines tOFFP datasheet parameter.
tCLS-C core parameter. Determines tCAC and tOFFP parameters.
tCDLY0-C core parameter. Programmable delay for read data.
ASYMA
CCB
04416
04516
CCB
ASYMB
NAPXA
NAPX
DQS
NAPX
04616
04716
04816
PDNXA
PDNX
PDNXA
PDNX
TCAS
TCLS
TCDLY0
TPARM
Page 30
Rev. 0.9 Apr. 1999
Preliminary
Direct RDRAM
™
KM416RD8C/KM418RD8C
Table 16: Control Register Summary
SA11..SA0
Register
Field
read-write/ read-only
Description
04916
04a16
04b16
TFRM
TCDLY1
SKIP
TFRM
TCDLY1
AS
read-write, 4 bits
read-write, 3 bits
read, 1 bit
tFRM-C core parameter. Determines ROW-COL packet framing interval.
tCDLY1-C core parameter. Programmable delay for read data.
Auto Skip.
MSE
read-write, 1 bit
read-write, 1 bit
read-write, 14 bits
read-write, 16 bits
read-write, 16 bits
read-write, 16 bits
vendor-specific
Manual Skip Enable.
MS
Manual Skip.
04c16
04d16
04e16
04f16
TCYCLE
TEST77
TEST78
TEST79
TCYCLE
TEST77
TEST78
TEST79
reserved
tCYCLE datasheet parameter. Specifies cycle time in 64ps units.
Test register. Write with zero after SIO reset.
Test register. Do not read or write after SIO reset.
Test register. Do not read or write after SIO reset.
Vendor-specific test registers. Do not read or write after SIO reset.
08016 - 0ff16 reserved
Page 31
Rev. 0.9 Apr. 1999
Preliminary
Direct RDRAM
™
KM416RD8C/KM418RD8C
.
.
Read/write register.
Reset values are undefined except as affected by SIO Reset as noted
below. SETR/CLRR Reset does not affect this register.
Control Register: INIT
Address: 021
16
15 14 13 12 11 10
9
8
7
6
5
0
4
3
2
1
0
SDEVID5..0 - Serial Device Identification. Compared to SDEV5..0
serial address field of serial request packet for register read/write transac-
tions. This determines which RDRAM is selected for the register read or
SDE
DIS TSQ TEN LSR PSR NSR SRP PSX
VID
SDEVID4..SDEVID0
0
5
write operation. SDEVID resets to 3f16
.
PSX - Power Exit Select. PDN and NAP are exited with (=0) or without (=1) a device address on the
DQA5..0 pins.
SRP - SIO Repeater. Controls value on SIO1; SIO1=SIO0 if SRP=1, SIO1=1 if SRP=0. SRP resets
to 1.
NAP Self-Refresh. NSR=1 enables self-refresh in NAP mode. NSR can’t be set while in NAP
mode. NSR resets to 0.
PDN Self-Refresh. PSR=1 enables self-refresh in PDN mode. PSR can’t be set while in PDN mode.
PSR resets to 0.
Low Power Self-Refresh. LSR=1 enables longer self-refresh interval. The self-refresh supply
current is reduced. LSR resets to 0.
Temperature Sensing Enable. TEN=1 enables temperature sensing circuitry, permitting the TSQ bit
to be read to determine if a thermal trip point has been exceeded. TEN resets to 0.
Temperature Sensing Output. TSQ=1 when a temperature trip point has been exceeded, TSQ=0
when it has not. TSQ is available during a current control operation (see Figure 51).
RDRAM Disable. DIS=1 causes RDRAM to ignore NAP/PDN exit sequence, DIS=0 permits
normal operation. This mechanism disables an RDRAM. DIS resets to 0.
Figure 27: INIT Register
Control Register: CNFGA
Address: 023
16
Read-only register.
15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
REFBIT2..0 - Refresh Bank Bits. Specifies the number of
bank address bits used by REFA and REFP commands.
Permits multi-bank refresh in future RDRAMs.
PVER5..0
= 000001
MVER5..0
= mmmmmm
DBL REFBIT2..0
= 100
1
DBL - Doubled-Bank. DBL=1 means the device uses a
doubled-bank architecture with adjacent-bank dependency.
DBL=0 means no dependency.
MVER5..0 - Manufacturer Version. Specifies the manufac-
turer identification number.
PVER5..0 - Protocol Version. Specifies the Direct Protocol
version used by this device:
0 - Compliant with version 0.62 and ECO1-ECO18.
1 - Compliant with version 0.7 and ECO1-ECO38.
2 to 63 - Reserved.
Note: In RDRAMs with protocol version 1 PVER[5:0] = 000001, the
range of the PDNX field (PDNX[2:0] in the PDNX register) may not
be large enough to specify the location of the restricted interval in
Figure 47. In this case, the effective tS4 parameter must increase and
no row or column packets may overlap the restricted interval. See
Figure 47 and Table 19.
Figure 28: CNFGA Register
Page 32
Rev. 0.9 Apr. 1999
Preliminary
Direct RDRAM
™
KM416RD8C/KM418RD8C
. .
Read-only register.
Control Register: CNFGB
Address: 024
16
15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
BYT - Byte width. B=1 means the device reads and
writes 9-bit memory bytes. B=0 means 8 bits.
SVER5..0
= ssssss
CORG4..0
= xxxxx
SPT DEVTYP2..0 BYT
1
= 000
B
DEVTYP2..0 - Device type. DEVTYP = 000 means
that this device is an RDRAM.
SPT - Split-core. SPT=1 means the core is split, SPT=0 means it is not.
CORG4..0 - Core organization. This field specifies the number of bank (3,
4, 5, or 6 bits), row (9, 10, 11, or 12 bits), and column (5, 6, or 7 bits)
address bits. The encoding of this field will be specified in a later version of
this document.
SVER5..0 - Stepping version. Specifies the mask version number of this
device.
Figure 29: CNFGB Register
Control Register: TEST34
Control Register: DEVID
Address: 022
Address: 040
16
16
0
15 14 13 12 11 10
9
0
8
0
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
15 14 13 12 11 10
9
0
8
0
7
0
6
0
5
0
4
3
2
1
DEVID4..DEVID0
0
0
0
0
0
0
0
0
0
0
0
0
0
Read/write register.
Reset value of TEST34 is zero (from SIO Reset)
This register are used for testing purposes. It must not
be read or written after SIO Reset.
Read/write register.
Reset value is undefined.
Device Identification register.
DEVID4..DEVID0 is compared to DR4..DR0,
DC4..DC0, and DX4..DX0 fields for all memory read
or write transactions. This determines which RDRAM
is selected for the memory read or write transaction.
Figure 30: TEST Register
Figure 31: DEVID Register
Page 33
Rev. 0.9 Apr. 1999
Preliminary
Direct RDRAM
™
KM416RD8C/KM418RD8C
Control Register: REFB
Control Register: REFR
Address: 041
Address: 042
16
0
16
0
15 14 13 12 11 10
9
0
8
0
7
0
6
0
5
0
4
0
3
2
1
15 14 13 12 11 10
9
0
8
7
6
5
4
3
2
1
REFB3..REFB0
REFR8..REFR0
0
0
0
0
0
0
0
0
0
0
0
0
Read/write register.
Read/write register.
Reset value is zero (from SETR/CLRR).
Refresh Bank register.
Reset value is zero (from SETR/CLRR).
Refresh Row register.
REFB3..REFB0 is the bank that will be refreshed next
during self-refresh. REFB3..0 is incremented after each
self-refresh activate and precharge operation pair.
REFR8..REFR0 is the row that will be refreshed next
by the REFP command or by self-refresh. REFR8..0 is
incremented when BR3..0=1111 for the REFA
command. REFR8..0 is incremented when
REFB3..0=1111 for self-refresh.
Figure 32: REFB Register
Figure 34: REFR Register
Control Register: CCA
Control Register: CCB
Address: 043
Address: 044
16
0
16
0
15 14 13 12 11 10
9
0
8
7
6
5
4
3
2
1
15 14 13 12 11 10
9
0
8
7
6
5
4
3
2
1
0ASYMA
0
0
0
0
0
0
0ASYMB
CCA6..CCA0
CCB6..CCB0
0
0
0
0
0
0
0
0
Read/write register.
Read/write register.
Reset value is zero (SETR/CLRR or SIO Reset).
CCA6..CCA0 - Current Control A. Controls the I
output current for the DQA8..DQA0 pins.
Reset value is zero (SETR/CLRR or SIO Reset).
CCB6..CCB0 - Current Control B. Controls the I
output current for the DQB8..DQB0 pins.
OL
OL
ASYMA0 control the asymmetry of the V /V
ASYMB0 control the asymmetry of the V /V
OL OH
OL OH
voltage swing about the V
DQA8..0 pins.
reference voltage for the
voltage swing about the V
DQB8..0 pins.
reference voltage for the
REF
REF
Figure 33: CCA Register
Figure 35: CCB Register
Page 34
Rev. 0.9 Apr. 1999
Preliminary
Direct RDRAM
™
KM416RD8C/KM418RD8C
.
Read/write register.
Reset value is undefined
Control Register: NAPX
Address: 045
16
15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
Note - t
is t
(SCK cycle time).
CYCLE1
SCYCLE
DQS
NAPX4..0
NAPXA4..0
0
0
0
0
0
NAPXA4..0 - Nap Exit Phase A. This field specifies
the number of SCK cycles during the first phase for
exiting NAP mode. It must satisfy:
NAPXA•t
³ t
NAPXA,MAX
SCYCLE
Do not set this field to zero.
NAPX4..0 - Nap Exit Phase A plus B. This field specifies the number of SCK
cycles during the first plus second phases for exiting NAP mode. It must satisfy:
NAPX•t
³ NAPXA•t
+t
SCYCLE NAPXB,MAX
SCYCLE
Do not set this field to zero.
DQS - DQ Select. This field specifies the number of SCK cycles (0 => 0.5
cycles, 1 => 1.5 cycles) between the CMD pin framing sequence and the device
selection on DQ5..0. See Figure 48 - This field must be written with a ²1² for
this RDRAM.
Figure 36: NAPX Register
Control Register: PDNXA
Control Register: PDNX
Address: 046
Address: 047
16
16
0
15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
PDNXA12..0
PDNX12..0
0
0
0
0
0
0
Read/write register.
Reset value is undefined
Read/write register.
Reset value is undefined
PDNXA4..0 - PDN Exit Phase A. This field specifies
the number of (64•SCK cycle) units during the first
phase for exiting PDN mode. It must satisfy:
PDNX4..0 - PDN Exit Phase A plus B. This field spec-
ifies the number of (256•SCK cycle) units during the
first plus second phases for exiting PDN mode. It must
satisfy:
PDNXA•64•t
³ t
PDNXA,MAX
SCYCLE
Do not set this field to zero.
Note - only PDNXA5..0 are implemented.
PDNX•256•t
³ PDNXA•64•t
+
SCYCLE
SCYCLE
t
PDNXB,MAX
Note - t
is t
(SCK cycle time).
CYCLE1
Do not set this field to zero.
Note - only PDNX2..0 are implemented.
Note - t is t (SCK cycle time).
SCYCLE
SCYCLE
CYCLE1
Figure 37: PDNXA Register
Figure 38: PDNX Register
Page 35
Rev. 0.9 Apr. 1999
Preliminary
Direct RDRAM
™
KM416RD8C/KM418RD8C
.
The equations relating the core parameters to the
datasheet parameters follow:
Control Register: TPARM
Address: 048
16
15 14 13 12 11 10
9
0
8
0
7
0
6
5
4
3
2
1
0
t
t
t
= 2·t
= 2· t
= 1·t
CAS-C
CLS-C
CPS-C
CYCLE
CYCLE
CYCLE
TCDLY0
TCLS
TCAS
0
0
0
0
0
0
Not programmable
+ t - 1·t
CYCLE
Read/write register.
t
= t
+ t
Reset value is undefined.
TCAS1..0 - Specifies the t
OFFP
CPS-C
CAS-C
CLS-C
= 4·t
core parameter in
CYCLE
CAS-C
t
units. This should be “ 10” (2·t
).
CYCLE
CYCLE
t
= t
= t
RCD-C
+ 1·t
- t
RCD
RCD-C
CYCLE CLS-C
- 1·t
CYCLE
TCLS1..0 - Specifies the t
core parameter in
CLS-C
t
units. Should be “10” (2·t
).
CYCLE
CYCLE
TCDLY0 - Specifies the t
core parameter in
CDLY0-C
t
= 3·t
+ t
+ t
+ t
CDLY0-C CDLY1-C
CAC
CYCLE
CLS-C
t
units. This adds a programmable delay to Q
CYCLE
(see table below for programming ranges)
(read data) packets, permitting round trip read delay to
all devices to be equalized. This field may be written
TCDLY0
011
TCDLY1
000
t
t
t
CAC
CDLY0-C
CDLY1-C
with the values “010” (2·t
) through “101”
CYCLE
3•t
3•t
3•t
4•t
5•t
0
·
t
t
t
t
t
8
·
t
t
CYCLE
CYCLE
CYCLE
CYCLE
CYCLE
CYCLE
CYCLE
CYCLE
CYCLE
CYCLE
CYCLE
(5·t
).
CYCLE
011
001
1·
9·
CYCLE
011
010
2·
10·
11·
12·
t
CYCLE
100
010
t
CYCLE
2·
101
010
t
CYCLE
2·
Figure 39: TPARM Register
Control Register: TFRM
Control Register: TCDLY1
Address: 049
Address: 04a
16
0
16
0
15 14 13 12 11 10
9
0
8
0
7
0
6
0
5
0
4
0
3
2
1
15 14 13 12 11 10
9
0
8
0
7
0
6
0
5
4
0
3
0
2
1
TFRM3..0
TCDLY1
0
0
0
0
0
0
0
0
0
0
0
0
0
Read/write register.
Reset value is undefined.
TFRM3..0 - Specifies the position of the framing point
in t units. This value must be greater than or
Read/write register.
Reset value is undefined.
TCDLY1 - Specifies the value of the t
core
CDLY1-C
parameter in t
units. This adds a programmable
CYCLE
CYCLE
equal to the t
parameter. This is the minimum
delay to Q (read data) packets, permitting round trip
read delay to all devices to be equalized. This field may
be written with the values “000” (0·t ) through
FRM,MIN
offset between a ROW packet (which places a device
at ATTN) and the first COL packet (directed to that
device) which must be framed. This field may be
CYCLE
“010” (2·t
). Refer to Figure 39 for more details.
CYCLE
written with the values “ 0111” (7·t
) through
CYCLE
“1010” (10·t
). TFRM is usually set to the value
CYCLE
which matches the largest t
parameter (modulo
RCD,MIN
4· t
) that is present in an RDRAM in the memory
CYCLE
system. Thus, if an RDRAM with t
=
RCD,MIN
11·t
were present, then TFRM would be
CYCLE
programmed to 7· t
.
CYCLE
Figure 40: TFRM Register
Figure 41: TRDLY Register
Page 36
Rev. 0.9 Apr. 1999
Preliminary
Direct RDRAM
™
KM416RD8C/KM418RD8C
Control Register: SKIP
Address: 04b
Control Register: TCYCLE
Address: 04c
16
16
0
15 14 13 12 11 10
9
0
8
0
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
0
15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
AS MSE MS
TCYCLE13..TCYCLE0
0
0
0
0
0
Read/write register (except AS field).
Reset value is zero (SIO Reset).
Read/write register.
Reset value is undefined
TCYCLE13..0 - Specifies the value of the t
datasheet parameter in 64ps units. For the t
AS - Autoskip. Read-only value determined by
autoskip circuit and stored when SETF serial command
is received by RDRAM during initialization. In figure
58, AS=1 corresponds to the early Q(a1) packet and
CYCLE
CYCLE,MIN
of 2.5ns (2500ps), this field should be written with the
AS=0 to the Q(a1) packet one t
uncertain cases.
later for the four
CYCLE
value “00027 ” (39· 64ps).
16
MSE - Manual skip enable (0=auto, 1=manual).
MS - Manual skip (MS must be 1 when MSE=1).>
During initialization, the RDRAMs at the furthest point
in the fifth read domain may have selected the AS=0
value, placing them at the closest point in a sixth read
domain. Setting the MSE/MS fields to 1/1 overrides
the autoskip value and returns them to the furthest
point of the fifth read domain.
Figure 42: SKIP Register
Figure 44: TCYCLE Register
Control Register: TEST77
Control Register: TEST78
Control Register: TEST79
Address: 04d
16
Address: 04e
Address: 04f
16
16
0
15 14 13 12 11 10
9
0
8
0
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
0
0
0
0
0
0
Read/write registers.
Reset value of TEST78,79 is zero ( SIO Reset).
Do not read or write TEST78,79 after SIO reset.
TEST77 must be written with zero after SIO reset.
These registers must only be used for testing purposes.
Figure 43: TEST Registers
Page 37
Rev. 0.9 Apr. 1999
Preliminary
Direct RDRAM
™
KM416RD8C/KM418RD8C
TCLK/RCLK block must resynchronize itself to the external
clock signal.
Power State Management
Table 17 summarizes the power states available to a Direct
RDRAM. In general, the lowest power states have the
longest operational latencies. For example, the relative
power levels of PDN state and STBY state have a ratio of
about 1:110, and the relative access latencies to get read data
have a ratio of about 250:1.
NAP state is another low-power state in which either self-
refresh or REFA-refresh are used to maintain the core. See
“Refresh” on page 43 for a description of the two refresh
mechanisms. NAP has a shorter exit latency than PDN
because the TCLK/RCLK block maintains its synchroniza-
tion state relative to the external clock signal at the time of
PDN state is the lowest power state available. The informa-
tion in the RDRAM core is usually maintained with self-
refresh; an internal timer automatically refreshes all rows of
all banks. PDN has a relatively long exit latency because the
NAP entry. This imposes a limit (t
RDRAM may remain in NAP state before briefly returning
to STBY or ATTN to update this synchronization state.
) on how long an
NLIMIT
Table 17: Power State Summary
Power
State
Power
State
Description
Blocks consuming power
Description
Blocks consuming power
PDN
Powerdown state.
Self-refresh
NAP
Nap state. Similar to PDN
except lower wake-up
latency.
Self-refresh or
REFA-refresh
TCLK/RCLK-Nap
STBY
Standby state.
Ready for ROW
packets.
REFA-refresh
TCLK/RCLK
ROW demux receiver
ATTN
Attention state.
Ready for ROW and COL
packets.
REFA-refresh
TCLK/RCLK
ROW demux receiver
COL demux receiver
ATTNR
Attention read state.
Ready for ROW and COL
packets.
Sending Q (read data)
packets.
REFA-refresh
TCLK/RCLK
ROW demux receiver
COL demux receiver
DQ mux transmitter
Core power
ATTNW
Attention write state.
Ready for ROW and COL
packets.
Ready for D (write data)
packets.
REFA-refresh
TCLK/RCLK
ROW demux receiver
COL demux receiver
DQ demux receiver
Core power
Figure 45 summarizes the transition conditions needed for
moving between the various power states. Note that NAP
and PDN have been divided into two substates (NAP-
A/NAP-S and PDN-A/PDN-S) to account for the fact that a
NAP or PDN exit may be made to either ATTN or STBY
states.
The RDRAM returns to the ATTN or STBY state it was
originally in when it first entered NAP or PDN.
An RDRAM may only remain in NAP state for a time
t
. It must periodically return to ATTN or STBY.
NLIMIT
The NAPRC command causes a napdown operation if the
RDRAM’s NCBIT is set. The NCBIT is not directly visible.
It is undefined on reset. It is set by a NAPR command to the
RDRAM, and it is cleared by an ACT command to the
RDRAM. It permits a controller to manage a set of
RDRAMs in a mixture of power states.
At initialization, the SETR/CLRR Reset sequence will put
the RDRAM into PDN-S state. The PDN exit sequence
involves an optional PDEV specification and bits on the
CMD and SIO pins.
IN
Once the RDRAM is in STBY, it will move to the
STBY state is the normal idle state of the RDRAM. In this
state all banks and sense amps have usually been left
precharged and ROWA and ROWR packets on the ROW
pins are being monitored. When a non-broadcast ROWA
packet or non-broadcast ROWR packet (with the ATTN
command) packet addressed to the RDRAM is seen, the
RDRAM enters ATTN state (see the right side of Figure 46).
ATTN/ATTNR/ATTNW states when it receives a non-
broadcast ROWA packet or non-broadcast ROWR packet
with the ATTN command. The RDRAM returns to STBY
from these three states when it receives a RLX command.
Alternatively, it may enter NAP or PDN state from ATTN or
STBY states with a NAPR or PDNR command in an ROWR
packet. The PDN or NAP exit sequence involves an optional
PDEV specification and bits on the CMD and SIO0 pins.
This requires a time t during which the RDRAM activates
SA
the specified row of the specified bank. A time
TFRM·t
after the ROW packet, the RDRAM will be
CYCLE
Page 38
Rev. 0.9 Apr. 1999
Preliminary
Direct RDRAM
™
KM416RD8C/KM418RD8C
able to frame COL packets (TFRM is a control register field
- see Figure 40). Once in ATTN state, the RDRAM will
automatically transition to the ATTNW and ATTNR states
as it receives WR and RD commands.
provided for power calculation purposes). The clock on
CTM/CFM must remain stable for a time t after the
CD
NAPR command.
The RDRAM may be in ATTN or STBY state when the
NAPR command is issued. When NAP state is exited, the
RDRAM will return to the original starting state (ATTN or
STBY). If it is in ATTN state and a RLXR command is
specified with NAPR, then the RDRAM will return to STBY
state when NAP is exited.
automatic
ATTNR
ATTN
ATTNW
automatic
Figure 47 also shows the PDN entry sequence (right). PDN
state is entered by sending a PDNR command in a ROW
tNLIMIT
packet. A time t
is required to enter PDN state (this spec-
ASP
NAPR • RLXR
ification is provided for power calculation purposes). The
NAP-A
clock on CTM/CFM must remain stable for a time t after
CD
PDEV.CMD•SIO0
NAPR • RLXR
the PDNR command.
NAP
The RDRAM may be in ATTN or STBY state when the
PDNR command is issued. When PDN state is exited, the
RDRAM will return to the original starting state (ATTN or
STBY). If it is in ATTN state and a RLXR command is
specified with PDNR, then the RDRAM will return to STBY
state when PDN is exited. The current- and slew-rate-control
levels are re-established.
NAP-S
PDEV.CMD•SIO0
PDNR • RLXR
PDEV.CMD•SIO0
PDNR • RLXR
PDN-A
PDN
PDN-S
PDEV.CMD•SIO0
The RDRAM’s write buffer must be retired with the appro-
priate COP command before NAP or PDN are entered. Also,
all the RDRAM’s banks must be precharged before NAP or
PDN are entered. The exception to this is if NAP is entered
with the NSR bit of the INIT register cleared (disabling self-
refresh in NAP). The commands for relaxing, retiring, and
precharging may be given to the RDRAM as late as the
ROPa0, COPa0, and XOPa0 packets in Figure 47. No broad-
cast packets nor packets directed to the RDRAM entering
Nap or PDN may overlay the quiet window. This window
SETR/CLRR
STBY
Notation:
SETR/CLRR - SETR/CLRR Reset sequence in SRQ packets
PDNR - PDNR command in ROWR packet
NAPR - NAPR command in ROWR packet
RLXR - RLX command in ROWR packet
RLX - RLX command in ROWR,COLC,COLX packets
SIO0 - SIO0 input value
PDEV.CMD - (PDEV=DEVID)•(CMD=01)
ATTN - ROWA packet (non-broadcast) or ROWR packet
(non-broadcast) with ATTN command
extends for a time t
PDNR command.
after the packet with the NAPR or
NPQ
Figure 45: Power State Transition Diagram
Figure 48 shows the NAP and PDN exit sequences. These
sequences are virtually identical; the minor differences will
be highlighted in the following description.
Once the RDRAM is in ATTN, ATTNW, or ATTNR states,
it will remain there until it is explicitly returned to the STBY
state with a RLX command. A RLX command may be given
in an ROWR, COLC , or COLX packet (see the left side of
Figure 46). It is usually given after all banks of the RDRAM
have been precharged; if other banks are still activated, then
the RLX command would probably not be given.
Before NAP or PDN exit, the CTM/CFM clock must be
stable for a time t . Then, on a falling and rising edge of
CE
SCK, if there is a “ 01” on the CMD input, NAP or PDN state
will be exited. Also, on the falling SCK edge the SIO0 input
must be at a 0 for NAP exit and 1 for PDN exit.
If a broadcast ROWA packet or ROWR packet (with the
ATTN command) is received, the RDRAM’s power state
doesn’t change. If a broadcast ROWR packet with RLXR
command is received, the RDRAM goes to STBY.
If the PSX bit of the INIT register is 0, then a device
PDEV5..0 is specified for NAP or PDN exit on the DQA5..0
pins. This value is driven on the rising SCK edge 0.5 or 1.5
SCK cycles after the original falling edge, depending upon
the value of the DQS bit of the NAPX register. If the PSX bit
of the INIT register is 1, then the RDRAM ignores the
Figure 47 shows the NAP entry sequence (left). NAP state is
entered by sending a NAPR command in a ROW packet. A
time t
is required to enter NAP state (this specification is
ASN
Page 39
Rev. 0.9 Apr. 1999
Preliminary
Direct RDRAM
™
KM416RD8C/KM418RD8C
PDEV5..0 address packet and exits NAP or PDN when the
wake-up sequence is presented on the CMD wire. The ROW
Figure 49 shows the constraints for entering and exiting
NAP and PDN states. On the left side, an RDRAM exits
and COL pins must be quiet at a time t /t around the indi-
NAP state at the end of cycle T . This RDRAM may not re-
3
S4 H4
cated falling SCK edge (timed with the PDNX or NAPX
register fields). After that, ROW and COL packets may be
directed to the RDRAM which is now in ATTN or STBY
state.
enter NAP or PDN state for an interval of t
RDRAM enters NAP state at the end of cycle T . This
RDRAM may not re-exit NAP state for an interval of t
The equations for these two parameters depend upon a
. The
NU0
13
.
NU1
number of factors, and are shown at the bottom of the figure.
NAPX is the value in the NAPX field in the NAPX register.
T
T1 T2 T3 T T5 T6 T7 T T9 T10 T11 T T13 T14 T1
TT1 T2 T3
4 8 12
0
T T5 T6 T7 T T9 T10 T11 T T13 T14 T15 T
4 8 12 16
0
CTM/CFM
CTM/CFM
ROP = non-broadcast ROWA
or ROWR/ATTN
a0 = {d0,b0,r0}
a1 = {d1,b1,c1}
ROW2
ROW2
RLXR
ROP a0
..ROW0
..ROW0
No COL packets may be
placed in the three
COP a1
COP a1
1
indicated positions; i.e. at
COP a1
COL4
..COL0
COL4
..COL0
RLXC
RLXX
COP a1 COP a0
(TFRM - {1,2,3})•t
.
CYCLE
XOP a1
XOP a0
A COL packet to device d0
(or any other device) is okay
at
TFRM•t
CYCLE
DQA8..0
DQB8..0
DQA8..0
DQB8..0
(TFRM)•t
CYCLE
or later.
t
t
SA
AS
A COL packet to another
device (d1!= d0) is okay at
(TFRM - 4)•t
CYCLE
Power
State
Power
State
ATTN
ATTN
STBY
STBY
or earlier.
Figure 46: STBY Entry (left) and STBY Exit (right)
T
T1 T2 T3
T
T5 T6 T7
T
T9 T10 T11
T
T13 T14 T1
TT1 T2 T3
0
T
T5 T6 T7
T
T9 T10 T11
T
T13 T1
0
4
8
12
4
8
12
CTM/CFM
CTM/CFM
a0 = {d0,b0,r0,c0}
a1 = {d1,b1,r1,c1}
t
t
CD
CD
No ROW or COL packets
directed to device d0 may
overlap the restricted
interval. No broadcast ROW
packets may overlap the quiet
interval.
ROW2
..ROW0
ROW2
..ROW0
ROP a0 restricted ROP a1
ROP a0 restricted ROP a1
(NAPR)
(PDNR)
t
t
NPQ
NPQ
COL4
..COL0
COL4
..COL0
COP a0
XOP a0
COP a1
XOP a1
COP a0
XOP a0
COP a1
XOP a1
restricted
restricted
ROW or COL packets to a
device other than d0 may
overlap the restricted
interval.
DQA8..0
DQB8..0
DQA8..0
DQB8..0
ROW or COL packets
directed to device d0 after the
restricted interval will be
ignored.
t
t
ASN
ASP
Power
State
Power
State
a
a
ATTN/STBY
NAP
ATTN/STBY
PDN
a The (eventual) NAP/PDN exit will be to the same ATTN/STBY state the RDRAM was in prior to NAP/PDN entry
Figure 47: NAP Entry (left) and PDN Entry (right)
On the right side of Figure 48, an RDRAM exits PDN state
at the end of cycle T . This RDRAM may not re-enter PDN
exit PDN state for an interval of t . The equations for
PU1
these two parameters depend upon a number of factors, and
are shown at the bottom of the figure. PDNX is the value in
the PDNX field in the PDNX register.
3
or NAP state for an interval of t . The RDRAM enters
PU0
PDN state at the end of cycle T . This RDRAM may not re-
13
Page 40
Rev. 0.9 Apr. 1999
Preliminary
Direct RDRAM
™
KM416RD8C/KM418RD8C
T
T1 T2 T3 T T5 T6 T7 T T9 T10 T11 T T13 T14 T15 T T17 T18 T19 T T21 T22 T23 T T25 T26 T27 T T29 T30 T31 T34 T35 T T37 T38 T39 T T41 T42 T43 T T45 T46 T47
4 8 12 16 20 24 28 36 40 44
0
CTM/CFM
If PSX=1 in Init register, then
NAP/PDN exit is broadcast
(no PDEV field).
ROW2
..ROW0
No ROW packets may
overlap the restricted interval
ROP
restricted
ROP
t
t
S4 H4
No COL packets may
COL4
..COL0
COP
XOP
COP
XOP
restricted
overlap the restricted interval
if device PDEV is exiting the
NAP-A or PDN-A states
t
t
t
t
S3 H3 S3 H3
t
t
S4 H4
DQA8..0
DQB8..0
b
b
PDEV5..0
PDEV5..0
t
CE
DQS=0 b,c
DQS=1 b
SCK
CMD
SIO0
SIO1
0
1
Effective setup becomes
tS4’=t S4+[PDNXA • 64 • t SCYCLE+tPDNXB,MAX]-[PDNX • 256 • t
if [PDNX • 256 • t SCYCLE] < [PDNXA • 64 • t SCYCLE+tPDNXB,MAX].
]
SCYCLE
0/1a
The packet is repeated
from SIO0 to SIO1
0/1a
(NAPX)•tSCYCLE)/(256•PDNX•t SCYCLE
)
Power
State
d
NAP/PDN
STBY/ATTN
DQS=0 b DQS=1b
c The DQS field must be written with “1” for this RDRAM.
d Exit to STBY or ATTN depends upon whether RLXR was
asserted at NAP or PDN entry time
a Use 0 for NAP exit, 1 for PDN exit
b Device selection timing slot is selected by DQS field of NAPX register
Figure 48: NAP and PDN Exit
T
T1 T2 T3
T
T5 T6 T7
T
T9 T10 T11
T
T13 T14 T15
T
T17 T18 T19
T2 T3
T
T5 T6 T7
T
T9 T10 T11
T
T13 T14 T15
T
T17 T18 T19
T
T2
0
4
8
12
16
4
8
12
16
20
CTM/CFM
CTM/CFM
NAP entry
NAPR
PDN entry
PDNR
ROW2
ROW2
..ROW0
..ROW0
SCK
SCK
NAP exit
PDN exit
0
1
0
0
1
0
1
CMD
CMD
t
t
t
t
PU0
no entry to NAP or PDN
PU1
NU0
NU1
no exit
no entry to NAP or PDN
no exit
tNU0 = 5•t CYCLE + (2+NAPX)•t SCYCLE
tPU0 = 5 • t CYCLE + (2+256 • PDNX) • t
SCYCLE
tNU1 = 8•tCYCLE - (0.5•t SCYCLE
= 23•t CYCLE
)
tPU1 = 8 • t CYCLE - (0.5 • tSCYCLE
= 23 • t CYCLE
)
if NSR=0
if NSR=1
if PSR=0
if PSR=1
Figure 49: NAP Entry/Exit Windows (left) and PDN Entry/Exit Windows (right)
Page 41
Rev. 0.9 Apr. 1999
Preliminary
Direct RDRAM
™
KM416RD8C/KM418RD8C
Note that a broadcast REFP command is issued a time t
RAS
Refresh
after the initial REFA command in order to precharge the
refreshed bank in all RDRAMs. After a bank is given a
REFA command, no other core operations (activate or
precharge) should be issued to it until it receives a REFP.
RDRAMs, like any other DRAM technology, use volatile
storage cells which must be periodically refreshed. This is
accomplished with the REFA command. Figure 50 shows an
example of this.
It is also possible to interleave refresh transactions (not
shown). In the figure, the ACT b0 command would be
The REFA command in the transaction is typically a broad-
cast command (DR4T and DR4F are both set in the ROWR
packet), so that in all devices bank number Ba is activated
with row number REFR, where REFR is a control register in
the RDRAM. When the command is broadcast and ATTN is
set, the power state of the RDRAMs (ATTN or STBY) will
remain unchanged. The controller increments the bank
address Ba for the next REFA command. When Ba is equal
to its maximum value, the RDRAM automatically incre-
ments REFR for the next REFA command.
replaced by a REFA b0 command. The b0 address would be
broadcast to all devices, and would be {Broadcast, Ba+2,
REFR}. Note that the bank address should skip by two to
avoid adjacent bank interference. A possible bank incre-
menting pattern would be: {13, 11, 9, 7, 5, 3, 1, 8, 10, 12, 14,
0, 2, 4, 6, 15, 29, 27, 25, 23, 21, 19, 17, 24, 26, 28, 30, 16,
18, 20, 22, 31}. Every time bank 31 is reached, the REFA
command would automatically increment the REFR register.
A second refresh mechanism is available for use in PDN and
NAP power states. This mechanism is called self-refresh
mode. When the PDN power state is entered, or when NAP
power state is entered with the NSR control register bit set,
then self-refresh is automatically started for the RDRAM.
On average, these REFA commands are sent once every
BBIT+RBIT
t
/2
(where BBIT are the number of bank
REF
address bits and RBIT are the number of row address bits) so
that each row of each bank is refreshed once every t
REF
interval.
Self-refresh uses an internal time base reference in the
The REFA command is equivalent to an ACT command, in
terms of the way that it interacts with other packets (see
Table 10). In the example, an ACT command is sent after
RDRAM. This causes an activate and precharge to be
BBIT+RBIT
carried out once in every t /2
interval. The
REF
REFB and REFR control registers are used to keep track of
the bank and row being refreshed.
t
to address b0, a different (non-adjacent) bank than the
RR
REFA command.
Before a controller places an RDRAM into self-refresh
mode, it should perform REFA/REFP refreshes until the
bank address is equal to the maximum value. This ensures
that no rows are skipped. When a controller returns an
RDRAM to REFA/REFP refresh, it should start with the
minimum bank address value (zero).
A second ACT command can be sent after a time t to
address c0, the same bank (or an adjacent bank) as the REFA
command.
RC
T
T1 T2 T3
T
T5 T6 T7
T
T9 T10 T11
T
T13 T14 T15
T
T17 T18 T19
T
T21 T22 T23
T
T25 T26 T27
T
T29 T30 T31 T T33 T34 T35 T T37 T41 T42 T43 T T45 T46 T47
32 36 44
0
4
8
12
16
20
24
28
CTM/CFM
t
RC
ROW2
REFA a0
ACT b0
REFP a1
ACT c0
REFA d0
..ROW0
t
t
RAS
RP
COL4
..COL0
t
RR
BBIT+RBIT
t
/2
REF
DQA8..0
DQB8..0
BBIT = # bank address bits
RBIT = # row address bits
REFB = REFB3..REFB0
REFR = REFR8..REFR0
Transaction a: REFA
Transaction b: xx
Transaction c: xx
a0 = {Broadcast,Ba,REFR}
b0 = {Db, /={Ba,Ba+1,Ba-1}, Rb}
c0 = {Dc, ==Ba, Rc}
a1 = {Broadcast,Ba}
Transaction d: REFA d0 = {Broadcast,Ba+1,REFR}
Figure 50: REFA/REFP Refresh Transaction Example
Page 42
Rev. 0.9 Apr. 1999
Preliminary
Direct RDRAM
™
KM416RD8C/KM418RD8C
samples the last calibration packet and adjusts its I current
value.
OL
Current and Temperature Control
Figure 51 shows an example of a transaction which performs
current control calibration. It is necessary to perform this
Unlike REF commands, CAL and SAM commands cannot
be broadcast. This is because the calibration packets from
different devices would interfere. Therefore, a current
operation once to every RDRAM in every t
interval in
CCTRL
order to keep the I output current in its proper range.
OL
control transaction must be sent every t
/N, where N is
CCTRL
This example uses four COLX packets with a CAL
command. These cause the RDRAM to drive four calibra-
the number of RDRAMs on the Channel. The device field
Da of the address a0 in the CAL/SAM command should be
incremented after each transaction.
tion packets Q(a0) a time t
later. An offset of t
CAC
RDTOCC
must be placed between the Q(a0) packet and read data
Q(a1)from the same device. These calibration packets are
driven on the DQA4..3 and DQB4..3 wires. The TSQ bit of
the INIT register is driven on the DQA5 wire during same
interval as the calibration packets. The remaining DQA and
DQB wires are not used during these calibration packets.
The last COLX packet also contains a SAM command
(concatenated with the CAL command). The RDRAM
Figure 52 shows an example of a temperature calibration
sequence to the RDRAM. This sequence is broadcast once
every t
interval to all the RDRAMs on the Channel.
TEMP
The TCEN and TCAL are ROP commands, and cause the
slew rate of the output drivers to adjust for temperature drift.
During the quiet interval t
the devices being cali-
TCQUIET
brated can’t be read, but they can be written.
T
T1 T2 T3 T T5 T6 T7 T T9 T10 T11 T T13 T14 T15 T T17 T18 T19 T T21 T22 T23 T T25 T26 T27 T T29 T30 T31 T T33 T34 T35 T T37 T38 T39 T 42 T43 T T45 T46 T47
4 8 12 16 20 24 28 32 36 44
0
CTM/CFM
Read data from a different
device from a later RD
command can be anywhere
after to the Q(a0) packet.
Read data from the same device
from a later RD command must
be at this packet position or
later.
Read data from the same
device from an earlier RD
command must be at this
packet position or earlier.
Read data from a different
device from an earlier RD
ROW2
..ROW0
command can be anywhere
prior to the Q(a0) packet. .
t
CCTRL
COL4
..COL0
CAL a0
CAL a0
CAL a0
CAL/SAM a0
CAL a2
CL
t
t
CAC
CCSAMTOREAD
Q (a1)
Q (a1)
Q (a0)
DQA8..0
DQB8..0
DQA5 of the first calibrate packet has the inverted TSQ bit of INIT
control register; i.e. logic 0 or high voltage means hot temperature.
When used for monitoring, it should be enabled with the DQA3
bit (current control one value) in case there is no RDRAM present:
t
READTOCC
Transaction a0: CAL/SAM
Transaction a1: RD
Transaction a2: CAL/SAM
a0 = {Da, Bx}
a1 = {Da, Bx}
a2 = {Da+1, Bx}
HotTemp = DQA5•DQA3
Figure 51: Current Control CAL/SAM Transaction Example
T
T1 T2 T3
T
T5 T6 T7
T
T9 T10 T11
T
T13 T14 T15 T T17 T18 T19 T T21 T22 T23 T T25 T26 T27 T T21 T T33 T34 T35 T T37 T38 T41 T42 T43 T T45 T46 T47
16 20 24 28 32 36 44
0
4
8
12
CTM/CFM
t
TEMP
ROW2
TCEN
TCAL
TCEN
..ROW0
t
t
TCQUIET
tTCEN
TCAL
COL4
..COL0
Any ROW packet may be placed
in the gap between the ROW
packets with the TCEN and
TCAL commands.
DQA8..0
DQB8..0
No read data from devices
being calibrated
Figure 52: Temperature Calibration (TCEN-TCAL) Transactions to RDRAM
Page 43
Rev. 0.9 Apr. 1999
Preliminary
Direct RDRAM
™
KM416RD8C/KM418RD8C
Electrical Conditions
Table 18: Electrical Conditions
Symbol
Parameter and Conditions
Min
Max
Unit
TJ
Junction temperature under bias
Supply voltage
TBD
2.50 - 0.13
-
TBD
2.50 + 0.13
2.0
°C
V
%
%
V
V
V
V
V
V
V
%
V
V
V
V
V
V
VDD, VDDA
VDD,N, VDDA,N
vDD,N, vDDA,N
VCMOS
Supply voltage droop (DC) during NAP interval (tNLIMIT
Supply voltage ripple (AC) during NAP interval (tNLIMIT
Supply voltage for CMOS pins (2.5V controllers)
Supply voltage for CMOS pins (1.8V controllers)
Termination voltage
)
)
-2.0
2.0
2.50 - 0.13
1.80 - 0.1
1.80 - 0.1
1.40 - 0.2
VREF - 0.5
VREF + 0.2
0.4
2.50 + 0.25
1.80 + 0.2
1.80 + 0.1
1.40 + 0.2
VREF - 0.2
VREF + 0.5
1.0
VTERM
VREF
Reference voltage
VDIL
RSL data input - low voltage
VDIH
RSL data input - high voltage
VDIS
RSL data input swing: VDIS = VDIH - VDIL
ADI
RSL data asymmetry: ADI = [(VDIH - VREF) + (VDIL - VREF)]/VDIS
RSL clock input - crossing point of true and complement signals
RSL clock input - common mode VCM = (VCIH+VCIL)/2
RSL clock input swing: VCIS = VCIH - VCIL (CTM,CTMN pins).
RSL clock input swing: VCIS = VCIH - VCIL (CFM,CFMN pins).
CMOS input low voltage
-10
10
VX
1.3
1.8
VCM
1.4
1.7
VCIS,CTM
VCIS,CFM
VIL,CMOS
VIH,CMOS
0.35
0.70
0.125
0.70
- 0.3
VCMOS/2 - 0.25
VCMOS+0.3
CMOS input high voltage
VCMOS/2 + 0.25
Timing Conditions
Table 19: Timing Conditions
Symbol
Parameter
Min
Max
Unit
Figure(s)
tCYCLE
CTM and CFM cycle times (-600)
CTM and CFM cycle times (-800)
CTM and CFM input rise and fall times
CTM and CFM high and low times
3.33
2.50
0.2
3.83
3.40
0.5
ns
ns
Figure 53
Figure 53
Figure 53
Figure 53
tCR, tCF
tCH, tCL
tTR
ns
40%
60%
tCYCLE
tCYCLE
CTM-CFM differential (MSE/MS=0/0)
CTM-CFM differential (MSE/MS=1/1)a
0.0
0.9
1.0
1.0
Figure 42
Figure 53
tDCW
Domain crossing window
-0.1
0.2
0.1
0.65
-
tCYCLE
ns
Figure 59
Figure 54
Figure 54
tDR, tDF
tS, tH
DQA/DQB/ROW/COL input rise/fall times
DQA/DQB/ROW/COL-to-CFM setup/hold @ tCYCLE=2.5ns
@ tCYCLE=3.33ns
0.190
0.275b
ns
Page 44
Rev. 0.9 Apr. 1999
Preliminary
Direct RDRAM
™
KM416RD8C/KM418RD8C
Table 19: Timing Conditions
Symbol
Parameter
Min
Max
Unit
Figure(s)
tDR1, tDF1
tDR2, tDF2
tCYCLE1
SIO0, SIO1 input rise and fall times
-
-
5.0
ns
ns
Figure 56
Figure 56
Figure 56
Figure 56
Figure 56
Figure 56
Figure 56
Figure 56
Figure 56
CMD, SCK input rise and fall times
2.0
-
SCK cycle time - Serial control register transactions
SCK cycle time - Power transitions
1000
10
4.25
1
ns
-
ns
tCH1, tCL1
tS1
SCK high and low times
-
ns
CMD setup time to SCK rising or falling edgec
CMD hold time to SCK rising or falling edgec
SIO0 setup time to SCK falling edge
-
ns
tH1
1
-
ns
tS2
40
40
0
-
ns
tH2
SIO0 hold time to SCK falling edge
-
ns
tS3
PDEV setup time on DQA5..0 to SCK rising edge.
PDEV hold time on DQA5..0 to SCK rising edge.
ROW2..0, COL4..0 setup time for quiet windowd
ROW2..0, COL4..0 hold time for quiet window
-
ns
Figure 48,
Figure 57
tH3
5.5
-1
-
ns
tS4
-
tCYCLE
tCYCLE
V
Figure 48
Figure 48
tH4
5
-
vIL,CMOS
CMOS input low voltage - over/undershoot voltage duration is less
than or equal to 5ns
- 0.7
VCMOS/2 -
0.6
vIH,CMOS
CMOS input high voltage - over/undershoot voltage duration is
less than or equal to 5ns
VCMOS/2
+ 0.6
VCMOS
0.7
+
V
tNPQ
Quiet on ROW/COL bits during NAP/PDN entry
Offset between read data and CC packets (same device)
Offset between CC packet and read data (same device)
CTM/CFM stable before NAP/PDN exit
CTM/CFM stable after NAP/PDN entry
ROW packet to COL packet ATTN framing delay
Maximum time in NAP mode
4
12
8
-
tCYCLE
tCYCLE
tCYCLE
tCYCLE
tCYCLE
tCYCLE
ms
Figure 47
Figure 51
Figure 51
Figure 48
Figure 47
Figure 46
Figure 45
Figure 50
Figure 51
Figure 52
Figure 52
Figure 52
Figure 52
page 28
tREADTOCC
tCCSAMTOREAD
tCE
-
-
2
-
tCD
100
7
-
tFRM
-
10.0
32
tNLIMIT
tREF
tCCTRL
tTEMP
Refresh interval
ms
Current control interval
34 tCYCLE
100ms
100
-
ms/tCYCLE
ms
Temperature control interval
tTCEN
TCE command to TCAL command
TCAL command to quiet window
150
6
tCYCLE
tCYCLE
tCYCLE
ms
tTCAL
6
tTCQUIET
tPAUSE
Quiet window (no read data)
140
-
RDRAM delay (no RSL operations allowed)
200.0
a. MSE/MS are fields of the SKIP register. For this combination (skip override) the tDCW parameter range is effectively 0.0 to 0.0.
b. This parameter also applies to a -800 part when operated with tCYCLE=3.33ns. Timing parameters for other tCYCLE values can be determined by inter-
polation between or extrapolation from the timings at tCYCLE=2.5ns and tCYCLE=3.33ns
c. With VIL,CMOS=0.5VCMOS-0.6V and VIH,CMOS=0.5VCMOS+0.6V
d. Effective setup becomes tS4 ’ =tS4+[PDNXA•64•t SCYCLE+tPDNXB,MAX]-[PDNX•256•t SCYCLE
]
if [PDNX•256•t SCYCLE] < [PDNXA•64•t SCYCLE+tPDNXB,MAX]. See Figure 48.
Page 45
Rev. 0.9 Apr. 1999
Preliminary
Direct RDRAM
™
KM416RD8C/KM418RD8C
Electrical Characteristics
Table 20: Electrical Characteristics
Symbol
Parameter and Conditions
Min
Max
Unit
QJC
Junction-to-Case thermal resistance
VREF current @ VREF,MAX
TBD
10
°C/Watt
mA
mA
mA
mA
W
IREF
-10
IOH
RSL output high current @ (0£VOUT£VDD
)
-10
10
a
IALL
RSL IOL current @ VOL = 0.9V, VDD,MIN , TJ,MAX
RSL IOL current resolution step
30.0
90.0
1.5
-
DIOL
-
150
rOUT
Dynamic output impedance
II,CMOS
VOL,CMOS
VOH,CMOS
CMOS input leakage current @ (0£VI,CMOS£VCMOS
CMOS output voltage @ IOL,CMOS= 1.0mA
)
-10.0
-
10.0
0.3
-
mA
V
CMOS output high voltage @ IOH,CMOS= -0.25mA
VCMOS-0.3
V
a. This measurement is made in manual current control mode; i.e. with all output device legs sinking current.
Timing Characteristics
Table 21: Timing Characteristics
Symbol
Parameter
Min
Max
Unit
Figure(s)
tQ
CTM-to-DQA/DQB output time
@ tCYCLE=2.5ns
@ tCYCLE=3.33ns
-0.260
+0.260
ns
Figure 55
-0.350a
+0.350a
tQR, tQF
tQ1
DQA/DQB output rise and fall times
0.2
-
0.45
10
5
ns
ns
Figure 55
Figure 58
Figure 58
Figure 58
Figure 48
Figure 48
Figure 48
Figure 48
Figure 46
Figure 46
Figure 47
Figure 47
SCK-to-SIO0 delay @ CLOAD,MAX = 20pF (SD read packet).
SIOOUT rise/fall @ CLOAD,MAX = 20pF
SIO0-to-SIO1 or SIO1-to-SIO0 delay @ CLOAD,MAX = 20pF
NAP exit delay - phase A
tQR1, tQF1
tPROP1
tNAPXA
tNAPXB
tPDNXA
tPDNXB
tAS
-
ns
-
10
50
40
4
ns
-
ns
NAP exit delay - phase B
-
ns
PDN exit delay - phase A
-
ms
PDN exit delay - phase B
-
9000
1
tCYCLE
tCYCLE
tCYCLE
tCYCLE
tCYCLE
ATTN-to-STBY power state delay
STBY-to-ATTN power state delay
ATTN/STBY-to-NAP power state delay
ATTN/STBY-to-PDN power state delay
-
tSA
-
0
tASN
-
8
tASP
-
8
a. This parameter also applies to a -800 part when operated with tCYCLE=3.33ns. Timing parameters for other tCYCLE values can be determined by inter-
polation between or extrapolation from the timings at tCYCLE=2.5ns and tCYCLE=3.33ns
Page 46
Rev. 0.9 Apr. 1999
Preliminary
Direct RDRAM
™
KM416RD8C/KM418RD8C
Most timing is measured relative to the points where they
RSL - Clocking
cross. The t
parameter is measured from the falling
CYCLE
Figure 53 is a timing diagram which shows the detailed
requirements for the RSL clock signals on the Channel.
CTM edge to the falling CTM edge. The t and t param-
CL
CH
eters are measured from falling to rising and rising to falling
edges of CTM. The t and t rise- and fall-time parame-
CR
CF
The CTM and CTMN are differential clock inputs used for
transmitting information on the DQA and DQB, outputs.
ters are measured at the 20% and 80% points.
t
CYCLE
t
t
CH
CL
t
t
CR
CR
CTM
V
CIH
80%
50%
20%
V
X-
V
CM
V
X+
V
CIL
CTMN
CFM
t
t
CF
CF
t
TR
t
t
CR
CR
V
CIH
80%
50%
20%
V
X-
V
CM
V
X+
V
CIL
CFMN
t
t
CF
CF
t
t
CH
CL
t
CYCLE
Figure 53: RSL Timing - Clock Signals
The CFM and CFMN are differential clock outputs used for
receiving information on the DQA, DQB, ROW and COL
outputs. Most timing is measured relative to the points
The t parameter specifies the phase difference that may be
tolerated with respect to the CTM and CFM differential
clock inputs (the CTM pair is always earlier).
TR
where they cross. The t
parameter is measured from
CYCLE
the falling CFM edge to the falling CFM edge. The t and
CL
t
parameters are measured from falling to rising and rising
CH
to falling edges of CFM. The t and t rise- and fall-time
CR
CF
parameters are measured at the 20% and 80% points.
Page 47
Rev. 0.9 Apr. 1999
Preliminary
Direct RDRAM
™
KM416RD8C/KM418RD8C
The set/hold window of the sample points is t /t The
sample points are centered at the 0% and 50% points of a
S
H.
RSL - Receive Timing
Figure 54 is a timing diagram which shows the detailed
requirements for the RSL input signals on the Channel.
cycle, measured relative to the crossing points of the falling
CFM clock edge. The set and hold parameters are measured
at the V
voltage point of the input transition.
REF
The DQA, DQB, ROW, and COL signals are inputs which
receive information transmitted by a Direct RAC on the
The t and t rise- and fall-time parameters are measured
DR
DF
Channel. Each signal is sampled twice per t
interval.
at the 20% and 80% points of the input transition.
CYCLE
CFM
V
CIH
80%
50%
20%
V
X-
V
CM
V
X+
V
CIL
CFMN
0.5•t
DQA
DQB
ROW
COL
CYCLE
t
DR
t
t
t
H
t
S
S
H
V
DIH
80%
even
odd
V
REF
20%
V
DIL
t
DF
Figure 54: RSL Timing - Data Signals for Receive
Page 48
Rev. 0.9 Apr. 1999
Preliminary
Direct RDRAM
™
KM416RD8C/KM418RD8C
25% point and at the 75% point of the current cycle. These
transmit points are measured relative to the crossing points
of the falling CTM clock edge. The size of the actual
RSL - Transmit Timing
Figure 55 is a timing diagram which shows the detailed
requirements for the RSL output signals on the Channel.
transmit window is less than the ideal t
/2, as indicated
CYCLE
by the non-zero values of t
eters are measured at the V
transition.
and t
. The t param-
Q,MIN
Q,MAX Q
The DQA and DQB signals are outputs to transmit informa-
tion that is received by a Direct RAC on the Channel. Each
voltage point of the output
REF
signal is driven twice per t
interval. The beginning
CYCLE
and end of the even transmit window is at the 75% point of
the previous cycle and at the 25% point of the current cycle.
The beginning and end of the odd transmit window is at the
The t and t rise- and fall-time parameters are measured
at the 20% and 80% points of the output transition.
QR
QF
CTM
V
CIH
80%
50%
20%
V
X-
V
CM
V
X+
V
CIL
CTMN
0.75•t
0.75•t
CYCLE
CYCLE
0.25•t
CYCLE
t
t
Q,MAX
Q,MAX
DQA
DQB
t
QR
t
t
Q,MIN
Q,MIN
V
QH
80%
50%
20%
even
odd
V
QL
t
QF
Figure 55: RSL Timing - Data Signals for Transmit
Page 49
Rev. 0.9 Apr. 1999
Preliminary
Direct RDRAM
™
KM416RD8C/KM418RD8C
50% level. The rise and fall times of SCK, CMD, and SIO0
are t and t , measured at the 20% and 80% levels.
CMOS - Receive Timing
DR1
DF1
Figure 56 is a timing diagram which shows the detailed
requirements for the CMOS input signals .
The CMD signal is sampled twice per t
the rising edge (odd data) and the falling edge (even data).
interval, on
CYCLE1
The CMD and SIO0 signals are inputs which receive infor-
mation transmitted by a controller (or by another RDRAM’s
SIO1 output. SCK is the CMOS clock signal driven by the
controller. All signals are high true.
The set/hold window of the sample points is t /t The
SCK and CMD timing points are measured at the 50% level.
S1 H1.
The SIO0 signal is sampled once per t
interval on the
CYCLE1
falling edge. The set/hold window of the sample points is
The cycle time, high phase time, and low phase time of the
t /t The SCK and SIO0 timing points are measured at the
S2 H2.
SCK clock are t
, t
and t , all measured at the
50% level.
CYCLE1 CH1 CL1
t
DR2
V
IH,CMOS
SCK
80%
50%
20%
t
CYCLE1
V
IL,CMOS
t
t
t
CH1
CL1
DF2
t
t
t
t
H1
t
DR2
S1
S1
H1
V
IH,CMOS
CMD
80%
even
odd
50%
20%
V
IL,CMOS
t
DF2
t
t
t
DR1
S2
H2
V
IH,CMOS
SIO0
80%
50%
20%
V
IL,CMOS
t
DF1
Figure 56: CMOS Timing - Data Signals for Receive
Page 50
Rev. 0.9 Apr. 1999
Preliminary
Direct RDRAM
™
KM416RD8C/KM418RD8C
The SCK clock is also used for sampling data on RSL inputs
in one situation. Figure 48 shows the PDN and NAP exit
sequences. If the PSX field of the INIT register is one (see
Figure 27), then the PDN and NAP exit sequences are broad-
cast; i.e. all RDRAMs that are in PDN or NAP will perform
the exit sequence. If the PSX field of the INIT register is
zero, then the PDN and NAP exit sequences are directed; i.e.
only one RDRAM that is in PDN or NAP will perform the
exit sequence.
The address of that RDRAM is specified on the DQA[5:0]
bus in the set hold window t /t around the rising edge of
S3 H3
SCK. This is shown in Figure 57. The SCK timing point is
measured at the 50% level, and the DQA[5:0] bus signals are
measured at the V
level.
REF
V
IH,CMOS
SCK
80%
50%
20%
V
IL,CMOS
t
t
S3
H3
V
DIH
DQA[5:0]
80%
PDEV
V
REF
20%
V
DIL
Figure 57: CMOS Timing - Device Address for NAP or PDN Exit
Page 51
Rev. 0.9 Apr. 1999
Preliminary
Direct RDRAM
™
KM416RD8C/KM418RD8C
clock-to-output window is t
SIO0 timing points are measured at the 50% level. The rise
/t
The SCK and
Q1,MIN Q1,MAX.
CMOS - Transmit Timing
Figure 58 is a timing diagram which shows the detailed
requirements for the CMOS output signals. The SIO0 signal
and fall times of SIO0 are t
20% and 80% levels.
and t , measured at the
QF1
QR1
is driven once per t
interval on the falling edge. The
CYCLE1
V
IH,CMOS
SCK
80%
50%
20%
V
IL,CMOS
t
t
Q1,MAX
Q1,MIN
t
QR1
V
OH,CMOS
SIO0
80%
50%
20%
V
OL,CMOS
t
QF1
t
DR1
V
IH,CMOS
SIO0
or
80%
SIO1
50%
20%
V
IL,CMOS
t
t
PROP1,MIN
t
PROP1,MAX
DF1
t
QR1
V
OH,CMOS
SIO1
or
80%
SIO0
50%
20%
V
OL,CMOS
t
QF1
Figure 58: CMOS Timing - Data Signals for Transmit
Page 52
Rev. 0.9 Apr. 1999
Preliminary
Direct RDRAM
™
KM416RD8C/KM418RD8C
Figure 58 also shows the combinational path connecting
SIO0 to SIO1 and the path connecting SIO1 to SIO0 (read
the delay between a RD command packet and read data
packet varies as a function of the t value.
TR
data only). The t
parameter specified this propagation
PROP1
Figure 59 shows this timing for five distinct values of t
.
TR
delay. The rise and fall times of SIO0 and SIO1 inputs must
be t and t , measured at the 20% and 80% levels. The
Case A (t =0) is what has been used throughout this docu-
TR
DR1
DF1
ment. The delay between the RD command and read data is
rise and fall times of SIO0 and SIO1 outputs are t
and
QR1
t
. As t varies from zero to t
(cases A through
CAC
TR
CYCLE
t
, measured at the 20% and 80% levels.
QF1
E), the command to data delay is (t
-t ). When the t
TR
CAC TR
value is in the range 0 to t
, the command to data
). This is shown as cases
DCW,MAX
RSL - Domain Crossing Window
delay can also be (t
-t -t
CAC TR CYCLE
A’ and B’ (the gray packets). Similarly, when the t
value
TR
When read data is returned by the RDRAM, imformation
must cross from the receive clock domain (CFM) to the
is in the range (t
+t
) to t
, the command
CYCLE DCW,MIN
CYCLE
to data delay can also be (t
-t +t
). This is shown
CAC TR CYCLE
transmit clock domain (CTM). The t parameter permits
TR
as cases D’ and E’ (the gray packets). The RDRAM will
work reliably with either the white or gray packet timing.
The delay value is selected at initialization, and remains
fixed thereafter.
the CFM to CTM phase to vary through an entire cycle; i.e.
there is no restriction on the alignment of these two clocks.
A second parameter t
is needed in order to describe how
DCW
CFM
COL
···
t
CYCLE
RD a1
···
CTM
t
=0
=0
Case A
Case A’
DQA/B
DQA/B
TR
t
t
-t
Q(a1)
Q(a1)
CAC TR
t
TR
t
TR
-t -t
Q(a1)
Q(a1)
CAC TR CYCLE
···
CTM
t
t
=t
Case B
Case B’
DQA/B
DQA/B
TR DCW,MAX
t
t
-t
CAC TR
t
TR
=t
TR DCW,MAX
-t -t
CAC TR CYCLE
···
···
CTM
t
TR
t
=0.5•t
CYCLE
Case C
DQA/B
TR
t
-t
Q(a1)
CAC TR
CTM
t
t
=t
+t
Case D
Case D’
DQA/B
DQA/B
t
TR CYCLE DCW,MIN
t
-t
Q(a1)
TR
CAC TR
=t
+t
TR CYCLE DCW,MIN
t
-t +t
Q(a1)
CAC TR CYCLE
···
CTM
t
=t
Case E
Case E’
DQA/B
DQA/B
t
TR
TR CYCLE
t
-t
Q(a1)
CAC TR
t
=t
TR CYCLE
t
-t +t
Q(a1)
CAC TR CYCLE
Figure 59: RSL Transmit - Crossing Read Domains
Page 53
Rev. 0.9 Apr. 1999
Preliminary
Direct RDRAM
™
KM416RD8C/KM418RD8C
Timing Parameters
Table 22: Timing Parameter Summary
Min
-40
Min
-45
Min
-53
Parameter Description
Max
Units
Figure(s)
-800
-800
-600
tRC
Row Cycle time of RDRAM banks -the interval between ROWA packets with 28
28
28
-
tCYCLE
Figure 15
Figure 16
ACT commands to the same bank.
tRAS
RAS-asserted time of RDRAM bank - the interval between ROWA packet
with ACT command and next ROWR packet with PRERa command to the
same bank.
20
8
20
20
64msb tCYCLE
Figure 15
Figure 16
tRP
Row Precharge time of RDRAM banks - the interval between ROWR packet
with PRERa command and next ROWA packet with ACT command to the
same bank.
8
8
-
tCYCLE
Figure 15
Figure 16
tPP
Precharge-to-precharge time of RDRAM device - the interval between succes-
sive ROWR packets with PRERa commands to any banks of the same device.
8
8
7
8
8
9
8
8
7
-
-
-
tCYCLE
tCYCLE
tCYCLE
Figure 12
Figure 13
tRR
RAS-to-RAS time of RDRAM device - the interval between successive
ROWA packets with ACT commands to any banks of the same device.
tRCD
RAS-to-CAS Delay - the interval from ROWA packet with ACT command to
COLC packet with RD or WR command). Note - the RAS-to-CAS delay seen
by the RDRAM core (tRCD-C) is equal to tRCD-C = 1 + tRCD because of differ-
ences in the row and column paths through the RDRAM interface.
Figure 15
Figure 16
tCAC
CAS Access delay - the interval from RD command to Q read data. The equa-
tion for tCAC is given in the TPARM register in Figure 39.
8
8
8
12
tCYCLE
Figure 4
Figure 39
tCWD
tCC
CAS Write Delay (interval from WR command to D write data.
6
4
6
4
6
4
6
-
tCYCLE
tCYCLE
Figure 4
CAS-to-CAS time of RDRAM bank - the interval between successive COLC
commands).
Figure 15
Figure 16
tPACKET
tRTR
Length of ROWA, ROWR, COLC, COLM or COLX packet.
4
8
4
8
4
8
4
-
tCYCLE
tCYCLE
Figure 3
Interval from COLC packet with WR command to COLC packet which causes
retire, and to COLM packet with bytemask.
Figure 17
tOFFP
The interval (offset) from COLC packet with RDA command, or from COLC
packet with retire command (after WRA automatic precharge), or from COLC
packet with PREC command, or from COLX packet with PREX command to
the equivalent ROWR packet with PRER. The equation for tOFFP is given in
the TPARM register in Figure 39.
4
4
4
4
tCYCLE
Figure 14
Figure 39
tRDP
Interval from last COLC packet with RD command to ROWR packet with
PRER.
4
4
4
4
4
4
-
-
tCYCLE
Figure 15
Figure 16
tRTP
Interval from last COLC packet with automatic retire command to ROWR
packet with PRER.
tCYCLE
a. Or equivalent PREC or PREX command. See Figure 14.
b. This is a constraint imposed by the core, and is therefore in units of ms rather than tCYCLE
.
Page 54
Rev. 0.9 Apr. 1999
Preliminary
Direct RDRAM
™
KM416RD8C/KM418RD8C
Absolute Maximum Ratings
Table 23: Absolute Maximum Ratings
Symbol
Parameter
Min
Max
Unit
VI,ABS
Voltage applied to any RSL or CMOS pin with respect to Gnd
Voltage on VDD and VDDA with respect to Gnd
Storage temperature
- 0.3
- 0.5
- 50
VDD+0.3
VDD+1.0
100
V
V
VDD,ABS, VDDA,ABS
TSTORE
°C
IDD - Supply Current Profile
Table 24: Supply Current Profile
a
I
value
RDRAM blocks consuming power @ t
=2.5ns
CYCLE
Min
Max
Unit
DD
IDD,PDN
Self-refresh only for INIT.LSR=0
Self-refresh only for INIT.LSR= 1
T/RCLK-Nap
TBD
TBD
TBD
TBD
TBD
TBD
TBD
3300
TBD
4.4
mA
mA
IDD,PDN,L
IDD,NAP
mA
mA
mA
mA
mA
IDD,STBY
T/RCLK, ROW-demux
120
200
700
575
IDD,ATTN
T/RCLK, ROW-demux, COL-demux
IDD,ATTN-W
IDD,ATTN-R
T/RCLK, ROW-demux,COL-demux,DQ-demux,1·WR-SenseAmp,4· ACT-Bank
T/RCLK, ROW-demux,COL-demux,DQ-mux,1·RD-SenseAmp,4·ACT-Bank b
a. The CMOS interface consumes power in all power states.
b. This does not include the IOL sink current. The RDRAM dissipates IOL • VOL in each output driver when a logic one is driven.
a
I
value
RDRAM blocks consuming power @ t
=3.3ns
CYCLE
Min
Max
Unit
DD
IDD,PDN
Self-refresh only for INIT.LSR=0
Self-refresh only for INIT.LSR= 1
Refresh, T/RCLK-Nap
TBD
TBD
TBD
TBD
TBD
TBD
TBD
3300
TBD
4.4
mA
mA
IDD,PDN,L
IDD,NAP
mA
mA
mA
mA
mA
IDD,STBY
Refresh, T/RCLK, ROW-demux
100
175
600
460
IDD,ATTN
Refresh, T/RCLK, ROW-demux, COL-demux
IDD,ATTN-W
IDD,ATTN-R
Refresh,T/RCLK, ROW-demux,COL-demux,DQ-demux,1·WR-SenseAmp,4· ACT-Bank
Refresh,T/RCLK, ROW-demux,COL-demux,DQ-mux,1·RD-SenseAmp,4· ACT-Bank b
a. The CMOS interface consumes power in all power states.
b. This does not include the IOL sink current. The RDRAM dissipates IOL· VOL in each output driver when a logic one is driven.
Page 55
Rev. 0.9 Apr. 1999
Preliminary
Direct RDRAM
™
KM416RD8C/KM418RD8C
Capacitance and Inductance
Figure 60 shows the equivalent load circuit of the RSL and
CMOS pins. The circuit models the load that the device
presents to the Channel.
Pad
LI
DQA,DQB,RQ Pin
CI
RI
Gnd Pin
Pad
LI
CTM,CTMN,
CFM,CFMN Pin
CI
RI
Gnd Pin
Pad
LI,CMOS
SCK,CMD Pin
CI,CMOS
Gnd Pin
Pad
LI,CMOS
SIO0,SIO1 Pin
CI,CMOS,SIO
Gnd Pin
Figure 60: Equivalent Load Circuit for RSL Pins
Page 56
Rev. 0.9 Apr. 1999
Preliminary
Direct RDRAM
™
KM416RD8C/KM418RD8C
This circuit does not include pin coupling effects that are
often present in the packaged device. Because coupling
each RSL signal adjacent to an AC ground (a Gnd or Vdd
pin), the effective inductance must be defined based on this
effects make the effective single-pin inductance L , and
configuration. Therefore, L assumes a loop with the RSL
I
I
capacitance C , a function of neighboring pins, these param-
pin adjacent to an AC ground.
I
eters are intrinsically data-dependent. For purposes of speci-
fying the device electrical loading on the Channel, the
C is defined as the effective pin capacitance based on the
device pin assignment. It is the sum of the effective package
pin capacitance and the IO pad capacitance.
I
effective L and C are defined as the worst-case values over
I
I
all specified operating conditions.
L is defined as the effective pin inductance based on the
I
device pin assignment. Because the pad assignment places
Table 25: RSL Pin Parasitics
Parameter and Conditions - RSL pins
RSL effective input inductance
Symbol
Min
Max
Unit
L
L
4.0
0.2
0.6
2.4
2.6
nH
nH
nH
pF
I
Mutual inductance between any DQA or DQB RSL signals.
12
Mutual inductance between any ROW or COL RSL signals.
a
C
RSL effective input capacitance
-800
-600
2.0
2.0
I
C
Mutual capacitance between any RSL signals.
-
-
0.1
pF
pF
12
DC
Difference in C value between average of CTM/CFM and any
0.06
I
I
RSL pins of a single device.
R
RSL effective input resistance
4
15
W
I
a. This value is a combination of the device IO circuitry and package capacitances.
Table 26: CMOS Pin Parasitics
Parameter and Conditions - CMOS pins
CMOS effective input inductance
CMOS effective input capacitance (SCK,CMD)
Symbol
Min
Max
Unit
L
8.0
2.1
7.0
nH
I ,CMOS
a
C
C
1.7
pF
pF
I ,CMOS
I ,CMOS,SIO
a
CMOS effective input capacitance (SIO1, SIO0)
-
a. This value is a combination of the device IO circuitry and package capacitances.
Page 57
Rev. 0.9 Apr. 1999
Preliminary
Direct RDRAM
™
KM416RD8C/KM418RD8C
Center-Bonded uBGA Package
Figure 61 shows the form and dimensions of the recom-
mended package for the center-bonded CSP device class.
D
Top
A
B
C
D
E
F
G
H
J
Top
Bottom
12
11
10
9
8
7
A
6
5
4
3
2
1
e2
e1
d
E
E1
Bottom
Figure 61: Center-Bonded uBGA Package
Table 27 lists the numerical values corresponding to dimen-
sions shown in Figure 61.
Table 27: Center-Bonded uBGA Package Dimensions
Symbol
Parameter
Min(128Mb/144Mb)
Max(128Mb/144Mb)
Unit
mm
e1
e2
A
Ball pitch (x-axis)
Ball pitch (y-axis)
Package body length
Package body width
Package total thickness
Ball height
1.00
1.00
0.80
0.80
mm
mm
mm
mm
mm
mm
13.05
11.40/12.50
-
13.25
11.60/12.70
1.00
D
E
E1
d
0.20
0.30
Ball diameter
0.30
0.40
Page 58
Rev. 0.9 Apr. 1999
Preliminary
Direct RDRAM
™
KM416RD8C/KM418RD8C
controller
A logic-device which drives the
ROW/COL /DQ wires for a Channel of
RDRAMs.
Glossary of Terms
ACT
Activate command from AV field.
COP
Column opcode field in COLC packet.
activate
adjacent
To access a row and place in sense amp.
core
The banks and sense amps of an RDRAM.
Clock pins for transmitting packets.
Two RDRAM banks which share sense
amps (also called doubled banks).
CTM,CTMN
ASYM
ATTN
CCA register field for RSL V /V
.
current control Periodic operations to update the proper
value of RSL output drivers.
OL OH
I
OL
Power state - ready for ROW/COL
packets.
D
Write data packet on DQ pins.
CNFGB register field - doubled-bank.
Device address field in COLC packet.
An RDRAM on a Channel.
ATTNR
ATTNW
AV
Power state - transmitting Q packets.
Power state - receiving D packets.
DBL
DC
Opcode field in ROW packets.
device
DEVID
RBIT CBIT
bank
A block of 2
•2
storage cells in the
Control register with device address that is
matched against DR, DC, and DX fields.
core of the RDRAM.
BC
Bank address field in COLC packet.
DM
Device match for ROW packet decode.
BBIT
CNFGA register field - # bank address
bits.
doubled-bank RDRAM with shared sense amp.
DQ
DQA and DQB pins.
broadcast
BR
An operation executed by all RDRAMs.
Bank address field in ROW packets.
DQA
DQB
DQS
Pins for data byte A.
Pins for data byte B.
bubble
Idle cycle(s) on RDRAM pins needed
because of a resource constraint.
NAPX register field - PDN/NAP exit.
DR,DR4T,DR4F Device address field and packet framing
BYT
BX
CNFGB register field - 8/9 bits per byte.
Bank address field in COLX packet.
Column address field in COLC packet.
fields in ROWA and ROWR packets.
dualoct
DX
16 bytes - the smallest addressable datum.
Device address field in COLX packet.
A collection of bits in a packet.
C
CAL
CBIT
Calibrate (I ) command in XOP field.
OL
field
INIT
CNFGB register field - # column address
bits.
Control register with initialization fields.
initialization Configuring a Channel of RDRAMs so
CCA
Control register - current control A.
Control register - current control B.
Clock pins for receiving packets.
they are ready to respond to transactions.
CCB
LSR
CNFGA register field - low-power self-
refresh.
CFM,CFMN
Channel
CLRR
CMD
ROW/COL/DQ pins and external wires.
Clear reset command from SOP field.
CMOS pin for initialization/power control.
Control register with configuration fields.
Control register with configuration fields.
Pins for column-access control.
M
Mask opcode field (COLM/COLX packet).
Field in COLM packet for masking byte A.
Field in COLM packet for masking byte B.
Mask command in M field.
MA
MB
CNFGA
CNFGB
COL
MSK
MVER
NAP
Control register - manufacturer ID.
Power state - needs SCK/CMD wakeup.
Nap command in ROP field.
COL
COLC,COLM,COLX packet on COL pins.
Column operation packet on COL pins.
Write mask packet on COL pins.
NAPR
NAPRC
NAPXA
NAPXB
NOCOP
NOROP
COLC
COLM
column
Conditional nap command in ROP field.
NAPX register field - NAP exit delay A.
NAPX register field - NAP exit delay B.
No-operation command in COP field.
No-operation command in ROP field.
Rows in a bank or activated row in sense
CBIT
amps have 2
dualocts column storage.
command
COLX
A decoded bit-combination from a field.
Extended operation packet on COL pins.
Page 59
Rev. 0.9 Apr. 1999
Preliminary
Direct RDRAM
™
KM416RD8C/KM418RD8C
NOXOP
NSR
No-operation command in XOP field.
INIT register field- NAP self-refresh.
A collection of bits carried on the Channel.
Power state - needs SCK/CMD wakeup.
Powerdown command in ROP field.
Control register - PDN exit delay A.
Control register - PDN exit delay B.
ROWR
RQ
Row operation packet on ROW pins.
Alternate name for ROW/COL pins.
Rambus Signaling Levels.
packet
PDN
RSL
SAM
SA
Sample (I ) command in XOP field.
OL
PDNR
PDNXA
PDNXB
Serial address packet for control register
transactions w/ SA address field.
SBC
SCK
SD
Serial broadcast field in SRQ.
CMOS clock pin..
pin efficiency The fraction of non-idle cycles on a pin.
Serial data packet for control register
transactions w/ SD data field.
PRE
PREC,PRER,PREX precharge commands.
Precharge command in COP field.
PREC
precharge
PRER
PREX
PSX
SDEV
Serial device address in SRQ packet.
INIT register field - Serial device ID.
Refresh mode for PDN and NAP.
Prepares sense amp and bank for activate.
Precharge command in ROP field.
SDEVID
self-refresh
sense amp
SETF
Precharge command in XOP field.
Fast storage that holds copy of bank’s row.
Set fast clock command from SOP field.
Set reset command from SOP field.
INIT register field - PDN/NAP exit.
INIT register field - PDN self-refresh.
CNFGB register field - protocol version.
Read data packet on DQ pins.
PSR
SETR
PVER
Q
SINT
Serial interval packet for control register
read/write transactions.
SIO0,SIO1
SOP
CMOS serial pins for control registers.
Serial opcode field in SRQ.
R
Row address field of ROWA packet.
CNFGB register field - # row address bits.
Read (/precharge) command in COP field.
Operation of accesssing sense amp data.
RBIT
RD/RDA
read
SRD
Serial read opcode command from SOP.
INIT register field - Serial repeat bit.
SRP
SRQ
Serial request packet for control register
read/write transactions.
receive
Moving information from the Channel into
the RDRAM (a serial stream is demuxed).
STBY
Power state - ready for ROW packets.
Control register - stepping version.
Serial write opcode command from SOP.
REFA
Refresh-activate command in ROP field.
Control register - next bank (self-refresh).
SVER
REFB
SWR
REFBIT
CNFGA register field - ignore bank bits
(for REFA and self-refresh).
TCAS
TCLSCAS register field - t
TCLSCAS register field - t
core delay.
core delay.
CAS
CLS
REFP
REFR
refresh
retire
Refresh-precharge command in ROP field.
Control register - next row for REFA.
Periodic operations to restore storage cells.
TCLS
TCLSCAS
TCYCLE
TDAC
Control register - t
Control register - t
Control register - t
and t
delays.
CLS
CAS
delay.
CYCLE
The automatic operation that stores write
buffer into sense amp after WR command.
delay.
DAC
TEST77
TEST78
TRDLY
transaction
Control register - for test purposes.
Control register - for test purposes.
RLX
RLXC,RLXR,RLXX relax commands.
Relax command in COP field.
Relax command in ROP field.
Relax command in XOP field.
RLXC
RLXR
RLXX
ROP
Control register - t
delay.
RDLY
ROW,COL,DQ packets for memory
access.
Row-opcode field in ROWR packet.
transmit
Moving information from the RDRAM
onto the Channel (parallel word is muxed).
CBIT
row
2
dualocts of cells (bank/sense amp).
WR/WRA
write
Write (/precharge) command in COP field.
Operation of modifying sense amp data.
Extended opcode field in COLX packet
ROW
ROW
ROWA
Pins for row-access control
ROWA or ROWR packets on ROW pins.
Activate packet on ROW pins.
XOP
Page 60
Rev. 0.9 Apr. 1999
Preliminary
Direct RDRAM
™
KM416RD8C/KM418RD8C
Capacitance and Inductance . . . . . . . . . . . . . . . .56-57
Edge-Bonded mBGA Package . . . . . . . . . . . . . . . . 58
Edge-Bonded mBGA Package . . . . . . . . . . . . . . . . 59
Glossary of Terms . . . . . . . . . . . . . . . . . . . . . . . .60-61
Table Of Contents
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Key Timing Parameters/Part Numbers . . . . . . . . . . . 1
Pinouts and Definitions . . . . . . . . . . . . . . . . . . . . . . . 2
Pin Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
General Description . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Packet Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6,7
Field Encoding Summary. . . . . . . . . . . . . . . . . . . . .8,9
DQ Packet Timing . . . . . . . . . . . . . . . . . . . . . . . . . . 10
COLM Packet to D Packet Mapping . . . . . . . . . .10,11
ROW-to-ROW Packet Interaction . . . . . . . . . . . 12, 13
ROW-to-COL Packet Interaction . . . . . . . . . . . . . . . 13
COL-to-COL Packet Interaction . . . . . . . . . . . . . . . . 14
COL-to-ROW Packet Interaction . . . . . . . . . . . . . . . 15
ROW-to-ROW Examples . . . . . . . . . . . . . . . . . . .16,17
Row and Column Cycle Description . . . . . . . . . . . . 17
Precharge Mechanisms . . . . . . . . . . . . . . . . . . . .18,19
Read Transaction - Example . . . . . . . . . . . . . . . . . . 20
Write Transaction - Example . . . . . . . . . . . . . . . . . . 21
Write/Retire - Examples . . . . . . . . . . . . . . . . . . . 22, 23
Interleaved Write - Example. . . . . . . . . . . . . . . . . . . 24
Interleaved Read - Example . . . . . . . . . . . . . . . . . . 25
Interleaved RRWW . . . . . . . . . . . . . . . . . . . . . . . . . 25
Control Register Transactions . . . . . . . . . . . . . . . . . 26
Control Register Packets . . . . . . . . . . . . . . . . . . . . . 27
Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28-29
Control Register Summary. . . . . . . . . . . . . . . . . 30-37
Power State Management . . . . . . . . . . . . . . . . . 38-41
Refresh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Current and Temperature Control . . . . . . . . . . . . . . 43
Electrical Conditions . . . . . . . . . . . . . . . . . . . . . . . . 44
Timing Conditions . . . . . . . . . . . . . . . . . . . . . . . .44-45
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . 46
Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . 46
RSL Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
RSL - Receive Timing . . . . . . . . . . . . . . . . . . . . . . . 48
RSL - Transmit Timing . . . . . . . . . . . . . . . . . . . . . . . 49
CMOS - Receive Timing . . . . . . . . . . . . . . . . . . .50-51
CMOS - Transmit Timing . . . . . . . . . . . . . . . . . . .52-53
RSL - Domain Crossing Window . . . . . . . . . . . . . . . 53
Timing Parameters. . . . . . . . . . . . . . . . . . . . . . . . . . 54
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . 55
IDD - Supply Current Profile . . . . . . . . . . . . . . . . . . 55
© Copyright April 1999 Samsung Electronics.
All rights reserved.
Direct Rambus and Direct RDRAM are trademarks of
Rambus Inc. Rambus, RDRAM, and the Rambus Logo are
registered trademarks of Rambus Inc.
This document contains advanced information that is subject
to change by Samsung without notice.
Document Version 0.9
Samsung Electronics Co., Ltd.
#24 Nongseo-Ri, Kiheung-Eup Yongin-City
Kyunggi-Do, KOREA
Telephone: 82-331-209-4519
Fax: 82-2-760-7990
http://www.samsungsemi.com
Page 61
Rev. 0.9 Apr. 1999
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Synchronous DRAM, 1MX16, 5.5ns, CMOS, PDSO50, 0.400 X 0.825 INCH, 0.80 MM PITCH, TSOP2-50
SAMSUNG
KM416S1120DT-F8
Synchronous DRAM, 1MX16, 6ns, CMOS, PDSO50, 0.400 X 0.825 INCH, 0.80 MM PITCH, TSOP2-50
SAMSUNG
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