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KM416S8030BN-GH [SAMSUNG]

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KM416S8030BN-GH
型号： KM416S8030BN-GH
厂家： SAMSUNG    SAMSUNG
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动态存储器
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Preliminary  
KM416S8030  
CMOS SDRAM  
2M x 16Bit x 4 Banks Synchronous DRAM  
FEATURES  
GENERAL DESCRIPTION  
• JEDEC standard 3.3V power supply  
• LVTTL compatible with multiplexed address  
• Four banks operation  
The KM416S8030 is 134,217,728 bits synchronous high data  
rate Dynamic RAM organized as 4 x 2,097,152 words by 16  
bits, fabricated with SAMSUNG¢s high performance CMOS  
technology. Synchronous design allows precise cycle control  
with the use of system clock I/O transactions are possible on  
every clcok cycle. Range of operating frequencies, programma-  
ble burst length and programmable latencies allow the same  
device to be useful for a variety of high bandwidth, high perfor-  
mance memory system applications.  
• MRS cycle with address key programs  
-. CAS Latency (2 & 3)  
-. Burst Length (1, 2, 4, 8 & full page)  
-. Burst Type (Sequential & Interleave)  
• All inputs are sampled at the positive going edge of the system  
clock.  
• Burst Read Single-bit Write operation  
• DQM for masking  
ORDERING INFORMATION  
• Auto & self refresh  
Part NO.  
MAX Freq. Interface Package  
• 64ms refresh period (4K cycle)  
KM416S8030T-G/F8  
KM416S8030T-G/FH  
KM416S8030T-G/FL  
KM416S8030T-G/F10  
125MHz  
54pin  
TSOP(II)  
100MHz  
100MHz  
100MHz  
LVTTL  
FUNCTIONAL BLOCK DIAGRAM  
LWE  
Data Input Register  
LDQM  
Bank Select  
2M x 16  
2M x 16  
2M x 16  
2M x 16  
DQi  
CLK  
ADD  
Column Decoder  
Latency & Burst Length  
LCKE  
Programming Register  
LWCBR  
LRAS  
LCBR  
LWE  
LCAS  
LDQM  
Timing Register  
CLK  
CKE  
CS  
RAS  
CAS  
WE  
LDQM  
UDQM  
Samsung Electronics reserves the right to  
change products or specification without  
notice.  
*
REV. 2 Mar. '98  
Preliminary  
KM416S8030  
CMOS SDRAM  
PIN CONFIGURATION (TOP VIEW)  
VDD  
DQ0  
VDDQ  
DQ1  
DQ2  
VSSQ  
DQ3  
DQ4  
VDDQ  
DQ5  
DQ6  
VSSQ  
DQ7  
VDD  
LDQM  
WE  
CAS  
RAS  
CS  
BA0  
BA1  
A10/AP  
A0  
1
2
3
4
5
6
7
8
VSS  
54  
53  
52  
51  
50  
49  
48  
47  
46  
45  
44  
43  
42  
41  
40  
39  
38  
37  
36  
35  
34  
33  
32  
31  
30  
29  
28  
DQ15  
VSSQ  
DQ14  
DQ13  
VDDQ  
DQ12  
DQ11  
VSSQ  
DQ10  
DQ9  
VDDQ  
DQ8  
VSS  
N.C/RFU  
UDQM  
CLK  
CKE  
N.C  
A11  
A9  
9
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
A8  
A7  
A6  
A5  
A4  
VSS  
A1  
A2  
A3  
VDD  
54PIN TSOP (II)  
(400mil x 875mil)  
(0.8 mm PIN PITCH)  
PIN FUNCTION DESCRIPTION  
PIN  
CLK  
NAME  
System Clock  
INPUT FUNCTION  
Active on the positive going edge to sample all inputs.  
Disables or enables device operation by masking or enabling all inputs except  
CLK, CKE and DQM  
CS  
Chip Select  
Masks system clock to freeze operation from the next clock cycle.  
CKE should be enabled at least one cycle prior to new command.  
Disable input buffers for power down in standby.  
CKE  
Clock Enable  
Row / column addresses are multiplexed on the same pins.  
Row address : RA0 ~ RA11, column address : CA0 ~ CA8  
A0 ~ A11  
BA0 ~ BA1  
RAS  
Address  
Selects bank to be activated during row address latch time.  
Selects bank for read/write during column address latch time.  
Bank Select Address  
Row Address Strobe  
Latches row addresses on the positive going edge of the CLK with RAS low.  
Enables row access & precharge.  
Latches column addresses on the positive going edge of the CLK with CAS low.  
Enables column access.  
CAS  
Column Address Strobe  
Write Enable  
Enables write operation and row precharge.  
Latches data in starting from CAS, WE active.  
WE  
Makes data output Hi-Z, tSHZ after the clock and masks the output.  
Blocks data input when L(U)DQM active.  
L(U)DQM  
Data Input/Output Mask  
DQ0 ~ 15  
VDD/VSS  
Data Input/Output  
Data inputs/outputs are multiplexed on the same pins.  
Power and ground for the input buffers and the core logic.  
Power Supply/Ground  
Isolated power supply and ground for the output buffers to provide improved noise  
immunity.  
VDDQ/VSSQ  
N.C/RFU  
Data Output Power/Ground  
No Connection/  
Reserved for Future Use  
This pin is recommended to be left No Connection on the device.  
REV. 2 Mar. '98  
Preliminary  
KM416S8030  
CMOS SDRAM  
ABSOLUTE MAXIMUM RATINGS  
Parameter  
Voltage on any pin relative to Vss  
Voltage on VDD supply relative to Vss  
Storage temperature  
Symbol  
VIN, VOUT  
VDD, VDDQ  
TSTG  
Value  
-1.0 ~ 4.6  
-1.0 ~ 4.6  
-55 ~ +150  
1
Unit  
V
V
°C  
W
Power dissipation  
PD  
Short circuit current  
IOS  
50  
mA  
Note :  
Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded.  
Functional operation should be restricted to recommended operating condition.  
Exposure to higher than recommended voltage for extended periods of time could affect device reliability.  
DC OPERATING CONDITIONS  
Recommended operating conditions (Voltage referenced to VSS = 0V, TA = 0 to 70°C)  
Parameter  
Supply voltage  
Symbol  
Min  
3.0  
2.0  
-0.3  
2.4  
-
Typ  
Max  
Unit  
V
Note  
VDD, VDDQ  
3.3  
3.6  
Input logic high votlage  
VIH  
VIL  
VOH  
VOL  
IIL  
3.0  
VDDQ+0.3  
V
1
Input logic low voltage  
0
-
0.8  
-
V
2
IOH = -2mA  
IOL = 2mA  
3
Output logic high voltage  
Output logic low voltage  
Input leakage current(Inputs)  
Input leakage current (I/O pins)  
V
-
0.4  
5
V
-5  
-
uA  
uA  
IIL  
-5  
-
5
3,4  
Note :  
1. VIH (max) = 5.6V AC.The overshoot voltage duration is £ 3ns.  
2. VIL (min) = -2.0V AC. The undershoot voltage duration is £ 3ns.  
3. Any input 0V £ VIN £ VDDQ,  
Input leakage currents include HI-Z output leakage for all bi-directional buffers with Tri-State outputs.  
4. Dout is disabled, 0V £ VOUT £ VDDQ.  
CAPACITANCE (VDD = 3.3V, TA = 23°C, f = 1MHz, VREF =1.4V ± 200 mV)  
Parameter  
Clock  
Symbol  
CCLK  
CIN  
Min  
2.5  
2.5  
2.5  
4
Max  
4
Unit  
pF  
RAS, CAS, WE, CS, CKE, DQM  
Address  
5
pF  
CADD  
COUT  
5
pF  
DQ0 ~ DQ3  
6.5  
pF  
REV. 2 Mar. '98  
Preliminary  
KM416S8030  
CMOS SDRAM  
DC CHARACTERISTICS  
(Recommended operating condition unless otherwise noted, TA = 0 to 70°C)  
Version  
-H -L  
CAS  
Latency  
Parameter  
Symbol  
Test Condition  
Burst Length =1  
Unit  
mA  
Note  
-8  
-10  
Operating Current  
(One Bank Active)  
ICC1  
tRC ³ tRC(min)  
IOL = 0 mA  
130  
120 120 115  
1
ICC2P  
1
1
CKE £ VIL(max), tCC = 15ns  
Precharge Standby Current in  
power-down mode  
mA  
ICC2PS  
CKE & CLK £ VIL(max), tCC = ¥  
CKE ³ VIH(min),CS ³ VIH(min),tCC=15ns  
Input signals are changed one time during  
30ns  
ICC2N  
15  
7
Precharge Standby Current  
in non power-down mode  
mA  
mA  
CKE ³ VIH(min), CLK £ VIL(max), tCC = ¥  
Input signals are stable  
ICC2NS  
ICC3P  
5
5
CKE £ VIL(max), tCC = 15ns  
Active Standby Current  
in power-down mode  
ICC3PS  
CKE & CLK £ VIL(max), tCC = ¥  
CKE ³ VIH(min), CS ³ VIH(min), tCC = 15ns  
Input signals are changed one time during  
30ns.  
ICC3N  
30  
20  
mA  
mA  
Active Standby Current  
in non power-down mode  
(One Bank Active)  
CKE ³ VIH(min), CLK £ VIL(max), tCC = ¥  
Input signals are stable  
ICC3NS  
IOL = 0 mA  
Page Burst  
tCCD = 2CLKs  
3
2
170  
135  
145 145 145  
145 135 135  
Operating Current  
(Burst Mode)  
ICC4  
mA  
1
Refresh Current  
ICC5  
ICC6  
tRC ³ tRC(min)  
CKE £ 0.2V  
200  
165  
mA  
mA  
uA  
2
3
4
1
Self Refresh Current  
600  
Note :  
1. Measured with outputs open.  
2. Refresh period is 64ms.  
3. KM416S8030T-G**  
4. KM416S8030T-F**  
REV. 2 Mar. '98  
Preliminary  
KM416S8030  
CMOS SDRAM  
AC OPERATING TEST CONDITIONS (VDD = 3.3V ± 0.3V, TA = 0 to 70°C)  
Parameter  
Input levels (Vih/Vil)  
Value  
2.4 / 0.4  
1.4  
Unit  
V
Input timing measurement reference level  
Input rise and fall time  
V
tr / tf = 1 / 1  
1.4  
ns  
V
Output timing measurement reference level  
Output load condition  
See Fig. 2  
3.3V  
Vtt=1.4V  
1200W  
50W  
VOH (DC) = 2.4V, IOH = -2mA  
VOL (DC) = 0.4V, IOL = 2mA  
Output  
Output  
Z0=50W  
50pF  
50pF  
870W  
(Fig. 1) DC Output Load Circuit  
(Fig. 2) AC Output Load Circuit  
OPERATING AC PARAMETER  
(AC operating conditions unless otherwise noted)  
Version  
Parameter  
Symbol  
Unit  
Note  
-8  
16  
20  
20  
48  
-H  
20  
20  
20  
50  
100  
70  
10  
1
-L  
20  
20  
20  
50  
-10  
20  
24  
24  
50  
Row active to row active delay  
RAS to CAS delay  
tRRD(min)  
tRCD(min)  
tRP(min)  
ns  
ns  
1
1
1
1
Row precharge time  
ns  
tRAS(min)  
tRAS(max)  
tRC(min)  
ns  
Row active time  
us  
Row cycle time  
68  
8
70  
10  
80  
12  
ns  
1
2
2
2
3
Last data in to row precharge  
Last data in to new col. address delay  
Last data in to burst stop  
tRDL(min)  
tCDL(min)  
tBDL(min)  
tCCD(min)  
ns  
CLK  
CLK  
CLK  
1
Col. address to col. address delay  
1
CAS latency=3  
CAS latency=2  
2
Number of valid  
output data  
ea  
4
1
Note :  
1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time  
and then rounding off to the next higher integer.  
2. Minimum delay is required to complete write.  
3. All parts allow every cycle column address change.  
4. In case of row precharge interrupt, auto precharge and read burst stop.  
REV. 2 Mar. '98  
Preliminary  
KM416S8030  
CMOS SDRAM  
AC CHARACTERISTICS (AC operating conditions unless otherwise noted)  
-8  
-H  
-L  
-10  
Parameter  
Symbol  
tCC  
Unit Note  
Min  
8
Max  
Min  
10  
Max  
Min  
10  
Max  
Min  
Max  
CAS latency=3  
10  
13  
CLK cycle time  
1000  
1000  
1000  
1000  
ns  
ns  
ns  
1
1, 2  
2
CAS latency=2  
CAS latency=3  
CAS latency=2  
CAS latency=3  
CAS latency=2  
12  
10  
12  
6
6
6
6
6
7
7
7
CLK to valid  
output delay  
tSAC  
3
3
3
3
2
1
1
3
3
3
3
2
1
1
3
3
3
3
2
1
1
3
Output data  
hold time  
tOH  
3
CLK high pulse width  
CLK low pulse width  
Input setup time  
tCH  
tCL  
3.5  
3.5  
2.5  
1.5  
1
ns  
ns  
ns  
ns  
ns  
3
3
3
3
2
tSS  
Input hold time  
tSH  
tSLZ  
CLK to output in Low-Z  
CAS latency=3  
CAS latency=2  
6
6
6
6
6
7
7
7
CLK to output  
in Hi-Z  
tSHZ  
ns  
Note :  
1. Parameters depend on programmed CAS latency.  
2. If clock rising time is longer than 1ns, (tr/2-0.5)ns should be added to the parameter.  
3. Assumed input rise and fall time (tr & tf)=1ns.  
If tr & tf is longer than 1ns, transient time compensation should be considered,  
i.e., [(tr + tf)/2-1]ns should be added to the parameter.  
REV. 2 Mar. '98  
Preliminary  
KM416S8030  
CMOS SDRAM  
66Mhz and 100Mhz Pull-Up  
1.5 2.5  
IBIS Specification  
0
0.5  
1
2
3
3.5  
IOH Characteristics(Pull-up)  
0
-100  
-200  
-300  
-400  
-500  
-600  
Voltage  
100Mhz  
min  
I(mA)  
100Mhz  
max  
I(mA)  
-2.4  
-27.3  
66Mhz  
min  
I(mA)  
(V)  
3.45  
3.3  
3
2.6  
2.4  
2
1.8  
1.65  
1.5  
1.4  
1
0
-74.1  
-0.7  
-7.5  
-21.1  
-34.1  
-58.7  
-67.3  
-73  
-77.9  
-80.8  
-88.6  
-93  
-129.2  
-153.3  
-197  
-226.2  
-248  
-269.7  
-284.3  
-344.5  
-502.4  
-13.3  
-27.5  
-35.5  
-41.1  
-47.9  
-52.4  
-72.5  
-93  
0
voltage  
Ioh min(100Mhz)  
Ioh min(66Mhz)  
Ioh max(66 and 100Mhz)  
66Mhz and 100Mhz Pull-Down  
IOL Characteristics(Pull-Down)  
250  
200  
150  
100  
50  
100Mhz  
min  
I(mA)  
0.0  
100Mhz  
66Mhz  
min  
I(mA)  
0.0  
Voltage  
max  
I(mA)  
0.0  
(V)  
0
0.4  
0.65  
0.85  
1
1.4  
1.5  
1.65  
1.8  
1.95  
3
27.5  
41.8  
51.6  
58.0  
70.7  
72.9  
75.4  
77.0  
77.6  
80.3  
81.4  
70.2  
17.7  
26.9  
33.3  
37.6  
46.6  
48.0  
49.5  
50.7  
51.5  
54.2  
54.9  
107.5  
133.8  
151.2  
187.7  
194.4  
202.5  
208.6  
212.0  
219.6  
222.6  
3.45  
0
0
0.5  
1
1.5  
2
2.5  
3
3.5  
voltage  
Iol min(100Mhz)  
Iol min(66Mhz)  
Iol max(100Mhz)  
REV. 2 Mar. '98  
Preliminary  
KM416S8030  
CMOS SDRAM  
Minimum VDD Clamp Current  
(referenced to VDD)  
VDD Clamp @CLK,CKE, CS,DQM & DQ  
VDD  
0.0V  
0.2V  
0.4V  
0.6V  
0.7V  
0.8V  
0.9V  
1.0V  
1.2V  
1.4V  
1.6V  
1.8V  
2.0V  
2.2V  
2.4V  
2.6V  
I(mA)  
0.0mA  
0.0mA  
0.0mA  
0.0mA  
0.0mA  
0.0mA  
0.0mA  
0.23mA  
1.34mA  
3.02mA  
5.06mA  
7.35mA  
9.83mA  
12.48mA  
15.30mA  
18.31mA  
20  
15  
10  
5
0
0
1
2
3
Voltage  
I(ma)  
Minimum VSS Clamp Current  
-2 -1  
VSS Clamp @CLK,CKE, CS,DQM & DQ  
-3  
0
VSS  
-2.6  
-2.4  
-2.2  
-2.0  
-1.8  
-1.6  
-1.4  
-1.2  
-1.0  
-0.9  
-0.8  
-0.7  
-0.6  
-0.4  
-0.2  
0.0  
I(mA)  
0
-10  
-20  
-30  
-40  
-50  
-60  
-57.23mA  
-45.77mA  
-38.26mA  
-31.22mA  
-24.58mA  
-18.37mA  
-12.56mA  
-7.57mA  
-3.37mA  
-1.75mA  
-0.58mA  
-0.05mA  
0.0mA  
0.0mA  
0.0mA  
0.0mA  
Voltage  
I(ma)  
REV. 2 Mar. '98  
Preliminary  
KM416S8030  
CMOS SDRAM  
FREQUENCY vs. AC PARAMETER RELATIONSHIP TABLE  
(Unit : number of clock)  
KM416S8030T-8  
tRC  
tRAS  
tRP  
tRRD  
tRCD  
tCCD  
tCDL  
8ns  
1
tRDL  
8ns  
1
CAS  
Latency  
Frequency  
68ns  
48ns  
20ns  
16ns  
20ns  
8ns  
1
125MHz (8.0ns)  
100MHz (10.0ns)  
83MHz (12.0ns)  
75MHz (13.0ns)  
66MHz (15.0ns)  
3
3
2
2
2
9
7
6
6
5
6
5
4
4
4
3
2
2
2
2
2
2
2
2
2
3
2
2
2
2
1
1
1
1
1
1
1
1
1
1
1
1
(Unit : number of clock)  
KM416S8030T-H  
Frequency  
tRC  
tRAS  
tRP  
tRRD  
tRCD  
tCCD  
tCDL  
tRDL  
CAS  
Latency  
70ns  
50ns  
20ns  
20ns  
20ns  
10ns  
10ns  
10ns  
100MHz (10.0ns)  
83MHz (12.0ns)  
75MHz (13.0ns)  
66MHz (15.0ns)  
60MHz (16.7ns)  
2
2
2
2
2
7
6
6
5
5
5
5
4
4
3
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
(Unit : number of clock)  
KM416S8030T-L  
Frequency  
tRC  
tRAS  
tRP  
tRRD  
tRCD  
tCCD  
tCDL  
tRDL  
CAS  
Latency  
70ns  
50ns  
20ns  
20ns  
20ns  
10ns  
10ns  
10ns  
100MHz (10.0ns)  
83MHz (12.0ns)  
75MHz (13.0ns)  
66MHz (15.0ns)  
60MHz (16.7ns)  
3
2
2
2
2
7
6
6
5
5
5
5
4
4
3
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
(Unit : number of clock)  
KM416S8030T-10  
Frequency  
tRC  
tRAS  
tRP  
tRRD  
tRCD  
tCCD  
tCDL  
tRDL  
CAS  
Latency  
80ns  
50ns  
24ns  
20ns  
24ns  
10ns  
10ns  
12ns  
100MHz (10.0ns)  
83MHz (12.0ns)  
75MHz (13.0ns)  
66MHz (15.0ns)  
60MHz (16.7ns)  
3
3
2
2
2
8
7
7
6
5
5
5
4
4
3
3
2
2
2
2
2
2
2
2
2
3
2
2
2
2
1
1
1
1
1
1
1
1
1
1
2
1
1
1
1
REV. 2 Mar. '98  
Preliminary  
KM416S8030  
CMOS SDRAM  
SIMPLIFIED TRUTH TABLE  
CKEn-1  
CKEn  
CS  
RAS  
CAS  
WE  
DQM BA0,1  
A10/AP  
A8 ~ A0  
Note  
COMMAND  
Register  
Refresh  
Mode Register Set  
Auto Refresh  
H
X
H
L
L
L
L
L
X
OP CODE  
1, 2  
3
H
L
L
L
L
H
X
X
X
X
Entry  
3
Self  
L
H
L
H
X
L
H
X
H
H
X
H
3
Refresh  
Exit  
H
3
Bank Active & Row Addr.  
H
H
X
X
X
X
V
V
Row Address  
Column  
Address  
(A0~A8)  
Read &  
Column Address  
Auto Precharge Disable  
Auto Precharge Enable  
Auto Precharge Disable  
Auto Precharge Enable  
L
4
4, 5  
4
L
L
H
H
L
L
H
L
H
Column  
Address  
(A0~A8)  
Write &  
Column Address  
L
H
X
X
V
H
4, 5  
6
Burst Stop  
Precharge  
H
H
X
X
L
L
H
L
H
H
L
L
X
X
X
Bank Selection  
All Banks  
V
X
L
X
H
H
L
X
V
X
X
H
X
V
X
V
X
X
H
X
V
X
V
X
X
H
X
V
Entry  
H
L
X
Clock Suspend or  
Active Power Down  
X
Exit  
L
H
L
X
H
L
X
X
Entry  
H
Precharge Power Down Mode  
X
H
L
Exit  
L
H
X
X
DQM  
H
H
V
X
X
X
7
X
X
H
L
X
H
X
H
No Operation Command  
H
(V=Valid, X=Don¢t Care, H=Logic High, L=Logic Low)  
Note :  
1. OP Code : Operand Code  
A0 ~ A11 & BA0 ~ BA1 : Program keys. (@MRS)  
2. MRS can be issued only at all banks precharge state.  
A new command can be issued after 2 CLK cycles of MRS.  
3. Auto refresh functions are as same as CBR refresh of DRAM.  
The automatical precharge without row precharge command is meant by "Auto".  
Auto/self refresh can be issued only at all banks precharge state.  
4. BA0 ~ BA1 : Bank select addresses.  
If both BA0 and BA1 are "Low" at read, write, row active and precharge, bank A is selected.  
If both BA0 is "Low" and BA1 is "High" at read, write, row active and precharge, bank B is selected.  
If both BA0 is "High" and BA1 is "Low" at read, write, row active and precharge, bank C is selected.  
If both BA0 and BA1 are "High" at read, write, row active and precharge, bank D is selected.  
If A10/AP is "High" at row precharge, BA0 and BA1 is ignored and all banks are selected.  
5. During burst read or write with auto precharge, new read/write command can not be issued.  
Another bank read/write command can be issued after the end of burst.  
New row active of the assoiated bank can be issued at tRP after the end of burst.  
6. Burst stop command is valid at every burst length.  
7. DQM sampled at positive going edge of a CLK and masks the data-in at the very CLK (Write DQM latency is 0),  
but makes Hi-Z state the data-out of 2 CLK cycles after. (Read DQM latency is 2)  
REV. 2 Mar. '98  

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