KM41V4000DJ-L6 [SAMSUNG]
Fast Page DRAM, 4MX1, 60ns, CMOS, PDSO20, 0.300 INCH, PLASTIC, SOJ-26/20;
| 型号： | KM41V4000DJ-L6 |
| 厂家： | 
SAMSUNG |
| 描述： | Fast Page DRAM, 4MX1, 60ns, CMOS, PDSO20, 0.300 INCH, PLASTIC, SOJ-26/20 动态存储器 光电二极管 |
| 文件： | 总20页 (文件大小：340K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
KM41C4000D, KM41V4000D
CMOS DRAM
4M x 1Bit CMOS Dynamic RAM with Fast Page Mode
DESCRIPTION
This is a family of 4,194,304 x 1bit Fast Page Mode CMOS DRAMs. Fast Page Mode offers high speed random access of memory cells
within the same row. Power supply voltage (+5V or +3.3V), access time (-5, -6 or -7), power consumption(Normal or Low power), and
package type (SOJ or TSOP-II) are optional features of this family. All of this family have CAS-before-RAS refresh, RAS-only refresh and
Hidden refresh capabilities. Furthermore, self-refresh operation is available in Low power version.
This 4Mx1 Fast Page Mode DRAM family is fabricated using Samsung¢s advanced CMOS process to realize high band-width, low power
consumption and high reliability. It may be used as main memory for main frames and mini computers, personal computer and high per-
formance microprocessor systems.
• Fast Page Mode operation
FEATURES
• CAS-before-RAS refresh capability
• Part Identification
• RAS-only and Hidden refresh capability
• Self-refresh capability (3.3V, L-ver only)
• Fast parallel test mode capability
• TTL(5V)/LVTTL(3.3V) compatible inputs and outputs
• Common I/O using early write
- KM41C4000D/D-L(5V, 1K Ref.)
- KM41V4000D/D-L(3.3V, 1K Ref.)
• ActivePowerDissipation
• JEDEC Standard pinout
Unit : mW
5V
• Available in 26(20)-pin SOJ 300mil and TSOP(II)
300mil packages
Speed
-5
3.3V
-
470
• +5V±10% power supply(5V product)
• +3.3V±0.3V power supply(3.3V product)
-6
220
200
415
-7
360
FUNCTIONAL BLOCK DIAGRAM
• Refresh Cycles
RAS
CAS
W
Vcc
Vss
Control
Clocks
Part
NO.
Refresh
cycle
Refresh Period
VBB Generator
Normal
L-ver
KM41C4000D
KM41V4000D
1K
16ms
128ms
Row Decoder
Refresh Timer
Refresh Control
Data in
Buffer
D
Memory Array
4,194,304 x1
Cells
Refresh Counter
Row Address Buffer
Col. Address Buffer
• Performance Range
Speed
-5
Remark
tRAC
tCAC
tRC
tPC
50ns 15ns 90ns 35ns 5V only
60ns 15ns 110ns 40ns 5V/3.3V
70ns 20ns 130ns 45ns 5V/3.3V
Data out
Buffer
A0~A9
Q
Column Decoder
-6
-7
SAMSUNG ELECTRONICS CO., LTD. reserves the right to
change products and specifications without notice.
KM41C4000D, KM41V4000D
CMOS DRAM
PIN CONFIGURATION (Top Views)
•KM41C/V4000DT
•KM41C/V4000DJ
D
W
RAS
N.C
A10
1
2
3
4
5
20
19
18
17
16
VSS
Q
CAS
N.C
A9
D
W
RAS
N.C
A10
1
2
3
4
5
20
19
18
17
16
VSS
Q
CAS
N.C
A9
A0
A1
A2
A3
6
15
14
13
12
11
A8
A7
A6
A5
A4
A0
A1
6
7
8
9
10
15
14
13
12
11
A8
A7
A6
A5
A4
7
8
9
10
A2
A3
VCC
VCC
( SOJ )
( TSOP-II )
Pin Name
A0 - A10
D
Pin function
Address Inputs
Data In
Q
Data out
VSS
Ground
RAS
CAS
W
Row Address Strobe
Column Address Strobe
Read/Write Input
No Connection
Power(+5V)
N.C
VCC
Power(+3.3V)
KM41C4000D, KM41V4000D
ABSOLUTE MAXIMUM RATINGS
Parameter
CMOS DRAM
Rating
Symbol
Units
3.3V
-0.5 to +4.6
-0.5 to +4.6
-55 to +150
600
5V
Voltage on any pin relative to VSS
Voltage on VCC supply relative to VSS
Storage Temperature
VIN,VOUT
VCC
-1 to +7.0
-1 to +7.0
-55 to +150
600
V
V
Tstg
PD
°C
Power Dissipation
mW
mA
Short Circuit Output Current
IOS
50
50
* Permanent device damage may occur if "ABSOLUTE MAXIMUM RATINGS" are exceeded. Functional operation should be restricted to
the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended
periods may affect device reliability.
RECOMMENDED OPERATING CONDITIONS (Voltage referenced to Vss, TA= 0 to 70°C)
3.3V
5V
Typ
5.0
0
Parameter
Symbol
Units
Min
3.0
0
Typ
Max
3.6
0
Min
4.5
0
Max
5.5
0
Supply Voltage
VCC
VSS
VIH
VIL
3.3
V
V
V
V
Ground
0
-
*1
*1
Input High Voltage
Input Low Voltage
2.0
2.4
-
VCC+0.3
0.8
VCC+1.0
0.8
*2
*2
-
-
-0.3
-0.1
*1 : VCC +1.3V/15ns(3.3V), VCC +2.0V/20ns(5V), Pulse width is measured at VCC
*2 : - 1.3V/15ns(3.3V), - 2.0V/20ns(5V), Pulse width is measured at VSS
DC AND OPERATING CHARACTERISTICS (Recommended operating conditions unless otherwise noted.)
Parameter
Symbol
Min
Max
Units
Input Leakage Current (Any input 0£VIN£VCC+0.3V,
all other input pins not under test=0 Volt)
II(L)
-5
5
uA
Output Leakage Current
(Data out is disabled, 0V£VOUT£VCC)
IO(L)
-5
5
uA
3.3V
Output High Voltage Level(IOH=-2mA)
Output Low Voltage Level(IOL=2mA)
VOH
VOL
2.4
-
-
V
V
0.4
Input Leakage Current (Any input 0£VIN£VCC+0.5V,
all other input pins not under test=0 Volt)
II(L)
-5
-5
5
5
uA
uA
Output Leakage Current
(Data out is disabled, 0V£VOUT£VCC)
IO(L)
5V
Output High Voltage Level(IOH=-5mA)
Output Low Voltage Level(IOL=4.2mA)
VOH
VOL
2.4
-
-
V
V
0.4
KM41C4000D, KM41V4000D
CMOS DRAM
DC AND OPERATING CHARACTERISTICS (Recommend operating conditions unless otherwise noted.)
Max
Symbol
Power
Speed
Units
KM41V4000D
KM41C4000D
-5
-6
-7
-
60
55
85
75
65
mA
mA
mA
ICC1
ICC2
ICC3
Don¢t Care
Don¢t Care
Don¢t Care
Don¢t Care
1
2
mA
-5
-6
-7
-
60
55
85
75
65
mA
mA
mA
-5
-6
-7
-
45
40
65
55
45
mA
mA
mA
ICC4
ICC5
ICC6
Don¢t Care
Normal
L
0.5
100
1
200
mA
uA
Don¢t Care
-5
-6
-7
-
60
55
85
75
65
mA
mA
mA
Don¢t Care
ICC7
ICCS
L
L
Don¢t Care
Don¢t Care
200
150
300
-
uA
uA
ICC1* : Operating Current (RAS and CAS cycling @tRC=min.)
ICC2 : Standby Current (RAS=CAS=W=VIH)
ICC3* : RAS-only Refresh Current (CAS=VIH, RAS, Address cycling @tRC=min.)
ICC4* : Fast Page Mode Current (RAS=VIL, CAS, Address cycling @tPC=min.)
ICC5 : Standby Current (RAS=CAS=W=VCC-0.2V)
ICC6* : CAS-Before-RAS Refresh Current (RAS and CAS cycling @tRC=min)
ICC7 : Battery back-up current, Average power supply current, Battery back-up mode
Input high voltage(VIH)=VCC-0.2V, Input low voltage(VIL)=0.2V, CAS=0.2V,
DQ=Don¢t Care, TRC=125us(L-ver.), TRAS=TRASmin~300ns
ICCS : Self refresh current
RAS=CAS=VIL, W=OE =A0 ~ A10=D=VCC-0.2V or 0.2V
*Note :
ICC1, ICC3, ICC4 and ICC6 are dependent on output loading and cycle rates. Specified values are obtained with the output open.
ICC is specified as an average current. In ICC1, ICC3 ICC6 and ICC7, address can be changed maximum once while RAS=VIL. In
ICC4, address can be changed maximum once within one fast page mode cycle time, tPC.
KM41C4000D, KM41V4000D
CMOS DRAM
CAPACITANCE (TA=25°C, VCC=5V or 3.3V, f=1MHz)
Parameter
Symbol
Min
Max
Units
pF
Input capacitance [D]
CIN1
CIN2
CIN3
COUT
-
-
-
-
5
5
7
7
Input capacitance [A0 ~ A10]
Input capacitance [RAS, CAS, W]
Output capacitance [Q]
pF
pF
pF
AC CHARACTERISTICS (0°C£TA£70°C, See note 1,2)
Test condition (5V device) : VCC=5.0V±10%, Vih/Vil=2.4/0.8V, Voh/Vol=2.4/0.4V
Test condition (3.3V device) : VCC=3.3V±0.3V, Vih/Vil=2.2/0.7V, Voh/Vol=2.0/0.8V
*1
-6
7
-5
Parameter
Symbol
Units
Notes
Min
90
Max
Min
Max
Min
130
150
Max
Random read or write cycle time
Read-modify-write cycle time
Access time from RAS
110
130
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tRC
110
tRWC
tRAC
tCAC
tAA
50
15
25
60
15
30
70
20
35
3,4,10
3,4,5
3,10
3
Access time from CAS
Access time from column address
CAS to output in Low-Z
0
0
0
0
0
0
tCLZ
tOFF
tT
Output buffer turn-off delay
Transition time (rise and fall)
RAS precharge time
12
50
12
50
17
50
6
3
3
3
2
30
50
15
50
15
20
15
5
40
60
15
60
15
20
15
5
50
70
20
70
20
20
15
5
tRP
RAS pulse width
10K
10K
10K
tRAS
tRSH
tCSH
tCAS
tRCD
tRAD
tCRP
tASR
tRAH
tASC
tCAH
tRAL
tRCS
tRCH
tRRH
tWCH
tWP
RAS hold time
CAS hold time
CAS pulse width
10K
35
10K
45
10K
50
RAS to CAS delay time
4
RAS to column address delay time
CAS to RAS precharge time
Row address set-up time
Row address hold time
25
30
35
10
0
0
0
10
0
10
0
10
0
Column address set-up time
Column address hold time
Column address to RAS lead time
Read command set-up time
Read command hold time referenced to CAS
Read command hold time referenced to RAS
Write command hold time
Write command pulse width
Write command to RAS lead time
Write command to CAS lead time
Note) *1 : 5V only
10
25
0
10
30
0
15
35
0
0
0
0
8
8
0
0
0
10
10
15
13
10
10
15
15
15
15
15
15
tRWL
tCWL
KM41C4000D, KM41V4000D
CMOS DRAM
AC CHARACTERISTICS (0°C£TA£70°C, See note 2)
*1
-6
-7
-5
Parameter
Symbol
Units
Notes
Min
0
Max
Min
0
Max
Min
0
Max
Data set-up time
Data hold time
ns
ns
ms
ms
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
us
ns
ns
9
9
tDS
10
10
15
tDH
Refresh period (Normal)
16
16
16
tREF
tREF
tWCS
tCWD
tRWD
tAWD
tCPWD
tCSR
tCHR
tRPC
tCPT
tCPA
tPC
Refresh period (L-ver)
128
128
128
Write command set-up time
0
0
0
7
7
7
7
7
CAS to W delay time
15
50
25
30
10
10
5
15
60
30
35
10
10
5
20
70
35
40
10
15
5
RAS to W delay time
Column address to W delay time
CAS precharge to W delay time
CAS set-up time (CAS-before-RAS refresh)
CAS hold time (CAS-before-RAS refresh)
RAS to CAS precharge time
CAS precharge time (C-B-R counter test cycle)
Access time from CAS precharge
Fast Page mode cycle time
20
20
25
30
35
40
3
35
53
10
50
30
10
10
10
10
100
90
-50
40
60
45
70
Fast Page read-modify-write cycle time
CAS precharge time (Fast Page cycle)
RAS pulse width (Fast Page cycle)
RAS hold time from CAS precharge
Write command set-up time (Test mode in)
Write command hold time (Test mode in)
W to RAS precharge time (C-B-R refresh)
W to RAS hold time (C-B-R refresh)
RAS pulse width (C-B-R self refresh)
RAS precharge time (C-B-R self refresh)
CAS Hold time (C-B-R self refresh)
Note) *1 : 5V only
tPRWC
tCP
10
10
200K
60
200K
70
200K
tRASP
tRHCP
tWTS
tWTH
tWRP
tWRH
tRASS
tRPS
tCHS
35
40
10
10
10
10
10
10
10
10
100
110
-50
100
130
-50
14,15,16
14,15,16
14,15,16
KM41C4000D, KM41V4000D
CMOS DRAM
TEST MODE CYCLE
( Note 11 )
*1
-6
-7
-5
Parameter
Symbol
Units
Notes
Min
95
Max
Min
115
135
Max
Min
135
160
Max
Random read or write cycle time
Read-modify-write cycle time
Access time from RAS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tRC
113
tRWC
tRAC
tCAC
tAA
55
18
65
20
75
25
3,4,10
3,4,5
3,10
Access time from CAS
Access time from column address
RAS pulse width
30
35
40
55
18
18
55
30
18
55
30
40
58
55
10K
10K
65
20
20
65
35
20
65
35
45
65
65
10K
10K
75
25
25
75
40
25
75
40
50
75
75
10K
10K
tRAS
tCAS
tRSH
tCSH
tRAL
tCWD
tRWD
tAWD
tPC
CAS pulse width
RAS hold time
CAS hold time
Column Address to RAS lead time
CAS to W delay time
7
7
7
RAS to W delay time
Column Address to W delay time
Fast Page mode cycle time
Fast Page mode read-modify-write cycle
RAS pulse width (Fast Page cycle)
Access time from CAS precharge
Note) *1 : 5V only
tPRWC
tRASP
tCPA
200K
35
200K
40
200K
45
3
KM41C4000D, KM41V4000D
CMOS DRAM
NOTES
An initial pause of 200us is required after power-up followed by any 8 RAS-only refresh or CAS-before-RAS refresh cycles
before proper device operation is achieved.
1.
2. VIH(min) and VIL(max) are reference levels for measuring timing of input signals. Transition times are measured between
VIH(min) and VIL(max) and are assumed to be 5ns for all inputs.
Measured with a load equivalent to 2 TTL(5V)/1 TTL(3.3V) loads and 100pF.
3.
4.
Operation within the tRCD(max) limit insures that tRAC(max) can be met. tRCD(max) is specified as a reference point only.
If tRCD is greater than the specified tRCD(max) limit, then access time is controlled exclusively by tCAC.
Assumes that tRCD³ tRCD(max).
5.
6.
This parameter defines the time at which the output achieves the open circuit condition and is not referenced to Voh or Vol.
tWCS, tRWD, tCWD, tAWD and tCPWD are non restrictive operating parameters. They are included in the data sheet as electrical
characteristics only. If tWCS³ tWCS(min), the cycle is an early write cycle and the data output will remain high impedance for
the duration of the cycle. If tCWD³ tCWD(min), tRWD³ tRWD(min), tAWD³ tAWD(min) and tCPWD³ tCPWD(min) then the cycle is a
read-modify-write cycle and the data output will contain the data read from the selected address. If neither of the above con-
ditions is satisfied, the condition of the data out is indeterminate.
7.
8.
9.
Either tRCH or tRRH must be satisfied for a read cycle.
These parameters are referenced to CAS falling edge in early write cycles and to W falling edge in read-modify-write cycles.
Operation within the tRAD(max) limit insures that tRAC(max) can be met. tRAD(max) is specified as a reference point only.
If tRAD is greater than the specified tRAD(max) limit, then access time is controlled by tAA.
10.
11.
12.
These specifiecations are applied in the test mode.
In test mode read cycle, the value of tRAC, tAA, tCAC is delayed by 2ns to 5ns for the specified values. These parameters
should be specified in test mode cycles by adding the above value to the specified value in this data sheet.
13. tOFF(MAX) defines the time at which the output achieves the open circuit condition and are not referenced to output voltage
level.
14.
15.
If tRASS³ 100us, then RAS precharge time must use tRPS instead of tRP.
For RAS-only refresh and burst CAS-before-RAS refresh mode, 1024(1K) cycle of burst refresh must be executed within
16ms before and after self refresh, in order to meet refresh specification.
For distributed CAS-before-RAS with 15.6us interval, CAS-before-RAS refresh should be executed with in 15.6us immedi-
ately before and after self refresh in order to meet refresh specification.
16.
KM41C4000D, KM41V4000D
CMOS DRAM
READ CYCLE
tRC
tRAS
tRP
VIH -
RAS
VIL -
tCSH
tCRP
tCRP
tRCD
tRSH
tCAS
VIH -
VIL -
CAS
tRAD
tRAL
tASR
tRAH
tASC
tRCS
tCAH
VIH -
VIL -
ROW
ADDRESS
COLUMN
ADDRESS
A
tRCH
tRRH
VIH -
VIL -
W
tOFF
tAA
tCAC
tCLZ
tRAC
VIH -
VIL -
OPEN
Q
DATA-OUT
Don¢t care
Undefined
KM41C4000D, KM41V4000D
CMOS DRAM
WRITE CYCLE ( EARLY WRITE )
tRC
tRAS
tRP
VIH -
RAS
VIL -
tCSH
tCRP
tCRP
tRCD
tRSH
tCAS
VIH -
VIL -
CAS
tRAD
tRAL
tASR
tRAH
tASC
tCAH
VIH -
VIL -
ROW
ADDRESS
COLUMN
ADDRESS
A
tCWL
tRWL
tWCS
tWCH
tWP
VIH -
VIL -
W
D
tDS
tDH
DATA-IN
VIH -
VIL -
Don¢t care
Undefined
KM41C4000D, KM41V4000D
CMOS DRAM
READ-WRITE / READ - MODIFY - WRTIE CYCLE
tRWC
tRP
tRAS
VIH -
RAS
VIL -
tCRP
tRCD
tRSH
tCAS
VIH -
CAS
VIL -
tRAD
tRAH
tASR
tASC
tCAH
tCSH
VIH -
VIL -
ROW
ADDR
COLUMN
ADDRESS
A
tRWL
tCWL
tAWD
tCWD
VIH -
VIL -
tWP
tDH
W
tDS
DATA-IN
VIH -
VIL -
D
tCLZ
tCAC
tOFF
tAA
tRAC
VIH -
VIL -
Q
DATA-OUT
Don¢t care
Undefined
KM41C4000D, KM41V4000D
CMOS DRAM
FAST PAGE READ CYCLE
tRP
tRASP
VIH -
tRHCP
RAS
VIL -
¡ ó
tPC
tCRP
tRCD
tCP
tCP
tRSH
tCAS
tCAS
VIH -
CAS
tCAS
VIL -
tRAD
tASC
¡ ó
tCSH
tASR
ROW
tASC
tCAH
tASC
tCAH
tRAH
tCAH
¡ ó
¡ ó
VIH -
VIL -
COLUMN
ADDRESS
COLUMN
COLUMN
ADDRESS
A
ADDRESS
ADDR
tRAL
tRCS
tRRH
tRCS
tRCH
tCAC
tRCS
tRCH
¡ ó
VIH -
VIL -
W
tCAC
tCAC
tAA
tOFF
tAA
tOFF
tAA
tOFF
tRAC
tCLZ
tCLZ
VALID
tCLZ
VIH -
VIL -
VALID
DATA-OUT
VALID
DATA-OUT
Q
DATA-OUT
Don¢t care
Undefined
KM41C4000D, KM41V4000D
CMOS DRAM
FAST PAGE WRITE CYCLE ( EARLY WRITE )
tRP
tRASP
VIH -
tRHCP
RAS
VIL -
¡ ó
tPC
tPC
tCRP
tCP
tRCD
tCP
tRSH
tCAS
tCAS
VIH -
VIL -
tCAS
CAS
tRAD
tASC
tRAH
ROW
¡ ó
tCStHCAH
tASC
tCAH
tASC
tCAH
tASR
¡ ó
¡ ó
VIH -
VIL -
COLUMN
ADDRESS
COLUMN
ADDRESS
COLUMN
A
ADDRESS
ADDR
tRAL
tWCH
tWP
tWCS
tWCS
tWCH
tWP
tWCS
tWCH
¡ ó
VIH -
VIL -
tWP
W
tCWL
tCWL
tRWL
tCWL
tDS
tDH
tDS
tDH
tDS
tDH
¡ ó
¡ ó
VIH -
VIL -
VALID
DATA-IN
VALID
DATA-IN
VALID
DATA-IN
D
Don¢t care
Undefined
KM41C4000D, KM41V4000D
CMOS DRAM
FAST PAGE READ - MODIFY - WRITE CYCLE
tRP
tRASP
tCP
VIH -
VIL -
tCSH
RAS
CAS
tRSH
tCAS
tRCD
tRAD
tCRP
VIH -
VIL -
tCAS
tPRWC
tCAH
tRAH
tASC
tRAL
tCAH
tASR
ROW
tASC
VIH -
VIL -
COL.
COL.
A
ADDR
ADDR
ADDR
tRWL
tWP
tRCS
tCWL
tCWL
VIH -
VIL -
tWP
W
tCWD
tAWD
tRWD
tCWD
tAWD
tCPWD
tDS
tDH
tDS
tDH
VIH -
VIL -
VALID
DATA-IN
VALID
DATA-IN
D
Q
tCAC
tAA
tCAC
tAA
tOFF
tOFF
tRAC
VIH -
VIL -
VALID
DATA-OUT
VALID
DATA-OUT
tCLZ
tCLZ
Don¢t care
Undefined
KM41C4000D, KM41V4000D
CMOS DRAM
RAS - ONLY REFRESH CYCLE
NOTE : W, DIN = Don¢t care
DOUT = OPEN
tRC
tRP
tRAS
VIH -
RAS
VIL -
tRPC
tCRP
tCRP
VIH -
CAS
VIL -
tASR
tRAH
VIH -
VIL -
ROW
ADDR
A
CAS - BEFORE - RAS REFRESH CYCLE
NOTE : A = Don¢t care
tRC
tRP
tRAS
tRP
VIH -
RAS
tRPC
tCP
VIL -
tRPC
VIH -
VIL -
tCSR
tWRP
CAS
W
tCHR
tWRH
VIH -
VIL -
tOFF
VIH -
VIL -
OPEN
Q
Don¢t care
Undefined
KM41C4000D, KM41V4000D
CMOS DRAM
HIDDEN REFRESH CYCLE ( READ )
tRC
tRC
tRP
tRP
tRAS
tRAS
VIH -
RAS
VIL -
tCRP
tRCD
tRSH
tCAH
tCHR
VIH -
VIL -
CAS
tRAD
tASR
tRAH
tASC
tRCS
VIH -
VIL -
ROW
ADDRESS
COLUMN
ADDRESS
A
tRAL
tWRH
VIH -
VIL -
W
tAA
tCAC
tCLZ
tOFF
tRAC
tWEZ
DATA-OUT
VIH -
VIL -
Q
OPEN
Don¢t care
Undefined
KM41C4000D, KM41V4000D
CMOS DRAM
HIDDEN REFRESH CYCLE ( WRITE )
NOTE : DOUT = OPEN
tRC
tRC
tRP
tRP
tRAS
tRAS
VIH -
RAS
VIL -
tCRP
tRCD
tRSH
tCHR
VIH -
CAS
VIL -
tRAD
tASR
tRAH
tASC
tCAH
VIH -
VIL -
ROW
ADDRESS
COLUMN
ADDRESS
A
W
D
tWRH
tWRP
tRAL
tWCS
tDS
tWCH
VIH -
VIL -
tWP
tDH
VIH -
VIL -
DATA-IN
Don¢t care
Undefined
KM41C4000D, KM41V4000D
CMOS DRAM
CAS-BEFORE-RAS REFRESH COUNTER TEST CYCLE
tRP
VIH -
VIL -
tRAS
RAS
CAS
tCPT
tRSH
tCAS
tCSR
VIH -
VIL -
tCHR
tRAL
tASC
tCAH
VIH -
VIL -
COLUMN
ADDRESS
A
READ CYCLE
tRRH
tAA
tWRP
tWRH
tRCS
tRCH
tCAC
VIH -
W
VIL -
tCLZ
tOFF
VIH -
Q
DATA-OUT
VIL -
WRITE CYCLE
tRWL
tWRP
tWRH
tCWL
VIH -
W
tWCS
tDS
tWCH
VIL -
tWP
tDH
VIH -
Q
DATA-IN
VIL -
READ-MODIFY-WRITE
tAWD
tCWL
tRWL
tWRP
tWRH
tRCS
tCWD
VIH -
tWP
W
VIL -
tCAC
tAA
tOLZ
tOFF
VIH -
Q
DATA-OUT
tDH
VIL -
tDS
VIH -
D
VIL -
VALID
DATA-IN
Don¢t care
Undefined
KM41C4000D, KM41V4000D
CMOS DRAM
CAS - BEFORE - RAS SELF REFRESH CYCLE
NOTE : A = Don¢t care
tRP
tRASS
tRPS
VIH -
RAS
tRPC
tCP
VIL -
tRPC
tCHR
VIH -
VIL -
tCSR
tWRP
CAS
tWRP
tWRH
VIH -
VIL -
W
Q
tOFF
VOH -
VOL -
OPEN
TEST MODE IN CYCLE
NOTE : D, A = Don¢t care
tRC
tRP
tRPC
tCP
tRAS
tRP
VIH -
RAS
VIL -
tRPC
VIH -
tCSR
tWTS
tCHR
CAS
VIL -
tWTH
VIH -
W
VIL -
tOFF
VIH -
D
OPEN
VIL -
Don¢t care
Undefined
KM41C4000D, KM41V4000D
CMOS DRAM
PLASTIC SMALL OUT-LINE J-LEAD
26(20) SOJ 300mil
Units : Inches (millimeters)
#26(20)
0.006 (0.15)
0.012 (0.30)
0.027 (0.69)
MIN
0.691 (17.55)
MAX
0.670 (17.03)
0.680 (17.27)
0.0375 (0.95)
0.050 (1.27)
0.026 (0.66)
0.032 (0.81)
0.015 (0.38)
0.021 (0.53)
26(20) TSOP(II) 300mil
Units : Inches (millimeters)
0.004 (0.10)
0.010 (0.25)
0.691 (17.54)
MAX
0.671 (17.04)
0.679 (17.24)
0.047 (1.20)
MAX
0.010 (0.25)
TYP
O
0~8
0.002 (0.05)
0.037 (0.95)
0.050 (1.27)
0.018 (0.45)
0.030 (0.75)
MIN
0.012 (0.30)
0.020 (0.50)
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