KM44C1004DT-L6 [SAMSUNG]
EDO DRAM, 1MX4, 60ns, CMOS, PDSO20, 0.300 INCH, TSOP2-26/20;
| 型号： | KM44C1004DT-L6 |
| 厂家： | 
SAMSUNG |
| 描述： | EDO DRAM, 1MX4, 60ns, CMOS, PDSO20, 0.300 INCH, TSOP2-26/20 动态存储器 光电二极管 |
| 文件： | 总22页 (文件大小：413K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
KM44C1004D, KM44V1004D
CMOS DRAM
1M x 4Bit CMOS Dynamic RAM with Extended Data Out
DESCRIPTION
This is a family of 1,048,576 x 41bit Extended Data Out CMOS DRAMs. Extended Data Out offers high speed random access of memory
cells within the same row. Power supply voltage (+5V or +3.3V), access time (-5, -6 or -7), power consumption(Normal or Low power),
and package type (SOJ or TSOP-II) are optional features of this family. All of this family have CAS-before-RAS refresh, RAS-only refresh
and Hidden refresh capabilities.
This 1Mx4 Extended Data Out DRAM family is fabricated using Samsung¢s advanced CMOS process to realize high band-width, low
power consumption and high reliability. It may be used as main memory for main frames and mini computers, personal computer and
high performance microprocessor systems.
• Extended Data Out operation
FEATURES
•
•
CAS-before-RAS refresh capability
• Part Identification
RAS-only and Hidden refresh capability
• Self-refresh capability (3.3V, L-ver only)
- KM44C1004D/D-L(5V)
- KM44V1004D/D-L(3.3V)
• TTL(5V)/LVTTL(3.3V) compatible inputs and outputs
• Early write or output enable controlled write
•
•
JEDEC Standard pinout
• Active Power Dissipation
Available in 26(20)-pin SOJ 300mil and TSOP(II)
300mil packages
Unit : mW
5V
Speed
-5
3.3V
-
•
Single +5V±10% power supply(5V product)
468
• Single +3.3V±0.3V power supply(3.3V product)
-6
220
200
413
-7
358
FUNCTIONAL BLOCK DIAGRAM
• Refresh Cycles
RAS
CAS
W
Vcc
Vss
Control
Clocks
Part
NO.
Refresh
cycle
Refresh Period
VBB Generator
Normal
L-ver
KM44C1004D
KM44V1004D
1K
16ms
128ms
Row Decoder
Refresh Timer
Refresh Control
Data in
Buffer
Memory Array
1,048,576 x4
Cells
DQ0
to
DQ3
Refresh Counter
Row Address Buffer
Col. Address Buffer
• Performance Range
Spee
-5
Remark
5V only
tRAC
50n
60n
70n
tCAC
tRC
tHPC
A0~A9
Data out
Buffer
15ns
84ns
20ns
Column Decoder
OE
-6
15ns 104ns 25ns 5V/3.3V
20ns 124ns 30ns 5V/3.3V
-7
SAMSUNG ELECTRONICS CO., LTD. reserves the right to
change products and specifications without notice.
KM44C1004D, KM44V1004D
CMOS DRAM
PIN CONFIGURATION (Top Views)
•KM44C/V1004DJ
•KM44C/V1004DT
¡ Û
DQ0
DQ1
W
RAS
A9
1 ¡ Û
2
20
19
18
17
16
VSS
DQ3
DQ2
CAS
OE
DQ0
DQ1
W
RAS
A9
1
2
3
4
5
20
19
18
17
16
VSS
DQ3
DQ2
CAS
OE
3
4
5
A0
A1
A2
A3
6
7
8
9
15
14
13
12
11
A8
A7
A6
A5
A4
A0
A1
A2
A3
6
15
14
13
12
11
A8
A7
A6
A5
A4
7
8
9
10
¡ Û
¡ Û
VCC
10
VCC
( SOJ )
( TSOP-II )
Pin Name
A0 - A9
DQ0 - 3
VSS
Pin function
Address Inputs
Data In/out
Ground
RAS
Row Address Strobe
Column Address Strobe
Data Outputs Enable
Data Outputs Enable
Power(+5V)
CAS
W
OE
VCC
Power(+3.3V)
KM44C1004D, KM44V1004D
CMOS DRAM
ABSOLUTE MAXIMUM RATINGS
Rating
Parameter
Symbol
Units
3.3V
-0.5 to +4.6
-0.5 to +4.6
-55 to +150
600
5V
Voltage on any pin relative to VSS
Voltage on VCC supply relative to VSS
Storage Temperature
VIN,VOUT
VCC
-1 to +7.0
-1 to +7.0
-55 to +150
600
V
V
Tstg
PD
°C
Power Dissipation
mW
mA
Short Circuit Output Current
IOS
50
50
* Permanent device damage may occur if "ABSOLUTE MAXIMUM RATINGS" are exceeded. Functional operation should be restricted to
the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended
periods may affect device reliability.
RECOMMENDED OPERATING CONDITIONS (Voltage referenced to Vss, TA= 0 to 70°C)
3.3V
Typ
5V
Typ
Parameter
Symbol
Units
Min
3.0
0
Max
3.6
0
Min
4.5
0
Max
5.5
0
Supply Voltage
VCC
VSS
VIH
VIL
3.3
5.0
V
V
V
V
Ground
0
-
0
-
*1
*1
Input High Voltage
Input Low Voltage
2.0
2.4
VCC+0.3
0.8
VCC+1.0
0.8
*2
*2
-
-
-0.3
-0.1
*1 : VCC +1.3V/15ns(3.3V), VCC +2.0V/20ns(5V), Pulse width is measured at VCC
*2 : - 1.3V/15ns(3.3V), - 2.0V/20ns(5V), Pulse width is measured at VSS
DC AND OPERATING CHARACTERISTICS (Recommended operating conditions unless otherwise noted.)
Parameter
Symbol
Min
Max
Units
Input Leakage Current (Any input 0£VIN£VCC+0.3V,
all other input pins not under test=0 Volt)
II(L)
-5
5
uA
Output Leakage Current
(Data out is disabled, 0V£VOUT£VCC)
IO(L)
-5
5
uA
3.3V
Output High Voltage Level(IOH=-2mA)
Output Low Voltage Level(IOL=2mA)
VOH
VOL
2.4
-
-
V
V
0.4
Input Leakage Current (Any input 0£VIN£VCC+0.5V,
all other input pins not under test=0 Volt)
II(L)
-5
-5
5
5
uA
uA
Output Leakage Current
(Data out is disabled, 0V£VOUT£VCC)
IO(L)
5V
Output High Voltage Level(IOH=-5mA)
Output Low Voltage Level(IOL=4.2mA)
VOH
VOL
2.4
-
-
V
V
0.4
KM44C1004D, KM44V1004D
CMOS DRAM
DC AND OPERATING CHARACTERISTICS (Recommend operating conditions unless otherwise noted.)
Max
Symbol
Power
Speed
Units
KM44V1004D
KM44C1004D
-5
-6
-7
-
60
55
85
75
65
mA
mA
mA
ICC1
ICC2
ICC3
Don¢t Care
Don¢t Care
Don¢t Care
Don¢t Care
1
2
mA
-5
-6
-7
-
60
55
85
75
65
mA
mA
mA
-5
-6
-7
-
60
55
85
75
65
mA
mA
mA
ICC4
ICC5
ICC6
Don¢t Care
Normal
L
0.5
100
1
200
mA
uA
Don¢t Care
-5
-6
-7
-
60
55
85
75
65
mA
mA
mA
Don¢t Care
ICC7
ICCS
L
L
Donn¢t Care
Donn¢t Care
200
150
300
-
uA
uA
ICC1* : Operating Current (RAS and CAS cycling @tRC=min.)
ICC2 : Standby Current (RAS=CAS=W=VIH)
ICC3* : RAS-only Refresh Current (CAS=VIH, RAS, Address cycling @tRC=min.)
ICC4* : EDO Mode Current (RAS=VIL, CAS, Address cycling @tHPC=min.)
ICC5 : Standby Current (RAS=CAS=W=VCC-0.2V)
ICC6* : CAS-Before-RAS Refresh Current (RAS and CAS cycling @tRC=min)
ICC7 : Battery back-up current, Average power supply current, Battery back-up mode
Input high voltage(VIH)=VCC-0.2V, Input low voltage(VIL)=0.2V, CAS=0.2V,
DQ0 ~ 3=Don¢t Care, TRC=125us, TRAS=TRASmin~300ns
ICCS : Self refresh current
RAS=CAS=VIL, W=OE =A0 ~ A9=VCC-0.2V or 0.2V
DQ0 ~ DQ3=VCC-0.2V, 0.2V or OPEN
*Note :
ICC1, ICC3, ICC4 and ICC6 are dependent on output loading and cycle rates. Specified values are obtained with the output open.
ICC is specified as an average current. In ICC1, ICC3 ICC6 and ICC7, address can be changed maximum once while RAS=VIL. In
ICC4, address can be changed maximum once within one EDO mode cycle time, tHPC.
KM44C1004D, KM44V1004D
CMOS DRAM
CAPACITANCE (TA=25°C, VCC=5V or 3.3V, f=1MHz)
Parameter
Input capacitance [A0 ~ A9]
Symbol
Min
Max
Units
pF
CIN1
CIN2
CDQ
-
-
-
5
7
7
Input capacitance [RAS, CAS, W, OE]
Output capacitance [DQ0 - DQ3]
pF
pF
AC CHARACTERISTICS (0°C£TA£70°C, See note 1,2)
Test condition (5V device) : VCC=5.0V±10%, Vih/Vil=2.4/0.8V, Voh/Vol=2.0/0.8V
Test condition (3.3V device) : VCC=3.3V±0.3V, Vih/Vil=2.2/0.7V, Voh/Vol=2.0/0.8V
-5 *1
-6
7
Parameter
Symbol
Units
Notes
Min
84
Max
Min
Max
Min
124
163
Max
Random read or write cycle time
Read-modify-write cycle time
Access time from RAS
104
138
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tRC
116
tRWC
tRAC
tCAC
tAA
50
15
25
60
15
30
70
20
35
3,4,10
3,4,5
3,10
3
Access time from CAS
Access time from column address
CAS to output in Low-Z
3
3
3
3
3
3
tCLZ
tCEZ
tT
Output buffer turn-off dealy from CAS
Transition time (rise and fall)
RAS precharge time
13
50
13
50
18
50
7,13
2
2
2
2
30
50
15
40
8
40
60
15
50
10
20
15
5
50
70
20
60
15
20
15
5
tRP
RAS pulse width
10K
10K
10K
tRAS
tRSH
tCSH
tCAS
tRCD
tRAD
tCRP
tASR
tRAH
tASC
tCAH
tRAL
tRCS
tRCH
tRRH
tWCH
tWP
RAS hold time
CAS hold time
CAS pulse width
10K
35
10K
45
10K
50
RAS to CAS delay time
20
15
5
4
RAS to column address delay time
CAS to RAS precharge time
Row address set-up time
Row address hold time
25
30
35
10
0
0
0
10
0
10
0
10
0
Column address set-up time
Column address hold time
Column address to RAS lead time
Read command set-up time
Read command hold time referenced to CAS
Read command hold time referenced to RAS
Write command hold time
Write command pulse width
Write command to RAS lead time
Write command to CAS lead time
Note) *1 : 5V only
8
10
30
0
15
35
0
25
0
0
0
0
8
8
0
0
0
10
10
13
8
10
10
15
10
15
15
15
15
tRWL
tCWL
KM44C1004D, KM44V1004D
CMOS DRAM
AC CHARACTERISTICS (0°C£TA£70°C, See note1, 2)
-5*1
Max
-6
-7
Parameter
Symbol
Units Notes
Max
Min
0
Min
0
Max
Min
0
Data set-up time
Data hold time
ns
ns
ms
ms
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
us
ns
ns
9
9
tDS
8
10
15
tDH
Refresh period (Normal)
16
16
16
tREF
tREF
tWCS
tCWD
tRWD
tAWD
tCPWD
tCSR
tCHR
tRPC
tCPT
tCPA
tHPC
tHPRWC
tCP
Refresh period (L-ver)
128
128
128
Write command set-up time
CAS to W delay time
0
0
0
7
7
7
7
7
32
67
42
45
5
32
77
47
52
5
42
92
57
62
5
RAS to W delay time
Column address to W delay time
CAS precharge to W delay time
CAS set-up time (CAS -before-RAS refresh)
CAS hold time (CAS -before-RAS refresh)
RAS to CAS precharge time
CAS precharge time (CBR counter test cycle)
Access time from CAS precharge
Hyper Page mode cycle time
Hyper Page read-modify-write cycle time
CAS precharge time (Hyper Page cycle)
RAS pulse width (Hyper Page cycle)
RAS hold time from CAS precharge
OE access time
10
5
10
5
15
5
20
20
25
28
35
40
3
20
57
8
25
66
10
60
35
30
81
10
70
40
15
50
30
200K
15
200K
15
200K
20
tRASP
tRHCP
tOEA
tOED
tOEZ
tOLZ
OE to data delay
13
3
13
3
18
3
Out put buffer turn off delay time from OE
OE to output in low-Z
13
13
18
6,13
3
3
3
OE command hold time
15
5
15
5
20
5
tOEH
tDOH
tREZ
tWEZ
tWED
tOCH
tCHO
tOEP
tWPE
tRASS
tRPS
tCHS
Output data hold time
Output buffer turn off delay time from RAS
Output buffer turn off delay time from W
W to data delay
3
15
13
3
15
13
3
20
18
6,13
6,13
3
3
3
13
5
13
5
18
5
OE to RAS hold time
CAS Hold time to OE
5
5
5
OE precharge time
5
5
5
W pulse width(hyper page cycle)
RAS pulse width (C-B-R self refresh)
RAS precharge time width (C-B-R self
CAS Hold time (C-B-R self refresh)
Note) *1 : 5V only
5
5
5
100
90
-50
100
110
-50
100
130
-50
16
16
16
KM44C1004D, KM44V1004D
CMOS DRAM
TEST MODE CYCLE
( Note 11 )
-5*1
Max
-6
-7
Parameter
Symbol
Units
Notes
Min
89
Min
109
145
Max
Min
129
170
Max
Random read or write cycle time
Read-modify-write cycle time
Access time from RAS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tRC
121
tRWC
tRAC
tCAC
tAA
55
18
65
20
75
25
3,4,10
3,4,5
3,10
Access time from CAS
Access time from column address
RAS pulse width
30
35
40
55
13
18
45
30
35
72
47
25
52
55
10K
10K
65
15
20
55
35
39
84
54
30
61
65
10K
10K
75
20
25
65
40
49
94
64
35
76
75
10K
10K
tRAS
tCAS
tRSH
tCSH
tRAL
CAS pulse width
RAS hold time
CAS hold time
Column Address to RAS lead time
CAS to W delay time
7
7
tCWD
tRWD
tAWD
tHPC
tHPRWC
tRASP
tCPA
RAS to W delay time
Column Address to W delay time
Hyper Page mode cycle time
Hyper Page mode read-modify-write cycle
RAS pulse width (Hyper Page cycle)
Access time from CAS precharge
7
15
200K
33
200K
40
200K
45
3
OE access time
18
20
25
ns
ns
ns
tOEA
tOED
tOEH
OE to data delay
OE command hold time
Note) *1 : 5V only
18
18
20
20
25
25
KM44C1004D, KM44V1004D
CMOS DRAM
NOTES
An initial pause of 200us is required after power-up followed by any 8 RAS-only or CAS-before-RAS refresh cycles before
proper device operation is achieved.
1.
2.
Input voltage levels are Vih/Vil. VIH(min) and VIL(max) are reference levels for measuring timing of input signals. Transition
times are measured between VIH(min) and VIL(max) and are assumed to be 2ns for all inputs.
Measured with a load equivalent to 2 TTL(5V device)/1TTL(3.3V device) loads and 100pF.
Operation within the tRCD(max) limit insures that tRAC(max) can be met. tRCD(max) is specified as a reference point only.
If tRCD is greater than the specified tRCD(max) limit, then access time is controlled exclusively by tCAC.
Assumes that tRCD³ tRCD(max).
3.
4.
5.
6.
This parameter defines the time at which the output achieves the open circuit condition and is not referenced to Voh or Vol.
tWCS, tRWD, tCWD, tAWD and tCPWD are non restrictive operating parameters. They are included in the data sheet as electrical
characteristics only. If tWCS³ tWCS(min), the cycles is an early write cycle and the data output will remain high impedance for
the duration of the cycle. If tCWD³ tCWD(min), tRWD³ tRWD(min), tAWD³ tAWD(min) and tCPWD³ tCPWD(min) then the cycle is a
read-modify-write cycle and the data output will contain the data read from the selected address. If neither of the above con-
ditions is satisfied, the condition of the data out is indeterminate.
7.
8.
9.
Either tRCH or tRRH must be satisfied for a read cycle.
These parameters are referenced to the CAS falling edge in ealy write cycles and to the W falling edge in read-modify-write
cycles.
10. Operation within the tRAD(max) limit insures that tRAC(max) can be met. tRAD(max) is specified as a reference point only. If
tRAD is greater than the specified tRAD(max) limit, then access time is controlled by tAA.
11. These specifiecations are applied in the test mode.
12. In test mode read cycle, the value of tRAC, tAA, tCAC is delayed by 2ns to 5ns for the specified values. These parameters
should be specified in test mode cycles by adding the above value to the specified value in this data sheet.
13.
tCEZ(MAX) , tREZ(MAX), tOEZ(MAX) and tWEZ(MAX) define the time at which the output achieves the open circuit condition and are
not referenced to output voltage level.
14. If RAS goes high before CAS high going, the open circuit condition of the output is achieved by CAS high going. If CAS goes
high before CAS high going, the open circuit condition of the output is achieved by RAS high going.
tASC³ 6.0ns, Assume tT=2.0ns.
15.
16.
For all of the refresh mode except for distributed CAS-before-RAS refresh mode, 1024cycles of burst refresh must be exe-
cuted within 16ms before and after self refresh, in order to meet refresh specification.(3.3V L-ver.)
KM44C1004D, KM44V1004D
CMOS DRAM
READ CYCLE
tRC
tRAS
tRP
VIH -
RAS
VIL -
tCSH
tCRP
tCRP
tRCD
tRSH
VIH -
VIL -
tCAS
CAS
tRAD
tRAL
tASR
tRAH
tASC
tRCS
tCAH
VIH -
VIL -
ROW
ADDRESS
COLUMN
ADDRESS
A
tRCH
tRRH
VIH -
VIL -
W
tWEZ
tCEZ
tOEZ
tAA
VIH -
VIL -
tOEA
tOLZ
OE
tCAC
tCLZ
DQ0 ~ DQ3(7)
VOH -
VOL -
tREZ
DATA-OUT
tRAC
OPEN
Don¢t care
Undefined
KM44C1004D, KM44V1004D
CMOS DRAM
WRITE CYCLE ( EARLY WRITE )
NOTE : DOUT = OPEN
tRC
tRAS
tRP
VIH -
RAS
VIL -
tCSH
tCRP
tCRP
tRCD
tRSH
VIH -
VIL -
tCAS
CAS
tRAD
tRAL
tASR
tRAH
tASC
tCAH
VIH -
VIL -
ROW
ADDRESS
COLUMN
ADDRESS
A
tCWL
tRWL
tWCH
tWCS
VIH -
VIL -
tWP
W
VIH -
VIL -
OE
tDS
DQ0 ~ DQ3(7)
VIH -
VIL -
tDH
DATA-IN
Don¢t care
Undefined
KM44C1004D, KM44V1004D
CMOS DRAM
WRITE CYCLE ( OE CONTROLLED WRITE )
NOTE : DOUT = OPEN
tRC
tRAS
tRP
VIH -
RAS
VIL -
tCSH
tCRP
tCRP
tRCD
tRSH
tCAS
VIH -
VIL -
CAS
tRAD
tASC
tRAL
tASR
tRAH
tCAH
COLUMN
ADDRESS
VIH -
VIL -
ROW
ADDRESS
A
W
tCWL
tRWL
VIH -
VIL -
tWP
VIH -
VIL -
OE
tOEH
tOED
tDS
DQ0 ~ DQ3(7)
VIH -
VIL -
tDH
DATA-IN
Don¢t care
Undefined
KM44C1004D, KM44V1004D
CMOS DRAM
READ - MODIFY - WRITE CYCLE
tRWC
tRAS
tRP
VIH -
RAS
VIL -
tCRP
tRCD
tRSH
VIH -
CAS
tCAS
tCSH
VIL -
tRAD
tRAH
tASR
tASC
tCAH
VIH -
VIL -
ROW
ADDR
COLUMN
ADDRESS
A
tAWD
tCWD
tRWL
tCWL
VIH -
VIL -
W
tWP
tRWD
tOEA
VIH -
VIL -
OE
tOLZ
tCLZ
tCAC
tAA
tOED
tOEZ
tDS
tDH
DQ0 ~ DQ3(7)
tRAC
VI/OH -
VI/OL -
VALID
DATA-OUT
VALID
DATA-IN
Don¢t care
Undefined
KM44C1004D, KM44V1004D
CMOS DRAM
HYPER PAGE READ CYCLE
tRP
tRASP
VIH -
RAS
VIL -
¡ ó
tCSH
tRHCP
tCAS
tHPC
tHPC
tCAS
tHPC
tCAS
tCRP
tASR
tCP
tCP
tCP
tRCD
tCAS
VIH -
VIL -
CAS
tRAD
tRAH tASC
tCAH
tASC
tCAH
tASC
tCAH
tASC
tCAH
tREZ
VIH -
VIL -
COLUMN
ADDRESS
COLUMN
ADDRESS
COLUMN
ADDR
COLUMN
ADDRESS
ROW
A
ADDR
tRRH
tRCH
tRCS
VIH -
VIL -
W
tCPA
tCAC
tAA
tCHO
tOEP
tCAC
tAA
tCPA
tCAC
tAA
tCPA
tOCH
tOEA
tAA
VIH -
VIL -
tOEA
OE
tOEP
tOEZ
tOEA
tCAC
tDOH
tOEZ
tOEZ
DQ0 ~ DQ3(7)
VOH -
tRAC
VALID
DATA-OUT
VALID
VALID
DATA-OUT
DATA-OUT
VOL -
tOLZ
tCLZ
VALID
DATA-OUT
Don¢t care
Undefined
KM44C1004D, KM44V1004D
CMOS DRAM
HYPER PAGE WRITE CYCLE ( EARLY WRITE )
NOTE : DOUT = OPEN
tRP
tRASP
VIH -
tRHCP
RAS
VIL -
¡ ó
tHPC
tHPC
tRSH
tCRP
tRCD
tCP
tCP
VIH -
VIL -
tCAS
tCAS
tCAS
¡ ó
CAS
tRAD
tRAH
tCSH
tASC
tASR
tCAH
tASC
tCAH
COLUMN
tASC
tCAH
¡ ó
¡ ó
VIH -
VIL -
ROW
ADDR.
COLUMN
ADDRESS
COLUMN
ADDRESS
A
ADDRESS
tWCS
tWCH
tWCS
tWP
tWCH
tWCS
tWCH
tWP
¡ ó
VIH -
VIL -
tWP
W
tCWL
tCWL
tCWL
tRWL
¡ ó
¡ ó
VIH -
VIL -
OE
tDS
tDH
tDS
tDH
tDS
tDH
DQ0 ~ DQ3(7)
VIH -
¡ ó
¡ ó
VALID
DATA-IN
VALID
DATA-IN
VALID
DATA-IN
VIL -
Don¢t care
Undefined
KM44C1004D, KM44V1004D
CMOS DRAM
HYPER PAGE READ-MODIFY-WRITE CYCLE
tRP
tRASP
tCP
VIH -
VIL -
tCSH
tRSH
RAS
CAS
tHPRWC
tCAS
tCRP
tCRP
tRCD
VIH -
VIL -
tCAS
tRAD
tRAH
tRAL
tCAH
tCAH
tASR
tASC
tASC
VIH -
VIL -
ROW
ADDR
COL.
COL.
ADDR
A
W
ADDR
tRWL
tCWL
tRCS
tCWL
VIH -
VIL -
tWP
tWP
tCWD
tAWD
tRWD
tCWD
tAWD
tCPWD
VIH -
VIL -
tOEA
tOEA
OE
tOED
tOED
tCAC
tCAC
tDH
tDH
tAA
tAA
tOEZ
tOEZ
tDS
tDS
DQ0 ~ DQ3(7)
tRAC
VI/OH -
VI/OL -
tCLZ
tCLZ
VALID
tOLZ
tOLZ
VALID
DATA-OUT
VALID
DATA-OUT
VALID
DATA-IN
DATA-IN
Don¢t care
Undefined
KM44C1004D, KM44V1004D
CMOS DRAM
HYPER PAGE READ AND WRITE MIXED CYCLE
tRP
tRASP
VIH -
VIL -
READ(tCAC)
READ(tCPA)
READ(tAA)
WRITE
RAS
tHPC
tHPC
tHPC
tCAS
tCP
tCP
tCP
VIH -
VIL -
tCAS
tCAS
tCAH
tCAS
tCAH
CAS
A
tRAD
tRAH
tASR
tASC tCAH
tASC
tASC
tCAH
tASC
VIH -
VIL -
COLUMN
COL.
ADDR
COL.
ROW
ADDR
COLUMN
ADDRESS
ADDR
ADDRESS
tRCS
tRCH
tRCS
tRCH
tWCH
tRCH
VIH -
VIL -
tWCS
W
tWPE
tCPA
tCLZ
tWED
VIH -
VIL -
OE
tDH
tDS
tOEA
tCAC
tAA
tRAC
tWEZ
tREZ
tAA
tWEZ
DQ0 ~ DQ3(7)
VI/OH -
VALID
DATA-OUT
VALID
DATA-IN
VALID
DATA-OUT
VALID
DATA-OUT
VI/OL -
Don¢t care
Undefined
KM44C1004D, KM44V1004D
CMOS DRAM
RAS - ONLY REFRESH CYCLE*
NOTE : W, OE, DIN = Don¢t care
DOUT = OPEN
tRC
tRP
VIH -
tRAS
RAS
VIL -
tRPC
tCRP
tCRP
VIH -
CAS
VIL -
tASR
tRAH
VIH -
VIL -
ROW
ADDR
A
CAS - BEFORE - RAS REFRESH CYCLE
NOTE : OE , A = Don¢t care
tRC
tRP
tRP
tRAS
VIH -
RAS
VIL -
tRPC
tRPC
tCP
tCSR
VIH -
tCHR
CAS
VIL -
tWRP
tWRH
VIH -
W
VIL -
DQ0 ~ DQ3(7)
VOH -
VOL -
tCEZ
OPEN
Don¢t care
Undefined
* In RAS-only refresh cycle of 64Mb A-dile & B-die, when CAS signal transits from Low to High, the valid data may be cut off.
KM44C1004D, KM44V1004D
CMOS DRAM
HIDDEN REFRESH CYCLE ( READ )
tRC
tRC
tRP
tRP
tRAS
tRAS
VIH -
RAS
VIL -
tCRP
tRCD
tRSH
tCHR
VIH -
VIL -
CAS
tRAD
tASR
tRAH
tASC
tRCS
tCAH
COLUMN
ADDRESS
VIH -
VIL -
ROW
ADDRESS
A
W
tWRH
tWRP
tRRH
VIH -
VIL -
tAA
VIH -
VIL -
tOEA
OE
tCEZ
tOLZ
tCAC
tREZ
tWEZ
tCLZ
tRAC
DQ0 ~ DQ3(7)
VOH -
tOEZ
DATA-OUT
OPEN
VOL -
Don¢t care
Undefined
KM44C1004D, KM44V1004D
CMOS DRAM
HIDDEN REFRESH CYCLE ( WRITE )
NOTE : DOUT = OPEN
tRC
tRAS
tRC
tRAS
tRP
tRP
VIH -
RAS
VIL -
tCRP
tRCD
tRSH
tCHR
VIH -
VIL -
CAS
tRAD
tASR
tRAH
tASC
tCAH
VIH -
VIL -
ROW
ADDRESS
COLUMN
ADDRESS
A
W
tWRH
tWRP
tWCS
tWCH
VIH -
VIL -
tWP
VIH -
VIL -
OE
tDS
tDH
DATA-IN
DQ0 ~ DQ3(7)
VIH -
VIL -
Don¢t care
Undefined
KM44C1004D, KM44V1004D
CMOS DRAM
CAS-BEFORE-RAS REFRESH COUNTER TEST CYCLE
tRP
VIH -
VIL -
tRAS
RAS
CAS
tCPT
tRSH
tCAS
tCSR
VIH -
VIL -
tCHR
tRAL
tASC
tCAH
VIH -
VIL -
COLUMN
ADDRESS
A
tRRH
tAA
tWRP
tWRH
tRCS
READ CYCLE
tRCH
tCAC
VIH -
W
VIL -
VIH -
OE
VIL -
tREZ
tOEA
tOEZ
tCLZ
VOH -
DQ0 ~ DQ3(7)
DATA-OUT
VOL -
tWEZ
tCEZ
WRITE CYCLE
tRWL
tWRP
tWRH
tCWL
VIH -
W
tWCS
tWCH
tWP
VIL -
VIH -
OE
VIL -
tDS
tDH
DATA-IN
VIH -
DQ0 ~ DQ3(7)
VIL -
READ-MODIFY-WRITE
tAWD
tCWL
tRWL
tWRP
tWRH
tRCS
tCWD
VIH -
tWP
W
tCAC
tOEA
VIL -
tAA
VIH -
OE
tOED
tOEZ
VIL -
tDH
tCLZ
tDS
VI/OH -
DQ0 ~ DQ3(7)
VI/OL -
VALID
DATA-IN
VALID
DATA-IN
Don¢t care
Undefined
NOTE : This timing diagram is applied to all devices besides 16M DRAM 4th & 64M DRAM.
KM44C1004D, KM44V1004D
CMOS DRAM
CAS - BEFORE - RAS SELF REFRESH CYCLE
NOTE : OE, A = Don¢t care
tRP
tRASS
tRPS
VIH -
RAS
VIL -
tRPC
tCP
tRPC
tCHS
tCSR
VIH -
CAS
VIL -
DQ0 ~ DQ3(7)
VOH -
tCEZ
OPEN
VOL -
VIH -
VIL -
W
tWRP
tWRH
TEST MODE IN CYCLE
NOTE : OE , A = Don¢t care
tRC
tRP
tRP
tRAS
VIH -
RAS
VIL -
tRPC
tCP
tRPC
tCSR
tWTS
VIH -
VIL -
tCHR
CAS
W
tWTH
VIH -
VIL -
tOFF
DQ0 ~ DQ3(7)
VOH -
VOL -
OPEN
Don¢t care
Undefined
KM44C1004D, KM44V1004D
PACKAGE DIMENSION
26(20) SOJ 300mil
CMOS DRAM
Units : Inches (millimeters)
#26(20)
0.006 (0.15)
0.012 (0.30)
0.027 (0.69)
MIN
0.691 (17.55)
MAX
0.670 (17.03)
0.680 (17.27)
0.0375 (0.95)
0.050 (1.27)
0.026 (0.66)
0.032 (0.81)
0.015 (0.38)
0.021 (0.53)
26(20) TSOP(II) 300mil
Units : Inches (millimeters)
0.004 (0.10)
0.010 (0.25)
0.691 (17.54)
MAX
0.671 (17.04)
0.679 (17.24)
0.047 (1.20)
MAX
0.010 (0.25)
TYP
O
0~8
0.037 (0.95)
0.050 (1.27)
0.002 (0.05)
0.018 (0.45)
0.030 (0.75)
MIN
0.012 (0.30)
0.020 (0.50)
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