KM44C4000CK-6 [SAMSUNG]
Fast Page DRAM, 4MX4, 60ns, CMOS, PDSO24, 0.300 INCH, PLASTIC, SOJ-26/24;
| 型号： | KM44C4000CK-6 |
| 厂家： | 
SAMSUNG |
| 描述： | Fast Page DRAM, 4MX4, 60ns, CMOS, PDSO24, 0.300 INCH, PLASTIC, SOJ-26/24 动态存储器 光电二极管 内存集成电路 |
| 文件： | 总20页 (文件大小：340K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
KM44C4000C, KM44C4100C
KM44V4000C, KM44V4100C
CMOS DRAM
4M x 4Bit CMOS Dynamic RAM with Fast Page Mode
DESCRIPTION
This is a family of 4,194,304 x 4 bit Fast Page Mode CMOS DRAMs. Fast Page Mode offers high speed random access of memory cells
within the same row. Power supply voltage (+5.0V or +3.3V), refresh cycle (2K Ref. or 4K Ref.), access time (-5 or -6), power consump-
tion(Normal or Low power) and package type(SOJ or TSOP-II) are optional features of this family. All of this family have CAS-before-
RAS refresh, RAS-only refresh and Hidden refresh capabilities. Furthermore, Self-refresh operation is available in L-version.
This 4Mx4 Fast Page Mode DRAM family is fabricated using Samsung¢s advanced CMOS process to realize high band-width, low power
consumption and high reliability. It may be used as main memory for high level computer, microcomputer and personal computer.
FEATURES
• Fast Page Mode operation
•
Part Identification
• CAS-before-RAS refresh capability
• RAS-only and Hidden refresh capability
• Self-refresh capability (L-ver only)
- KM44C4000C/C-L (5V, 4K Ref.)
- KM44C4100C/C-L (5V, 2K Ref.)
- KM44V4000C/C-L (3.3V, 4K Ref.)
- KM44V4100C/C-L (3.3V, 2K Ref.)
• Fast parallel test mode capability
• TTL(5V)/LVTTL(3.3V) compatible inputs and outputs
• Early Write or output enable controlled write
• JEDEC Standard pinout
• Active Power Dissipation
Unit : mW
5V
• Available in Plastic SOJ and TSOP(II) packages
• Single +5V±10% power supply (5V product)
• Single +3.3V±0.3V power supply (3.3V product)
3.3V
Speed
4K
2K
4K
2K
-5
-6
324
288
396
360
495
440
605
550
FUNCTIONAL BLOCK DIAGRAM
• Refresh Cycles
Part
VCC
Refresh
cycle
Refresh period
RAS
CAS
W
Vcc
Vss
Control
Clocks
NO.
Normal
L-ver
VBB Generator
C4000C
V4000C
C4100C
V4100C
5V
3.3V
5V
4K
2K
64ms
Data in
128ms
Buffer
Row Decoder
Refresh Timer
Refresh Control
Refresh Counter
32ms
3.3V
DQ0
to
DQ3
Memory Array
4,194,304 x 4
Cells
• Performance Range
A0-A11
(A0 - A10) *1
A0 - A9
(A0 - A10) *1
Row Address Buffer
Col. Address Buffer
Speed
-5
Remark
tRAC
50ns
60ns
tCAC
tRC
tPC
Data out
Buffer
13ns
90ns
35ns 5V/3.3V
Column Decoder
OE
-6
15ns 110ns 40ns 5V/3.3V
Note) *1 : 2K Refresh
SAMSUNG ELECTRONICS CO., LTD. reserves the right to
change products and specifications without notice.
KM44C4000C, KM44C4100C
KM44V4000C, KM44V4100C
CMOS DRAM
PIN CONFIGURATION (Top Views)
•KM44C/V40(1)00CK
•KM44C/V40(1)00CS
VCC
DQ0
DQ1
W
RAS
1
2
3
4
5
6
24 VSS
23 DQ3
22 DQ2
21 CAS
20 OE
19 A9
VCC
DQ0
DQ1
W
RAS
1
2
3
4
5
6
24
23
22
21
20
19
VSS
DQ3
DQ2
CAS
OE
*A11(N.C)
*A11(N.C)
A9
A10
A0
A1
A2
A3
7
8
9
10
11
12
18 A8
17 A7
16 A6
15 A5
14 A4
13 VSS
A10
A0
A1
A2
A3
7
8
9
10
11
12
18
17
16
15
14
13
A8
A7
A6
A5
A4
VSS
VCC
VCC
*A11 is N.C for KM44C/V4100C(5V/3.3V, 2K Ref. product)
K : 300mil 26(24) SOJ
S : 300mil 26(24) TSOP II
Pin Name
A0 - A11
A0 - A10
DQ0 - 3
VSS
Pin Function
Address Inputs (4K Product)
Address Inputs (2K Product)
Data In/Out
Ground
RAS
Row Address Strobe
Column Address Strobe
Read/Write Input
CAS
W
OE
Data Output Enable
Power(+5V)
VCC
N.C
Power(+3.3V)
No Connection (2K Ref. product)
KM44C4000C, KM44C4100C
KM44V4000C, KM44V4100C
CMOS DRAM
ABSOLUTE MAXIMUM RATINGS
Rating
Parameter
Symbol
Units
3.3V
-0.5 to +4.6
-0.5 to +4.6
-55 to +150
1
5V
Voltage on any pin relative to VSS
Voltage on VCC supply relative to VSS
Storage Temperature
VIN,VOUT
VCC
-1.0 to +7.0
-1.0 to +7.0
-55 to +150
1
V
V
Tstg
PD
°C
W
Power Dissipation
Short Circuit Output Current
IOS
50
50
mA
* Permanent device damage may occur if "ABSOLUTE MAXIMUM RATINGS" are exceeded. Functional operation should be restricted
to the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.
RECOMMENDED OPERATING CONDITIONS (Voltage referenced to Vss, TA= 0 to 70°C)
3.3V
5V
Typ
5.0
0
Parameter
Symbol
Units
Min
3.0
0
Typ
Max
3.6
0
Min
4.5
0
Max
5.5
0
Supply Voltage
VCC
VSS
VIH
VIL
3.3
V
V
V
V
Ground
0
-
*1
*1
Input High Voltage
Input Low Voltage
2.0
2.4
-
VCC+0.3
0.8
VCC+1.0
0.8
*2
*2
-
-
-0.3
-1.0
*1 : VCC+1.3V/15ns(3.3V), VCC+2.0V/20ns(5V), Pulse width is measured at VCC
*2 : -1.3V/15ns(3.3V), -2.0V/20ns(5V), Pulse width is measured at VSS
DC AND OPERATING CHARACTERISTICS (Recommended operating conditions unless otherwise noted.)
Max
Parameter
Symbol
Min
Max
Units
Input Leakage Current (Any input 0£VIN£VIN+0.3V,
all other input pins not under test=0 Volt)
II(L)
-5
5
uA
Output Leakage Current
(Data out is disabled, 0V£VOUT£VCC)
IO(L)
-5
5
uA
3.3V
Output High Voltage Level(IOH=-2mA)
Output Low Voltage Level(IOL=2mA)
VOH
VOL
2.4
-
-
V
V
0.4
Input Leakage Current (Any input 0£VIN£VIN+0.5V,
all other input pins not under test=0 Volt)
II(L)
-5
-5
5
5
uA
uA
Output Leakage Current
(Data out is disabled, 0V£VOUT£VCC)
IO(L)
5V
Output High Voltage Level(IOH=-5mA)
Output Low Voltage Level(IOL=4.2mA)
VOH
VOL
2.4
-
-
V
V
0.4
KM44C4000C, KM44C4100C
KM44V4000C, KM44V4100C
CMOS DRAM
DC AND OPERATING CHARACTERISTICS (Continued)
Max
Symbol
Power
Speed
Units
KM44V4000C
KM44V4100C
KM44C4000C
KM44C4100C
-5
-6
90
80
110
100
90
80
110
100
mA
mA
ICC1
ICC2
ICC3
ICC4
ICC5
ICC6
Don¢t care
Normal
L
1
1
1
1
2
1
2
1
mA
mA
Don¢t care
-5
-6
90
80
110
100
90
80
110
100
mA
mA
Don¢t care
Don¢t care
-5
-6
80
70
90
80
80
70
90
80
mA
mA
Normal
L
0.5
200
0.5
200
1
250
1
250
mA
uA
Don¢t care
-5
-6
90
80
110
100
90
80
110
100
mA
mA
Don¢t care
ICC7
ICCS
L
L
Don¢t care
Don¢t care
250
200
250
200
300
250
300
250
uA
uA
ICC1* : Operating Current (RAS and CAS, Address cycling @tRC=min.)
ICC2 : Standby Current (RAS=CAS=W=VIH)
ICC3* : RAS-only Refresh Current (CAS=VIH, RAS, Address cycling @tRC=min.)
ICC4* : Fast Page Mode Current (RAS=VIL, CAS, Address cycling @tPC=min.)
ICC5 : Standby Current (RAS=CAS=W=VCC-0.2V)
ICC6* : CAS-Before-RAS Refresh Current (RAS and CAS cycling @tRC=min.)
ICC7 : Battery back-up current, Average power supply current, Battery back-up mode
Input high voltage(VIH)=VCC-0.2V, Input low voltage(VIL)=0.2V, CAS=0.2V,
DQ=Don¢t care, TRC=31.25us(4K/L-ver), 62.5us(2K/L-ver), TRAS=TRASmin~300ns
ICCS : Self Refresh Current
RAS=CAS=0.2V, W=OE=A0 ~ A11=VCC-0.2V or 0.2V,
DQ0 ~ DQ3=VCC-0.2V, 0.2V or Open
*Note :
ICC1, ICC3, ICC4 and ICC6 are dependent on output loading and cycle rates. Specified values are obtained with the output open.
ICC is specified as an average current. In ICC1, ICC3 and ICC6 address can be changed maximum once while RAS=VIL. In ICC4,
address can be changed maximum once within one fast page mode cycle time, tPC.
KM44C4000C, KM44C4100C
KM44V4000C, KM44V4100C
CMOS DRAM
CAPACITANCE (TA=25°C, VCC=5V or 3.3V, f=1MHz)
Parameter
Input capacitance [A0 ~ A11]
Symbol
Min
Max
Units
pF
CIN1
CIN2
CDQ
-
-
-
5
7
7
Input capacitance [RAS, CAS, W, OE]
Output capacitance [DQ0 - DQ3]
pF
pF
AC CHARACTERISTICS (0°C£TA£70°C, See note 1,2)
Test condition (5V device) : VCC=5.0V±10%, Vih/Vil=2.4/0.8V, Voh/Vol=2.4/0.4V
Test condition (3.3V device) : VCC=3.3V±0.3V, Vih/Vil=2.0/0.8V, Voh/Vol=2.0/0.8V
-5
-6
Parameter
Symbol
Units
Notes
Min
90
Max
Min
110
155
Max
Random read or write cycle time
Read-modify-write cycle time
Access time from RAS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tRC
133
tRWC
tRAC
tCAC
tAA
50
13
25
60
15
30
3,4,10
3,4,5
3,10
3
Access time from CAS
Access time from column address
CAS to output in Low-Z
0
0
0
tCLZ
tOFF
tT
Output buffer turn-off delay
Transition time (rise and fall)
RAS precharge time
13
50
0
15
50
6
3
3
2
30
50
13
50
13
20
15
5
40
60
15
60
15
20
15
5
tRP
RAS pulse width
10K
10K
tRAS
tRSH
tCSH
tCAS
tRCD
tRAD
tCRP
tASR
tRAH
tASC
tCAH
tRAL
tRCS
tRCH
tRRH
tWCH
tWP
RAS hold time
CAS hold time
CAS pulse width
10K
37
10K
45
RAS to CAS delay time
4
RAS to column address delay time
CAS to RAS precharge time
Row address set-up time
Row address hold time
25
30
10
0
0
10
0
10
0
Column address set-up time
Column address hold time
Column address to RAS lead time
Read command set-up time
Read command hold time referenced to CAS
Read command hold time referenced to RAS
Write command hold time
Write command pulse width
Write command to RAS lead time
Write command to CAS lead time
10
25
0
10
30
0
0
0
8
8
0
0
10
10
13
13
10
10
15
15
tRWL
tCWL
KM44C4000C, KM44C4100C
KM44V4000C, KM44V4100C
CMOS DRAM
AC CHARACTERISTICS (Continued)
-5
-6
Parameter
Symbol
Units
Note
Min
0
Max
Min
0
Max
Data set-up time
Data hold time
ns
ns
ms
ms
ms
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
us
ns
ns
9
9
tDS
10
10
tDH
Refresh period (2K, Normal)
32
64
32
64
tREF
tREF
tREF
tWCS
tCWD
tRWD
tAWD
tCPWD
tCSR
tCHR
tRPC
tCPA
tPC
Refresh period (4K, Normal)
Refresh period (L-ver)
128
128
Write command set-up time
0
0
7
7
7
7
CAS to W delay time
36
73
48
53
5
40
85
55
60
5
RAS to W delay time
Column address to W delay time
CAS precharge to W delay time
CAS set-up time (CAS -before-RAS refresh)
CAS hold time (CAS -before-RAS refresh)
RAS to CAS precharge time
10
5
10
5
Access time from CAS precharge
Fast Page cycle time
30
35
3
35
76
10
50
30
40
85
10
60
35
Fast Page read-modify-write cycle time
CAS precharge time (Fast Page cycle)
RAS pulse width (Fast Page cycle)
RAS hold time from CAS precharge
OE access time
tPRWC
tCP
200K
13
200K
15
tRASP
tRHCP
tOEA
tOED
tOEZ
tOEH
tWTS
tWTH
tWRP
tWRH
tRASS
tRPS
tCHS
OE to data delay
13
0
15
0
Output buffer turn off delay time from OE
OE command hold time
13
15
6
13
10
10
10
10
100
90
-50
15
Write command set-up time (Test mode in)
Write command hold time (Test mode in)
W to RAS precharge time(C-B-R refresh)
W to RAS hold time(C-B-R refresh)
RAS pulse width (C-B-R self refresh)
RAS precharge time (C-B-R self refresh)
CAS hold time (C-B-R self refresh)
10
11
11
10
10
10
100
110
-50
13,14,15
13,14,15
13,14,15
KM44C4000C, KM44C4100C
KM44V4000C, KM44V4100C
CMOS DRAM
( Note 11 )
TEST MODE CYCLE
-5
-6
Parameter
Symbol
Units
Notes
Min
95
Max
Min
115
160
Max
Random read or write cycle time
Read-modify-write cycle time
Access time from RAS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tRC
138
tRWC
tRAC
tCAC
tAA
55
18
65
20
3,4,10,12
3,4,5,12
3,10,12
Access time from CAS
Access time from column address
RAS pulse width
30
35
55
18
18
55
30
41
78
53
58
40
81
55
10K
10K
65
20
20
65
35
45
90
60
65
45
90
65
10K
10K
tRAS
tCAS
tRSH
tCSH
tRAL
CAS pulse width
RAS hold time
CAS hold time
Column address to RAS lead time
CAS to W delay time
7
7
7
tCWD
tRWD
tAWD
tCPWD
tPC
RAS to W delay time
Column address to W delay time
CAS precharge to W delay time
Fast Page cycle time
Fast Page read-modify-write cycle time
RAS pulse width (Fast Page cycle)
Access time from CAS precharge
OE access time
tPRWC
tRASP
tCPA
tOEA
tOED
tOEH
200K
35
200K
40
3
18
20
OE to data delay
18
18
20
20
OE command hold time
KM44C4000C, KM44C4100C
KM44V4000C, KM44V4100C
CMOS DRAM
NOTES
1. An initial pause of 200us is required after power-up followed by any 8 RAS-only refresh or CAS-before-RAS refresh cycles
before proper device operation is achieved.
2. VIH(min) and VIL(max) are reference levels for measuring timing of input signals. Transition times are measured between
VIH(min) and VIL(max) and are assumed to be 5ns for all inputs.
Measured with a load equivalent to 2 TTL(5V)/1 TTL(3.3V) loads and 100pF.
3.
4.
Operation within the tRCD(max) limit insures that tRAC(max) can be met. tRCD(max) is specified as a reference point only.
If tRCD is greater than the specified tRCD(max) limit, then access time is controlled exclusively by tCAC.
Assumes that tRCD³ tRCD(max).
5.
6.
tOFF(min)and tOEZ(max) define the time at which the output achieves the open circuit condition and are not referenced Voh
or Vol.
tWCS, tRWD, tCWD and tAWD are non restrictive operating parameters. They are included in the data sheet as electrical char-
acteristics only. If tWCS³ tWCS(min), the cycle is an early write cycle and the data output will remain high impedance for the
duration of the cycle. If tCWD³ tCWD(min), tRWD³ tRWD(min) and tAWD³ tAWD(min), then the cycle is a read-modify-write cycle
and the data output will contain the data read from the selected address. If neither of the above conditions is satisfied, the
condition of the data out is indeterminate.
7.
Either tRCH or tRRH must be satisfied for a read cycle.
8.
9.
These parameters are referenced to CAS falling edge in early write cycles and to W falling edge in read-modify-write cycles.
Operation within the tRAD(max) limit insures that tRAC(max) can be met. tRAD(max) is specified as a reference point only.
If tRAD is greater than the specified tRAD(max) limit, then access time is controlled by tAA.
These specifications are applied in the test mode.
10.
11.
12.
In test mode read cycle, the value of tRAC, tAA, tCAC is delayed by 2ns to 5ns for the specified values. These parameters
should be specified in test mode cycles by adding the above value to the specified value in this data sheet.
If tRASS³ 100us, then RAS precharge time must use tRPS instead of tRP.
13.
14. For RAS-only refresh and burst CAS-before-RAS refresh mode, 4096(4K)/2048(2K) cycles of burst refresh must be exe-
cuted within 64ms/32ms before and after self refresh, in order to meet refresh specification.
15.
For distributed CAS-before-RAS with 15.6us interval CAS-before-RAS refresh should be executed with in 15.6us immedi-
ately before and after self refresh in order to meet refresh specification.
KM44C4000C, KM44C4100C
KM44V4000C, KM44V4100C
CMOS DRAM
READ CYCLE
tRC
tRAS
tRP
VIH -
RAS
VIL -
tCSH
tCRP
tCRP
tRCD
tRSH
tCAS
VIH -
VIL -
CAS
tRAD
tRAL
tASR
tRAH
tASC
tRCS
tCAH
VIH -
VIL -
ROW
ADDRESS
COLUMN
ADDRESS
A
W
tRCH
tRRH
VIH -
VIL -
tOFF
tOEZ
tAA
VIH -
VIL -
tOEA
OE
tCAC
tCLZ
DQ0 ~ DQ3(7)
VOH -
VOL -
tRAC
DATA-OUT
OPEN
Don¢t care
Undefined
KM44C4000C, KM44C4100C
KM44V4000C, KM44V4100C
CMOS DRAM
WRITE CYCLE ( EARLY WRITE )
NOTE : DOUT = OPEN
tRC
tRAS
tRP
VIH -
RAS
VIL -
tCSH
tCRP
tCRP
tRCD
tRSH
tCAS
VIH -
VIL -
CAS
tRAD
tRAL
tASR
tRAH
tASC
tCAH
VIH -
VIL -
ROW
ADDRESS
COLUMN
ADDRESS
A
tCWL
tRWL
tWCS
tWCH
tWP
VIH -
VIL -
W
VIH -
VIL -
OE
DQ0 ~ DQ3(7)
VIH -
tDS
tDH
DATA-IN
VIL -
Don¢t care
Undefined
KM44C4000C, KM44C4100C
KM44V4000C, KM44V4100C
CMOS DRAM
WRITE CYCLE ( OE CONTROLLED WRITE )
NOTE : DOUT = OPEN
tRC
tRP
tRAS
VIH -
RAS
VIL -
tCSH
tCRP
tCRP
tRCD
tRSH
tCAS
VIH -
VIL -
CAS
tRAD
tRAL
tASR
tRAH
tASC
tCAH
COLUMN
ADDRESS
VIH -
VIL -
ROW
ADDRESS
A
W
tCWL
tRWL
VIH -
VIL -
tWP
VIH -
VIL -
OE
tOED
tOEH
tDS
DQ0 ~ DQ3(7)
VIH -
tDH
DATA-IN
VIL -
Don¢t care
Undefined
KM44C4000C, KM44C4100C
KM44V4000C, KM44V4100C
CMOS DRAM
READ - MODIFY - WRTIE CYCLE
tRWC
tRP
tRAS
VIH -
RAS
VIL -
tCRP
tRCD
tRSH
tCAS
VIH -
CAS
VIL -
tRAD
tRAH
tASR
tASC
tCAH
tCSH
VIH -
VIL -
ROW
ADDR
COLUMN
ADDRESS
A
tRWL
tCWL
tAWD
tCWD
VIH -
VIL -
tWP
W
tRWD
tOEA
VIH -
VIL -
OE
tCLZ
tCAC
tOED
tOEZ
tAA
tDS
tDH
DQ0 ~ DQ3(7)
VI/OH -
tRAC
VALID
DATA-OUT
VALID
DATA-IN
VI/OL -
Don¢t care
Undefined
KM44C4000C, KM44C4100C
KM44V4000C, KM44V4100C
CMOS DRAM
FAST PAGE READ CYCLE
tRP
tRASP
VIH -
tRHCP
RAS
VIL -
¡ ó
tPC
tCRP
tRCD
tCP
tCP
tRSH
tCAS
tCAS
VIH -
CAS
tCAS
VIL -
tRAD
tASC
¡ ó
tCSH
tASR
ROW
tASC
tCAH
tASC
tCAH
tRAH
tCAH
tRCH
¡ ó
¡ ó
VIH -
VIL -
COLUMN
ADDRESS
COLUMN
COLUMN
ADDRESS
A
W
ADDRESS
ADDR
tRAL
tRCS
tRRH
tRCS
tRCS
tRCH
¡ ó
VIH -
VIL -
tCAC
tOEA
tCAC
tOEA
tCAC
tOEA
¡ ó
¡ ó
VIH -
VIL -
OE
tAA
tOFF
tAA
tOFF
tCLZ
tAA
tOFF
tOEZ
tRAC
tCLZ
tCLZ
DQ0 ~ DQ3(7)
VOH -
VOL -
tOEZ
VALID
tOEZ
VALID
VALID
DATA-OUT
DATA-OUT
DATA-OUT
Don¢t care
Undefined
KM44C4000C, KM44C4100C
KM44V4000C, KM44V4100C
CMOS DRAM
FAST PAGE WRITE CYCLE ( EARLY WRITE )
NOTE : DOUT = OPEN
tRP
tRASP
VIH -
tRHCP
RAS
VIL -
¡ ó
tPC
tPC
tCRP
tCP
tRCD
tCP
tRSH
tCAS
tCAS
VIH -
VIL -
tCAS
CAS
tRAD
tASC
tRAH
ROW
¡ ó
tRAL
tCAH
tCStHCAH
tASC
tCAH
tASC
tASR
¡ ó
¡ ó
VIH -
VIL -
COLUMN
ADDRESS
COLUMN
ADDRESS
COLUMN
A
ADDRESS
ADDR
tWCS
tWCS
tWCH
tWP
tWCS
tWCH
¡ ó
tWCH
VIH -
VIL -
tWP
tWP
W
tCWL
tCWL
tRWL
tCWL
¡ ó
VIH -
VIL -
OE
¡ ó
tDS
tDH
tDS
tDH
tDS
tDH
DQ0 ~ DQ3(7)
VIH -
VIL -
¡ ó
¡ ó
VALID
DATA-IN
VALID
DATA-IN
VALID
DATA-IN
Don¢t care
Undefined
KM44C4000C, KM44C4100C
KM44V4000C, KM44V4100C
CMOS DRAM
FAST PAGE READ - MODIFY - WRITE CYCLE
tRP
tRASP
tCP
VIH -
VIL -
tCSH
RAS
CAS
tRSH
tCAS
tRCD
tRAD
tCRP
VIH -
VIL -
tCAS
tPRWC
tCAH
tRAH
tASC
tRAL
tCAH
tASR
ROW
tASC
VIH -
VIL -
COL.
COL.
A
ADDR
ADDR
ADDR
tRWL
tWP
tRCS
tCWL
tCWL
VIH -
VIL -
tWP
W
tCWD
tAWD
tRWD
tCWD
tAWD
tCPWD
VIH -
VIL -
tOEA
tOEA
OE
tOED
tCAC
tOED
tCAC
tDH
tDH
tAA
tAA
tDS
tOEZ
tDS
DQ0 ~ DQ3(7)
tOEZ
tRAC
VI/OH -
VI/OL -
tCLZ
tCLZ
VALID
DATA-IN
VALID
DATA-IN
VALID
DATA-OUT
VALID
DATA-OUT
Don¢t care
Undefined
KM44C4000C, KM44C4100C
KM44V4000C, KM44V4100C
CMOS DRAM
RAS - ONLY REFRESH CYCLE
NOTE : W, OE, DIN = Don¢t care
DOUT = OPEN
tRC
tRP
tRAS
VIH -
RAS
VIL -
tRPC
tCRP
tCRP
VIH -
CAS
VIL -
tASR
tRAH
VIH -
VIL -
ROW
ADDR
A
CAS - BEFORE - RAS REFRESH CYCLE
NOTE : OE, A = Don¢t care
tRC
tRP
tRAS
tRP
VIH -
RAS
tRPC
tCP
VIL -
tRPC
VIH -
VIL -
tCSR
tWRP
CAS
W
tCHR
tWRH
VIH -
VIL -
tOFF
DQ0 ~ DQ3(7)
VOH -
VOL -
OPEN
Don¢t care
Undefined
KM44C4000C, KM44C4100C
KM44V4000C, KM44V4100C
CMOS DRAM
HIDDEN REFRESH CYCLE ( READ )
tRC
tRC
tRP
tRP
tRAS
tRAS
VIH -
RAS
VIL -
tCRP
tRCD
tRSH
tCHR
VIH -
VIL -
CAS
tRAD
tASR
tRAH
tASC
tRCS
tCAH
COLUMN
VIH -
VIL -
ROW
ADDRESS
A
ADDRESS
tWRH
tRAL
VIH -
VIL -
W
tAA
VIH -
VIL -
OE
tOEA
tOFF
tCAC
tCLZ
DQ0 ~ DQ3(7)
VOH -
VOL -
tRAC
tOEZ
DATA-OUT
OPEN
Don¢t care
Undefined
KM44C4000C, KM44C4100C
KM44V4000C, KM44V4100C
CMOS DRAM
HIDDEN REFRESH CYCLE ( WRITE )
NOTE : DOUT = OPEN
tRC
tRC
tRP
tRP
tRAS
tRAS
VIH -
RAS
VIL -
tCRP
tRCD
tRSH
tCHR
VIH -
CAS
VIL -
tRAD
tASR
tRAH
tASC
tCAH
VIH -
VIL -
ROW
ADDRESS
COLUMN
ADDRESS
A
tWRH
tWRP
tRAL
tWCS
tWCH
VIH -
VIL -
W
tWP
VIH -
VIL -
OE
tDS
tDH
DQ0 ~ DQ3(7)
VIH -
VIL -
DATA-IN
Don¢t care
Undefined
KM44C4000C, KM44C4100C
KM44V4000C, KM44V4100C
CMOS DRAM
CAS - BEFORE - RAS SELF REFRESH CYCLE
NOTE : OE, A = Don¢t care
tRP
tRASS
tRPS
VIH -
RAS
tRPC
tCP
VIL -
tRPC
tCHS
VIH -
VIL -
tCSR
CAS
DQ0 ~ DQ3(7)
VOH -
tOFF
OPEN
VOL -
tWRP
tWRH
VIH -
W
VIL -
TEST MODE IN CYCLE
NOTE : OE, A = Don¢t care
tRC
tRP
tRAS
tRP
VIH -
RAS
VIL -
tRPC
tCP
tRPC
VIH -
tCSR
tWTS
tCHR
CAS
VIL -
tWTH
VIH -
W
VIL -
DQ0 ~ DQ3(7)
VOH -
tOFF
OPEN
VOL -
Don¢t care
Undefined
KM44C4000C, KM44C4100C
KM44V4000C, KM44V4100C
CMOS DRAM
PACKAGE DIMENSION
26(24) SOJ 300mil
Units : Inches (millimeters)
#26(24)
0.006 (0.15)
0.012 (0.30)
0.027 (0.69)
MIN
0.691 (17.55)
MAX
0.670 (17.03)
0.680 (17.28)
0.0375 (0.95)
0.050 (1.27)
0.026 (0.66)
0.032 (0.81)
0.015 (0.38)
0.021 (0.53)
26(24) TSOP(II) 300mil
Units : Inches (millimeters)
0.004 (0.10)
0.010 (0.25)
0.691 (17.54)
MAX
0.671 (17.04)
0.679 (17.24)
0.047 (1.20)
MAX
0.010 (0.25)
TYP
O
0~8
0.002 (0.05)
0.037 (0.95)
0.050 (1.27)
0.018 (0.45)
0.030 (0.75)
MIN
0.012 (0.30)
0.020 (0.50)
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