KM44C4103CS-L5 [SAMSUNG]
Fast Page DRAM, 4MX4, 50ns, CMOS, PDSO28, 0.300 INCH, PLASTIC, TSOP2-28;型号: | KM44C4103CS-L5 |
厂家: | SAMSUNG |
描述: | Fast Page DRAM, 4MX4, 50ns, CMOS, PDSO28, 0.300 INCH, PLASTIC, TSOP2-28 动态存储器 光电二极管 内存集成电路 |
文件: | 总20页 (文件大小:376K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
KM44C4003C, KM44C4103C
CMOS DRAM
4M x 4Bit CMOS Quad CAS DRAM with Fast Page Mode
DESCRIPTION
This is a family of 4,194,304 x 4 bit Quad CAS with Fast Page Mode CMOS DRAMs. Fast Page Mode offers high speed random access
of memory cells within the same row. Refresh cycle (2K Ref. or 4K Ref.), access time (-5 or -6), power consumption(Normal or Low
power) and package type(SOJ or TSOP-II) are optional features of this family. All of this family have CAS-before-RAS refresh, RAS-only
refresh and Hidden refresh capabilities. Furthermore, Self-refresh operation is available in L-version. Four separate CAS pins provide for
seperate I/O operation allowing this device to operate in parity mode.
This 4Mx4 Fast Page Mode Quad CAS DRAM family is fabricated using Samsung¢s advanced CMOS process to realize high band-
width, low power consumption and high reliability.
FEATURES
• Part Identification
• Fast Page Mode operation
• Four seperate CAS pins provide for separate I/O operation
• CAS-before-RAS refresh capability
- KM44C4003C/C-L (5V, 4K Ref.)
- KM44C4103C/C-L (5V, 2K Ref.)
• RAS-only and Hidden refresh capability
• Self-refresh capability (L-ver only)
• Fast paralleltest mode capability
• TTL compatible inputs and outputs
• Early Write or output enable controlled write
• JEDEC Standard pinout
• Active Power Dissipation
Unit : mW
Refresh Cycle
Speed
• Available in Plastic SOJ and TSOP(II) packages
• Single +5V±10% power supply
4K
495
440
2K
-5
-6
605
550
FUNCTIONAL BLOCK DIAGRAM
• Refresh Cycles
Part
NO.
Refresh
cycle
Refresh period
RAS
CAS0 - 3
W
Vcc
Vss
Control
Clocks
Normal
L-ver
VBB Generator
C4003C
C4103C
4K
2K
64ms
32ms
128ms
Data in
Buffer
Row Decoder
Refresh Timer
Refresh Control
Refresh Counter
DQ0
to
DQ3
Memory Array
4,194,304 x 4
Cells
• Performance Range
Speed
-5
Remark
35ns 5V/3.3V
tRAC
50ns
60ns
tCAC
tRC
tPC
A0-A11
(A0 - A10) *1
A0 - A9
Row Address Buffer
Col. Address Buffer
13ns
90ns
Data out
Buffer
Column Decoder
-6
15ns 110ns 40ns 5V/3.3V
OE
(A0 - A10) *1
Note) *1 : 2K Refresh
SAMSUNG ELECTRONICS CO., LTD. reserves the right to
change products and specifications without notice.
KM44C4003C, KM44C4103C
CMOS DRAM
PIN CONFIGURATION (Top Views)
• KM44C40(1)03CS
• KM44C40(1)03CK
VCC
DQ0
DQ1
W
1
2
3
4
5
6
7
8
28
27
26
25
24
23
22
21
20
19
18
17
16
15
VSS
DQ3
DQ2
CAS3
OE
VCC
DQ0
DQ1
W
1
2
3
4
5
6
7
8
28
27
26
25
24
23
22
21
20
19
18
17
16
15
VSS
DQ3
DQ2
CAS3
OE
RAS
*A11(N.C)
CAS0
CAS1
A10
RAS
*A11(N.C)
CAS0
CAS1
A10
A9
A9
CAS2
N.C
A8
A7
A6
A5
A4
VSS
CAS2
N.C
A8
A7
A6
A5
A4
VSS
9
9
A0
A1
A2
A3
10
11
12
13
14
A0
A1
A2
A3
10
11
12
13
14
VCC
VCC
*A11 is N.C for KM44C4103C(5V, 2K Ref. product)
K : 300mil 28 SOJ
S : 300mil 28 TSOP II
Pin Name
A0 - A11
A0 - A10
DQ0 - 3
VSS
Pin Function
Address Inputs (4K Product)
Address Inputs (2K Product)
Data In/Out
Ground
RAS
Row Address Strobe
Column Address Strobe
Read/Write Input
Data Output Enable
Power(+5.0V)
CAS0~CAS3
W
OE
VCC
N.C
No Connection
KM44C4003C, KM44C4103C
CMOS DRAM
ABSOLUTE MAXIMUM RATINGS
Parameter
Symbol
VIN,VOUT
VCC Inputs
Tstg
Rating
-1.0 to +7.0
-1.0 to +7.0
-55 to +150
1
Units
V
Voltage on any pin relative to VSS
Voltage on VCC supply relative to VSS
Storage Temperature
V
°C
Power Dissipation
PD
W
Short Circuit Output Current
IOS
50
mA
* Permanent device damage may occur if "ABSOLUTE MAXIMUM RATINGS" are exceeded. Functional operation should be restricted
to the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.
RECOMMENDED OPERATING CONDITIONS (Voltage referenced to Vss, TA= 0 to 70°C)
Parameter
Supply Voltage
Symbol
VCC
Min
4.5
0
Typ
Max
5.5
0
Units
5.0
V
V
V
V
Ground
VSS
0
-
*1
Input High Voltage
Input Low Voltage
VIH
2.4
VCC+1.0
0.8
*2
VIL
-
-1.0
*1 : VCC+2.0V/20ns, Pulse width is measured at VCC
*2 : -2.0/20ns, Pulse width is measured at VSS
DC AND OPERATING CHARACTERISTICS (Recommended operating conditions unless otherwise noted.)
Parameter
Symbol
Min
Max
Units
Input Leakage Current (Any input 0£VIN£VIN+0.5V,
all other input pins not under test=0 Volt)
II(L)
-5
5
uA
Output Leakage Current
(Data out is disabled, 0V£VOUT£VCC)
IO(L)
-5
5
uA
Output High Voltage Level(IOH=-5mA)
Output Low Voltage Level(IOL=4.2mA)
VOH
VOL
2.4
-
-
V
V
0.4
KM44C4003C, KM44C4103C
CMOS DRAM
DC AND OPERATING CHARACTERISTICS (Continued)
Max
Symbol
Power
Speed
Units
KM44C4003C
KM44C4103C
mA
mA
mA
-5
-6
90
80
110
100
ICC1
ICC2
ICC3
Don¢t care
Normal
L
2
1
2
1
mA
mA
Don¢t care
mA
mA
mA
-5
-6
90
80
110
100
Don¢t care
Don¢t care
mA
mA
mA
-5
-6
80
70
90
80
ICC4
ICC5
ICC6
Normal
L
1
250
1
250
mA
uA
Don¢t care
mA
mA
mA
-5
-6
90
80
110
100
Don¢t care
ICC7
ICCS
L
L
Don¢t care
Don¢t care
300
250
300
250
uA
uA
ICC1* : Operating Current (RAS and CAS, Address cycling @tRC=min.)
ICC2 : Standby Current (RAS=CAS=W=VIH)
ICC3* : RAS-only Refresh Current (CAS=VIH, RAS, Address cycling @tRC=min.)
ICC4* : Fast Page Mode Current (RAS=VIL, CAS, Address cycling @tPC=min.)
ICC5 : Standby Current (RAS=CAS=W=VCC-0.2V)
ICC6* : CAS-Before-RAS Refresh Current (RAS and CAS cycling @tRC=min.)
ICC7 : Battery back-up current, Average power supply current, Battery back-up mode
Input high voltage(VIH)=VCC-0.2V, Input low voltage(VIL)=0.2V, CAS=0.2V,
DQ=Don¢t care, TRC=31.25us(4K/L-ver), 62.5us(2K/L-ver), TRAS=TRASmin~300ns
ICCS : Self Refresh Current
RAS=CAS=0.2V, W=OE=A0 ~ A11=VCC-0.2V or 0.2V,
DQ0 ~ DQ3=VCC-0.2V, 0.2V or Open
*Note :
ICC1, ICC3, ICC4 and ICC6 are dependent on output loading and cycle rates. Specified values are obtained with the output open.
ICC is specified as an average current. In ICC1, ICC3 and ICC6 address can be changed maximum once while RAS=VIL. In ICC4,
address can be changed maximum once within one fast page mode cycle time, tPC.
KM44C4003C, KM44C4103C
CMOS DRAM
CAPACITANCE (TA=25°C, VCC=5V, f=1MHz)
Parameter
Symbol
CIN1
Min
Max
Units
pF
Input capacitance [A0 ~ A11]
-
-
-
5
7
7
Input capacitance [RAS, CASx, W, OE]
Output capacitance [DQ0 - DQ3]
CIN2
pF
CDQ
pF
AC CHARACTERISTICS (0°C£TA£70°C, See note 1,2)
Test condition : VCC=5.0V±10%, Vih/Vil=2.4/0.8V, Voh/Vol=2.4/0.4V
-5
-6
Parameter
Symbol
Units
Notes
Min
90
Max
Min
110
155
Max
Random read or write cycle time
Read-modify-write cycle time
Access time from RAS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tRC
133
tRWC
tRAC
tCAC
tAA
50
13
25
60
15
30
3,4,10
3,4,5,18
3,10
3,18
6
Access time from CAS
Access time from column address
CAS to output in Low-Z
0
0
0
0
tCLZ
tOFF
tT
Output buffer turn-off delay
Transition time (rise and fall)
RAS precharge time
13
50
15
50
3
3
2
30
50
13
50
13
20
15
5
40
60
15
60
15
20
15
5
tRP
RAS pulse width
10K
10K
tRAS
tRSH
tCSH
tCAS
tRCD
tRAD
tCRP
tASR
tRAH
tASC
tCAH
tRAL
tRCS
tRCH
tRRH
tWCH
tWP
RAS hold time
14
17
CAS hold time
CAS pulse width
10K
37
10K
45
23
RAS to CAS delay time
4,16
10
RAS to column address delay time
CAS to RAS precharge time
Row address set-up time
Row address hold time
25
30
15
0
0
10
0
10
0
Column address set-up time
Column address hold time
Column address to RAS lead time
Read command set-up time
Read command hold time referenced to
Read command hold time referenced to
Write command hold time
Write command pulse width
Write command to RAS lead time
Write command to CAS lead time
16
16
10
25
0
10
30
0
0
0
8,15
8
0
0
10
10
13
13
10
10
15
15
14
tRWL
tCWL
17
KM44C4003C, KM44C4103C
CMOS DRAM
AC CHARACTERISTICS (Continued)
-5
-6
Parameter
Symbol
Units
Notes
Min
0
Max
Min
0
Max
Data set-up time
Data hold time
ns
ns
ms
ms
ms
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
us
ns
ns
ns
9
9
tDS
10
10
tDH
Refresh period (2K, Normal)
32
64
32
64
tREF
tREF
tREF
tWCS
tCWD
tRWD
tAWD
tCPWD
tCSR
tCHR
tRPC
tCPA
tPC
Refresh period (4K, Normal)
Refresh period (L-ver)
128
128
Write command set-up time
0
0
7,16
7,14
7
CAS to W delay time
36
73
48
53
5
40
85
55
60
5
RAS to W delay time
Column address to W delay time
CAS precharge to W delay time
CAS set-up time (CAS -before-RAS refresh)
CAS hold time (CAS -before-RAS refresh)
RAS to CAS precharge time
7
7
16
15
16
3,15
19
19
20
10
5
10
5
Access time from CAS precharge
Fast Page mode cycle time
30
35
35
76
10
50
30
40
85
10
60
35
Fast Page read-modify-write cycle time
CAS precharge time (Fast Page cycle)
RAS pulse width (Fast Page cycle)
RAS hold time from CAS precharge
OE access time
tPRWC
tCP
200K
13
200K
15
tRASP
tRHCP
tOEA
tOED
tOEZ
tOEH
tWTS
tWTH
tWRP
tWRH
tRASS
tRPS
tCHS
tCLCH
21
22
6
OE to data delay
13
0
15
0
Output buffer turn off delay time from OE
OE command hold time
13
15
13
10
10
10
10
100
90
-50
5
15
10
10
10
10
100
110
-50
5
Write command set-up time (Test mode in)
Write command hold time (Test mode in)
W to RAS precharge time(C-B-R refresh)
W to RAS hold time(C-B-R refresh)
RAS pulse width (C-B-R self refresh)
RAS precharge time (C-B-R self refresh)
CAS hold time (C-B-R self refresh)
Hold time CAS low to CAS high
11
11
25,26,27
25,26,27
25,26,27
13,24
KM44C4003C, KM44C4103C
CMOS DRAM
( Note 11 )
TEST MODE CYCLE
-5
-6
Parameter
Symbol
Units
Notes
Min
95
Max
Min
115
160
Max
Random read or write cycle time
Read-modify-write cycle time
Access time from RAS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tRC
138
tRWC
tRAC
tCAC
tAA
55
18
65
20
3,4,10,12
3,4,5,12
3,10,12
Access time from CAS
Access time from column address
RAS pulse width
30
35
55
18
18
55
30
41
78
53
58
40
81
55
10K
10K
65
20
20
65
35
45
90
60
65
45
90
65
10K
10K
tRAS
tCAS
tRSH
tCSH
tRAL
CAS pulse width
RAS hold time
CAS hold time
Column address to RAS lead time
CAS to W delay time
7
7
7
7
tCWD
tRWD
tAWD
tCPWD
tPC
RAS to W delay time
Column address to W delay time
CAS precharge to W delay time
Fast Page mode cycle time
Fast Page read-modify-write cycle time
RAS pulse width (Fast Page cycle)
Access time from CAS precharge
OE access time
tPRWC
tRASP
tCPA
tOEA
tOED
tOEH
200K
35
200K
40
3
18
20
OE to data delay
18
18
20
20
OE command hold time
KM44C4003C, KM44C4103C
CMOS DRAM
NOTES
An initial pause of 200us is required after power-up followed by any 8 RAS-only refresh or CAS-before-RAS refresh cycles
before proper device operation is achieved.
1.
2. VIH(min) and VIL(max) are reference levels for measuring timing of input signals.
Transition times are measured between VIH(min) and VIL(max) and are assumed to be 5ns for all inputs.
Measured with a load equivalent to 2 TTL loads and 100pF.
3.
4.
Operation within the tRCD(max) limit insures that tRAC(max) can be met. tRCD(max) is specified as a reference point only.
If tRCD is greater than the specified tRCD(max) limit, then access time is controlled exclusively by tCAC.
Assumes that tRCD³ tRCD(max).
5.
6. This parameter defines the time at which the output achieves the open circuit condition and is not referenced to Voh or Vol.
7. tWCS, tRWD, tCWD, tAWD and tCPWD are non restrictive operating parameters. They are included in the data sheet as electrical
characteristics only. If tWCS³ tWCS(min), the cycle is an early write cycle and the data output will remain high impedance for the
duration of the cycle. If tCWD³ tCWD(min), tRWD³ tRWD(min), tAWD³ tAWD(min) and tCPWD³ tCPWD(min), then the cycle is a read-
modify-write cycle and the data output will contain the data read from the selected address. If neither of the above conditions
is satisfied, the condition of the data out is indeterminate.
tRCH and tRRH must be satisfied for a read cycle.
8.
9.
These parameters are referenced to the first CAS falling edge in early write cycles and to W falling edge in OE controlled write
cycle and read-modify-write cycles.
Operation within the tRAD(max) limit insures that tRAC(max) can be met. tRAD(max) is specified as a reference point only.
If tRAD is greater than the specified tRAD(max) limit, then access time is controlled by tAA.
These specifications are applied in the test mode.
10.
11.
12.
In test mode read cycle, the values of tRAC, tAA and tCAC are delayed by 2ns to 5ns for the specified values. These parame-
ters should be specified in test mode cycles by adding 5ns to the specified value in this data sheet.
13. In order to hold the address latched by the first CAS going low, the parameter tCLCH must be met.
14.
15.
16.
The last CASx edge to go low.
The last CASx edge to go high.
The first CASx edge to go low.
17. The first CASx edge to go high.
Output parameter is refrenced to corresponding CASx input.
18.
19. The last rising CASx edge to next cycle¢s last rising CASx edge.
20. The last rising CASx edge to first falling CASx edge.
21.
The first DQx controlled by the first CASx to go low.
22. The last DQx controlled by the last CASx to go high.
23. Each CASx must meet minimum pulse width.
The last falling CASx edge to the first rising CASx edge.
24.
25.
26.
If tRASS³ 100us, then RAS precharge time must use tRPS instead of tRP.
For RAS-only refresh and burst CAS-before-RAS refresh mode, 4096(4K)/2048(2K) cycles of burst refresh must be executed
within 64ms/32ms before and after self refresh, in order to meet refresh specification.
27. For distributed CAS-before-RAS with 15.6us interval, CAS-before-RAS refresh should be executed with in 15.6us immedi-
ately before and after self refresh in order to meet refresh specification.
KM44C4003C, KM44C4103C
CMOS DRAM
READ CYCLE
NOTE : DOUT = OPEN
tRC
tRAS
tRP
VIH -
RAS
VIL -
tCSH
tCRP
tCRP
tRCD
tRSH
VIH -
tCAS
CAS0
VIL -
tCRP
VIH -
CAS1
VIL -
tCRP
VIH -
CAS2
VIL -
tCRP
tCLCH
VIH -
CAS3
VIL -
tRAD
tRAL
tASR
tRAH
tASC
tRCS
tCAH
COLUMN
ADDRESS
VIH -
VIL -
ROW
ADDRESS
A
W
tRCH
tRRH
VIH -
VIL -
tROH
tAA
tOEZ
VIH -
VIL -
tOEA
OE
tOFF
tCAC
tCLZ
DQ0 ~ DQ3
VIH -
VIL -
tRAC
OPEN
DATA-OUT
tOLZ
Don¢t care
Undefined
KM44C4003C, KM44C4103C
CMOS DRAM
WRITE CYCLE ( EARLY WRITE )
tRC
tRAS
tRP
VIH -
RAS
VIL -
tCSH
tCRP
tCRP
tRCD
tRSH
tCAS
VIH -
CAS0
VIL -
tCRP
VIH -
CAS1
VIL -
tCRP
VIH -
CAS2
VIL -
tCRP
tCLCH
tRAL
VIH -
CAS3
VIL -
tCSH
tCAH
tRAD
tASR
tRAH
tASC
VIH -
VIL -
ROW
ADDRESS
COLUMN
ADDRESS
A
tWCS
tWCH
tWP
VIH -
VIL -
W
VIH -
VIL -
OE
DQ0 ~ DQ3
VIH -
VIL -
tDS
tDH
DATA-IN
Don¢t care
Undefined
KM44C4003C, KM44C4103C
CMOS DRAM
WRITE CYCLE ( OE CONTROLLED WRITE )
tRC
tRAS
tRP
VIH -
RAS
VIL -
tCSH
tCRP
tCRP
tCRP
tCRP
tCRP
tRCD
tRSH
VIH -
VIL -
tCAS
CAS0
CAS1
CAS2
CAS3
VIH -
VIL -
VIH -
VIL -
tCLCH
tRAL
VIH -
VIL -
tRAD
tASR
tRAH
tASC
tCAH
VIH -
VIL -
ROW
ADDRESS
COLUMN
ADDRESS
A
W
tCWL
tRWL
VIH -
VIL -
tWP
VIH -
VIL -
OE
tOED
tOEH
tDS
DQ0 ~ DQ3
VIH -
VIL -
tDH
DATA-IN
Don¢t care
Undefined
KM44C4003C, KM44C4103C
CMOS DRAM
READ - MODIFY - WRTIE CYCLE
tRC
tRAS
tRP
VIH -
RAS
VIL -
tCSH
tCRP
tCRP
tRCD
tRSH
VIH -
tCAS
CAS0
VIL -
tCRP
VIH -
CAS1
VIL -
tCRP
VIH -
CAS2
VIL -
tCRP
tCLCH
VIH -
CAS3
VIL -
tRAD
tRAL
tASR
tRAH
tASC
tCAH
VIH -
VIL -
ROW
ADDRESS
COLUMN
ADDRESS
A
tRWL
tAWD
tCWD
tCWL
tWP
VIH -
VIL -
W
tRWD
tOEA
VIH -
VIL -
OE
tCLZ
tCAC
tOED
tOEZ
tDS
tAA
tDH
DQ0 ~ DQ3
VOH -
VOL -
tRAC
tOLZ
VALID
DATA-OUT
VALID
DATA-IN
Don¢t care
Undefined
KM44C4003C, KM44C4103C
CMOS DRAM
FAST PAGE READ CYCLE
NOTE : DOUT = OPEN
tRP
tRASP
VIH -
tRHCP
RAS
VIL -
¡ ó
tPC
tPC
tCRP
tRCD
tCP
tCP
tRSH
tCAS
tCAS
VIH -
tCAS
CAS0
VIL -
tASC
¡ ó
tCLCH
VIH -
CAS1
VIL -
VIH -
tCAS
CAS2
VIL -
¡ ó
VIH -
CAS3
VIL -
tRAD
tRAH
¡ ó
tCSH
tASR
ROW
tASC
tCAH
tASC
tCAH
tCAH
¡ ó
VIH -
VIL -
COLUMN
ADDRESS
COLUMN
ADDRESS
COLUMN
A
ADDR
ADDRESS
tRCS
¡ ó
tRCH
¡ ó
tRRH
tRCH
tRCS
tRCH
tRCS
VIH -
VIL -
W
tAA
tAA
tAA
tCPA
tCPA
tOEA
¡ ó
¡ ó
VIH -
VIL -
OE
tCAC
tRAC
tOEZ
VALID
tOEZ
tOEZ
VALID
tCLZ
¡ ó
tCLZ
VIH -
VIL -
VALID
DATA-OUT
DQ0
DQ1
DQ2
DQ3
DATA-OUT
DATA-OUT
tOEZ
tCLZ
VIH -
VIL -
VALID
DATA-OUT
VALID
DATA-OUT
¡ ó
tCLZ
tCLZ
tOLZ
VIH -
VIL -
VALID
DATA-OUT
VALID
DATA-OUT
¡ ó
tCLZ
VIH -
VIL -
VALID
DATA-OUT
¡ ó
Don¢t care
Undefined
KM44C4003C, KM44C4103C
CMOS DRAM
FAST PAGE WRITE CYCLE ( EARLY WRITE )
tRP
tRASP
VIH -
tRHCP
RAS
VIL -
¡ ó
tPC
tPC
tCRP
tCP
tRCD
tCP
tRSH
tCAS
tCAS
VIH -
VIL -
tCAS
tCAS
tCAS
CAS0
¡ ó
¡ ó
VIH -
VIL -
tCAS
CAS1
CAS2
CAS3
tCAS
VIH -
VIL -
¡ ó
tCAS
VIH -
VIL -
tRAD
tASC
tRAH
ROW
¡ ó
tCStHCAH
tASC
tCAH
tASC
tCAH
tASR
¡ ó
¡ ó
VIH -
VIL -
COLUMN
ADDRESS
COLUMN
ADDRESS
COLUMN
ADDRESS
A
ADDR
tWCS
tWCS
tWCH
tWP
tWCS
tWCH
¡ ó
tWCH
tWP
VIH -
VIL -
tWP
W
¡ ó
VIH -
VIL -
OE
¡ ó
tDS
tDH
tDS
tDH
tDS
VALID
tDH
¡ ó
¡ ó
VIH -
VIL -
VALID
DATA-IN
VALID
DATA-IN
DQ0
DATA-IN
tDS
tDH
tDS tDH
¡ ó
¡ ó
¡ ó
VIH -
VIL -
VALID
VALID
DATA-IN
DQ1
DQ2
DQ3
DATA-IN
tDS
tDH
tDS
tDH
VIH -
VIL -
VALID
VALID
DATA-IN
DATA-IN
¡ ó
¡ ó
¡ ó
tDS
tDH
VIH -
VIL -
VALID
DATA-IN
Don¢t care
Undefined
KM44C4003C, KM44C4103C
CMOS DRAM
FAST PAGE READ - MODIFY - WRITE CYCLE
tRP
tRASP
tCP
VIH -
tPRWC
RAS
VIL -
tRSH
tCAS
tCRP
tRCD
VIH -
tCAS
CAS0
VIL -
VIH -
tCLCH
tCAS
CAS1
VIL -
VIH -
tCAS
tCAS
CAS2
VIL -
VIH -
tCAS
tCLCH
tRAL
CAS3
VIL -
tCSH
tRAD
tRAH
tCAH
tCAH
tASR
tASC
tASC
VIH -
ROW
COL.
COL.
ADDR
A
ADDR
ADDR
VIL -
tRWL
tCWL
tRCS
tCWL
VIH -
VIL -
tWP
tWP
W
tCWD
tCWD
tAWD
tRWD
tAWD
VIH -
VIL -
tOEA
tCAC
tAA
tOEA
OE
tOED
tOED
tCAC
tDH
tDH
tAA
tDS
tOEZ
tDS
DQ0 ~ DQ3
VIH -
VIL -
tOEZ
tRAC
tCLZ
tCLZ
VALID
VALID
DATA-IN
VALID
VALID
DATA-OUT
DATA-IN
DATA-OUT
Don¢t care
Undefined
KM44C4003C, KM44C4103C
CMOS DRAM
RAS - ONLY REFRESH CYCLE
NOTE : W, OE, DIN = Don¢t care
DOUT = OPEN
tRC
tRP
tRAS
VIH -
RAS
VIL -
tRPC
tCRP
tCRP
VIH -
CASX
VIL -
tASR
tRAH
VIH -
VIL -
ROW
ADDR
A
CAS - BEFORE - RAS REFRESH CYCLE
NOTE : OE, A = Don¢t care
tRC
tRP
tRAS
tRP
VIH -
RAS
tRPC
tCP
VIL -
tRPC
VIH -
VIL -
tCSR
tWRP
CASX
W
tCHR
tWRH
VIH -
VIL -
tOFF
DQ0 ~ DQ3
VIH -
VIL -
OPEN
Don¢t care
Undefined
KM44C4003C, KM44C4103C
CMOS DRAM
HIDDEN REFRESH CYCLE ( READ )
tRC
tRC
tRP
tRP
tRAS
tRAS
VIH -
RAS
VIL -
tCRP
tRCD
tRSH
tCAH
tCHR
VIH -
VIL -
CASX
tRAD
tASR
tRAH
tASC
tRCS
VIH -
VIL -
COLUMN
ADDRESS
ROW
ADDRESS
A
tWRH
VIH -
VIL -
W
tAA
VIH -
VIL -
OE
tOEA
tOFF
tCAC
tCLZ
tRAC
tOEZ
VIH -
VIL -
DQX
DATA-OUT
OPEN
Don¢t care
Undefined
KM44C4003C, KM44C4103C
CMOS DRAM
HIDDEN REFRESH CYCLE ( WRITE )
NOTE : DOUT = OPEN
tRC
tRC
tRP
tRP
tRAS
tRAS
VIH -
RAS
VIL -
tCRP
tRCD
tRSH
tCHR
VIH -
CASX
VIL -
tRAD
tASR
tRAH
tASC
tCAH
VIH -
VIL -
ROW
ADDRESS
COLUMN
ADDRESS
A
tWCS
tWCH
VIH -
VIL -
W
tWP
VIH -
VIL -
OE
tDS
tDH
VIH -
VIL -
DATA-IN
DQX
Don¢t care
Undefined
KM44C4003C, KM44C4103C
CMOS DRAM
CAS - BEFORE - RAS SELF REFRESH CYCLE
NOTE : OE, A = Don¢t care
tRP
tRASS
tRPS
tRPC
VIH -
RAS
tRPC
tCP
VIL -
tCHS
VIH -
VIL -
tCSR
CASX
DQ0 ~ DQ3
VOH -
tOFF
OPEN
VOL -
TEST MODE IN CYCLE
NOTE : OE, A = Don¢t care
tRC
tRP
tRPC
tCP
tRAS
tRP
VIH -
RAS
VIL -
tRPC
VIH -
tCSR
tWTS
tCHR
CASX
VIL -
tWTH
VIH -
W
VIL -
DQ0 ~ DQ3
VIH -
tOFF
OPEN
VIL -
Don¢t care
Undefined
KM44C4003C, KM44C4103C
PACKAGE DIMENSION
28 SOJ 300mil
CMOS DRAM
Units : Inches (millimeters)
#28
0.006 (0.15)
0.012 (0.30)
#1
0.027 (0.69)
MIN
0.741 (18.82)
MAX
0.720 (18.30)
0.730 (18.54)
0.0375 (0.95)
0.050 (1.27)
0.026 (0.66)
0.032 (0.81)
0.015 (0.38)
0.021 (0.53)
28 TSOP(II) 300mil
Units : Inches (millimeters)
0.004 (0.10)
0.010 (0.25)
0.741 (18.81)
MAX
0.721 (18.31)
0.729 (18.51)
0.047 (1.20)
MAX
0.010 (0.25)
TYP
O
0~8
0.002 (0.05)
0.037 (0.95)
0.050 (1.27)
0.018 (0.45)
0.030 (0.75)
MIN
0.012 (0.30)
0.020 (0.50)
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