KM48S8030DT-FH00 [SAMSUNG]
Synchronous DRAM, 8MX8, 6ns, CMOS, PDSO54, 0.400 X 0.875 INCH, 0.80 MM PITCH, TSOP2-54;
| 型号： | KM48S8030DT-FH00 |
| 厂家： | 
SAMSUNG |
| 描述： | Synchronous DRAM, 8MX8, 6ns, CMOS, PDSO54, 0.400 X 0.875 INCH, 0.80 MM PITCH, TSOP2-54 动态存储器 光电二极管 内存集成电路 |
| 文件： | 总11页 (文件大小：120K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
KM48S8030D
CMOS SDRAM
64Mbit SDRAM
2M x 8Bit x 4 Banks
Synchronous DRAM
LVTTL
Revision 0.0
May 1999
* Samsung Electronics reserves the right to change products or specification without notice.
Rev. 0.0 May 1999
KM48S8030D
CMOS SDRAM
Revision History
Revision 0.0 (May 15, 1999)
• Changed tRDL from 1CLK to 2CLK in OPERATING AC PARAMETER.
• Skip ICC4 value of CL=2 in DC characteristics in datasheet.
• Define a new parameter of tDAL( 2CLK +20ns), Last data in to Active delay in OPERATING AC PARAMETER.
• Eliminated FREQUENCY vs.PARAMETER RELATIONSHIP TABLE.
• Symbol Change Notice
Before
After
I
I
I
Input leakage current (inputs)
IL
I
I
Input leakage current
LI
Input leakage current (I/O pins)
IL
Output open @ DC characteristic table
o
Output open @ DC characteristic table
OL
• Test Condition in DC CHARACTERISTIC Change Notice
Symbol
Before
CKE £ VIL(max), tCC = 15ns
CKE ³ VIH(min), CS ³ VIH(min), tCC = 15ns
After
I
I
I
CKE £ VIL(max), tCC = 10ns
CC2P , CC3P
I
CKE ³ VIH(min), CS ³ VIH(min), tCC = 10ns
CC2N , CC3N
Input signals are changed one time during 30ns
Input signals are changed one time during 20ns
I
2 Banks activated
4 Banks activated
CC4
Rev. 0.0 May 1999
KM48S8030D
CMOS SDRAM
2M x 8Bit x 4 Banks Synchronous DRAM
FEATURES
GENERAL DESCRIPTION
• JEDEC standard 3.3V power supply
• LVTTL compatible with multiplexed address
• Four banks operation
The KM48S8030D is 67,108,864 bits synchronous high data
rate Dynamic RAM organized as 4 x 2,097,152 words by 8 bits,
fabricated with SAMSUNG¢s high performance CMOS technol-
ogy. Synchronous design allows precise cycle control with the
use of system clock I/O transactions are possible on every clock
cycle. Range of operating frequencies, programmable burst
length and programmable latencies allow the same device to be
useful for a variety of high bandwidth, high performance mem-
ory system applications.
• MRS cycle with address key programs
-. CAS latency (2 & 3)
-. Burst length (1, 2, 4, 8 & Full page)
-. Burst type (Sequential & Interleave)
• All inputs are sampled at the positive going edge of the system
clock
• Burst read single-bit write operation
• DQM for masking
ORDERING INFORMATION
• Auto & self refresh
Part No.
Max Freq.
Interface Package
• 64ms refresh period (4K Cycle)
KM48S8030DT-G/FA
KM48S8030DT-G/F8
KM48S8030DT-G/FH
KM48S8030DT-G/FL
133MHz(CL=3)
125MHz(CL=3)
100MHz(CL=2)
100MHz(CL=3)
54
LVTTL
TSOP(II)
FUNCTIONAL BLOCK DIAGRAM
LWE
Data Input Register
LDQM
Bank Select
2M x 8
2M x 8
2M x 8
2M x 8
DQi
CLK
ADD
Column Decoder
Latency & Burst Length
LCKE
Programming Register
LWCBR
LRAS
LCBR
LWE
LCAS
LDQM
Timing Register
CLK
CKE
CS
RAS
CAS
WE
DQM
Samsung Electronics reserves the right to change products or specification without notice.
*
Rev. 0.0 May 1999
KM48S8030D
CMOS SDRAM
PIN CONFIGURATION (Top view)
VDD
DQ0
VDDQ
N.C
DQ1
VSSQ
N.C
DQ2
VDDQ
N.C
DQ3
VSSQ
N.C
VDD
N.C
WE
CAS
RAS
CS
1
2
3
4
5
6
7
8
VSS
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
DQ7
VSSQ
N.C
DQ6
VDDQ
N.C
DQ5
VSSQ
N.C
DQ4
VDDQ
N.C
VSS
N.C/RFU
DQM
CLK
CKE
N.C
A11
A9
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
BA0
BA1
A10/AP
A0
A8
A7
A6
A5
A4
VSS
A1
A2
A3
VDD
54Pin TSOP (II)
(400mil x 875mil)
(0.8 mm Pin pitch)
PIN FUNCTION DESCRIPTION
Pin
Name
System clock
Input Function
CLK
CS
Active on the positive going edge to sample all inputs.
Disables or enables device operation by masking or enabling all inputs except
CLK, CKE and DQM
Chip select
Masks system clock to freeze operation from the next clock cycle.
CKE should be enabled at least one cycle prior to new command.
Disable input buffers for power down in standby.
CKE
Clock enable
Row/column addresses are multiplexed on the same pins.
Row address : RA0 ~ RA11, Column address : CA0 ~ CA8
A0 ~ A11
BA0 ~ BA1
RAS
Address
Selects bank to be activated during row address latch time.
Selects bank for read/write during column address latch time.
Bank select address
Row address strobe
Column address strobe
Write enable
Latches row addresses on the positive going edge of the CLK with RAS low.
Enables row access & precharge.
Latches column addresses on the positive going edge of the CLK with CAS low.
Enables column access.
CAS
Enables write operation and row precharge.
Latches data in starting from CAS, WE active.
WE
Makes data output Hi-Z, tSHZ after the clock and masks the output.
Blocks data input when DQM active.
DQM
Data input/output mask
DQ0 ~ 7
VDD/VSS
Data input/output
Data inputs/outputs are multiplexed on the same pins.
Power and ground for the input buffers and the core logic.
Power supply/ground
Isolated power supply and ground for the output buffers to provide improved noise
immunity.
VDDQ/VSSQ
N.C/RFU
Data output power/ground
No connection
/reserved for future use
This pin is recommended to be left No Connection on the device.
Rev. 0.0 May 1999
KM48S8030D
CMOS SDRAM
ABSOLUTE MAXIMUM RATINGS
Parameter
Voltage on any pin relative to Vss
Voltage on VDD supply relative to Vss
Storage temperature
Symbol
VIN, VOUT
VDD, VDDQ
TSTG
Value
-1.0 ~ 4.6
-1.0 ~ 4.6
-55 ~ +150
1
Unit
V
V
°C
W
Power dissipation
PD
Short circuit current
IOS
50
mA
Note :
Permanent device damage may occur if "ABSOLUTE MAXIMUM RATINGS" are exceeded.
Functional operation should be restricted to recommended operating condition.
Exposure to higher than recommended voltage for extended periods of time could affect device reliability.
DC OPERATING CONDITIONS
Recommended operating conditions (Voltage referenced to VSS = 0V, TA = 0 to 70°C)
Parameter
Supply voltage
Symbol
VDD, VDDQ
VIH
Min
3.0
2.0
-0.3
2.4
-
Typ
Max
3.6
Unit
V
Note
3.3
Input logic high voltage
Input logic low voltage
Output logic high voltage
Output logic low voltage
Input leakage current
3.0
VDD+0.3
0.8
V
1
VIL
0
-
V
2
VOH
-
V
IOH = -2mA
IOL = 2mA
3
VOL
-
0.4
V
ILI
-10
-
10
uA
Notes :
1. VIH (max) = 5.6V AC. The overshoot voltage duration is £ 3ns.
2. VIL (min) = -2.0V AC. The undershoot voltage duration is £ 3ns.
3. Any input 0V £ VIN £ VDDQ.
Input leakage currents include Hi-Z output leakage for all bi-directional buffers with Tri-State outputs.
CAPACITANCE (VDD = 3.3V, TA = 23°C, f = 1MHz, VREF =1.4V ± 200 mV)
Pin
Symbol
CCLK
CIN
Min
2.5
2.5
2.5
4.0
Max
4.0
5.0
5.0
6.5
Unit
pF
Note
Clock
1
2
2
3
RAS, CAS, WE, CS, CKE, DQM
Address
pF
CADD
COUT
pF
DQ0 ~ DQ7
pF
Notes :
1. -A only specify a maximum value of 3.5pF
2. -A only specify a maximum value of 3.8pF
3. -A only specify a maximum value of 6.0pF
Rev. 0.0 May 1999
KM48S8030D
CMOS SDRAM
DC CHARACTERISTICS
(Recommended operating condition unless otherwise noted, TA = 0 to 70°C)
Version
Parameter
Symbol
Test Condition
Unit
Note
-A
-8
-H
-L
Burst length = 1
tRC ³ tRC(min)
IO = 0 mA
Operating current
(One bank active)
ICC1
75
75
70
70
mA
mA
1
ICC2P CKE £ VIL(max), tCC = 10ns
1
1
Precharge standby current in
power-down mode
ICC2PS CKE & CLK £ VIL(max), tCC = ¥
CKE ³ VIH(min), CS ³ VIH(min), tCC = 10ns
ICC2N
15
6
Input signals are changed one time during 20ns
Precharge standby current in
non power-down mode
mA
mA
CKE ³ VIH(min), CLK £ VIL(max), tCC = ¥
ICC2NS
Input signals are stable
ICC3P CKE £ VIL(max), tCC = 10ns
3
3
Active standby current in power-
down mode
ICC3PS CKE & CLK £ VIL(max), tCC = ¥
CKE ³ VIH(min), CS ³ VIH(min), tCC = 10ns
ICC3N
25
15
mA
mA
Active standby current in
non power-down mode
(One bank active)
Input signals are changed one time during 20ns
CKE ³ VIH(min), CLK £ VIL(max), tCC = ¥
ICC3NS
Input signals are stable
IO = 0 mA
Operating current
(Burst mode)
Page burst
4Banks Activated
ICC4
115 110 95
95
mA
1
tCCD = 2CLKs
Refresh current
ICC5
ICC6
tRC ³ tRC(min)
CKE £ 0.2V
135 130 125 125
mA
mA
uA
2
3
4
G
F
1
Self refresh current
400
Notes :
1. Measured with outputs open.
2. Refresh period is 64ms.
3. KM48S8030DT-G**
4. KM48S8030DT-F**
5. Unless otherwise noted, input swing IeveI is CMOS(VIH /VIL=VDDQ/VSSQ)
Rev. 0.0 May 1999
KM48S8030D
CMOS SDRAM
AC OPERATING TEST CONDITIONS(VDD = 3.3V ± 0.3V, TA = 0 to 70°C)
Parameter
Input levels (Vih/Vil)
Value
2.4/0.4
1.4
Unit
V
Input timing measurement reference level
Input rise and fall time
V
tr/tf = 1/1
1.4
ns
V
Output timing measurement reference level
Output load condition
See Fig. 2
3.3V
Vtt = 1.4V
1200W
50W
VOH (DC) = 2.4V, IOH = -2mA
VOL (DC) = 0.4V, IOL = 2mA
Output
Output
Z0 = 50W
50pF
50pF
870W
(Fig. 1) DC output load circuit
(Fig. 2) AC output load circuit
OPERATING AC PARAMETER
(AC operating conditions unless otherwise noted)
Version
Parameter
Symbol
Unit
Note
-A
15
20
20
45
-8
-H
20
20
20
50
-L
20
20
20
50
Row active to row active delay
RAS to CAS delay
tRRD(min)
tRCD(min)
tRP(min)
16
20
20
48
ns
ns
1
1
1
1
Row precharge time
ns
tRAS(min)
tRAS(max)
tRC(min)
ns
Row active time
100
2
us
Row cycle time
65
68
70
70
ns
1
2
Last data in to row precharge
Last data in to Active delay
Last data in to new col. address delay
Last data in to burst stop
tRDL(min)
tDAL(min)
tCDL(min)
tBDL(min)
tCCD(min)
CLK
2 CLK + 20 ns
1
1
1
2
CLK
CLK
CLK
2
2
3
Col. address to col. address delay
CAS latency=3
CAS latency=2
Number of valid output data
ea
4
-
1
Notes :
1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time
and then rounding off to the next higher integer.
2. Minimum delay is required to complete write.
3. All parts allow every cycle column address change.
4. In case of row precharge interrupt, auto precharge and read burst stop.
Rev. 0.0 May 1999
KM48S8030D
CMOS SDRAM
AC CHARACTERISTICS(AC operating conditions unless otherwise noted)
-A
-8
-H
-L
Parameter
Symbol
tCC
Unit
ns
Note
1
Min
7.5
-
Max
Min
Max
Min
10
Max
Min
10
Max
CAS latency=3
8
-
CLK cycle time
1000
1000
1000
1000
CAS latency=2
CAS latency=3
CAS latency=2
CAS latency=3
CAS latency=2
10
12
5.4
-
6
-
6
6
6
7
CLK to valid
output delay
tSAC
ns
1,2
2
2.7
-
3
-
3
3
3
3
2
1
1
3
3
3
3
2
1
1
Output data
hold time
tOH
ns
CLK high pulse width
CLK low pulse width
Input setup time
tCH
tCL
2.5
2.5
1.5
0.8
1
3
3
2
1
1
ns
ns
ns
ns
ns
3
3
3
3
2
tSS
Input hold time
tSH
tSLZ
CLK to output in Low-Z
CAS latency=3
CAS latency=2
5.4
-
6
-
6
6
6
7
CLK to output
in Hi-Z
tSHZ
ns
Notes : 1. Parameters depend on programmed CAS latency.
2. If clock rising time is longer than 1ns, (tr/2-0.5)ns should be added to the parameter.
3. Assumed input rise and fall time (tr & tf) = 1ns.
If tr & tf is longer than 1ns, transient time compensation should be considered,
i.e., [(tr + tf)/2-1]ns should be added to the parameter.
DQ BUFFER OUTPUT DRIVE CHARACTERISTICS
Parameter
Symbol
Condition
Min
Typ
Max
Unit
Notes
Measure in linear
region : 1.2V ~1.8V
Output rise time
trh
1.37
4.37
Volts/ns
3
Measure in linear
region : 1.2V ~1.8V
Output fall time
Output rise time
Output fall time
tfh
trh
tfh
1.30
2.8
3.8
5.6
5.0
Volts/ns
Volts/ns
Volts/ns
3
Measure in linear
region : 1.2V ~1.8V
3.9
2.9
1,2
1,2
Measure in linear
region : 1.2V ~1.8V
2.0
Notes :
1. Rise time specification based on 0pF + 50 Ohms to VSS, use these values to design to.
2. Fall time specification based on 0pF + 50 Ohms to VDD, use these values to design to.
3. Measured into 50pF only, use these values to characterize to.
4. All measurements done with respect to VSS.
Rev. 0.0 May 1999
KM48S8030D
CMOS SDRAM
66MHz and 100MHz Pull-up
1.5 2.5
IBIS SPECIFICATION
0
0.5
1
2
3
3.5
I
OH Characteristics (Pull-up)
0
-100
-200
-300
-400
-500
-600
100MHz
Min
I (mA)
100MHz
Max
I (mA)
-2.4
-27.3
66MHz
Min
I (mA)
Voltage
(V)
3.45
3.3
3.0
2.6
2.4
2.0
1.8
1.65
1.5
1.4
1.0
0.0
0.0
-21.1
-34.1
-58.7
-67.3
-73.0
-77.9
-80.8
-88.6
-93.0
-74.1
-0.7
-7.5
-129.2
-153.3
-197.0
-226.2
-248.0
-269.7
-284.3
-344.5
-502.4
-13.3
-27.5
-35.5
-41.1
-47.9
-52.4
-72.5
-93.0
Voltage
IOH Min (100MHz)
IOH Min (66MHz)
IOH Max (66 and 100MHz)
66MHz and 100MHz Pull-down
I
OL Characteristics (Pull-down)
250
200
150
100
50
100MHz
Min
100MHz
Max
66MHz
Min
I (mA)
0.0
Voltage
(V)
0
I (mA)
0.0
I (mA)
0.0
0.4
0.65
0.85
1
1.4
1.5
1.65
1.8
1.95
3
27.5
41.8
51.6
58.0
70.7
72.9
75.4
77.0
77.6
80.3
81.4
70.2
17.7
26.9
33.3
37.6
46.6
48.0
49.5
50.7
51.5
54.2
54.9
107.5
133.8
151.2
187.7
194.4
202.5
208.6
212.0
219.6
222.6
3.45
0
0
0.5
1
1.5
2
2.5
3
3.5
Voltage
IOL Min (100MHz)
IOL Min (66MHz)
IOL Max (100MHz)
Rev. 0.0 May 1999
KM48S8030D
CMOS SDRAM
Minimum VDD clamp current
(Referenced to VDD
V
DD Clamp @ CLK, CKE,CS, DQM & DQ
)
VDD (V)
0.0
0.2
0.4
0.6
0.7
0.8
0.9
1.0
1.2
1.4
1.6
1.8
2.0
2.2
2.4
2.6
I (mA)
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.23
1.34
3.02
5.06
7.35
9.83
12.48
15.30
18.31
20
15
10
5
0
0
1
2
3
Voltage
I (mA)
Minimum VSS clamp current
-2 -1
V
SS Clamp @ CLK, CKE,CS, DQM & DQ
-3
0
VSS (V)
-2.6
-2.4
-2.2
-2.0
-1.8
-1.6
-1.4
-1.2
-1.0
-0.9
-0.8
-0.7
-0.6
-0.4
-0.2
0.0
I (mA)
-57.23
-45.77
-38.26
-31.22
-24.58
-18.37
-12.56
-7.57
-3.37
-1.75
-0.58
-0.05
0.0
0
-10
-20
-30
-40
-50
-60
0.0
0.0
0.0
Voltage
I (mA)
Rev. 0.0 May 1999
KM48S8030D
CMOS SDRAM
SIMPLIFIED TRUTH TABLE
A
11,
CKEn-1 CKEn
CS
RAS
CAS
WE
DQM
BA0,1
A10/AP
Note
Command
A9 ~ A0
Register
Refresh
Mode register set
Auto refresh
H
H
X
H
L
L
L
L
L
X
OP code
X
1,2
3
L
L
L
H
X
X
Entry
3
Self
L
H
L
H
X
L
H
X
H
H
X
H
3
refresh
Exit
L
H
X
3
Bank active & row addr.
H
H
X
X
X
X
V
V
Row address
Column
address
(A0 ~ A8)
Read &
column address
Auto precharge disable
Auto precharge enable
Auto precharge disable
Auto precharge enable
L
H
L
4
4,5
4
L
L
H
H
L
L
H
L
Column
address
(A0 ~ A8)
Write &
Column Address
H
X
X
V
H
4,5
6
Burst stop
Precharge
H
H
X
X
L
L
H
L
H
H
L
L
X
X
X
Bank selection
All banks
V
X
L
X
H
H
L
X
V
X
X
H
X
V
X
X
V
X
X
H
X
V
X
V
X
X
H
X
V
Entry
H
L
X
Clock suspend or
active power down
X
X
Exit
L
H
L
X
H
L
X
X
Entry
H
Precharge power down mode
H
L
Exit
L
H
X
X
DQM
H
H
V
X
X
X
7
H
L
X
H
X
H
X
H
No operation command
(V=Valid, X=Don¢t care, H=Logic high, L=Logic low)
Notes :
1. OP Code : Operand code
A0 ~ A11 & BA0 ~ BA1 : Program keys. (@ MRS)
2. MRS can be issued only at all banks precharge state.
A new command can be issued after 2 CLK cycles of MRS.
3. Auto refresh functions are as same as CBR refresh of DRAM.
The automatical precharge without row precharge command is meant by "Auto".
Auto/self refresh can be issued only at all banks precharge state.
4. BA0 ~ BA1 : Bank select addresses.
If both BA0 and BA1 are "Low" at read, write, row active and precharge, bank A is selected.
If both BA0 is "Low" and BA1 is "High" at read, write, row active and precharge, bank B is selected.
If both BA0 is "High" and BA1 is "Low" at read, write, row active and precharge, bank C is selected.
If both BA0 and BA1 are "High" at read, write, row active and precharge, bank D is selected.
If A10/AP is "High" at row precharge, BA0 and BA1 is ignored and all banks are selected.
5. During burst read or write with auto precharge, new read/write command can not be issued.
Another bank read/write command can be issued after the end of burst.
New row active of the associated bank can be issued at tRP after the end of burst.
6. Burst stop command is valid at every burst length.
7. DQM sampled at positive going edge of a CLK and masks the data-in at the very CLK (Write DQM latency is 0),
but makes Hi-Z state the data-out of 2 CLK cycles after. (Read DQM latency is 2)
Rev. 0.0 May 1999
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Synchronous DRAM, 8MX8, 5.4ns, CMOS, PDSO54, 0.400 X 0.875 INCH, 0.80 MM PITCH, TSOP2-54
SAMSUNG
KM48S8030DT-GH
Synchronous DRAM, 8MX8, 6ns, CMOS, PDSO54, 0.400 X 0.875 INCH, 0.80 MM PITCH, TSOP2-54
SAMSUNG
KM48S8030DT-GL
Synchronous DRAM, 8MX8, 6ns, CMOS, PDSO54, 0.400 X 0.875 INCH, 0.80 MM PITCH, TSOP2-54
SAMSUNG
KM48S8030DT-GL00
Synchronous DRAM, 8MX8, 6ns, CMOS, PDSO54, 0.400 X 0.875 INCH, 0.80 MM PITCH, TSOP2-54
SAMSUNG
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