KM6164002AJE-200 [SAMSUNG]

Standard SRAM, 256KX16, 20ns, CMOS, PDSO44, 0.400 INCH, PLASTIC, SOJ-44;


型号：	KM6164002AJE-200
厂家：	SAMSUNG
描述：	Standard SRAM, 256KX16, 20ns, CMOS, PDSO44, 0.400 INCH, PLASTIC, SOJ-44 静态存储器光电二极管
文件：	总9页 (文件大小：197K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

PRELIMINARY

KM6164002A, KM6164002AE, KM6164002AI

CMOS SRAM

Document Title

256Kx16 Bit High Speed Static RAM(5V Operating), Revolutionary Pin out.

Operated at Commercial, Extended and Industrial Temperature Ranges.

Revision History

RevNo.

Rev. 0.0

Rev. 0.5

History

Draft Data

Remark

Initial release with Design Target.

Jun. 14th, 1996

Design Target

Release to Preliminary Data Sheet.

Sep. 16th, 1996

Preliminary

0.1. Replace Design Target to Preliminary.

0.2. Delete 12ns part but add 17ns part.

0.3. Relax D.C and A.C parameters and insert new parameter(Icc1)

with the test condition.

0.3.1. Insert Icc1 parameter with the test condition as address is

increased with binary count.

0.3.2. Relax D.C and A.C parameters.

Previous spec.

(15/ - /20ns part)

250/ - /240mA

10/ - /12ns

Relaxed spec.

(15/17/20ns part)

280/275/270mA

12/13/14ns

Items

Icc

tCW

tAW

10/ - /12ns

12/13/14ns

tWP(OE=H)

tWP1(OE=L)

tDW

10/ - /12ns

12/ - /14ns

7/ - /9ns

12/13/14ns

15/17/20ns

8/ 9/10ns

Rev. 1.0

Release to Final Data Sheet.

Jun. 5th, 1997

Final

1.1. Delete Preliminary.

1.2. Delete Icc1 parameter with the test condition.

1.3. Update D.C parameters.

Previous spec.

(15/17/20ns part)

280/275/270mA

Updated spec.

(15/17/20ns part)

210/205/200mA

Items

Icc

1.4. Add the test condition for VOH1 with Vcc=5V±5% at 25°C.

1.5. Add timing diagram to define tWP1 as ²(Timing Wave Form of

Write Cycle(OE=Low fixed)².

Rev.2.0

Rev.2.1

2.1 Add extended and industrial temperature range parts.

Add 44-TSOP2 Package.

Feb. 25th, 1998

Dec. 14th, 1998

Final

The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the

specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions on the parameters of this device. If you have any ques-

tions, please contact the SAMSUNG branch office near your office, call or contact Headquarters.

Rev 2.1

December 1998

- 1 -

PRELIMINARY

CMOS SRAM

KM6164002A, KM6164002AE, KM6164002AI

256K x 16 Bit High-Speed CMOS Static RAM

FEATURES

GENERAL DESCRIPTION

• Fast Access Time 15, 17, 20ns(Max.)

• Low Power Dissipation

The KM6164002A is a 4,194,304-bit high-speed Static Ran-

dom Access Memory organized as 262,144 words by 16 bits.

The KM6164002A uses 16 common input and output lines and

has an output enable pin which operates faster than address

access time at read cycle. Also it allows that lower and upper

byte access by data byte control(UB, LB). The device is fabri-

cated using SAMSUNG¢s advanced CMOS process and

designed for high-speed circuit technology. It is particularly well

suited for use in high-density high-speed system applications.

The KM6164002A is packaged in a 400mil 44-pin plastic SOJ

or TSOP(II) forward.

Standby (TTL)

: 50mA(Max.)

(CMOS) : 10mA(Max.)

Operating KM6164002A - 15 : 210mA(Max.)

KM6164002A - 17 : 205mA(Max.)

KM6164002A - 20 : 200mA(Max.)

• Single 5.0V±10% Power Supply

• TTL Compatible Inputs and Outputs

• I/O Compatible with 3.3V Devices

• Fully Static Operation

- No Clock or Refresh required

• Three State Outputs

PIN CONFIGURATION (Top View)

• Center Power/Ground Pin Configuration

• Data Byte Control ; LB: I/O1~ I/O8, UB: I/O9~ I/O16

• Standard Pin Configuration

44 A17

43 A16

42 A15

41 OE

KM6164002AJ : 44-SOJ-400

KM6164002AT : 44-TSOP2-400F

ORDERING INFORMATION

40 UB

KM6164002A-15/17/20

KM6164002AE-15/17/20

KM6164002AI-15/17/20

Commercial Temp.

Extended Temp.

Industrial Temp.

I/O1

I/O2

I/O3

39 LB

38 I/O16

37 I/O15

36 I/O14

35 I/O13

34 Vss

33 Vcc

32 I/O12

31 I/O11

30 I/O10

29 I/O9

28 N.C

27 A14

26 A13

25 A12

24 A11

23 A10

I/O4 10

Vcc 11

Vss 12

I/O5 13

I/O6 14

I/O7 15

I/O8 16

WE 17

A5 18

SOJ/

TSOP2

FUNCTIONAL BLOCK DIAGRAM

Clk Gen.

Pre-Charge Circuit

A6 19

Memory Array

1024 Rows

256x16 Columns

A7 20

A8 21

A9 22

Data

Cont.

I/O Circuit &

Column Select

PIN FUNCTION

I/O1~I/O8

Pin Name

A0 - A17

Pin Function

Data

Cont.

I/O9~I/O16

Address Inputs

Write Enable

Chip Select

Gen.

CLK

A11

A13

A15

A14 A16

A17

A10

A12

Output Enable

Lower-byte Control(I/O1~I/O8)

Upper-byte Control(I/O9~I/O16)

Data Inputs/Outputs

Power(+5.0V)

I/O1 ~ I/O16

VCC

VSS

Ground

N.C

No Connection

Rev 2.1

December 1998

- 2 -

PRELIMINARY

CMOS SRAM

KM6164002A, KM6164002AE, KM6164002AI

ABSOLUTE MAXIMUM RATINGS*

Parameter

Voltage on Any Pin Relative to VSS

Voltage on VCC Supply Relative to VSS

Power Dissipation

Symbol

VIN, VOUT

VCC

Rating

-0.5 to 7.0

1.0

Unit

Storage Temperature

TSTG

-65 to 150

0 to 70

°C

Operating Temperature

Commercial

Extended

Industrial

-25 to 85

-40 to 85

* Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and

functional operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied.

Exposure to absolute maximum rating conditions for extended periods may affect reliability.

RECOMMENDED DC OPERATING CONDITIONS*(TA=0 to 70°C)

Parameter

Min

4.5

Symbol

VCC

VSS

Typ

Max

Unit

Supply Voltage

5.0

5.5

Ground

VCC + 0.5**

0.8

Input High Voltage

Input Low Voltage

VIH

2.2

-0.5*

VIL

The above parameters are also guaranteed at extended and industrial temperature ranges.

** VIL(Min) = -2.0V a.c(Pulse Width £ 10ns) for I £ 20mA.

*** VIH(Max) = VCC + 2.0V a.c (Pulse Width £ 10ns) for I £ 20mA.

DC AND OPERATING CHARACTERISTICS*(TA=0 to 70°C, Vcc=5.0V±10%, unless otherwise specified)

Min

Max

Parameter

Input Leakage Current

Output Leakage Current

Symbol

ILI

Test Conditions

VIN=VSS to VCC

Unit

-2

ILO

CS=VIH or OE=VIH or WE=VIL

VOUT = VSS to VCC

-2

Operating Current

ICC

Min. Cycle, 100% Duty

CS=VIL, VIN=VIH or VIL, IOUT=0mA

15ns

17ns

20ns

210

205

200

Standby Current

ISB

Min. Cycle, CS=VIH

ISB1

f=0MHz, CS³ VCC-0.2V,

VIN³ VCC-0.2V or VIN£0.2V

Output Low Voltage Level

Output High Voltage Level

VOL

VOH

IOL=8mA

0.4

IOH=-4mA

2.4

* The above parameters are also guaranteed at extended and industrial temperature ranges.

CAPACITANCE*(TA=25°C, f=1.0MHz)

Item

Input/Output Capacitance

Input Capacitance

Symbol

CI/O

Test Conditions

VI/O=0V

MIN

Max

Unit

CIN

VIN=0V

* Capacitance is sampled and not 100% tested.

Rev 2.1

December 1998

- 3 -

PRELIMINARY

CMOS SRAM

KM6164002A, KM6164002AE, KM6164002AI

AC CHARACTERISTICS(TA=0 to 70°C, VCC=5.0V±10%, unless otherwise noted.)

TEST CONDITIONS*

Parameter

Value

Input Pulse Levels

0V to 3V

3ns

Input Rise and Fall Times

Input and Output timing Reference Levels

Output Loads

1.5V

See below

* The above parameters are also guaranteed at extended and industrial temperature ranges.

Output Loads(A)

Output Loads(B)

for tHZ, tLZ, tWHZ, tOW, tOLZ & tOHZ

+5.0V

480W

DOUT

255W

30pF*

5pF*

* Including Scope and Jig Capacitance

READ CYCLE*

KM6164002A-15

Symbol

KM6164002A-17

KM6164002A-20

Parameter

Unit

Min

Max

Min

Max

Min

Max

Read Cycle Time

tRC

tAA

Address Access Time

Chip Select to Output

tCO

tOE

tBA

Output Enable to Valid Output

UB, LB Access Time

Chip Enable to Low-Z Output

Output Enable to Low-Z Output

UB, LB Enable to Low-Z Output

Chip Disable to High-Z Output

Output Disable to High-Z Output

UB, LB Disable to High-Z Output

Output Hold from Address Change

tLZ

tOLZ

tBLZ

tHZ

tOHZ

tBHZ

tOH

* The above parameters are also guaranteed at extended and industrial temperature ranges.

Rev 2.1

December 1998

- 4 -

PRELIMINARY

CMOS SRAM

KM6164002A, KM6164002AE, KM6164002AI

WRITE CYCLE*

KM6164002A-15

KM6164002A-17

KM6164002A-20

Parameter

Symbol

Unit

Min

Max

Min

Max

Min

Max

Write Cycle Time

tWC

tCW

tAS

Chip Select to End of Write

Address Set-up Time

Address Valid to End of Write

Write Pulse Width(OE High)

Write Pulse Width(OE Low)

UB, LB Valid to End of Write

Write Recovery Time

tAW

tWP

tWP1

tBW

tWR

tWHZ

tDW

tDH

Write to Output High-Z

Data to Write Time Overlap

Data Hold from Write Time

End Write to Output Low-Z

tOW

* The above parameters are also guaranteed at extended and industrial temperature ranges.

TIMMING DIAGRAMS

TIMING WAVEFORM OF READ CYCLE(1) (Address Controlled, CS=OE=VIL, WE=VIH, UB, LB=VIL)

tRC

Address

tAA

tOH

Valid Data

Data Out

Previous Valid Data

Rev 2.1

December 1998

- 5 -

PRELIMINARY

CMOS SRAM

KM6164002A, KM6164002AE, KM6164002AI

TIMING WAVEFORM OF READ CYCLE(2) (WE=VIH)

tRC

Address

tAA

tHZ(3,4,5)

tCO

tBHZ(3,4,5)

tBA

UB, LB

tBLZ(4,5)

tOHZ

tOE

tOLZ

tOH

tLZ(4,5)

Data out

High-Z

Valid Data

NOTES(READ CYCLE)

1. WE is high for read cycle.

2. All read cycle timing is referenced from the last valid address to the first transition address.

3. tHZ and tOHZ are defined as the time at which the outputs achieve the open circuit condition and are not referenced to VOH or VOL

levels.

4. At any given temperature and voltage condition, tHZ(Max.) is less than tLZ(Min.) both for a given device and from device to

device.

5. Transition is measured ±200mV from steady state voltage with Load(B). This parameter is sampled and not 100% tested.

6. Device is continuously selected with CS=VIL.

7. Address valid prior to coincident with CS transition low.

8. For common I/O applications, minimization or elimination of bus contention conditions is necessary during read and write cycle.

TIMING WAVEFORM OF WRITE CYCLE(1) (OE Clock)

tWC

tAW

Address

tWR(5)

tCW(3)

tBW

UB, LB

tAS(4)

tWP(2)

tDW

tDH

High-Z

Data in

Valid Data

tOHZ(6)

Data out

Rev 2.1

December 1998

- 6 -

PRELIMINARY

CMOS SRAM

KM6164002A, KM6164002AE, KM6164002AI

TIMING WAVEFORM OF WRITE CYCLE(2) (OE =Low fixed)

tWC

Address

tAW

tWR(5)

tCW(3)

tBW

UB, LB

tWP1(2)

tAS(4)

tDW

tDH

High-Z

Valid Data

Data in

tWHZ(6)

tOW

(9)

(10)

High-Z

Data out

TIMING WAVEFORM OF WRITE CYCLE(3) (CS=Controlled)

tWC

Address

tAW

tWR(5)

tCW(3)

tBW

UB, LB

tAS(4)

tWP(2)

tDH

tDW

High-Z

Data in

Valid Data

tLZ

tWHZ(6)

High-Z(8)

High-Z

Data out

Rev 2.1

December 1998

- 7 -

PRELIMINARY

CMOS SRAM

KM6164002A, KM6164002AE, KM6164002AI

TIMING WAVEFORM OF WRITE CYCLE(4) (UB, LB Controlled)

tWC

Address

tAW

tCW(3)

tWR(5)

tBW

UB, LB

tAS(4)

tWP(2)

tDH

tDW

High-Z

Data in

Valid Data

tBLZ

tWHZ(6)

High-Z(8)

High-Z

Data out

NOTES(WRITE CYCLE)

1. All write cycle timing is referenced from the last valid address to the first transition address.

2. A write occurs during the overlap of a low CS,WE,LB and UB. A write begins at the latest transition CS going low and WE going

low; A write ends at the earliest transition CS going high or WE going high. tWP is measured from the beginning of write to the

end of write.

3. tCW is measured from the later of CS going low to end of write.

4. tAS is measured from the address valid to the beginning of write.

5. tWR is measured from the end of write to the address change. tWR applied in case a write ends as CS or WE going high.

6. If OE, CS and WE are in the Read Mode during this period, the I/O pins are in the output low-Z state. Inputs of opposite phase

of the output must not be applied because bus contention can occur.

7. For common I/O applications, minimization or elimination of bus contention conditions is necessary during read and write cycle.

8. If CS goes low simultaneously with WE going or after WE going low, the outputs remain high impedance state.

9. Dout is the read data of the new address.

10. When CS is low: I/O pins are in the output state. The input signals in the opposite phase leading to the output should not be

applied.

FUNCTIONAL DESCRIPTION

I/O Pin

Mode

Supply Current

I/O1~I/O8

High-Z

I/O9~I/O16

High-Z

Not Select

ISB, ISB1

ICC

Output Disable

High-Z

Read

Write

DOUT

High-Z

DOUT

DIN

High-Z

DOUT

High-Z

DIN

ICC

High-Z

DIN

* X means Don¢t Care.

Rev 2.1

December 1998

- 8 -

PRELIMINARY

CMOS SRAM

KM6164002A, KM6164002AE, KM6164002AI

Units:millimeters/Inches

PACKAGE DIMENSIONS

44-SOJ-400

#44

#23

9.40 ±0.25

0.370 ±0.010

11.18 ±0.12

0.440 ±0.005

+0.10

-0.05

0.20

0.008 ^+0.004

-0.002

#22

28.98

MAX

0.69

MIN

0.027

1.141

25.58 ±0.12

1.125 ±0.005

1.19

(

)

0.047

3.76

0.148

1.27

MAX

(

)

0.050

0.10

0.004

MAX

+0.10

-0.05

0.43

+0.10

-0.05

0.71

0.017 ^+0.004

0.95

0.0375

1.27

0.050

-0.002

(

)

0.028 ^+0.004

-0.002

44-TSOP2-400F

0~8°

0.25

0.010

(

)

#44

#23

0.45 ~0.75

0.018 ~ 0.030

11.76 ±0.20

0.463 ±0.008

0.50

0.020

(

)

#22

18.81

0.741

MAX.

18.41 ±0.10

0.725 ±0.004

1.00 ±0.10

0.039 ±0.004

1.20

0.047

0.10

0.004

MAX.

MAX

0.05

MIN.

0.002

0.35 ±0.10

0.014 ±0.004

0.80

0.0315

0.805

0.032

(

)

Rev 2.1

December 1998

- 9 -

KM6164002AJE-200 [SAMSUNG]

相关型号：

KM6164002AT-15

KM6164002AT-1500

KM6164002AT-1700

KM6164002AT-2000

KM6164002ATE-150

KM6164002ATE-17

KM6164002ATE-170

KM6164002ATI-170

KM6164002ATI-200

KM6164002BTI-12

KM6164002CF-12

KM6164002CF-1500