KM616U4000BLR-10L0 [SAMSUNG]

Standard SRAM, 256KX16, 100ns, CMOS, PDSO44, 0.400 INCH, REVERSE, TSOP2-44;


型号：	KM616U4000BLR-10L0
厂家：	SAMSUNG
描述：	Standard SRAM, 256KX16, 100ns, CMOS, PDSO44, 0.400 INCH, REVERSE, TSOP2-44 静态存储器光电二极管内存集成电路
文件：	总9页 (文件大小：153K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

KM616V4000B, KM616U4000B Family

CMOS SRAM

Document Title

256Kx16 bit Low Power and Low Voltage CMOS Static RAM

Revision History

Revision No.

History

Draft Data

Remark

0.0

Initial draft

June 28, 1996

Advance

0.1

Revise

September 19, 1996

Preliminary

- Die name change ; A to B

1.0

2.0

Finalize

December 17, 1996

February 17, 1997

Final

Revise

- Operating current update and release.

ICC(Read/Write) = 20/40 ® 10/45mA

ICC1(Read/Write) = 20/40 ® 10/45mA

ICC2 = 90 ® 70mA

3.0

Revise

January 14, 1998

Final

- Change datasheet format

- Erase 70ns part from KM616V4000BI, KM616U4000B and

KM616U4000BI Family

- Power dissipation improved 0.7 to 1.0W

- VIL(MAX) improved 0.4 to 0.6V.

- ICC2 decreased 70 to 60mA.

- Erase 100ns from KM616V4000B commercial product

Error correction

3.01

August 7, 1998

The attached datasheets are provided by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the specifications and

products. SAMSUNG Electronics will answer to your questions about device. If you have any questions, please contact the SAMSUNG branch offices.

Revision 3.01

January 1998

KM616V4000B, KM616U4000B Family

CMOS SRAM

256Kx16 bit Low Power and Low Voltage CMOS Static RAM

GENERAL DESCRIPTION

FEATURES

· Process Technology : TFT

The KM616V4000B and KM616U4000B families are fabricated

by SAMSUNG¢s advanced CMOS process technology. The

families support various operating temperature range and have

small package types for user flexibility of system design. The

families also support low data retention voltage for battery

back-up operation with low data retention current.

· Organization : 256K x16

· Power Supply Voltage

KM68V4000B Family : 3.0~3.6V

KM68U4000B Family : 2.7~3.3V

· Low Data Retention Voltage : 2V(Min)

· Three state output and TTL Compatible

· Package Type : 44-TSOP2-400F/R

PRODUCT FAMILY

Power Dissipation

Product

List

Operating

Temperature

Vcc

Range

Speed

(ns)

PKG Type

Standby

Operating

(ICC2)

(ISB1, Max)

70¹⁾/85¹⁾

85¹⁾/100

KM616V4000BL-L

Commercial(0~70°C)

Industrial(-40~85°C)

Commercial(0~70°C)

Industrial(-40~85°C)

3.0~3.6V

2.7~3.3V

15mA

20mA

15mA

20mA

KM616V4000BLI-L

KM616U4000BL-L

60mA

44-TSOP2-F/R

KM616U4000BLI-L

1. The parameter is measured with 30pF test load.

PIN DESCRIPTION

FUNCTIONAL BLOCK DIAGRAM

I/O16

I/O15

I/O14

I/O13

Vss

Vcc

I/O12

I/O11

I/O10

I/O9

N.C

Clk gen.

Precharge circuit.

A13

A14

Vcc

Vss

I/O1

I/O2

I/O3

I/O4

Vcc

Vss

I/O5

I/O6

I/O7

I/O8

A17

A16

A15

A14

A13

I/OI

I/O2

I/O3

I/O4

Vcc

Vss

I/O5

I/O6

I/O7

I/O8

A17

A16

A15

A14

A13

I/O16

I/O15

I/O14

I/O13

Vss

Memory array

1024 rows

256´ 16 columns

A15

A16

A17

Row

select

44-TSOP2

Forward

44-TSOP2

Reverse

Vcc

I/O12

I/O11

I/O10

I/O9

N.C

A10

A11

Data

cont

I/O Circuit

Column select

I/O1~I/O8

A10

A11

A12

Data

cont

I/O9~I/O16

A12

Data

cont

A8 A9 A10 A5 A6 A7 A4 A12

Name

Function

Name

Function

Chip Select Input

Output Enable Input

Write Enable Input

Address Inputs

Lower Byte (I/O1~8)

Upper Byte(I/O9~16)

Vcc Power

Vss Ground

Control

logic

A0~A17

I/O1~I/O16 Data Inputs/Outputs N.C No Connection

SAMSUNG ELECTRONICS CO., LTD. reserves the right to change products and specifications without notice.

Revision 3.01

January 1998

KM616V4000B, KM616U4000B Family

CMOS SRAM

PRODUCT LIST

Commercial Temperature Product(0~70°C)

Industrial Temperature Products(-40~85°C)

Part Name

Function

Part Name

Function

KM616V4000BLT-7L

KM616V4000BLT-8L

KM616V4000BLR-7L

KM616V4000BLR-8L

44-TSOP2-F, 70ns, 3.3V,LL

44-TSOP2-F, 85ns, 3.3V,LL

44-TSOP2-R, 70ns, 3.3V,LL

44-TSOP2-R, 85ns, 3.3V,LL

KM616V4000BLTI-8L

KM616V4000BLTI-10L

KM616V4000BLRI-8L

KM616V4000BLRI-10L

44-TSOP2-F, 85ns, 3.3V,LL

44-TSOP2-F, 100ns, 3.3V,LL

44-TSOP2-R, 85ns, 3.3V,LL

44-TSOP2-R, 100ns, 3.3V,LL

KM616U4000BLT-8L

KM616U4000BLT-10L

KM616U4000BLR-8L

KM616U4000BLR-10L

44-TSOP2-F, 85ns, 3.0V,LL

44-TSOP2-F, 100ns, 3.0V,LL

44-TSOP2-R, 85ns, 3.0V,LL

44-TSOP2-R, 100ns, 3.0V,LL

KM616U4000BLTI-8L

KM616U4000BLTI-10L

KM616U4000BLRI-8L

KM616U4000BLRI-10L

44-TSOP2-F, 85ns, 3.0V,LL

44-TSOP2-F, 100ns, 3.0V,LL

44-TSOP2-R, 85ns, 3.0V,LL

44-TSOP2-R, 100ns, 3.0V,LL

FUNCTIONAL DESCRIPTION

X¹⁾

I/O1~8

High-Z

Dout

I/O9~16

High-Z

Dout

Mode

Power

Standby

Active

Deselected

Output Disabled

Lower Byte Read

Upper Byte Read

Word Read

X¹⁾

High-Z

Dout

X¹⁾

Din

High-Z

Din

Lower Byte Write

Upper Byte Write

Word Write

High-Z

Din

1. X means don¢t care. (Must be in low or high state)

ABSOLUTE MAXIMUM RATINGS¹⁾

Item

Symbol

Ratings

-0.5 to VCC+0.5

-0.3 to 4.6

1.0

Unit

Remark

Voltage on any pin relative to Vss

Voltage on Vcc supply relative to Vss

Power Dissipation

VIN,VOUT

VCC

Storage temperature

TSTG

-65 to 150

°C

KM616V4000BL-L

KM616U4000BL-L

0 to 70

°C

Operating Temperature

KM616V4000BLI-L

KM616U4000BLI-L

-40 to 85

°C

Soldering temperature and time

TSOLDER

260°C, 10sec (Lead Only)

1. Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. Functional operation should be

restricted to recommended operating condition. Exposure to absolute maximum rating conditions for extended periods may affect reliability.

Revision 3.01

January 1998

KM616V4000B, KM616U4000B Family

CMOS SRAM

RECOMMENDED DC OPERATING CONDITIONS¹⁾

Item

Supply voltage

Symbol

Product

Min

Typ

Max

Unit

KM616V4000B Family

KM616U4000B Family

3.0

2.7

3.3

3.0

3.6

3.3

Vcc

Ground

Vss

VIH

VIL

All Family

Vcc+0.3²⁾

0.6

Input high voltage

Input low voltage

KM616V4000B, KM616U4000B Family

2.2

-0.3³⁾

Note:

1. Commercial Product : TA=0 to 70°C, otherwise specified

Industrial Product : TA=-40 to 85°C, otherwise specified

2. Overshoot : V_CC+3.0V in case of pulse width £ 30ns

3. Undershoot : -3.0V in case of pulse width £ 30ns

4. Overshoot and undershoot are sampled, not 100% tested.

CAPACITANCE¹⁾(f=1MHz, TA=25°C)

Item

Input capacitance

Symbol

CIN

Test Condition

VIN=0V

Min

Max

Unit

Input/Output capacitance

CIO

VIO=0V

1. Capacitance is sampled, not 100% tested

DC AND OPERATING CHARACTERISTICS

Item

Symbol

ILI

Min

Typ Max Unit

Test Conditions

Input leakage current

Output leakage current

Operating power supply current

VIL=Vss to Vcc

-1

ILO

CS=VIH or OE=VIH or WE=VIL VIO=Vss to Vcc

IIO=0mA, CS=VIL, VIN=VIL or VIH, Read

-1

ICC

Read

Write

Cycle time=1ms, 100% duty, IIO=0mA

CS£0.2V, VIN£0.2V or VIN³ Vcc-0.2V

ICC1

Average operating current

0.4

ICC2

VOL

VOH

ISB

Cycle time=Min, 100% duty, IIO=0mA, CS=VIL, VIN=VIH or VIL

IOL=2.1mA

Output low voltage

2.2

Output high voltage

Standby Current(TTL)

Standby Current(CMOS)

IOH=-1.0mA

CS=VIH, Other inputs=VIL or VIH

CS³ Vcc-0.2V, Others inputs = 0~Vcc

0.5

15¹⁾

ISB1

1. Industrial product = 20mA

Revision 3.01

January 1998

KM616V4000B, KM616U4000B Family

CMOS SRAM

AC OPERATING CONDITIONS

TEST CONDITIONS (Test Load and Input/Output Reference)

Input pulse level : 0.4 to 2.2V

Input rising and falling time : 5ns

Input and output reference voltage :1.5V

Output load(see right) : CL=100pF+1TTL

CL=30pF+1TTL

)

1.Including scope and jig capacitance

AC CHARACTERISTICS (KM616V4000B Family :Vcc=3.0~3.6V, KM616U4000B Family :Vcc=2.7~3.3V,

Commercial product : TA=0 to 70°C, Industrial product : TA=-40 to 85°C)

Speed Bins

Parameter List

Symbol

Units

70ns¹⁾

85ns¹⁾

100ns

Min

Max

Min

Max

Min

Max

Read cycle time

tRC

tAA

100

Address access time

100

Chip select to output

tCO

tOE

tLZ

100

Output enable to valid output

Chip select to low-Z output

Output enable to low-Z output

UB, LB enable to low-Z output

Chip disable to high-Z output

OE disable to high-Z output

Output hold from address change

LB, UB valid to data output

UB, LB disable to high-Z output

Write cycle time

tOLZ

tBLZ

tHZ

Read

tOHZ

tOH

tBA

tBHZ

tWC

tCW

tAS

100

Chip select to end of write

Address set-up time

Address valid to end of write

Write pulse width

tAW

tWP

tWR

tWHZ

tDW

tDH

tOW

tBW

Write

Write recovery time

Write to output high-Z

Data to write time overlap

Data hold from write time

End write to output low-Z

LB, UB valid to end of write

1. The parameter is measured with 30pF test load.

DATA RETENTION CHARACTERISTICS

Item

Symbol

Min

Typ

Max

Unit

Test Condition

CS³ Vcc-0.2V

Vcc=3.0V, CS³ Vcc-0.2V

Vcc for data retention

Data retention current

Data retention set-up time

VDR

2.0

0.5

3.6

15¹⁾

IDR

tSDR

See data retention waveform

Recovery time

tRDR

1. Industrial product = 20mA

Revision 3.01

January 1998

KM616V4000B, KM616U4000B Family

CMOS SRAM

TIMMING DIAGRAMS

TIMING WAVEFORM OF READ CYCLE(1) (Address Controlled, CS=OE=VIL, WE=VIH, UB or/and LB=VIL)

tRC

Address

tAA

tOH

Data Valid

Data Out

Previous Data Valid

TIMING WAVEFORM OF READ CYCLE(2) (WE=VIH)

tRC

Address

tOH

tAA

tCO

tHZ

tBA

UB, LB

tBHZ

tOHZ

tOE

tOLZ

tBLZ

tLZ

Data out

High-Z

Data Valid

NOTES (READ CYCLE)

1. tHZ and tOHZ are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage

levels.

2. At any given temperature and voltage condition, tHZ(Max.) is less than tLZ(Min.) both for a given device and from device to device

interconnection.

Revision 3.01

January 1998

KM616V4000B, KM616U4000B Family

CMOS SRAM

TIMING WAVEFORM OF WRITE CYCLE(1) (WE Controlled)

tWC

Address

tCW(2)

tWR(4)

tAW

tBW

UB, LB

tWP(1)

tAS(3)

tDW

tDH

High-Z

Data in

Data out

Data Valid

tWHZ

tOW

Data Undefined

TIMING WAVEFORM OF WRITE CYCLE(2) (CS Controlled)

tWC

Address

tAS(3)

tCW(2)

tWR(4)

tAW

tBW

UB, LB

tWP(1)

tDW

tDH

Data Valid

Data in

Data out

High-Z

Revision 3.01

January 1998

KM616V4000B, KM616U4000B Family

CMOS SRAM

TIMING WAVEFORM OF WRITE CYCLE(3) (UB, LB Controlled)

tWC

Address

tCW(2)

tWR(4)

tAW

tBW

UB, LB

tAS(3)

tWP(1)

tDH

tDW

Data in

Data Valid

High-Z

Data out

High-Z

NOTES (WRITE CYCLE)

1. A write occurs during the overlap(tWP) of low CS and low WE. A write begins when CS goes low and WE goes low with asserting UB

or LB for single byte operation or simultaneously asserting UB and LB for double byte operation. A write ends at the earliest transi-

tion when CS goes high and WE goes high. The tWP is measured from the beginning of write to the end of write.

2. tCW is measured from the CS going low to end of write.

3. tAS is measured from the address valid to the beginning of write.

4. tWR is measured from the end or write to the address change. tWR applied in case a write ends as CS or WE going high.

DATA RETENTION WAVE FORM

CS controlled

Data Retention Mode

tSDR

tRDR

VCC

3.0/2.7V

2.2V

VDR

CS³ VCC - 0.2V

GND

Revision 3.01

January 1998

KM616V4000B, KM616U4000B Family

CMOS SRAM

Unit : millimeter(inch)

PACKAGE DIMENSIONS

44 PIN THIN SMALL OUTLINE PACKAGE TYPE II (400F)

0~8°

0.25

0.010

(

)

#44

#23

0.45 ~0.75

0.018 ~ 0.030

11.76±0.20

0.463±0.008

0.50

0.020

(

)

#22

1.00±0.10

0.039±0.004

18.81

0.741

1.20

0.047

MAX.

18.41±0.10

0.725±0.004

0.10

0.004

MAX

0.35± 0.10

0.014±0.004

0.80

0.0315

0.805

0.032

(

)

0~8°

44 PIN THIN SMALL OUTLINE PACKAGE TYPE II (400R)

0.25

0.010

(

)

#22

0.45 ~0.75

0.018 ~ 0.030

11.76±0.20

0.463±0.008

0.50

)

(

0.020

#44

#23

1.00±0.10

0.039±0.004

18.81

0.741

1.20

0.047

MAX.

18.41± 0.10

0.725±0.004

0.10

0.004

MAX

0.35±0.10

0.014±0.004

0.80

0.0315

0.805

0.032

(

)

Revision 3.01

January 1998

KM616U4000BLR-10L0 [SAMSUNG]

相关型号：

KM616U4000BLRI-10L

KM616U4000BLRI-8L

KM616U4000BLT-10L

KM616U4000BLT-8L

KM616U4000BLTI-10L

KM616U4000CLR-10L0

KM616U4000CLR-7L

KM616U4000CLRI-10L

KM616U4000CLRI-7L

KM616U4000CLRI-7L0

KM616U4000CLRI-8L0

KM616U4000CLT-10L0