KM616V1000BLT-7L [SAMSUNG]
Standard SRAM, 64KX16, 70ns, CMOS, PDSO44, 0.400 INCH, TSOP2-44;
| 型号： | KM616V1000BLT-7L |
| 厂家： | 
SAMSUNG |
| 描述： | Standard SRAM, 64KX16, 70ns, CMOS, PDSO44, 0.400 INCH, TSOP2-44 静态存储器 光电二极管 内存集成电路 |
| 文件： | 总9页 (文件大小：155K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
KM616V1000B, KM616U1000B Family
CMOS SRAM
Document Title
64K x16 bit Low Power and Low Voltage CMOS Static RAM
Revision History
Revision No.
History
Draft Data
Remark
0.0
Design target
July 24, 1995
Advance
0.1
1.0
Initial draft
August 12, 1995
April 13, 1996
Preliminary
Final
Finalize
- One datasheet for commercial and industrial part and 3.0, 3.3V prod-
uct.
2.0
Revised
- Change datasheet format.
February 25, 1998
August 13, 1998
Final
- Remove Icc write current value.
- Remove low power product from TSOP package
- Remove 100ns part from KM616V1000B Family
- Remove Extended product
Errata correction
2.01
The attached datasheets are provided by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the specifications and
products. SAMSUNG Electronics will answer to your questions about device. If you have any questions, please contact the SAMSUNG branch offices.
1
Revision 2.0
February 1998
KM616V1000B, KM616U1000B Family
CMOS SRAM
64K x16 bit Low Power and Low Voltage CMOS Static RAM
FEATURES
GENERAL DESCRIPTION
· Process Technology : Poly Load
· Organization : 64K x16
The KM616V1000B and KM616U1000B families are fabri-
cated by SAMSUNG¢s advanced CMOS process technology.
The families support various operating temperature ranges
and have small package types for user flexibility of system
design. The families also support low data retention voltage
for battery back-up operation with low data retention current.
· Data Byte Control : LB=I/O1~8, UB=I/O9~16
· Power Supply Voltage :
KM616V1000B family : 3.0~3.6V
KM616U1000B family : 2.7~3.3V
· Low Data Retention Voltage : 2V(Min)
· Three state output and TTL Compatible
· Package Type :44-TSOP2-400F/R
PRODUCT FAMILY
Power Dissipation
Product Family
Operating Temperature Vcc Range Speed(ns)
PKG Type
Standby
(ISB1, Max)
Operating
(Icc2, Max)
701)
100
851)
100
KM616V1000BL-L
KM616U1000BL-L
3.0~3.6V
2.7~3.3V
15mA
15mA
Commercial(0~70°C)
Industrial(-40~85°C)
44-TSOP2
Forward/Reverse
65mA
KM616V1000BLI-L
KM616U1000BLI-L
3.0~3.6V
2.7~3.3V
20mA
20mA
1. The parameter is measured with 30pF test load.
PIN DESCRIPTION
FUNCTIONAL BLOCK DIAGRAM
44
A4
1
2
A4
A3
1
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
A5
A6
A5
Clk gen.
Precharge circuit.
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
A3
2
A6
3
A2
A2
3
A7
OE
A7
OE
A0
A1
A2
A3
A4
A5
A6
A7
A8
A15
4
5
A1
A1
4
5
Vcc
Vss
A0
A0
UB
UB
6
CS
CS
6
LB
LB
7
I/OI
I/O2
I/O3
I/O4
Vcc
Vss
I/O5
I/O6
I/O7
I/O8
WE
A15
A14
A13
A12
N.C
I/OI
I/O2
I/O3
I/O4
Vcc
Vss
I/O5
I/O6
I/O7
I/O8
WE
A15
A14
A13
A12
N.C
7
I/O16
I/O15
I/O14
I/O13
Vss
I/O16
I/O15
I/O14
I/O13
Vss
Vcc
I/O12
I/O11
I/O10
I/O9
N.C
A8
8
8
9
Memory array
1024 rows
64´ 16 columns
Row
select
9
10
11
12
13
14
15
16
17
18
19
20
21
22
10
11
12
13
14
15
16
17
18
19
20
21
22
44-TSOP2
Reverse
44-TSOP2
Forward
Vcc
I/O12
I/O11
I/O10
I/O9
N.C
A8
I/O Circuit
Column select
Data
cont
I/O1~I/O8
A9
A9
A10
A11
N.C
A10
A11
N.C
Data
cont
I/O9~I/O16
Data
cont
A9 A10 A11 A12 A13 A14
Name
CS
Function
Name
Vcc
Function
Chip Select Input
Power
OE
Output Enable Input
Write Enable Input
Lower Byte (I/O1~8)
Upper Byte(I/O9~16)
Vss
Ground
WE
WE
LB
I/O1~16 Data Inputs/Outputs
A0~A15 Address Inputs
OE
UB
LB
Control
logic
UB
N.C
No Connection
CS
SAMSUNG ELECTRONICS CO., LTD. reserves the right to change products and specifications without notice.
2
Revision 2.0
February 1998
KM616V1000B, KM616U1000B Family
CMOS SRAM
PRODUCT LIST
Commercial Temperature Products(0~70°C)
Industrial Temperature Products(-40~85°C)
Part Name
KM616V1000BLT-7L
KM616U1000BLT-10L
Function
44-TSOP-2F, 3.3V, 70ns, LL
44-TSOP-2F, 3.0V, 100ns, LL
Part Name
KM616V1000BLTI-8L
KM616U1000BLTI-10L
Function
44-TSOP-2F, 3.3V, 85ns, LL
44-TSOP-2F, 3.0V, 100ns, LL
KM616V1000BLR-7L
KM616U1000BLR-10L
44-TSOP-2R, 3.3V, 70ns, LL
44-TSOP-2R, 3.0V, 100ns, LL
KM616V1000BLRI-8L
KM616U1000BLRI-10L
44-TSOP-2R, 3.3V, 85ns, LL
44-TSOP-2R, 3.0V, 100ns, LL
FUNCTIONAL DESCRIPTION
CS
H
L
OE
X1)
H
WE
X1)
H
LB
X1)
X1)
H
UB
X1)
X1)
H
I/O1~8
High-Z
High-Z
High-Z
Dout
I/O9~16
High-Z
High-Z
High-Z
High-Z
Dout
Mode
Power
Deselected
Standby
Active
Active
Active
Active
Active
Active
Active
Active
Output Disabled
Output Disabled
Lower Byte Read
Upper Byte Read
Word Read
X1)
L
X1)
H
L
L
L
H
L
L
H
H
L
High-Z
Dout
L
L
H
L
L
Dout
X1)
X1)
X1)
L
L
L
H
Din
High-Z
Din
Lower Byte Write
Upper Byte Write
Word Write
L
L
H
L
High-Z
Din
L
L
L
L
Din
1. X means don¢t care. (Must be in low or high state)
ABSOLUTE MAXIMUM RATINGS1)
Item
Symbol
Ratings
-0.5 to Vcc+0.5
-0.5 to 4.6
1.0
Unit
V
Remark
Voltage on any pin relative to Vss
Voltage on Vcc supply relative to Vss
Power Dissipation
VIN,VOUT
VCC
-
-
-
-
V
PD
W
Storage temperature
TSTG
-65 to 150
°C
KM616V1000BL-L
KM616U1000BL-L
0 to 70
°C
Operating Temperature
TA
KM616V1000BLI-L
KM616U1000BLI-L
-40 to 85
°C
Soldering temperature and time
TSOLDER
260°C, 10sec (Lead Only)
-
-
1. Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. Functional operation should be
restricted to recommended operating condition. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
3
Revision 2.0
February 1998
KM616V1000B, KM616U1000B Family
CMOS SRAM
RECOMMENDED DC OPERATING CONDITIONS1)
Item
Symbol
Product
Min
Typ
Max
Unit
KM616V1000B Family
KM616U1000B Family
3.0
2.7
3.3
3.0
3.6
3.3
Supply voltage
Vcc
V
Ground
Vss
VIH
VIL
All Family
0
0
-
0
V
V
V
VCC+0.32)
0.4
Input high voltage
Input low voltage
KM616V1000B, KM616U1000B Family
KM616V1000B, KM616U1000B Family
2.2
-0.33)
-
Note:
1. Commercial Product : TA=0 to 70°C, otherwise specified
Industrial Product : TA=-40 to 85°C, otherwise specified
2. Overshoot : VCC+3.0V in case of pulse width £ 30ns
3. Undershoot : -3.0V in case of pulse width £ 30ns
4. Overshoot and undershoot are sampled, not 100% tested
CAPACITANCE1)(f=1MHz, TA=25°C)
Item
Input capacitance
Symbol
Test Condition
VIN=0V
Min
Max
6
Unit
CIN
-
-
pF
pF
Input/Output capacitance
CIO
VIO=0V
8
1. Capacitance is sampled, not 100% tested
DC AND OPERATING CHARACTERISTICS
Item
Symbol
Test Conditions
Min
Typ Max Unit
Input leakage current
ILI
VIN=VSS to VCC
-1
-
-
-
-
-
-
-
-
-
-
1
1
mA
mA
mA
CS=VIH or OE=VIH or WE=VIL, VIO=VSS to VCC
IIO=0mA, CS=VIL, VIN=VIL or VIH, Read
Output leakage current
Operating power supply current
ILO
-1
ICC
-
10
15
40
65
0.4
-
Read
Write
-
Cycle time=1ms, 100% duty, IIO=0mA
CS£0.2V, VIN£0.2V or VIN³ Vcc-0.2V
1)
ICC1
mA
Average operating current
-
Cycle time=Min, 100% duty, IIO=0mA, CS=VIL, VIN=VIL or VIH
IOL=2.1mA
ICC2
VOL
VOH
ISB
-
mA
V
Output low voltage
-
2.2
-
Output high voltage
Standby Current(TTL)
Standby current(CMOS)
IOH=-1.0mA
V
CS=VIH, Other inputs=VIL or VIH
CS³ VCC-0.2V, Other inputs=0~VCC
0.5
152)
mA
mA
ISB1
-
1. Industrial Product : ICC1(Read/Write)=20mA/45mA
2. Industrial Product=20mA
4
Revision 2.0
February 1998
KM616V1000B, KM616U1000B Family
CMOS SRAM
AC OPERATING CONDITIONS
TEST CONDITIONS( Test Load and Input/Output Reference)
Input pulse level : 0.4 to 2.2V
Input rising and falling time : 5ns
1)
CL
Input and output reference voltage :1.5V
Output load(see right) : CL=100pF+1TTL
CL=30pF+1TTL
1. Including scope and jig capacitance
AC CHARACTERISTICS(KM616V1000B Family : Vcc=3.0~3.6V, KM616U1000B Family : Vcc=2.7~3.3V
Commercial product : TA=0 to70°C, Industrial product :TA=-40 to 85°C)
Speed Bins
Parameter List
Symbol
Units
70ns
Max
85ns
Max
100ns
Min
70
-
Min
85
-
Min
Max
Read cycle time
tRC
tAA
-
70
70
35
35
-
-
85
85
40
40
-
100
-
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Address access time
100
Chip select to output
tCO
tOE
-
-
-
100
Output enable to valid output
UB,LB Access Time
-
-
-
50
50
-
tBA
-
-
-
Chip select to low-Z output
Output enable to low-Z output
UB,LB enable to low-Z output
Chip disable to high-Z output
Output disable to high-Z output
UB,LB disable to high-Z output
Output hold from address change
Write cycle time
tLZ
10
5
10
5
10
5
Read
tOLZ
tBLZ
tHZ
-
-
-
5
-
5
-
5
-
0
25
25
25
-
0
25
25
25
-
0
30
30
30
-
tOHZ
tBHZ
tOH
tWC
tCW
tAS
0
0
0
0
0
0
10
70
60
0
10
85
70
0
15
100
80
0
-
-
-
Chip select to end of write
Address set-up time
-
-
-
-
-
-
Address valid to end of write
Write pulse width
tAW
tWP
tBW
tWR
tWHZ
tDW
tDH
60
50
60
0
-
70
60
70
0
-
80
70
80
0
-
-
-
-
Write
UB, LB valid to end of write
Write recovery time
-
-
-
-
-
-
Write to output high-Z
0
30
-
0
30
-
0
35
-
Data to write time overlap
Data hold from write time
End write to output low-Z
30
0
35
0
40
0
-
-
-
tOW
5
-
5
-
5
-
DATA RETENTION CHARACTERISTICS
Item
Symbol
VDR
Test Condition
CS³ Vcc-0.2V
Min
Typ
Max
Unit
V
VCC for data retention
Data retention current
Data retention set-up time
Recovery time
2.0
-
-
-
-
-
3.6
151)
-
IDR
VCC=3.0V, CS³ Vcc-0.2V
mA
tSDR
0
See data retention waveform
ms
tRDR
5
-
1. Industrial product=20mA
5
Revision 2.0
February 1998
KM616V1000B, KM616U1000B Family
CMOS SRAM
TIMMING DIAGRAMS
TIMING WAVEFORM OF READ CYCLE(1) (Address Controlled, CS=OE=VIL, WE=VIH, UB or/and LB=VIL)
tRC
Address
tAA
tOH
Data Valid
Data Out
Previous Data Valid
TIMING WAVEFORM OF READ CYCLE(2) (WE=VIH)
tRC
Address
tOH
tAA
tCO
CS
tHZ
tBA
UB, LB
OE
tBHZ
tOHZ
tOE
tOLZ
tBLZ
tLZ
Data out
High-Z
Data Valid
NOTES (READ CYCLE)
1. tHZ and tOHZ are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage
levels.
2. At any given temperature and voltage condition, tHZ(Max.) is less than tLZ(Min.) both for a given device and from device to device
interconnection.
6
Revision 2.0
February 1998
KM616V1000B, KM616U1000B Family
CMOS SRAM
TIMING WAVEFORM OF WRITE CYCLE(1) (WE Controlled)
tWC
Address
tCW(2)
tWR(4)
CS
tAW
tBW
UB, LB
tWP(1)
WE
tAS(3)
tDW
tDH
High-Z
High-Z
Data in
Data out
Data Valid
tWHZ
tOW
Data Undefined
TIMING WAVEFORM OF WRITE CYCLE(2) (CS Controlled)
tWC
Address
tAS(3)
tCW(2)
tWR(4)
CS
tAW
tBW
UB, LB
tWP(1)
WE
tDW
tDH
Data Valid
Data in
Data out
High-Z
High-Z
7
Revision 2.0
February 1998
KM616V1000B, KM616U1000B Family
CMOS SRAM
TIMING WAVEFORM OF WRITE CYCLE(3) (UB, LB Controlled)
tWC
Address
tCW(2)
tWR(4)
CS
tAW
tBW
UB, LB
tAS(3)
tWP(1)
WE
tDH
tDW
Data in
Data Valid
High-Z
Data out
High-Z
NOTES (WRITE CYCLE)
1. A write occurs during the overlap(tWP) of low CS and low WE. A write begins when CS goes low and WE goes low with asserting UB
or LB for single byte operation or simultaneously asserting UB and LB for double byte operation. A write ends at the earliest transi-
tion when CS goes high and WE goes high. The tWP is measured from the beginning of write to the end of write.
2. tCW is measured from the CS going low to end of write.
3. tAS is measured from the address valid to the beginning of write.
4. tWR is measured from the end or write to the address change. tWR applied in case a write ends as CS or WE going high.
DATA RETENTION WAVE FORM
CS controlled
Data Retention Mode
tSDR
tRDR
VCC
3.0/2.7V1)
2.2V
VDR
CS³ VCC - 0.2V
CS
GND
1. 3.0V for KM616V1000B family, 2.7V KM616U1000B family
8
Revision 2.0
February 1998
KM616V1000B, KM616U1000B Family
CMOS SRAM
Unit : millimeter(inch)
PACKAGE DIMENSIONS
0~8°
44 PIN THIN SMALL OUTLINE PACKAGE TYPE II (400F)
0.25
0.010
(
)
#44
#23
0.45 ~0.75
0.018 ~ 0.030
11.76±0.20
0.463±0.008
0.50
)
(
0.020
#1
#22
1.00±0.10
0.039±0.004
18.81
0.741
1.20
0.047
MAX.
MAX.
18.41±0.10
0.725±0.004
0.10
0.004
MAX
0.35±0.10
0.014±0.004
0.80
0.0315
0.805
0.032
(
)
0~8°
44 PIN THIN SMALL OUTLINE PACKAGE TYPE II (400R)
0.25
0.010
(
)
#1
#22
0.45 ~0.75
0.018 ~ 0.030
11.76±0.20
0.463±0.008
0.50
0.020
(
)
#44
#23
1.00±0.10
0.039±0.004
18.81
0.741
1.20
0.047
MAX.
MAX.
18.41±0.10
0.725±0.004
0.10
0.004
MAX
0.35±0.10
0.014±0.004
0.80
0.0315
0.805
0.032
(
)
9
Revision 2.0
February 1998
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