KM62256CLTG-5L [SAMSUNG]
32Kx8 bit Low Power CMOS Static RAM; 32Kx8位低功耗CMOS静态RAM
| 型号： | KM62256CLTG-5L |
| 厂家： | 
SAMSUNG |
| 描述： | 32Kx8 bit Low Power CMOS Static RAM |
| 文件： | 总10页 (文件大小：165K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PRELIMINARY
KM62256C Family
CMOS SRAM
32Kx8 bit Low Power CMOS Static RAM
FEATURES
GENERAL DESCRIPTION
The KM62256C family is fabricated by SAMSUNG's advanced
CMOS process technology. The family can support various
operating temperature ranges and has various package types
for user flexibility of system design. The family also support low
data retention voltage for battery back-up operation with low
data retention current.
¡ Ü
§•
Process Technology : 0.7
Organization : 32Kx8
CMOS
¡ ¾
¡ Ü
¡ Ü
¡ Ü
¡ Ü
¡ Ü
Power Supply Voltage : Single 5V
10%
Low Data Retention Voltage : 2V(Min)
Three state output and TTL Compatible
Package Type : JEDEC Standard
28-DIP, 28-SOP, 28-TSOP I -Forward/Reverse
PRODUCT FAMILY
Power Dissipation
PKG Type
Product
Family
Operating
Temperature.
Speed
(ns)
Standby
Operating
(Icc2)
(ISB1, Max)
KM62256CL
28-DIP, 28-SOP
28-TSOP I R/F
§Ë
§Ë
§Ë
§Ë
§Ë
§Ë
100
¡ É
Commercial (0~70
)
45*/55/70ns
70/100ns
70/100ns
KM62256CL-L
KM62256CLE
KM62256CLE-L
KM62256CLI
KM62256CLI-L
20
28-SOP
28-TSOP I R/F
100
¡ É
)
Extended (-25~85
70mA
50
28-SOP
28-TSOP I R/F
100
¡ É
)
Industrial (-40~85
50
* The parameter is measured with 30pF test load.
PIN DESCRIPTION
FUNCTIONAL BLOCK DIAGRAM
A0~A2, A9~11
Y-Decoder
1
28
27
26
25
24
23
22
21
20
19
18
17
16
15
A10
OE
2
CS
I/O8
I/O7
I/O6
I/O5
I/O4
VSS
I/O3
I/O2
I/O1
A0
A11
A9
3
4
A8
A14
A12
A7
1
28
27
26
25
24
23
22
21
20
19
18
17
16
15
VCC
WE
A13
5
A13
WE
VCC
A14
A12
A7
A3~A8,
6
2
28-TSOP
Type I - Forward
A12~14
7
Cell
Array
8
3
9
4
A6
A8
10
11
12
13
14
A6
5
A5
A9
A5
CS
WE,OE
A1
A4
6
A11
A4
A2
A3
I/O Buffer
28-DIP
28-SOP
7
OE
A10
A3
I/O1~8
8
14
13
12
11
10
9
A3
A4
15
16
17
18
19
20
21
22
23
24
25
26
27
28
A2
A2
A1
9
CS
I/O8
I/O7
I/O6
I/O5
I/O4
A1
A5
A0
A6
I/O1
I/O2
I/O3
VSS
I/O4
I/O5
I/O6
I/O7
I/O8
CS
A10
10
11
12
13
14
A0
A7
A12
A14
VCC
WE
A13
A8
NameName
Function
O1
O2
O3
VSS
8
28-TSOP
Type I - Reverse
A0~A14
Address Inputs
Write Enable Input
Chip Select Input
Output Enable Input
Data Inputs/Outputs
Power(5V)
7
6
WE
5
4
CS
A9
3
A11
2
OE
1
OE
I/O1~I/O8
Vcc
Vss
Ground
Revision 3.0
April 1996
PRELIMINARY
KM62256C Family
CMOS SRAM
PRODUCT LIST & ORDERING INFORMATION
PRODUCT LIST
Commercial Temp Product
¡ É
Extended Temp Products
¡ É
Industrial Temp Products
¡ É
(0~70
)
(-25~85
)
(-40~85
)
Part Name
Function
Part Name
Function
Part Name
Function
KM62256CLP-4
KM62256CLP-4L
KM62256CLP-5
KM62256CLP-5L
KM62256CLP-7
KM62256CLP-7L
KM62256CLG-4
28-DIP, 45ns, L-pwr
28-DIP, 45ns, LL-pwr
28-DIP, 55ns, L-pwr
28-DIP, 55ns, LL-pwr
28-DIP, 70ns, L-pwr
28-DIP, 70ns, LL-pwr
28-SOP, 45ns, L-pwr
KM62256CLGE-7
KM62256CLGE-7L
KM62256CLGE-10
28-SOP, 70ns, L-pwr
28-SOP, 70ns, LL-pwr
28-SOP, 100ns, L-pwr
KM62256CLGI-7
KM62256CLGI-7L
KM62256CLGI-10
KM62256CLGI-10L
KM62256CLTGI-7
KM62256CLTGI-7L
KM62256CLTGI-10
28-SOP, 70ns, L-pwr
28-SOP, 70ns, LL-pwr
28-SOP, 100ns, L-pwr
28-SOP, 100ns, LL-pwr
28-TSOP F, 70ns, L-pwr
28-TSOP F, 70ns, LL-pwr
28-TSOP F, 100ns, L-pwr
KM62256CLGE-10L 28-SOP, 100ns, LL-pwr
KM62256CLTGE-7 28-TSOP F, 70ns, L-pwr
KM62256CLTGE-7L 28-TSOP F, 70ns, LL-pwr
KM62256CLTGE-10 28-TSOP F, 100ns, L-pwr
KM62256CLG-4L 28-SOP, 45ns, LL-pwr
KM62256CLG-5 28-SOP, 50ns, L-pwr
KM62256CLG-5L 28-SOP, 50ns, LL-pwr
KM62256CLG-7 28-SOP, 70ns, L-pwr
KM62256CLG-7L 28-SOP, 70ns, LL-pwr
KM62256CLTG-4 28-TSOP F, 45ns, L-pwr
KM62256CLTG-4L 28-TSOP F, 45ns, LL-pwr
KM62256CLTG-5 28-TSOP F, 55ns, L-pwr
KM62256CLTG-5L 28-TSOP F, 55ns, LL-pwr
KM62256CLTG-7 28-TSOP F, 70ns, L-pwr
KM62256CLTGE-10L 28-TSOP F, 100ns, LL-pwr KM62256CLTGI-10L 28-TSOP F, 100ns, LL-pwr
KM62256CLRGE-7
28-TSOP R, 70ns, L-pwr
KM62256CLRGI-7
28-TSOP R, 70ns, L-pwr
28-TSOP R, 70ns, LL-pwr
28-TSOP R, 100ns, L-pwr
KM62256CLRGE-7L 28-TSOP R, 70ns, LL-pwr KM62256CLRGI-7L
KM62256CLRGE-10 28-TSOP R, 100ns, L-pwr KM62256CLRGI-10
KM62256CLRGE-10L 28-TSOP R, 100ns, LL-pwr KM62256CLRGI-10L 28-TSOP R, 100ns, LL-pwr
KM62256CLTG-7L 28-TSOP F, 70ns, LL-pwr
KM62256CLRG-4 28-TSOP R, 45ns, L-pwr
KM62256CLRG-4L 28-TSOP R, 45ns, LL-pwr
KM62256CLRG-5 28-TSOP R, 55ns, L-pwr
KM62256CLRG-5L 28-TSOP R, 55ns, LL-pwr
KM62256CLRG-7 28-TSOP R, 70ns, L-pwr
KM62256CLRG-7L 28-TSOP R, 70ns, LL-pwr
ORDERING INFORMATION
KM6 2 X 256 C X X X - XX X
L-Low Low Power, Blank-Low Power or High Power
Access Time : 4=45ns, 5=55ns, 7=70ns, 10=100ns
Operating temperature : Blank=Commercial, I=Industrial, E=Extended
Package Type : G=SOP, P=DIP, TG=TSOP Forward, RG=TSOP Revers
L-Low Power or Low Low Power, Blank-High Power
Die Version : C=4th generation
Density : 256=256K bit
Blank=5V, V=3.0~3.6V, U=2.7~3.3V
Organization : 2=x8
SEC Standard SRAM
Revision 3.0
April 1996
PRELIMINARY
KM62256C Family
CMOS SRAM
ABSOLUTE MAXIMUM RATINGS*
Item
Voltage on any pin relative to Vss
Voltage on Vcc supply relative to Vss
Power Dissipation
Symbol
VIN,VOUT
VCC
Ratings
-0.5 to VCC+0.5
-0.5 to 7.0
1.0
Unit
V
Remark
-
V
-
PD
W
¡ É
¡ É
¡ É
¡ É
-
-
Storage temperature
TSTG
TA
-65 to 150
0 to 70
-
KM62256CL/L-L
KM62256CLE/LE-L
KM62256CLI/LI-L
-
Operating Temperature
-25 to 85
-40 to 85
¡ É
260 , 10sec (Lead Only)
Soldering temperature and time
TSOLDER
* Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of
the device at these or any other conditions above those indicated in the operating section of this specification is not implied. Exposure to absolute maximum rating conditions
for extended periods may affect reliability.
RECOMMENDED DC OPERATING CONDITIONS*
Item
Symbol
Vcc
Min
4.5
Typ**
Max
5.5
Unit
V
Supply voltage
Ground
5.0
Vss
0
0
-
0
V
Input high voltage
Input low voltage
VIH
2.2
Vcc+0.5V
0.8
V
VIL
-0.5***
-
V
¡É
* 1) Commercial Product : TA=0 to 70 , unless otherwise specified
¡É
2) Extended Product : TA=-25 to 85 , unless otherwise specified
¡É
3) Industrial Product : TA=-40 to 85 , unless otherwise specified
¡É
** TA=25
¡Â
*** VIL(min)=-3.0V for
50ns pulse width
¡ É
CAPACITANCE* (f=1MHz, TA=25
)
Item
Symbol
CIN
Test Condition
VIN=0V
Min
Max
Unit
Input capacitance
-
-
6
8
pF
pF
Input/Output capacitance
* Capacitance is sampled not 100% tested
CIO
VIO=0V
Revision 3.0
April 1996
PRELIMINARY
KM62256C Family
CMOS SRAM
DC AND OPERATING CHARACTERISTICS
Item
Symbol
Test Conditions*
VIN=Vss to Vcc
Min Typ**
Max
Unit
Input leakage current
ILI
-1
-1
-
-
1
§Ë
CS=VIH or WE=VIL
VIO=Vss to Vcc
Output leakage current
ILO
ICC
1
§Ë
Operating power supply current
-
-
7
-
15***
mA
CS=VIL, VIN=VIH or VIL, IIO=0mA
§Á
Cycle time=1
100% duty
0.2V
Vcc -0.2V, IIO=0mA
ICC1
ICC2
¡ Â 0.2V, VIL¡ Â
7****
70
mA
mA
CS
VIN ¡ Ã
Average operating current
Min cycle, 100% duty
CS=VIL, IIO=0mA
-
-
Output low voltage
Output high voltage
Standby Current(TTL)
VOL
VOH
ISB
IOL=2.1mA
IOH=-1.0mA
CS=VIH
-
2.4
-
-
-
-
0.4
-
V
V
1*****
mA
§Ë
§Ë
KM62256CL
KM62256CL-L
L(Low Power)
LL(L Low Power)
-
-
2
1
100
20
¡ Ã
CS Vcc-0.2V
§Ë
§Ë
StandbyCurrent KM62256CLE
L(Low Power)
LL(L Low Power)
-
-
-
-
100
50
VIN¡ Ã
ISB1
0.2V or
¡ Â
(CMOS)
KM62256CLE-L
VIN VCC-0.2V
§Ë
§Ë
KM62256CLI
KM62256CLI-L
L(Low Power)
LL(L Low Power)
-
-
-
-
100
50
¡É
¡É
¡¾
¡ ¾
* 1) Commercial Product : TA=0 to 70 , Vcc=5V 10% unless otherwise specified
2) Extended Product : TA=-25 to 85 , Vcc=5V 10% nless otherwise specified
¡É ¡¾
3) Industrial Product : TA=-40 to 85 , Vcc=5V 10% unless otherwise specified
¡É
** TA=25
*** 20mA for Extended and Industrial Products
****10mA for Extended and Industrial Products
*****2mA for Extended and Industrial Products
A.C CHARACTERISTICS
TEST CONDITIONS(1.Test Load and Test Input/Output Reference)*
Item
Input pulse level
Value
0.8 to 2.4V
5ns
Remark
-
-
-
-
-
Input rising & falling time
CL*
input and output reference voltage
1.5V
CL=100pF+1TTL
**CL=30pF+1TTL
Output load (See right)
* Including scope and jig capacitance
* See DC Operating conditions
** Test load for 45ns commercial products
Revision 3.0
April 1996
PRELIMINARY
KM62256C Family
CMOS SRAM
TEST CONDITIONS(2. Temperature and Vcc Conditions)
Product Family
KM62256CL/L-L
KM62256CLE/LE-L
KM62256CLI/LI-L
Temperature
¡ É
Power Supply(Vcc)
Speed Bin
45*/55/70ns
70/100ns
Comments
Commercial
Extended
¡ ¾
¡ ¾
¡ ¾
0~70
5V
5V
5V
10%
10%
10%
¡ É
¡ É
-25~85
-40~85
70/100ns
Industrial
* The parameter is measured with 30pF test load
PARAMETER LIST FOR EACH SPEED BIN
Speed Bins
70ns
Parameter List
Symbol
Units
45ns*
55ns
100ns
Min
Max
Min
Max
Min
Max
Min
Max
Read
Read cycle time
45
-
-
45
45
25
-
55
-
-
55
55
25
-
70
-
-
70
70
35
-
100
-
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tRC
tAA
Address access time
100
Chip select to output
-
-
-
-
100
tCO
tOE
Output enable to valid output
Chip select to low-Z output
Output enable to low-Z output
Chip disable to high-Z output
Output disable to high-Z output
Output hold from address change
Write cycle time
-
-
-
-
50
-
10
5
10
5
10
5
10
5
tLZ
-
-
-
-
tOLZ
tHZ
0
20
20
-
0
20
20
-
0
30
30
-
0
35
35
-
0
0
0
0
tOHZ
tOH
tWC
tCW
tAS
5
5
5
5
Write
45
45
0
-
55
45
0
-
70
60
0
-
100
80
0
-
Chip select to end of write
Address set-up time
-
-
-
-
-
-
-
-
Address valid to end of write
Write pulse width
45
40
0
-
45
40
0
-
60
50
0
-
80
60
0
-
tAW
tWP
tWR
tWHZ
tDW
tDH
-
-
-
-
Write recovery time
-
-
-
-
Write to output high-Z
0
20
-
0
20
-
0
25
-
0
35
-
Data to write time overlap
Data hold from write time
End write to output low-Z
25
0
25
0
30
0
50
0
-
-
-
-
5
-
5
-
5
-
5
-
tOW
* The parameter is measured with 30pF test load
Revision 3.0
April 1996
PRELIMINARY
KM62256C Family
CMOS SRAM
DATA RETENTION CHARACTERISTICS
Item
Symbol
Test Condition*
Min
Typ**
Max
Unit
¡ Ã
Vcc for data retention
VDR
IDR
CS Vcc-0.2V
2.0
-
5.5
V
KM62256CL
KM62256CL-L
L-Ver
LL-Ver
-
-
1
0.5
50
10
KM62256CLE
KM62256CLE-L
Vcc=3.0V
L-Ver
LL-Ver
-
-
-
-
50
25
§Ë
Data retention current
¡ Ã
CS Vcc-0.2V
KM62256CLI
KM62256CLI-L
L-Ver
LL-Ver
-
-
-
-
50
25
Data retention set-up time
Recovery time
0
5
-
-
-
-
tSDR
tRDR
See data retention
waveform
ms
¡É
* 1) Commercial Product : Ta=0 to 70 , unless otherwise specified
¡É
2) Extended Product : TA=-25 to 85 , nless otherwise specified
¡ É
3) Industrial Product : Ta=-40 to 85 , unless otherwise specified
¡É
** TA=25
DATA RETENTION WAVE FORM
1) CS Controlled
Data Retention Mode
tRDR
tSDR
VCC
4.5V
2.2V
VDR
¡ Ã
CS VCC - 0.2V
CS
GND
FUNCTIONAL DESCRIPTION
CS
WE
X
OE
X
Mode
I/O Pin
High-Z
High-Z
Dout
Current Mode
H
Power Down
Output Disable
Read
ISB ISB1
ICC
L
H
H
L
H
L
ICC
L
L
X
Write
Din
ICC
* X means don't care
Revision 3.0
April 1996
PRELIMINARY
KM62256C Family
CMOS SRAM
TIMMING DIAGRAMS
TIMING WAVEFORM OF READ CYCLE (1()Address Controlled)
( CS=OE=VIL, WE=VIH)
tRC
Address
tAA
tOH
Data Out
Previous Data Valid
Data Valid
TIMING WAVEFORM OF READ CYCLE(2()WE=VIH)
tRC
Address
CS
tOH
tAA
tCO
tHZ
tOE
OE
tOLZ
tOHZ
tLZ
Data out
High-Z
Data Valid
NOTES (READ CYCLE)
1. tHZ and tOHZ are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage levels.
2. At any given temperature and voltage condition, tHZ(max.) is less than tLZ(min.) both for a given device and from device to device.
Revision 3.0
April 1996
PRELIMINARY
KM62256C Family
CMOS SRAM
TIMING WAVEFORM OF WRITE CYCLE(1()WE Controlled)
tWC
Address
CS
tWR(4)
tCW(2)
tAW
tWP(1)
WE
tAS(3)
tDW
tDH
Data in
Data Valid
tWHZ
tOW
Data out
Data Undefined
TIMING WAVEFORM OF WRITE CYCLE(2()CS Controlled)
tWC
Address
tWR(4)
tAS(3)
tCW(2)
CS
tAW
tWP(1)
WE
tDH
tDW
Data in
Data Valid
High-Z
Data out
High-Z
NOTES (WRITE CYCLE)
1. A write occurs during the overlap(tWP) of low CS and low WE. A write begins at the latest transition among CS goes low and WE going low : A write end
at the earliest transition among CS going high and WE going high, tWP is measured from the beginning of write to the end of write.
2. tCW is measured from the CS going low to end of write.
3. tAS is measured from the address valid to the beginning of write.
4. tWR is measured from the end of write to the address change. tWR applied in case a write ends as CS or WE going high.
Revision 3.0
April 1996
PRELIMINARY
KM62256C Family
CMOS SRAM
Units :Millimeters(Inches )
PACKAGE DIMENSIONS
28 PIN DUAL INLINE PACKAGE(600mil)
+0.10
0.25
-0.05
+0.004
0.010
-0.002
#28
#15
¡¾
13.60
0.535
0.20
¡¾
0.008
#1
#14
¡É
0~15
¡¾
¡¾
3.81
0.150
0.20
0.008
36.72
1.446
MAX
5.08
0.200
MAX
¡¾
36.32
1.430
0.20
¡¾
0.008
¡¾
¡¾
3.30
0.130
0.30
0.012
¡¾
¡¾
0.46
0.10
0.004
0.018
0.38
0.015
2.54
0.100
1.65
0.065
¡¾
¡¾
1.52
0.060
0.10
0.004
MIN
(
)
28 PIN PLASTIC SMALL OUTLINE PACKAGE(450mil)
¡É
0~8
#28
#15
¡¾
¡¾
¡¾
8.38
0.330
0.20
11.81
0.465
0.30
¡¾
0.008
0.012
#1
#14
¡¾
¡¾
1.02
0.040
0.20
+0.10
-0.05
+0.004
-0.05
0.15
0.008
¡¾
¡¾
2.59
0.102
0.20
18.69
0.736
0.006
MAX
0.008
3.00
0.118
MAX
¡¾
18.29
0.720
0.20
¡¾
0.008
0.10 MAX
0.004 MAX
1.27
0.050
0.89
0.035
¡¾
¡¾
0.41
0.016
0.10
(
)
0.05
0.002
MIN
0.004
Revision 3.0
April 1996
PRELIMINARY
KM62256C Family
CMOS SRAM
Units :Millimeters(Inches )
PACKAGE DIMENSIONS
28 PIN THIN SMALL OUTLINE PACKAGE TYPE I (0813.4F)
¡¾
13.40
0.528
0.20
+0.10
-0.05
0.20
¡¾
0.008
+0.004
0.008
-0.002
#1
#28
0.425
0.017
(
)
0.55
0.0217
#14
#15
¡¾
¡¾
1.00
0.039
0.10
0.05
0.002
MIN
0.004
1.20
0.047
MAX
28 PIN THIN SMALL OUTLINE PACKAGE TYPE I (0813.4R)
¡¾
13.40
0.528
0.20
+0.10
-0.05
0.20
¡¾
0.008
0.008+0.004
-0.002
#14
#15
0.425
0.017
(
)
0.55
0.0217
#1
#28
¡¾
0.25
0.010
11.80
0.465
0.10
+0.10
-0.05
¡¾
0.10
1.00
0.039
0.05
0.002
TYP
0.15
MIN
¡¾
0.004
¡¾
0.004
0.006+0.004
-0.002
1.20
0.047
MAX
¡É
0~8
0.50
0.020
0.45 ~0.75
0.018 ~0.030
(
)
Revision 3.0
April 1996
相关型号：
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