KM62U256CLGI-10L [SAMSUNG]
Standard SRAM, 32KX8, 100ns, CMOS, PDSO28, 0.450 INCH, SOP-28;
| 型号： | KM62U256CLGI-10L |
| 厂家： | 
SAMSUNG |
| 描述： | Standard SRAM, 32KX8, 100ns, CMOS, PDSO28, 0.450 INCH, SOP-28 静态存储器 光电二极管 |
| 文件： | 总9页 (文件大小：148K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
KM62V256C, KM62U256C Family
CMOS SRAM
Document Title
32Kx8 bit Low Power and Low Voltage CMOS Static RAM
Revision History
Revision No. History
Draft Data
Remark
0.0
0.1
1.0
2.0
3.0
Design target
Initial draft
Finalize
February 12, 1993
Advance
November 2, 1993
Preliminary
September 24, 1994 Final
Revised
August 12, 1995
April 1, 1997
Final
Final
Revised
- One datasheet for commercial, extended, industrial product.
- Increased KM62V256C Family¢s ICC2 30 to 35mA.
- Increased tDW 50 to 60ns for KM62U256C Family.
- Remove SOP package from KM62V256C Family.
4.0
Revised
February 12, 1998
Final
- Change datasheets format.
- Improved power dissipation : 0.7W® 1W
The attached datasheets are provided by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the specifications and
products. SAMSUNG Electronics will answer to your questions about device. If you have any questions, please contact the SAMSUNG branch offices.
1
Revision 4.0
February 1998
KM62V256C, KM62U256C Family
CMOS SRAM
32Kx8 bit Low Power and Low Voltage CMOS Static RAM
FEATURES
GENERAL DESCRIPTION
· Process Technology : Poly Load
· Organization : 32Kx8
The KM62V256C and KM62U256C families are fabricated
by SAMSUNG¢s advanced CMOS process technology. The
families support various operating temperature ranges and
has various package types for user flexibility of system
design. The families also support low data retention voltage
for battery back-up operation with low data retention current.
· Power Supply Voltage
KM62V256C family : 2.7~3.3V
KM62U256C family : 3.0~3.6V
· Low Data Retention Voltage : 2V(Min)
· Three state output and TTL Compatible
· Package Type : 28-SOP-450, 28-TSOP1-0813.4F/R
PRODUCT FAMILY
Power Dissipation
Operating
Temperature
Product Family
VCC Range
Speed(ns)
PKG Type
Standby
Operating
(ICC2, Max)
(ISB1, Max)
701)/100
851)/100
701)/100
851)/100
701)/100
851)/100
KM62V256CL-L
KM62U256CL-L
KM62V256CLE-L
KM62U256CLE-L
KM62V256CL-L
KM62U256CLI-L
3.0 ~ 3.6V
2.7 ~ 3.3V
3.0 ~ 3.6V
2.7 ~ 3.3V
3.0 ~ 3.6V
2.7 ~ 3.3V
10mA
10mA
20mA
15mA
20mA
15mA
Commercial(0~70°C)
Extended(-25~85°C)
Industrial(-40~85°C)
28-SOP2)
28-TSOP1-F/R
35mA
1. The parameter is measured with 30pF test load.
2. The device with 100ns SOP package in 3.0~3.6V VCC range which is not produced.
PIN DESCRIPTION
FUNCTIONAL BLOCK DIAGRAM
1
2
3
4
5
6
7
8
28
27
26
25
24
23
22
21
20
19
18
17
16
15
A10
CS
OE
A11
A9
A8
A13
WE
VCC
A14
A12
A7
Clk gen.
Precharge circuit.
I/O8
I/O7
I/O6
I/O5
I/O4
VSS
I/O3
I/O2
I/O1
A0
A14
1
28
27
26
25
24
23
22
21
20
19
18
17
16
15
VCC
WE
A12
A7
2
28-TSOP
A3
A4
3
A13
A8
Type1 - Forward
9
4
A6
A5
A6
A7
10
11
12
13
14
5
Memory array
512 rows
64´ 8 columns
A5
A9
A6
A5
A4
A3
Row
select
6
A11
OE
A4
A1
A2
7
A3
A8
28-SOP
8
A10
CS
A2
A12
A13
A14
14
13
12
11
10
9
8
7
6
5
A3
A4
A5
A6
A7
A12
A14
VCC
WE
A13
A8
15
16
17
18
19
20
21
22
23
24
25
26
27
28
A2
A1
A0
9
A1
10
11
12
13
14
I/O8
I/O7
I/O6
I/O5
I/O4
A0
I/O1
I/O2
I/O3
VSS
I/O4
I/O5
I/O6
I/O7
I/O8
CS
I/O1
I/O2
I/O3
VSS
28-TSOP
I/O1
I/O8
Data
cont
I/O Circuit
Type1 - Reverse
Column select
4
3
2
1
A9
A11
Data
cont
A10
OE
Pin Name
CS
Function
A0 A1
A2 A9 A10
A11
Chip Select Input
Output Enable Input
Write Enable Input
Address Inputs
Data Inputs/Outputs
Power
OE
CS
WE
Control
logic
WE
OE
A0~A14
I/O1~I/O8
Vcc
Vss
Ground
SAMSUNG ELECTRONICS CO., LTD. reserves the right to change products and specifications without notice.
2
Revision 4.0
February 1998
KM62V256C, KM62U256C Family
CMOS SRAM
PRODUCT LIST
Commercial Temperature Products
Extended Temperature Products
(-25~85°C)
Industrial Temperature Products
(-40~85°C)
(0~70°C)
Part Name
Function
Part Name
Function
Part Name
Function
KM62V256CLG-7L
KM62V256CLG-10L
KM62V256CLTG-7L
28-SOP, 70ns, 3.3V
28-SOP, 100ns, 3.3V
28-TSOP F, 70ns, 3.3V
KM62V256CLGE-7L
KM62V256CLGE-10L
KM62V256CLTGE-7L
28-SOP, 70ns, 3.3V
28-SOP, 100ns, 3.3V
28-TSOP F, 70ns, 3.3V
KM62V256CLGI-7L
KM62V256CLGI-10L
KM62V256CLTGI-7L
28-SOP, 70ns, 3.3V
28-SOP, 100ns, 3.3V
28-TSOP F, 70ns, 3.3V
KM62V256CLTG-10L 28-TSOP F, 100ns, 3.3V KM62V256CLTGE-10L 28-TSOP F, 100ns, 3.3V KM62V256CLTGI-10L 28-TSOP F, 100ns, 3.3V
KM62V256CLRG-7L 28-TSOP R, 70ns, 3.3V KM62V256CLRGE-7L 28-TSOP R, 70ns, 3.3V KM62V256CLRGI-7L 28-TSOP R, 70ns, 3.3V
KM62V256CLRG-10L 28-TSOP R, 100ns, 3.3V KM62V256CLRGE-10L 28-TSOP R, 100ns, 3.3V KM62V256CLRGI-10L 28-TSOP R, 100ns, 3.3V
KM62U256CLG-8L
KM62U256CLG-10L
KM62U256CLTG-8L
28-SOP, 85ns, 3.0V
28-SOP, 100ns, 3.0V
28-TSOP F, 85ns, 3.0V
KM62U256CLGE-8L
KM62U256CLGE-10L
KM62U256CLTGE-8L
28-SOP, 85ns, 3.0V
28-SOP, 100ns, 3.0V
28-TSOP F, 85ns, 3.0V
KM62U256CLGI-8L
KM62U256CLGI-10L
KM62U256CLTGI-8L
28-SOP, 85ns, 3.0V
28-SOP, 100ns, 3.0V
28-TSOP F, 85ns, 3.0V
KM62U256CLTG-10L 28-TSOP F, 100ns, 3.0V KM62U256CLTGE-10L 28-TSOP F, 100ns, 3.0V KM62U256CLTGI-10L 28-TSOP F, 100ns, 3.0V
KM62U256CLRG-8L 28-TSOP R, 85ns, 3.0V KM62U256CLRGE-8L 28-TSOP R, 85ns, 3.0V KM62U256CLRGI-8L 28-TSOP R, 85ns, 3.0V
KM62U256CLRG-10L 28-TSOP R, 100ns, 3.0V KM62U256CLRGE-10L 28-TSOP R, 100ns, 3.0V KM62U256CLRGI-10L 28-TSOP R, 100ns, 3.0V
FUNCTIONAL DESCRIPTION
CS
H
L
OE
X1)
H
WE
X1)
H
I/O
High-Z
High-Z
Dout
Mode
Deselected
Output Disabled
Read
Power
Standby
Active
L
L
H
Active
X1)
L
L
Din
Write
Active
1. X means don¢t care(Must be low or high state.)
ABSOLUTE MAXIMUM RATINGS1)
Item
Symbol
VIN,VOUT
VCC
Ratings
Unit
Remark
Voltage on any pin relative to Vss
Voltage on Vcc supply relative to Vss
Power Dissipation
-0.5 to VCC+0.5
-0.3 to 4.6
V
V
-
-
-
-
PD
1.0
W
°C
°C
°C
°C
-
Storage temperature
TSTG
-65 to 150
0 to 70
KM62V256CL-L, KM62U256CL-L
KM62V256CLE-L, KM62U256CLE-L
KM62V256CLI-L, KM62U256CLI-L
-
Operating Temperature
TA
-25 to 85
-40 to 85
Soldering temperature and time
TSOLDER
260°C, 10sec (Lead Only)
1. Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. Functional operation should be
restricted to recommended operating condition. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
3
Revision 4.0
February 1998
KM62V256C, KM62U256C Family
CMOS SRAM
RECOMMENDED DC OPERATING CONDITIONS1)
Item
Symbol
Product
Min
Typ
Max
Unit
KM62V256C Family
KM62U256C Family
3.0
2.7
3.3
3.0
3.6
3.3
Supply voltage
Vcc
V
Ground
Vss
VIH
VIL
All
0
0
-
0
V
V
V
Vcc+0.3V2)
0.4
Input high voltage
Input low voltage
KM62V256C, KM62U256C Family
KM62V256C, KM62U256C Family
2.2
-0.33)
-
Note:
1. Commercial Product : TA=0 to 70°C, otherwise specified
Extended Product : TA=-25 to 85°C, unless otherwise specified
Industrial Product : TA=-40 to 85°C, otherwise specified
2. Overshoot : VCC+3.0V in case of pulse width £ 30ns
3. Undershoot : -3.0V in case of pulse width £ 30ns
4. Overshoot and undershoot are sampled, not 100% tested.
CAPACITANCE1) (f=1MHz, TA=25°C)
Item
Symbol
CIN
Test Condition
VIN=0V
Min
Max
6
Unit
pF
Input capacitance
-
-
Input/Output capacitance
CIO
VIO=0V
8
pF
1. Capacitance is sampled, not 100% tested
DC AND OPERATING CHARACTERISTICS
Item
Symbol
ILI
Test Conditions
Min Typ Max Unit
Input leakage current
Output leakage current
Operating power supply
VIN=Vss to Vcc
-1
-1
-
-
-
1
1
mA
mA
mA
mA
mA
V
ILO
CS=VIH or OE=VIH or WE=VIL, VIO=VSS to Vcc
IIO=0mA, CS=VIL, VIN=VIH or VIL
ICC
1.0
2.5
20
-
2.0
5
ICC1
ICC2
VOL
VOH
ISB
Cycle time=1ms, 100% duty, IIO=0mA, CS£0.2V, VIN£0.2V, VIN³ Vcc -0.2V
Cycle time=Min,100% duty, IIO=0mA, CS=VIL, VIN=VIH or VIL
IOL=2.1mA
-
Average operating current
-
35
0.4
-
Output low voltage
Output high voltage
Standby Current(TTL)
-
IOH=-1.0mA
2.2
-
-
V
CS=VIH, Other inputs=VIH or VIL
-
0.3
mA
KM62V256CL-L
KM62V256CLE-L
KM62V256CLI-L
-
-
-
1.5
1.5
1.5
10
20
20
mA
mA
Standby Current(CMOS)
ISB1
CS³ Vcc-0.2V, Other inputs=0~Vcc
KM62U256CL-L
KM62U256CLE-L
KM62U256CLI-L
-
-
-
1.0
1.0
1.0
10
15
15
4
Revision 4.0
February 1998
KM62V256C, KM62U256C Family
CMOS SRAM
AC OPERATING CONDITIONS
TEST CONDITIONS( Test Load and Input/Output Reference)
Input pulse level : 0.4 to 2.2V
Input rising and falling time : 5ns
1)
Input and output reference voltage :1.5V
Output load(see right) : CL=100pF+1TTL
CL
1)CL=30pF+1TTL
1. KM62V256CL-7L Family, KM62U256CL-8L Family
1. Including scope and jig capacitance
AC CHARACTERISTICS (KM62V256C Family : Vcc=3.0~3.6V, KM62U256C Family : Vcc=2.7~3.3V
Commercial product :TA=0 to 70°C, Extended product :TA=-25 to 85°C, Industrial product : TA=-40 to 85°C)
Speed Bins
Parameter List
Symbol
Units
70ns
85ns
100ns
Min
70
-
Max
Min
85
-
Max
Min
100
-
Max
Read cycle time
tRC
tAA
-
70
70
35
-
-
85
85
40
-
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Address access time
100
Chip select to output
tCO
tOE
-
-
-
100
Output enable to valid output
Chip select to low-Z output
Output enable to low-Z output
Chip disable to high-Z output
Output disable to high-Z output
Output hold from address change
Write cycle time
-
-
-
50
-
Read
tLZ
10
5
10
5
10
5
tOLZ
tHZ
-
-
-
0
30
30
-
0
30
30
-
0
35
35
-
tOHZ
tOH
tWC
tCW
tAS
0
0
0
5
10
85
70
0
15
100
70
0
70
60
0
-
-
-
Chip select to end of write
Address set-up time
-
-
-
-
-
-
Address valid to end of write
Write pulse width
tAW
tWP
tWR
tWHZ
tDW
tDH
60
50
0
-
70
60
0
-
70
60
0
-
-
-
-
Write
Write recovery time
-
-
-
Write to output high-Z
0
25
-
0
25
-
0
30
-
Data to write time overlap
Data hold from write time
End write to output low-Z
50
0
60
0
60
0
-
-
-
tOW
5
-
10
-
10
-
DATA RETENTION CHARACTERISTICS
Item
Symbol
Test Condition
Min
Typ
Max
Unit
Vcc for data retention
VDR
CS³ Vcc-0.2V
2.0
-
3.6
V
KM62V256CL-L
KM62U256CL-L
-
-
1
0.6
8
8
Vcc=3.0V
CS³ Vcc-0.2V
KM62V256CLE-L
KM62U256CLE-L
-
-
1
0.6
10
10
Data retention current
IDR
mA
KM62V256CLI-L
KM62U256CLI-L
-
-
1
0.6
10
10
Data retention set-up time
Recovery time
tSDR
tRDR
0
5
-
-
-
-
See data retention waveform
ms
5
Revision 4.0
February 1998
KM62V256C, KM62U256C Family
CMOS SRAM
TIMMING DIAGRAMS
TIMING WAVEFORM OF READ CYCLE(1) (Address Controlled, CS=OE=VIL, WE=VIH)
tRC
Address
tAA
tOH
Data Valid
Data Out
Previous Data Valid
TIMING WAVEFORM OF READ CYCLE(2) (WE=VIH)
tRC
Address
tOH
tAA
tCO
CS
tHZ
tOE
OE
tOHZ
tOLZ
tLZ
High-Z
Data out
Data Valid
NOTES (READ CYCLE)
1. tHZ and tOHZ are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage
levels.
2. At any given temperature and voltage condition, tHZ(Max.) is less than tLZ(Min.) both for a given device and from device to device
interconnection.
6
Revision 4.0
February 1998
KM62V256C, KM62U256C Family
CMOS SRAM
TIMING WAVEFORM OF WRITE CYCLE(1) (WE Controlled)
tWC
Address
tCW(2)
tWR(4)
CS
tAW
tWP(1)
WE
tAS(3)
tDW
tDH
Data Valid
Data in
Data out
tWHZ
tOW
Data Undefined
TIMING WAVEFORM OF WRITE CYCLE(2) (CS Controlled)
tWC
Address
tCW(2)
tAS(3)
tWR(4)
CS
tAW
tWP(1)
WE
tDW
tDH
Data in
Data Valid
High-Z
Data out
High-Z
NOTES (WRITE CYCLE)
1. A write occurs during the overlap of a low CS and a low WE. A write begins at the latest transition among CS going Low and WE
going low : A write end at the earliest transition among CS going high and WE going high, tWP is measured from the begining of write
to the end of write.
2. tCW is measured from the CS going low to end of write.
3. tAS is measured from the address valid to the beginning of write.
4. tWR is measured from the end of write to the address change. tWR applied in case a write ends as CS or WE going high.
DATA RETENTION WAVE FORM
CS controlled
Data Retention Mode
tSDR
tRDR
VCC
3.0/2.7V1)
2.2V
VDR
CS³ VCC - 0.2V
CS
GND
1. 3.0V for KM62V256C Family, 2.7V for KM62U256C Family.
7
Revision 4.0
February 1998
KM62V256C, KM62U256C Family
PACKAGE DIMENSIONS
CMOS SRAM
Units : millimeter(inch)
28 PIN PLASTIC SMALL OUTLINE PACKAGE(450mil)
0~8°
#28
#15
8.38±0.20
0.330±0.008
11.81±0.30
0.465±0.012
#1
#14
1.02±0.20
0.040±0.008
+0.10
-0.05
0.15
2.59±0.20
0.102±0.008
18.69
0.736
+0.004
-0.002
MAX
0.006
3.00
0.118
MAX
18.29±0.20
0.720±0.008
0.10 MAX
0.004 MAX
0.89
0.035
1.27
0.050
0.41±0.10
0.016±0.004
(
)
0.05
0.002
MIN
8
Revision 4.0
February 1998
KM62V256C, KM62U256C Family
CMOS SRAM
Units : millimeter(inch)
PACKAGE DIMENSIONS
28 PIN THIN SMALL OUTLINE PACKAGE TYPE I (0813.4F)
13.40±0.20
0.528±0.008
+0.10
0.20
-0.05
+0.004
0.008
-0.002
#1
#28
0.425
0.017
(
)
0.55
0.0217
#14
#15
1.00±0.10
0.039±0.004
0.05
0.002
MIN
1.20
MAX
0.047
28 PIN THIN SMALL OUTLINE PACKAGE TYPE I (0813.4R)
13.40±0.20
0.528±0.008
+0.10
-0.05
0.20
0.008+0.004
-0.002
#14
#15
0.425
0.017
(
)
0.55
0.0217
#1
#28
0.25
0.010
11.80±0.10
0.465±0.004
+0.10
-0.05
1.00±0.10
0.039±0.004
0.05
0.002
TYP
0.15
MIN
0.006+0.004
-0.002
1.20
MAX
0.047
0~8°
0.50
0.020
0.45 ~0.75
0.018 ~0.030
(
)
9
Revision 4.0
February 1998
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