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KM681002AJI-2000 [SAMSUNG]

Standard SRAM, 128KX8, 20ns, CMOS, PDSO32, 0.400 INCH, PLASTIC, SOJ-32;
KM681002AJI-2000
型号： KM681002AJI-2000
厂家： SAMSUNG    SAMSUNG
描述：

Standard SRAM, 128KX8, 20ns, CMOS, PDSO32, 0.400 INCH, PLASTIC, SOJ-32

静态存储器 光电二极管
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PRELIMINARY  
KM681002A, KM681002AI  
CMOS SRAM  
Document Title  
128Kx8 High Speed Static RAM(5V Operating), Revolutionary Pin out.  
Operated at Commercial and Industrial Temperature Range.  
Revision History  
Rev.No.  
Rev. 0.0  
Rev. 1.0  
History  
Remark  
Preliminary  
Final  
DraftData  
Initial release with Preliminary.  
Apr. 22th, 1995  
Feb. 29th, 1996  
Release to final Data Sheet.  
1.1. Delete Preliminary  
Rev. 2.0  
Update D.C parameters.  
Final  
Jul. 16th, 1996  
2.1. Update D.C parameters  
Previous spec.  
Updated spec.  
(12/15/17/20ns part)  
170/165/165/160mA  
25mA  
Items  
(12/15/17/20ns part)  
200/190/180/170mA  
30mA  
Icc  
Isb  
Isb1  
10mA  
8mA  
Rev. 3.0  
Add Industrial Temperature Range parts and 300mil-SOJ PKG.  
3.1. Add 32-Pin 300mil-SOJ Package.  
Final  
Jun. 2nd, 1997  
3.2. Add Industrial Temperature Range parts with the same parame-  
ters as Commercial Temperature Range parts.  
3.2.1. Add KM68002AI parts for Industrial Temperature Range.  
3.2.2. Add ordering information.  
3.2.3. Add the condition for operating at Industrial Temp. Range.  
3.3. Add the test condition for Voh1 with Vcc=5V±5% at 25°C  
3.4. Add timing diagram to define tWP as ²(Timing Wave Form of  
Write Cycle(CS=Controlled)²  
Rev. 4.0  
4.1. Delete 17ns Part  
Final  
Feb. 25th, 1998  
The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right  
to change the specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions on the parameters of this  
device. If you have any questions, please contact the SAMSUNG branch office near your office, call or contact Headquarters.  
Rev 4.0  
Ferruary 1998  
- 1 -  
PRELIMINARY  
KM681002A, KM681002AI  
CMOS SRAM  
128K x 8 Bit High-Speed CMOS Static RAM  
FEATURES  
GENERAL DESCRIPTION  
• Fast Access Time 12, 15, 20ns(Max.)  
The KM681002A is a 1,048,576-bit high-speed Static Random  
• Low Power Dissipation  
Access Memory organized as 131,072 words by 8 bits. The  
KM681002A uses 8 common input and output lines and has an  
output enable pin which operates faster than address access  
time at read cycle. The device is fabricated using Samsung¢s  
advanced CMOS process and designed for high-speed circuit  
technology. It is particularly well suited for use in high-density  
high-speed system applications. The KM681002A is packaged  
in a 400mil 32-pin plastic SOJ or TSOP2 forward.  
Standby (TTL)  
: 25mA(Max.)  
(CMOS) : 8mA(Max.)  
Operating KM681002A - 12 : 170mA(Max.)  
KM681002A - 15 : 165mA(Max.)  
KM681002A - 20 : 160mA(Max.)  
• Single 5.0V±10% Power Supply  
• TTL Compatible Inputs and Outputs  
• I/O Compatible with 3.3V Device  
• Fully Static Operation  
- No Clock or Refresh required  
• Three State Outputs  
ORDERING INFORMATION  
• Center Power/Ground Pin Configuration  
• Standard Pin Configuration  
KM681002A -12/15/20  
Commercial Temp.  
KM681002AI -12/15/20  
Industrial Temp.  
KM681002AJ : 32-SOJ-400  
KM681002AT: 32-TSOP2-400F  
PIN CONFIGURATION(Top View)  
A0  
A1  
1
2
3
4
5
6
7
8
9
32 A16  
31 A15  
30 A14  
29 A13  
28 OE  
27 I/O8  
26 I/O7  
25 Vss  
24 Vcc  
23 I/O6  
22 I/O5  
21 A12  
20 A11  
19 A10  
18 A9  
17 A8  
FUNCTIONAL BLOCK DIAGRAM  
A2  
A3  
CS  
I/O1  
I/O2  
Vcc  
Vss  
Clk Gen.  
Pre-Charge Circuit  
A0  
A1  
A2  
A3  
A4  
A5  
A6  
A7  
A8  
SOJ/  
TSOP2  
I/O3 10  
I/O4 11  
WE 12  
A4 13  
A5 14  
A6 15  
A7 16  
Memory Array  
512 Rows  
256x8 Columns  
Data  
Cont.  
I/O Circuit  
Column Select  
I/O1~I/O8  
CLK  
Gen.  
PIN FUNCTION  
A9 A10 A11 A12 A13 A14 A15 A16  
Pin Name  
A0 - A16  
WE  
Pin Function  
Address Inputs  
Write Enable  
Chip Select  
CS  
WE  
OE  
CS  
OE  
Output Enable  
Data Inputs/Outputs  
Power(+5.0V)  
Ground  
I/O1 ~ I/O8  
VCC  
VSS  
Rev 4.0  
Ferruary 1998  
- 2 -  
PRELIMINARY  
KM681002A, KM681002AI  
CMOS SRAM  
ABSOLUTE MAXIMUM RATINGS*  
Parameter  
Symbol  
VIN, VOUT  
VCC  
Rating  
-0.5 to 7.0  
-0.5 to 7.0  
1.0  
Unit  
V
Voltage on Any Pin Relative to VSS  
Voltage on VCC Supply Relative to VSS  
Power Dissipation  
V
PD  
W
°C  
°C  
°C  
Storage Temperature  
TSTG  
TA  
-65 to 150  
0 to 70  
Operating Temperature  
Commercial  
Industrial  
TA  
-40 to 85  
* Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and  
functional operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied.  
Exposure to absolute maximum rating conditions for extended periods may affect reliability.  
RECOMMENDED DC OPERATING CONDITIONS(TA=0 to 70°C)  
Parameter  
Min  
4.5  
0
Symbol  
VCC  
Typ  
Max  
Unit  
V
Supply Voltage  
5.0  
5.5  
Ground  
VSS  
0
-
0
V
Input High Voltage  
Input Low Voltage  
VIH  
2.2  
-0.5*  
VCC + 0.5**  
0.8  
V
VIL  
-
V
NOTE: The above parameters are also guaranteed at industrial temperature range.  
* VIL(Min) = -2.0V a.c(Pulse Width£10ns) for I£20mA  
** VIH(Max) = VCC + 2.0V a.c (Pulse Width£10ns) for I£20mA  
DC AND OPERATING CHARACTERISTICS(TA=0 to 70°C, Vcc=5.0V±10%, unless otherwise specified)  
Parameter  
Input Leakage Current  
Output Leakage Current  
Symbol  
Test Conditions  
VIN=VSS to VCC  
Min  
-2  
Max  
2
Unit  
mA  
ILI  
ILO  
CS=VIH or OE=VIH or WE=VIL  
VOUT=VSS to VCC  
-2  
2
mA  
Operating Current  
ICC  
Min. Cycle, 100% Duty  
CS=VIL, VIN=VIH or VIL,  
IOUT=0mA  
12ns  
15ns  
20ns  
-
-
-
-
-
170  
165  
160  
25  
mA  
Standby Current  
ISB  
Min. Cycle, CS=VIH  
mA  
mA  
ISB1  
f=0MHz, CS ³ VCC-0.2V,  
VIN³ VCC-0.2V or VIN£0.2V  
8
Output Low Voltage Level  
Output High Voltage Level  
VOL  
VOH  
IOL=8mA  
-
2.4  
-
0.4  
-
V
V
V
IOH=-4mA  
IOH1=-0.1mA  
VOH1*  
3.95  
NOTE: The above parameters are also guaranteed at industrial temperature range.  
* VCC=5.0V, Temp.=25°C  
CAPACITANCE*(TA=25°C, f=1.0MHz)  
Item  
Input/Output Capacitance  
Input Capacitance  
Symbol  
CI/O  
Test Conditions  
VI/O=0V  
MIN  
Max  
8
Unit  
-
-
pF  
pF  
VIN=0V  
CIN  
6
* NOTE : Capacitance is sampled and not 100% tested.  
Rev 4.0  
Ferruary 1998  
- 3 -  
PRELIMINARY  
KM681002A, KM681002AI  
CMOS SRAM  
AC CHARACTERISTICS(TA=0 to 70°C, VCC=5.0V±10%, unless otherwise noted.)  
TEST CONDITIONS  
Parameter  
Value  
Input Pulse Levels  
0V to 3V  
3ns  
Input Rise and Fall Times  
Input and Output timing Reference Levels  
Output Loads  
1.5V  
See below  
NOTE : The above test conditions are also applied at industrial temperature range.  
Output Loads(A)  
Output Loads(B)  
for tHZ, tLZ, tWHZ, tOW, tOLZ & tOHZ  
+5.0V  
+5.0V  
480W  
480W  
DOUT  
DOUT  
255W  
255W  
30pF*  
5pF*  
* Including Scope and Jig Capacitance  
READ CYCLE  
KM681002A-12  
Symbol  
KM681002A-15  
KM681002A-20  
Unit  
Parameter  
Min  
12  
-
Max  
Min  
15  
-
Max  
Min  
20  
-
Max  
Read Cycle Time  
tRC  
tAA  
-
12  
12  
6
-
15  
15  
7
-
20  
20  
9
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
Address Access Time  
Chip Select to Output  
tCO  
tOE  
tLZ  
-
-
-
Output Enable to Valid Output  
Chip Enable to Low-Z Output  
Output Enable to Low-Z Output  
Chip Disable to High-Z Output  
Output Disable to High-Z Output  
Output Hold from Address Change  
Chip Selection to Power Up Time  
Chip Selection to Power DownTime  
-
-
-
3
-
3
-
3
-
tOLZ  
tHZ  
0
-
0
-
0
-
0
6
0
7
0
9
tOHZ  
tOH  
tPU  
tPD  
0
6
0
7
0
9
3
-
3
-
3
-
0
-
0
-
0
-
-
12  
-
15  
-
20  
NOTE : The above parameters are also guaranteed at industrial temperature range.  
Rev 4.0  
Ferruary 1998  
- 4 -  
PRELIMINARY  
KM681002A, KM681002AI  
CMOS SRAM  
WRITE CYCLE  
KM681002A-12  
KM681002A-15  
KM681002A-20  
Unit  
Parameter  
Symbol  
Min  
12  
8
Max  
Min  
15  
10  
0
Max  
Min  
20  
12  
0
Max  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
Write Cycle Time  
tWC  
tCW  
tAS  
-
-
-
-
-
-
-
6
-
-
-
-
-
-
-
-
-
-
7
-
-
-
-
-
-
-
-
-
-
9
-
-
-
Chip Select to End of Write  
Address Set-up Time  
0
Address Valid to End of Write  
Write Pulse Width(OE High)  
Write Pulse Width(OE Low)  
Write Recovery Time  
tAW  
tWP  
tWP1  
tWR  
tWHZ  
tDW  
tDH  
8
10  
10  
15  
0
12  
12  
20  
0
8
12  
0
Write to Output High-Z  
0
0
0
Data to Write Time Overlap  
Data Hold from Write Time  
End Write to Output Low-Z  
6
7
9
0
0
0
tOW  
3
3
3
NOTE : The above parameters are also guaranteed at industrial temperature range.  
TIMMING DIAGRAMS  
TIMING WAVEFORM OF READ CYCLE(1) (Address Controlled, CS=OE=VIL, WE=VIH)  
tRC  
Address  
tAA  
tOH  
Valid Data  
Data Out  
Previous Valid Data  
TIMING WAVEFORM OF READ CYCLE(2) (WE=VIH)  
tRC  
Address  
tAA  
tHZ(3,4,5)  
tCO  
CS  
tOE  
tOHZ  
tOH  
OE  
tOLZ  
tLZ(4,5)  
Data out  
Valid Data  
tPU  
tPD  
ICC  
ISB  
VCC  
50%  
50%  
Current  
Rev 4.0  
Ferruary 1998  
- 5 -  
PRELIMINARY  
KM681002A, KM681002AI  
CMOS SRAM  
NOTES(READ CYCLE)  
1. WE is high for read cycle.  
2. All read cycle timing is referenced from the last valid address to the first transition address.  
3. tHZ and tOHZ are defined as the time at which the outputs achieve the open circuit condition and are not referenced to VOH or  
VOL levels.  
4. At any given temperature and voltage condition, tHZ(Max.) is less than tLZ(Min.) both for a given device and from device to  
device.  
5. Transition is measured ±200mV from steady state voltage with Load(B). This parameter is sampled and not 100% tested.  
6. Device is continuously selected with CS=VIL.  
7. Address valid prior to coincident with CS transition low.  
8. For common I/O applications, minimization or elimination of bus contention conditions is necessary during read and write cycle.  
TIMING WAVEFORM OF WRITE CYCLE(1) (OE= Clock)  
tWC  
Address  
tWR(5)  
tAW  
OE  
tCW(3)  
CS  
tWP(2)  
tAS(4)  
WE  
tDW  
tDH  
High-Z  
Data in  
Data out  
Valid Data  
tOHZ(6)  
High-Z(8)  
TIMING WAVEFORM OF WRITE CYCLE(2) (OE=Low Fixed)  
tWC  
Address  
tWR(5)  
tAW  
tCW(3)  
CS  
tAS(4)  
tWP1(2)  
WE  
tDW  
tDH  
High-Z  
Data in  
Valid Data  
tWHZ(6)  
tOW  
(10)  
(9)  
High-Z(8)  
Data out  
Rev 4.0  
Ferruary 1998  
- 6 -  
PRELIMINARY  
KM681002A, KM681002AI  
CMOS SRAM  
TIMING WAVEFORM OF WRITE CYCLE(3) (CS = Controlled)  
tWC  
Address  
tAW  
tWR(5)  
tCW(3)  
CS  
tAS(4)  
tWP(2)  
WE  
tDH  
tDW  
High-Z  
High-Z  
High-Z  
Data in  
Data out  
Data Valid  
tLZ  
tWHZ(6)  
High-Z(8)  
NOTES(WRITE CYCLE)  
1. All write cycle timing is referenced from the last valid address to the first transition address.  
2. A write occurs during the overlap of a low CS and WE. A write begins at the latest transition CS going low and WE going low  
A write ends at the earliest transition CS going high or WE going high. tWP is measured from the beginning of write to the end of  
write.  
3. tCW is measured from the later of CS going low to end of write.  
4. tAS is measured from the address valid to the beginning of write.  
5. tWR is measured from the end of write to the address change. tWR applied in case a write ends as CS or WE going high.  
6. If OE, CS and WE are in the Read Mode during this period, the I/O pins are in the output low-Z state. Inputs of opposite phase  
of the output must not be applied because bus contention can occur.  
7. For common I/O applications, minimization or elimination of bus contention conditions is necessary during read and write cycle.  
8. If CS goes low simultaneously with WE going or after WE going low, the outputs remain high impedance state.  
9. Dout is the read data of the new address.  
10. When CS is low : I/O pins are in the output state. The input signals in the opposite phase leading to the output should not be  
applied.  
FUNCTIONAL DESCRIPTION  
CS  
H
L
WE  
X
OE  
X*  
H
Mode  
Not Select  
Output Disable  
Read  
I/O Pin  
High-Z  
High-Z  
DOUT  
Supply Current  
ISB, ISB1  
ICC  
H
L
H
L
ICC  
L
L
X
Write  
DIN  
ICC  
* NOTE : X means Don¢t Care.  
Rev 4.0  
Ferruary 1998  
- 7 -  
PRELIMINARY  
KM681002A, KM681002AI  
CMOS SRAM  
PACKAGE DIMENSIONS  
32-SOJ-400  
Units:millimeters/Inches  
#32  
#17  
9.40 ±0.25  
0.370 ±0.010  
11.18 ±0.12  
0.440 ±0.005  
+0.10  
-0.05  
0.20  
0.008 +0.004  
#1  
#16  
-0.002  
0.69  
MIN  
21.36  
0.841  
MAX  
0.027  
20.95 ±0.12  
0.825 ±0.005  
1.30  
(
(
)
)
0.051  
0.10  
0.004  
3.76  
0.148  
MAX  
MAX  
1.30  
0.051  
+0.10  
-0.05  
+0.10  
-0.05  
+0.004  
-0.002  
0.71  
0.43  
1.27  
0.050  
0.95  
0.0375  
(
)
0.028 +0.004  
0.017  
-0.002  
Units:millimeters/Inches  
32-TSOP2-400F  
0~8°  
0.25  
0.010  
(
)
#32  
#17  
0.45 ~0.75  
0.018 ~ 0.030  
11.76 ±0.20  
0.463 ±0.008  
0.50  
0.020  
(
)
#1  
#16  
+0.10  
0.15  
21.35  
0.841  
-0.05  
MAX  
+0.004  
-0.002  
0.006  
20.95 ±0.10  
0.825 ±0.004  
1.00 ±0.10  
0.10 MAX  
0.004 MAX  
1.20  
0.047  
MAX  
0.039 ±0.004  
1.27  
0.050  
0.95  
0.037  
0.05  
0.40 ±0.10  
(
)
MIN  
0.002  
0.016 ±0.004  
Rev 4.0  
Ferruary 1998  
- 8 -  
PRELIMINARY  
KM681002A, KM681002AI  
CMOS SRAM  
PACKAGE DIMENSIONS  
Rev 4.0  
Ferruary 1998  
- 9 -  

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