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KM684002AJE-1700 [SAMSUNG]

Standard SRAM, 512KX8, 17ns, CMOS, PDSO36, 0.400 INCH, PLASTIC, SOJ-36;
KM684002AJE-1700
型号： KM684002AJE-1700
厂家： SAMSUNG    SAMSUNG
描述：

Standard SRAM, 512KX8, 17ns, CMOS, PDSO36, 0.400 INCH, PLASTIC, SOJ-36

静态存储器 光电二极管
文件： 总8页 (文件大小：153K)
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PRELIMINARY  
KM684002A, KM684002AE, KM684002AI  
CMOS SRAM  
Document Title  
512Kx8 Bit High Speed Static RAM(5V Operating), Revolutionary Pin out.  
Operated at Commercial Temperature Range.  
Revision History  
RevNo.  
Rev. 0.0  
Rev. 0.5  
History  
Draft Data  
Remark  
Initial release with Design Target.  
Jun. 14th, 1996  
Sep. 16th, 1996  
Design Target  
Preliminary  
Release to Preliminary Data Sheet.  
0.1. Replace Design Target to Preliminary.  
0.2. Delete 12ns part but add 17ns part.  
0.3. Relax D.C and A.C parameters and insert new parameter(Icc1)  
with the test condition.  
0.3.1. Insert Icc1 parameter with the test condition as address is  
increased with binary count.  
0.3.2. Relax D.C and A.C parameters.  
Previous spec.  
(15/ - /20ns part)  
190/ - /180mA  
10/ - /12ns  
Relaxed spec.  
(15/17/20ns part)  
220/215/210mA  
12/13/14ns  
Items  
Icc  
tCW  
tAW  
10/ - /12ns  
12/13/14ns  
tWP(OE=H)  
tWP1(OE=L)  
tDW  
10/ - /12ns  
12/ - /14ns  
7/ - /9ns  
12/13/14ns  
15/17/20ns  
8/9/10ns  
Rev. 1.0  
Release to Final Data Sheet.  
Jun. 5th, 1997  
Final  
1.1. Delete Preliminary.  
1.2. Delete Icc1 parameter with the test condition.  
1.3. Update D.C parameters.  
Previous spec.  
Items  
Updated spec.  
(15/17/20ns part)  
170/165/160mA  
(15/17/20ns part)  
Icc  
220/215/210mA  
1.4. Add the test condition for VOH1 with Vcc=5V±5% at 25°C  
1.5. Add timing diagram to define tWP as ²(Timing Wave Form of  
Write Cycle(CS=Low fixed)²  
Rev. 2.0  
2.1 Add extended and industrial temperature range parts.  
Jun. 5th, 1997  
Final  
The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the  
specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions on the parameters of this device. If you have any ques-  
tions, please contact the SAMSUNG branch office near your office, call or contact Headquarters.  
Rev 2.0  
February 1998  
- 1 -  
PRELIMINARY  
CMOS SRAM  
KM684002A, KM684002AE, KM684002AI  
512K x 8 Bit High-Speed CMOS Static RAM  
FEATURES  
GENERAL DESCRIPTION  
• Fast Access Time 15,17,20ns(Max.)  
The KM684002A is a 4,194,304-bit high-speed Static Random  
Access Memory organized as 524,288 words by 8 bits. The  
KM684002A uses 8 common input and output lines and has an  
output enable pin which operates faster than address access  
time at read cycle. The device is fabricated using SAMSUNG¢s  
advanced CMOS process and designed for high-speed circuit  
technology. It is particularly well suited for use in high-density  
high-speed system applications. The KM684002A is packaged  
in a 400mil 36-pin plastic SOJ.  
• Low Power Dissipation  
Standby (TTL)  
: 50mA(Max.)  
(CMOS) : 10mA(Max.)  
Operating KM684002A - 15 : 170mA(Max.)  
KM684002A - 17 : 165mA(Max.)  
KM684002A - 20 : 160mA(Max.)  
• Single 5.0V±10% Power Supply  
• TTL Compatible Inputs and Outputs  
• I/O Compatible with 3.3V Device  
• Fully Static Operation  
- No Clock or Refresh required  
• Three State Outputs  
PIN CONFIGURATION(Top View)  
• Center Power/Ground Pin Configuration  
• Standard Pin Configuration  
KM684002AJ : 36-SOJ-400  
A0  
A1  
1
2
3
4
5
6
7
8
9
36 N.C  
35 A18  
34 A17  
33 A16  
32 A15  
31 OE  
30 I/O8  
29 I/O7  
28 Vss  
27 Vcc  
26 I/O6  
25 I/O5  
24 A14  
23 A13  
22 A12  
21 A11  
20 A10  
19 N.C  
A2  
ORDERING INFORMATION  
A3  
KM684002A-15/17/20  
KM684002AE-15/17/20  
KM684002AI-15/17/20  
Commercial Temp.  
A4  
Extended Temp.  
Industrial Temp.  
CS  
I/O1  
I/O2  
Vcc  
SOJ  
FUNCTIONAL BLOCK DIAGRAM  
Vss 10  
I/O3 11  
I/O4 12  
WE 13  
A5 14  
A6 15  
A7 16  
A8 17  
A9 18  
Clk Gen.  
Pre-Charge Circuit  
A0  
A1  
A2  
A3  
A4  
A5  
A6  
A7  
A8  
A9  
Memory Array  
1024 Rows  
512x8 Columns  
Data  
Cont.  
I/O Circuit  
Column Select  
I/O1~I/O8  
PIN FUNCTION  
Pin Name  
A0 - A18  
WE  
Pin Function  
CLK  
Gen.  
Address Inputs  
Write Enable  
Chip Select  
A10  
A12  
A11  
A14  
A13  
A16  
A18  
A15  
A17  
CS  
OE  
Output Enable  
Data Inputs/Outputs  
Power(+5.0V)  
Ground  
CS  
WE  
OE  
I/O1 ~ I/O8  
VCC  
VSS  
N.C  
No Connection  
Rev 2.0  
February 1998  
- 2 -  
PRELIMINARY  
CMOS SRAM  
KM684002A, KM684002AE, KM684002AI  
ABSOLUTE MAXIMUM RATINGS*  
Parameter  
Voltage on Any Pin Relative to VSS  
Voltage on VCC Supply Relative to VSS  
Power Dissipation  
Symbol  
VIN, VOUT  
VCC  
Rating  
-0.5 to 7.0  
-0.5 to 7.0  
1.0  
Unit  
V
V
PD  
W
Storage Temperature  
TSTG  
TA  
-65 to 150  
0 to 70  
°C  
°C  
°C  
°C  
Operating Temperature  
Commercial  
Extended  
Industrial  
TA  
-25 to 85  
-40 to 85  
TA  
* Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and  
functional operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied.  
Exposure to absolute maximum rating conditions for extended periods may affect reliability.  
RECOMMENDED DC OPERATING CONDITIONS(TA=0 to 70°C)  
Parameter  
Supply Voltage  
Symbol  
Min  
4.5  
0
Typ  
Max  
Unit  
V
VCC  
5.0  
5.5  
0
Ground  
VSS  
0
-
V
Input High Voltage  
Input Low Voltage  
VIH  
2.2  
-0.5*  
VCC+0.5**  
0.8  
V
VIL  
-
V
NOTE: The above parameters are also guaranteed at extended and industrial temperature ranges.  
* VIL(Min) = -2.0V a.c(Pulse Width £ 10ns) for I £ 20mA  
** VIH(Max) = VCC + 2.0V a.c (Pulse Width £ 10ns) for I £ 20mA  
DC AND OPERATING CHARACTERISTICS(TA=0 to 70°C, Vcc=5.0V±10%, unless otherwise specified)  
Parameter  
Input Leakage Current  
Output Leakage Current  
Symbol  
Test Conditions  
Min  
-2  
Max  
2
Unit  
mA  
ILI  
VIN=VSS to VCC  
ILO  
CS=VIH or OE=VIH or WE=VIL  
VOUT=VSS to VCC  
-2  
2
mA  
Operating Current  
ICC  
Min. Cycle, 100% Duty  
CS=VIL, VIN=VIH or VIL, IOUT=0mA  
15ns  
17ns  
20ns  
-
-
-
-
-
170  
165  
160  
50  
mA  
Standby Current  
ISB  
Min. Cycle, CS=VIH  
mA  
mA  
ISB1  
f=0MHz, CS³ VCC-0.2V,  
10  
VIN³ VCC-0.2V or VIN£0.2V  
Output Low Voltage Level  
Output High Voltage Level  
VOL  
VOH  
IOL=8mA  
-
2.4  
-
0.4  
-
V
V
IOH=-4mA  
IOH1=-100mA  
VOH1*  
3.95  
NOTE: The above parameters are also guaranteed at extended and industrial temperature ranges.  
* VCC=5.0V, Temp.=25°C  
CAPACITANCE*(TA=25°C, f=1.0MHz)  
Item  
Input/Output Capacitance  
Input Capacitance  
Symbol  
CI/O  
Test Conditions  
VI/O=0V  
MIN  
Max  
8
Unit  
-
-
pF  
pF  
VIN=0V  
CIN  
7
* NOTE : Capacitance is sampled and not 100% tested.  
Rev 2.0  
February 1998  
- 3 -  
PRELIMINARY  
KM684002A, KM684002AE, KM684002AI  
CMOS SRAM  
AC CHARACTERISTICS(TA=0 to 70°C, VCC=5.0V±10%, unless otherwise noted.)  
TEST CONDITIONS  
Parameter  
Value  
0V to 3V  
Input Pulse Levels  
Input Rise and Fall Times  
3ns  
1.5V  
Input and Output timing Reference Levels  
Output Loads  
See below  
NOTE: The above parameters are also guaranteed at extended and industrial temperature ranges.  
Output Loads(A)  
Output Loads(B)  
for tHZ, tLZ, tWHZ, tOW, tOLZ & tOHZ  
+5.0V  
+5.0V  
480W  
480W  
DOUT  
DOUT  
255W  
255W  
30pF*  
5pF*  
* Including Scope and Jig Capacitance  
READ CYCLE  
KM684002A-15  
Symbol  
KM684002A-17  
KM684002A-20  
Parameter  
Unit  
Min  
15  
-
Max  
Min  
17  
-
Max  
Min  
20  
-
Max  
Read Cycle Time  
tRC  
tAA  
-
15  
15  
7
-
17  
17  
8
-
20  
20  
9
ns  
ns  
ns  
ns  
ns  
Address Access Time  
Chip Select to Output  
tCO  
tOE  
tLZ  
-
-
-
Output Enable to Valid Output  
Chip Enable to Low-Z Output  
Output Enable to Low-Z Output  
Chip Disable to High-Z Output  
Output Disable to High-Z Output  
Output Hold from Address Change  
Chip Selection to Power Up Time  
Chip Selection to Power DownTime  
-
-
-
3
-
3
-
3
-
tOLZ  
tHZ  
0
-
0
-
0
-
ns  
ns  
0
7
0
8
0
9
tOHZ  
tOH  
tPU  
tPD  
0
7
0
8
0
9
ns  
ns  
ns  
ns  
3
-
3
-
3
-
0
-
0
-
0
-
-
15  
-
17  
-
20  
NOTE: The above parameters are also guaranteed at extended and industrial temperature ranges.  
Rev 2.0  
February 1998  
- 4 -  
PRELIMINARY  
CMOS SRAM  
KM684002A, KM684002AE, KM684002AI  
WRITE CYCLE  
KM684002A-15  
KM684002A-17  
KM684002A-20  
Parameter  
Symbol  
Unit  
Min  
15  
12  
0
Max  
Min  
17  
13  
0
Max  
Min  
20  
14  
0
Max  
Write Cycle Time  
tWC  
tCW  
tAS  
-
-
-
-
-
-
-
7
-
-
-
-
-
-
-
-
-
-
8
-
-
-
-
-
-
-
-
-
-
9
-
-
-
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
Chip Select to End of Write  
Address Set-up Time  
Address Valid to End of Write  
Write Pulse Width(OE High)  
Write Pulse Width(OE Low)  
Write Recovery Time  
tAW  
tWP  
tWP1  
tWR  
tWHZ  
tDW  
tDH  
12  
12  
15  
0
13  
13  
17  
0
14  
14  
20  
0
Write to Output High-Z  
0
0
0
Data to Write Time Overlap  
Data Hold from Write Time  
End Write to Output Low-Z  
8
9
10  
0
0
0
tOW  
3
3
3
NOTE: The above parameters are also guaranteed at extended and industrial temperature ranges.  
TIMMING DIAGRAMS  
TIMING WAVEFORM OF READ CYCLE(1) (Address Controlled, CS=OE=VIL, WE=VIH)  
tRC  
Address  
tAA  
tOH  
Valid Data  
Data Out  
Previous Valid Data  
TIMING WAVEFORM OF READ CYCLE(2) (WE=VIH)  
tRC  
Address  
tAA  
tHZ(3,4,5)  
tCO  
CS  
tOE  
tOHZ  
OE  
tOLZ  
tOH  
tLZ(4,5)  
Data out  
Valid Data  
tPU  
tPD  
ICC  
ISB  
VCC  
50%  
50%  
Current  
Rev 2.0  
February 1998  
- 5 -  
PRELIMINARY  
CMOS SRAM  
KM684002A, KM684002AE, KM684002AI  
NOTES(READ CYCLE)  
1. WE is high for read cycle.  
2. All read cycle timing is referenced from the last valid address to the first transition address.  
3. tHZ and tOHZ are defined as the time at which the outputs achieve the open circuit condition and are not referenced to VOH or  
VOL levels.  
4. At any given temperature and voltage condition, tHZ(Max.) is less than tLZ(Min.) both for a given device and from device to  
device.  
5. Transition is measured ±200mV from steady state voltage with Load(B). This parameter is sampled and not 100% tested.  
6. Device is continuously selected with CS=VIL.  
7. Address valid prior to coincident with CS transition low.  
8. For common I/O applications, minimization or elimination of bus contention conditions is necessary during read and write cycle.  
TIMING WAVEFORM OF WRITE CYCLE(1) (OE= Clock)  
tWC  
Address  
tWR(5)  
tAW  
OE  
tCW(3)  
CS  
tWP(2)  
tAS(4)  
WE  
tDW  
tDH  
High-Z  
Data in  
Data out  
Valid Data  
tOHZ(6)  
High-Z(8)  
TIMING WAVEFORM OF WRITE CYCLE(2) (OE=Low Fixed)  
tWC  
Address  
tWR(5)  
tAW  
tCW(3)  
CS  
tAS(4)  
tWP1(2)  
WE  
tDW  
tDH  
High-Z  
Data in  
Valid Data  
tWHZ(6)  
tOW  
(10)  
(9)  
High-Z(8)  
Data out  
Rev 2.0  
February 1998  
- 6 -  
PRELIMINARY  
KM684002A, KM684002AE, KM684002AI  
CMOS SRAM  
TIMING WAVEFORM OF WRITE CYCLE(3) (CS = Controlled)  
tWC  
Address  
tAW  
tWR(5)  
tCW(3)  
CS  
tAS(4)  
tWP(2)  
WE  
tDH  
tDW  
High-Z  
High-Z  
High-Z  
Data in  
Data out  
Valid Data  
tLZ  
tWHZ(6)  
High-Z(8)  
NOTES(WRITE CYCLE)  
1. All write cycle timing is referenced from the last valid address to the first transition address.  
2. A write occurs during the overlap of a low CS and WE. A write begins at the latest transition CS going low and WE going low ;  
A write ends at the earliest transition CS going high or WE going high. tWP is measured from the beginning of write to the end of  
write.  
3. tCW is measured from the later of CS going low to end of write.  
4. tAS is measured from the address valid to the beginning of write.  
5. tWR is measured from the end of write to the address change. tWR applied in case a write ends as CS or WE going high.  
6. If OE, CS and WE are in the Read Mode during this period, the I/O pins are in the output low-Z state. Inputs of opposite phase  
of the output must not be applied because bus contention can occur.  
7. For common I/O applications, minimization or elimination of bus contention conditions is necessary during read and write cycle.  
8. If CS goes low simultaneously with WE going or after WE going low, the outputs remain high impedance state.  
9. Dout is the read data of the new address.  
10. When CS is low : I/O pins are in the output state. The input signals in the opposite phase leading to the output should not be  
applied.  
FUNCTIONAL DESCRIPTION  
CS  
H
L
WE  
X
OE  
X*  
H
Mode  
Not Select  
Output Disable  
Read  
I/O Pin  
High-Z  
High-Z  
DOUT  
Supply Current  
ISB, ISB1  
ICC  
H
L
H
L
ICC  
L
L
X
Write  
DIN  
ICC  
* NOTE : X means Don¢t Care.  
Rev 2.0  
February 1998  
- 7 -  
PRELIMINARY  
CMOS SRAM  
KM684002A, KM684002AE, KM684002AI  
PACKAGE DIMENSIONS  
Units:millimeters/Inches  
36-SOJ-400  
#19  
#36  
11.18 ±0.12  
0.440 ±0.005  
9.40 ±0.25  
0.370 ±0.010  
+0.10  
-0.05  
0.20  
+0.004  
-0.002  
#1  
#18  
0.008  
0.69  
MIN  
0.027  
23.90  
MAX  
0.941  
23.50 ±0.12  
0.925 ±0.005  
1.19  
0.047  
1.27  
(
(
)
)
3.76  
0.148  
0.10  
0.004  
MAX  
MAX  
0.050  
+0.10  
-0.05  
0.43  
+0.10  
+0.004  
-0.002  
0.71  
0.028  
-0.05  
0.017  
0.95  
0.0375  
1.27  
0.050  
(
)
+0.004  
-0.002  
Rev 2.0  
February 1998  
- 8 -  

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