KM68FU1000ATGI-7_技术文档

KM68FU1000A Family

CMOS SRAM

Document Title

128Kx8 bit Super Low Power and Low Voltage CMOS Static RAM

Revision History

Revision No. History

Draft Data

Remark

0.0

0.1

1.0

Design target

November 3, 1998

January 9, 1999

February 25, 1999

Advance

Preliminary

Final

Revise

Finalize

- Change VDR : 1.0 to 1.5V

- Change IDR test condition : VCC=1.2 to 1.5V

The attached datasheets are provided by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserves the right to change the specifications and

products. SAMSUNG Electronics will answer to your questions. If you have any questions, please contact the SAMSUNG branch offices.

Revision 1.0

February 1999

KM68FU1000A Family

CMOS SRAM

128Kx8 bit Super Low Power and Low Voltage CMOS Static RAM

FEATURES

GENERAL DESCRIPTION

· Process Technology: Full CMOS

· Organization: 128K x8 bit

The KM68FU1000A families are fabricated by SAMSUNG¢s

advanced full CMOS process technology. The families support

industrial temperature range and have various package types

for user flexibility of system design. The families also support

low data retention voltage for battery back-up operation with low

data retention current.

· Power Supply Voltage: 2.7~3.3V

· Low Data Retention Voltage: 1.5V(Min)

· Three state output status and TTL Compatible

· Package Type: 32-TSOP1-0813.4F

48-FBGA-6.00x7.00

PRODUCT FAMILY

Power Dissipation

Product Family

Operating Temperature

Vcc Range

Speed

PKG Type

Standby

(ISB1, Typ.)

Operating

(ICC1, Max)

32-sTSOP1-F

48-FBGA

KM68FU1000A

Industrial(-40~85°C)

2.7~3.3V

70/100ns

0.5mA

4mA

FUNCTIONAL BLOCK DIAGRAM

PIN DESCRIPTION

A11

A9

1

32

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

OE

Clk gen.

Precharge circuit.

2

A10

CS1

I/O8

I/O7

I/O6

I/O5

I/O4

VSS

I/O3

I/O2

I/O1

A0

A8

3

A13

WE

CS2

A15

VCC

N.C

A16

A14

A12

A7

4

5

6

7

32-sTSOP

Type1-Forward

8

9

10

11

12

13

14

15

16

Memory array

1024 rows

128´ 8 columns

Row

select

A6

A1

A5

A2

A4

A3

1

2

3

4

5

6

A

0

A

1

CS

2

A

3

4

A

6

7

A8

B

C

D

E

F

I/O

5

6

A2

WE

NC

A

I/O

1

5

2

Data

cont

I/O Circuit

I/O1

I/O8

V

SS

CC

V

CC

SS

Column select

V

I/O

7

8

NC NC

I/O

15 I/O

13

3

4

Data

cont

OE CS

1

A

16

12

A

G

H

A9

A10

A

11

A

14

48-CSP - TOP VIEW

CS1

Name

Function

Name

Function

Control

logic

CS2

WE

CS1,CS2 Chip Select Inputs

I/O1~I/O8 Data Inputs/Outputs

OE

WE

Output Enable Input

Write Enable Input

Vcc

Vss

N.C.

Power

Ground

A0~A16 Address Inputs

No Connection

SAMSUNG ELECTRONICS CO., LTD. reserves the right to change products and specifications without notice.

Revision 1.0

February 1999

KM68FU1000A Family

CMOS SRAM

PRODUCT LIST

Industrial Temperature Products(-40~85°C)

Part Name

Function

KM68FU1000ATGI-7

KM68FU1000ATGI-10

32-sTSOP1 F, 70ns, 3.0V

32-sTSOP1 F, 100ns, 3.0V

KM68FU1000AFI-7

KM68FU1000AFI-10

48-FBGA with 48 ball, 70ns, 3.0V

48-FBGA with 48 ball, 100ns, 3.0V

FUNCTIONAL DESCRIPTION

CS1

CS2

OE

WE

I/O

Mode

Deselected

Output Disabled

Read

Power

Standby

Active

X¹⁾

L

X¹⁾

H

High-Z

Dout

X¹⁾

L

X¹⁾

H

X¹⁾

H

L

H

L

Active

X¹⁾

Din

Write

Active

1. X means don¢t care (Must be high or low states)

ABSOLUTE MAXIMUM RATINGS¹⁾

Item

Voltage on any pin relative to Vss

Voltage on Vcc supply relative to Vss

Power Dissipation

Symbol

VIN,VOUT

VCC

Ratings

-0.2 to 3.6V

-0.2 to 4.0V

1.0

Unit

V

PD

W

Storage temperature

TSTG

TA

-55 to 150

-40 to 85

°C

Operating Temperature

1. Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. Functional operation should be

restricted to recommended operating condition. Exposure to absolute maximum rating conditions for extended periods may affect reliability.

Revision 1.0

February 1999

KM68FU1000A Family

CMOS SRAM

RECOMMENDED DC OPERATING CONDITIONS¹⁾

Item

Symbol

Vcc

Min

2.7

0

Typ

Max

3.3

Unit

V

Supply voltage

Ground

3.0

Vss

0

-

0

V

Vcc+0.2²⁾

0.4

Input high voltage

Input low voltage

VIH

2.2

-0.2³⁾

V

VIL

-

V

Note :

1. TA=-40 to 85°C, otherwise specified

2. Overshoot: Vcc+2.0V in case of pulse width £20ns.

3. Undershoot: -2.0V in case of pulse width £20ns.

4. Overshoot and undershoot are sampled, not 100% tested.

CAPACITANCE¹⁾(f=1MHz, TA=25°C)

Item

Input capacitance

Symbol

CIN

Test Condition

Min

Max

8

Unit

pF

VIN=0V

VIO=0V

-

Input/Output capacitance

CIO

10

pF

1. Capacitance is sampled, not 100% tested

DC AND OPERATING CHARACTERISTICS

Item

Symbol

ILI

Test Conditions

Min Typ Max Unit

Input leakage current

VIN=Vss to Vcc

-1

-

1

2

4

mA

Output leakage current

Operating power supply current

ILO

CS1=VIH or CS2=VIL or OE=VIH or WE=VIL, VIO=Vss to Vcc

IIO=0mA, CS1=VIL, CS2=VIH, VIN=VIH or VIL

-1

-

ICC

-

mA

ICC1

ICC2

VOL

VOH

ISB

-

Cycle time=1ms, 100%duty, IIO=0mA, CS1£0.2V, CS2³ Vcc-0.2V, VIN£0.2V

Average operating current

Cycle time=Min, 100% duty, IIO=0mA, CS1=VIL, CS2=VIH, VIN=VIH or VIL

-

25 mA

Output low voltage

IOL=2.1mA

-

2.4

-

0.4

-

V

Output high voltage

Standby Current(TTL)

Standby Current(CMOS)

IOH=-1.0mA

CS1=VIH, CS2=VIL, Other inputs=VIH or VIL

CS1³ Vcc-0.2V, CS2³ Vcc-0.2V or CS2£0.2V, Other inputs=0~Vcc

-

0.3 mA

mA

5¹⁾

ISB1

-

0.5

1. Super low power product=1mA with special handling.

Revision 1.0

February 1999

KM68FU1000A Family

CMOS SRAM

3)

AC OPERATING CONDITIONS

VTM

TEST CONDITIONS(Test Load and Test Input/Output Reference)

Input pulse level: 0.2 to 2.2V

2)

R1

Input rising and falling time: 5ns

Input and output reference voltage: 1.5V

Output load (See right): CL= 100pF+1TTL

1)

2)

CL

R2

1. Including scope and jig capacitance

2. R1=3070W, R2=3150W

3. VTM =2.8V

AC CHARACTERISTICS (Vcc=2.7~3.3V, TA=-40 to 85°C)

Speed Bins

Parameter List

Symbol

Units

70ns

100ns

Min

70

-

Max

Min

100

-

Max

Read cycle time

tRC

tAA

-

70

35

-

ns

Address access time

100

Chip select to output

tCO1, tCO2

tOE

-

100

Output enable to valid output

Chip select to low-Z output

Output enable to low-Z output

Chip disable to high-Z output

Output disable to high-Z output

Output hold from address change

Write cycle time

-

50

-

Read

tLZ

10

5

10

5

tOLZ

tHZ

-

0

25

-

0

30

-

tOHZ

tOH

0

10

70

60

0

15

100

80

0

tWC

tCW

tAS

-

Chip select to end of write

Address set-up time

-

Address valid to end of write

Write pulse width

tAW

60

55

0

-

80

70

0

-

tWP

-

Write

Write recovery time

tWR

tWHZ

tDW

tDH

-

Write to output high-Z

0

25

-

0

30

-

Data to write time overlap

Data hold from write time

End write to output low-Z

30

0

40

0

-

tOW

5

-

5

-

DATA RETENTION CHARACTERISTICS

Item

Symbol

VDR

Test Condition

Min

1.5

-

Typ

Max

Unit

V

CS1³ Vcc-0.2V¹⁾

Vcc for data retention

Data retention current

Data retention set-up time

Recovery time

-

3.3

Vcc=1.5V, CS1³ Vcc-0.2V¹⁾

IDR

1

-

mA

tSDR

0

See data retention waveform

ms

tRDR

tRC

-

1. CS1³ Vcc-0.2V, CS2³ Vcc-0.2V(CS1 controlled) or CS2£0.2V(CS2 controlled)

Revision 1.0

February 1999

KM68FU1000A Family

CMOS SRAM

TIMMING DIAGRAMS

TIMING WAVEFORM OF READ CYCLE(1) (Address Controlled, CS1=OE=VIL, CS2=WE=VIH)

tRC

Address

tAA

tOH

Data Valid

Data Out

Previous Data Valid

TIMING WAVEFORM OF READ CYCLE(2) (WE=VIH)

tRC

Address

tOH

tAA

tCO1

CS1

tHZ(1,2)

CS2

tCO2

tOE

OE

tOHZ

tOLZ

tLZ

High-Z

Data out

Data Valid

NOTES (READ CYCLE)

1. tHZ and tOHZ are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage

levels.

2. At any given temperature and voltage condition, tHZ(Max.) is less than tLZ(Min.) both for a given device and from device to device

interconnection.

Revision 1.0

February 1999

KM68FU1000A Family

CMOS SRAM

TIMING WAVEFORM OF WRITE CYCLE(1) (WE Controlled)

tWC

Address

tCW(2)

tWR(4)

CS1

tAW

CS2

tCW(2)

tWP(1)

WE

tAS(3)

tDW

tDH

Data Valid

Data in

tWHZ

tOW

Data Undefined

Data out

TIMING WAVEFORM OF WRITE CYCLE(2) (CS¹Controlled)

tWC

Address

CS1

tCW(2)

tAS(3)

tWR(4)

tAW

CS2

tWP(1)

WE

tDW

tDH

Data in

Data out

Data Valid

High-Z

Revision 1.0

February 1999

KM68FU1000A Family

CMOS SRAM

TIMING WAVEFORM OF WRITE CYCLE(3) (CS2 Controlled)

tWC

Address

CS1

tAS(3)

tCW(2)

tWR(4)

tAW

CS2

tCW(2)

tWP(1)

WE

tDH

tDW

Data in

Data Valid

High-Z

Data out

NOTES (WRITE CYCLE)

1. A write occurs during the overlap of a low CS1, a high CS2 and a low WE. A write begins at the latest transition among CS1 goes low,

CS2 going high and WE going low : A write end at the earliest transition among CS1 going high, CS2 going low and WE going high,

tWP is measured from the begining of write to the end of write.

2. tCW is measured from the CS¹going low or CS2 going high to the end of write.

3. tAS is measured from the address valid to the beginning of write.

4. tWR is measured from the end of write to the address change. tWR1 applied in case a write ends as CS1 or WE going high tWR2 applied

in case a write ends as CS2 going to low.

DATA RETENTION WAVE FORM

CS1 controlled

Data Retention Mode

tSDR

tRDR

VCC

2.7V

2.2V

VDR

CS1³ VCC - 0.2V

CS1

GND

CS2 controlled

Data Retention Mode

VCC

2.7V

CS2

tSDR

tRDR

VDR

CS2£0.2V

0.4V

GND

Revision 1.0

February 1999

KM68FU1000A Family

CMOS SRAM

PACKAGE OUTLINE

Units: millimeters

48 BALL FINE PITCH BGA(0.75mm ball pitch)

Top View

B

Bottom View

B

A1 INDEX MARK

0.50

B1

0.50

6

5

4

3

2

1

A

B

C

D

E

F

#A1

G

H

B/2

Detail A

A

Side View

D

Y

C

Min

Typ

0.75

6.00

3.75

7.00

5.25

0.35

1.05

0.80

0.25

-

Max

-

A

B

-

Notes.

5.90

6.10

-

1. Bump counts: 48(8row x 6column)

2. Bump pitch : (x,y)=(0.75 x 0.75)(typ.)

3. All tolerence are +/-0.050 unless

otherwise specified.

B1

C

-

6.90

7.10

-

C1

D

-

4. Typ : Typical

0.30

0.40

1.20

-

5. Y is coplanarity: 0.08(Max)

E

-

E1

E2

Y

-

0.20

-

0.30

0.08

Revision 1.0

February 1999

KM68FU1000A Family

CMOS SRAM

PACKAGE DIMENSIONS

Units: millimeters(inches)

32 PIN THIN SMALL OUTLINE PACKAGE TYPE I (0813.4F)

13.40 ±0.20

0.528 ±0.008

+0.10

-0.05

+0.004

-0.002

0.20

0.008

#1

#32

0.25

0.010

(

)

0.50

0.0197

#16

#17

1.00 ±0.10

0.039 ±0.004

0.25

0.010

0.05

0.002

TYP

MIN

11.80 ±0.10

0.465 ±0.004

+0.10

-0.05

+0.004

-0.002

0.15

1.20

MAX

0.047

0.006

0~8¡Æ

0.50

0.020

0.45~0.75

0.018~0.030

(

)

Revision 1.0

February 1999


型号：	KM68FU1000ATGI-7
厂家：	SAMSUNG
描述：	Standard SRAM, 128KX8, 70ns, CMOS, PDSO32, 8 X 13.40 MM, STSOP1-32 静态存储器光电二极管
文件：	总10页 (文件大小：172K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

KM68FU1000ATGI-7 [SAMSUNG]

相关型号：

KM68FU1000G-8

KM68FU1000GI-7

KM68FU1000GI7H

KM68FU1000GI8H

KM68FU1000R7H

KM68FU1000R8H

KM68FU1000RI-7

KM68FU1000RI7H

KM68FU1000RI8H

KM68FU1000T-7

KM68FU1000T7H

KM68FU1000T8H