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KM68U4000BLG-8L0 [SAMSUNG]

Standard SRAM, 512KX8, 85ns, CMOS, PDSO32, 0.525 INCH, PLASTIC, SOP-32;
KM68U4000BLG-8L0
型号： KM68U4000BLG-8L0
厂家： SAMSUNG    SAMSUNG
描述：

Standard SRAM, 512KX8, 85ns, CMOS, PDSO32, 0.525 INCH, PLASTIC, SOP-32

静态存储器 光电二极管 内存集成电路
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KM68V4000B, KM68U4000B Family  
CMOS SRAM  
Document Title  
512Kx8 bit Low Power and Low Voltage CMOS Static RAM  
Revision History  
Revision No. History  
Draft Data  
Remark  
0.0  
Initial draft  
December 17, 1996  
Preliminary  
1.0  
Finalize  
Januarary 14, 1998  
Final  
- Change datasheet format  
- Erase low power part from product  
- Erase 70ns part from KM68U4000B family  
- Power dissipation Improved 0.7 to 1.0W  
- VIL(MAX) improved 0.4 to 0.6V.  
- ICC2 decreased 50 to 45mA.  
2.0  
Revised  
February 12, 1998  
Final  
- ICC1 decreased 20 to 25mA  
The attached datasheets are provided by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the specifications and  
products. SAMSUNG Electronics will answer to your questions about device. If you have any questions, please contact the SAMSUNG branch offices.  
Revision 2.0  
1
February 1998  
KM68V4000B, KM68U4000B Family  
CMOS SRAM  
512K´ 8 bit Low Power and Low Voltage CMOS Static RAM  
FEATURES  
GENERAL DESCRIPTION  
· Process Technology : TFT  
The KM68V4000B and KM68U4000B families are fabricated  
by SAMSUNG¢s advanced CMOS process technology. The  
families support various operating temperature range and have  
various package type for user flexibility of system design. The  
families also support low data retention voltage for battery  
back-up operation with low data retention current.  
· Organization : 512K´ 8  
· Power Supply Voltage  
KM68V4000B Family : 3.0~3.6V  
KM68U4000B Family : 2.7~3.3V  
· Low Data Retention Voltage : 2V(Min)  
· Three state output and TTL Compatible  
· Package Type : 32-SOP, 32-TSOP2-400F/R  
PRODUCT FAMILY  
Power Dissipation  
Product Family  
Operating Temperature Vcc Range  
Speed(ns)  
PKG Type  
Standby  
(ISB1, Max)  
Operating  
(ICC2)  
701)/851)/100  
851)/100  
KM68V4000BL-L  
KM68V4000BLI-L  
KM68U4000BL-L  
KM68U4000BLI-L  
Commercial(0~70°C)  
Industrial(-40~85°C)  
Commercial(0~70°C)  
Industrial(-40~85°C)  
3.0~3.6V  
3.0~3.6V  
2.7~3.3V  
2.7~3.3V  
15mA  
20mA  
15mA  
20mA  
32-SOP  
32-TSOP2-F/R  
45mA  
851)/100  
851)/100  
1. The paramerter is measured with 30pF test load.  
PIN DESCRIPTION  
FUNCTIONAL BLOCK DIAGRAM  
Clk gen.  
Precharge circuit.  
A18  
A16  
A14  
A12  
A7  
1
VCC  
A15  
A17  
WE  
A13  
A8  
VCC  
A15  
A17  
32  
31  
30  
29  
28  
27  
26  
25  
24  
23  
22  
21  
20  
19  
18  
17  
32  
31  
30  
29  
28  
27  
26  
25  
24  
23  
22  
21  
20  
19  
18  
17  
1
2
A18  
A16  
A14  
A12  
A7  
2
A18  
A16  
A14  
A12  
A7  
3
3
4
WE  
A13  
A8  
4
5
5
Memory array  
1024 rows  
512´ 8 columns  
Row  
select  
A6  
6
6
A6  
A5  
7
A9  
A9  
A6  
7
A5  
32-TSOP2  
Reverse  
32-SOP  
32-TSOP2  
Forward  
A5  
A11  
OE  
A11  
OE  
A4  
8
8
A4  
A4  
A3  
9
9
A3  
A1  
A10  
CS  
A10  
CS  
A2  
10  
11  
12  
13  
14  
15  
16  
10  
11  
12  
13  
14  
15  
16  
A2  
A0  
A1  
A1  
A0  
I/O8  
I/O7  
I/O6  
I/O5  
I/O4  
I/O8  
I/O7  
I/O6  
I/O5  
I/O4  
A0  
I/O1  
I/O8  
Data  
cont  
I/O Circuit  
I/O1  
I/O2  
I/O3  
VSS  
I/O1  
I/O2  
I/O3  
VSS  
Column select  
Data  
cont  
A9 A8 A13A17A15A10A11 A3 A2  
Name Function  
Name Function  
I/O1~I/O8 Data Inputs/Outputs  
CS  
OE  
WE  
Chip Select Input  
Output Enable Input  
Write Enable Input  
Vcc  
Vss  
Power  
CS  
Control  
logic  
WE  
OE  
Ground  
A0~A18 Address Inputs  
SAMSUNG ELECTRONICS CO., LTD. reserves the right to change products and specifications without notice.  
Revision 2.0  
February 1998  
2
KM68V4000B, KM68U4000B Family  
CMOS SRAM  
PRODUCT LIST  
Commercial Temp Products(0~70°C)  
Industrial Temp Products(-40~85°C)  
Part Name  
Function  
Part Name  
Function  
KM68V4000BLG-7L  
KM68V4000BLG-8L  
KM68V4000BLG-10L  
32-SOP, 70ns, 3.3V,LL  
32-SOP, 85ns, 3.3V,LL  
32-SOP, 100ns, 3.3V,LL  
KM68V4000BLGI-8L  
KM68V4000BLGI-10L  
32-SOP, 85ns, 3.3V,LL  
32-SOP, 100ns, 3.3V,LL  
KM68V4000BLTI-8L  
KM68V4000BLTI-10L  
KM68V4000BLRI-8L  
KM68V4000BLRI-10L  
32-TSOP2-F, 85ns, 3.3V,LL  
32-TSOP2-F, 100ns, 3.3V,LL  
32-TSOP2-R, 85ns, 3.3V,LL  
32-TSOP2-R, 100ns, 3.3V,LL  
KM68V4000BLT-7L  
KM68V4000BLT-8L  
KM68V4000BLT-10L  
KM68V4000BLR-7L  
KM68V4000BLR-8L  
KM68V4000BLR-10L  
32-TSOP2-F, 70ns, 3.3V,LL  
32-TSOP2-F, 85ns, 3.3V,LL  
32-TSOP2-F, 100ns, 3.3V,LL  
32-TSOP2-R, 70ns, 3.3V,LL  
32-TSOP2-R, 85ns, 3.3V,LL  
32-TSOP2-R, 100ns, 3.3V,LL  
KM68U4000BLGI-8L  
KM68U4000BLGI-10L  
32-SOP, 85ns, 3.0V,LL  
32-SOP, 100ns, 3.0V,LL  
KM68U4000BLG-8L  
KM68U4000BLG-10L  
32-SOP, 85ns, 3.0V,LL  
32-SOP, 100ns, 3.0V,LL  
KM68U4000BLTI-8L  
KM68U4000BLTI-10L  
KM68U4000BLRI-8L  
KM68U4000BLRI-10L  
32-TSOP2-F, 85ns, 3.0V,LL  
32-TSOP2-F, 100ns, 3.0V,LL  
32-TSOP2-R, 85ns, 3.0V,LL  
32-TSOP2-R, 100ns, 3.0V,LL  
KM68U4000BLT-8L  
KM68U4000BLT-10L  
KM68U4000BLR-8L  
KM68U4000BLR-10L  
32-TSOP2-F, 85ns, 3.0V,LL  
32-TSOP2-F, 100ns, 3.0V,LL  
32-TSOP2-R, 85ns, 3.0V,LL  
32-TSOP2-R, 100ns, 3.0V,LL  
Note : LL means Low Low standby current  
FUNCTIONAL DESCRIPTION  
CS  
H
L
OE  
WE  
I/O  
High-Z  
High-Z  
Dout  
Mode  
Deselected  
Output Disabled  
Read  
Power  
Standby  
Active  
X1)  
H
X1)  
H
L
L
H
L
Active  
X1)  
L
Din  
Write  
Active  
1. X means don¢t care (Must be in low or high state)  
ABSOLUTE MAXIMUM RATINGS1)  
Item  
Symbol  
Ratings  
Unit  
V
Remark  
Voltage on any pin relative to Vss  
Voltage on Vcc supply relative to Vss  
Power Dissipation  
VIN,VOUT  
VCC  
-0.5 to VCC+0.5  
-0.3 to 4.6  
1
-
V
-
PD  
W
-
Storage temperature  
TSTG  
-65 to 150  
0 to 70  
°C  
°C  
-
KM68V4000BL, KM68U4000BL  
Operating Temperature  
TA  
-40 to 85  
°C  
KM68V4000BLI, KM68U4000BLI  
-
Soldering temperature and time  
TSOLDER  
260°C, 10sec (Lead Only)  
-
1. Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. Functional operation should be  
restricted to recommended operating condition. Exposure to absolute maximum rating conditions for extended periods may affect reliability.  
Revision 2.0  
3
February 1998  
KM68V4000B, KM68U4000B Family  
CMOS SRAM  
RECOMMENDED DC OPERATING CONDITIONS1)  
Item  
Symbol  
Product  
Min  
Typ  
Max  
Unit  
KM68V4000B Family  
KM68U4000B Family  
3.0  
2.7  
3.3  
3.0  
3.6  
3.3  
Supply voltage  
Vcc  
V
Ground  
Vss  
VIH  
VIL  
All Family  
0
0
-
0
V
V
V
Vcc+0.32)  
0.6  
Input high voltage  
Input low voltage  
Note:  
KM68V4000B, KM68U4000B Family  
KM68V4000B, KM68U4000B Family  
2.2  
-0.33)  
-
1. Commercial Product : TA=0 to 70°C, otherwise specified  
Industrial Product : TA=-40 to 85°C, otherwise specified  
2. Overshoot : VCC+3.0V in case of pulse width £ 30ns  
3. Undershoot : -3.0V in case of pulse width £ 30ns  
4. Overshoot and undershoot are sampled, not 100% tested.  
CAPACITANCE1) (f=1MHz, TA=25°C)  
Item  
Input capacitance  
Symbol  
CIN  
Test Condition  
VIN=0V  
Min  
Max  
8
Unit  
pF  
-
-
Input/Output capacitance  
CIO  
VIO=0V  
10  
pF  
1. Capacitance is sampled, not 100% tested  
DC AND OPERATING CHARACTERISTICS  
Item  
Symbol  
ILI  
Min Typ Max Unit  
Test Conditions  
Input leakage current  
Output leakage current  
Operating power supply  
VIN=Vss to Vcc  
-1  
-
-
-
-
-
-
-
-
-
-
1
1
mA  
mA  
ILO  
CS=VIH or OE=VIH or WE=VIL VIO=Vss to Vcc  
IIO=0mA, CS=VIL, VIN=VIL or VIH, Read  
-1  
ICC  
-
10  
10  
25  
45  
0.4  
-
mA  
Read  
Write  
-
Cycle time=1ms, 100% duty, IIO=0mA, CS£0.2V  
VIN£0.2V or VIN³ Vcc-0.2V  
ICC1  
mA  
Average operating current  
-
ICC2  
VOL  
VOH  
ISB  
Cycle time=Min, 100% duty, IIO=0mA, CS=VIL, VIN=VIH or VIL  
IOL=2.1mA  
-
mA  
V
Output low voltage  
Output high voltage  
Standby Current(TTL)  
Standby  
-
2.2  
-
IOH=-1.0mA  
V
CS=VIH, Other inputs = VIL or VIH  
CS³ Vcc-0.2V, Other inputs=0~Vcc  
0.5  
mA  
mA  
151)  
ISB1  
-
1. Industrial product = 20mA  
Revision 2.0  
4
February 1998  
KM68V4000B, KM68U4000B Family  
CMOS SRAM  
AC OPERATING CONDITIONS  
TEST CONDITIONS( Test Load and Input/Output Reference)  
Input pulse level : 0.4 to 2.2V  
Input rising and falling time : 5ns  
1)  
CL  
Input and output reference voltage :1.5V  
Output load(see right) : CL=100pF+1TTL  
1)  
CL =30pF+1TTL  
1. Including scope and jig capacitance  
1. KM68V4000B-7, KM68V4000B-8 Family and KM68U4000B-8 Family  
AC CHARACTERISTICS (KM68V4000B Family : Vcc=3.0~3.6V, KM68U4000B Family : Vcc=2.7~3.3V  
Commercial product :TA=0 to 70°C, Industrial product : TA=-40 to 85°C)  
Speed Bins  
Parameter List  
Symbol  
Units  
70ns  
Max  
85ns  
Max  
100ns  
Min  
70  
-
Min  
85  
-
Min  
Max  
Read cycle time  
tRC  
tAA  
-
70  
70  
35  
-
-
85  
85  
40  
-
100  
-
-
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
Address access time  
100  
Chip select to output  
tCO  
tOE  
tLZ  
-
-
-
100  
Output enable to valid output  
Chip select to low-Z output  
Output enable to low-Z output  
Chip disable to high-Z output  
Output disable to high-Z output  
Output hold from address change  
Write cycle time  
-
-
-
50  
-
Read  
10  
5
10  
5
10  
5
tOLZ  
tHZ  
-
-
-
0
25  
25  
-
0
25  
25  
-
0
30  
30  
-
tOHZ  
tOH  
tWC  
tCW  
tAS  
0
0
0
10  
70  
60  
0
10  
85  
70  
0
15  
100  
80  
0
-
-
-
Chip select to end of write  
Address set-up time  
-
-
-
-
-
-
Address valid to end of write  
Write pulse width  
tAW  
tWP  
tWR  
tWHZ  
tDW  
tDH  
tOW  
60  
55  
0
-
70  
55  
0
-
80  
70  
0
-
-
-
-
Write  
Write recovery time  
-
-
-
Write to output high-Z  
0
25  
-
0
25  
-
0
30  
-
Data to write time overlap  
Data hold from write time  
End write to output low-Z  
30  
0
35  
0
40  
0
-
-
-
5
-
5
-
5
-
DATA RETENTION CHARACTERISTICS  
Item  
Symbol  
Test Condition  
Min  
Typ  
Max  
Unit  
V
Vcc for data retention  
Data retention current  
Data retention set-up time  
VDR  
CS³ Vcc-0.2V  
2.0  
-
-
0.5  
-
3.6  
151)  
-
IDR  
Vcc=3.0V, CS³ Vcc-0.2V  
mA  
tSDR  
0
See data retention waveform  
ms  
Recovery time  
tRDR  
5
-
-
1. Industrial product = 20mA  
Revision 2.0  
5
February 1998  
KM68V4000B, KM68U4000B Family  
CMOS SRAM  
TIMMING DIAGRAMS  
TIMING WAVEFORM OF READ CYCLE(1) (Address Controlled, CS=OE=VIL, WE=VIH)  
tRC  
Address  
tAA  
tOH  
Data Valid  
Data Out  
Previous Data Valid  
TIMING WAVEFORM OF READ CYCLE(2) (WE=VIH)  
tRC  
Address  
tOH  
tAA  
tCO1  
CS  
tHZ  
tOE  
OE  
tOHZ  
tOLZ  
tLZ  
High-Z  
Data out  
Data Valid  
NOTES (READ CYCLE)  
1. tHZ and tOHZ are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage  
levels.  
2. At any given temperature and voltage condition, tHZ(Max.) is less than tLZ(Min.) both for a given device and from device to device  
interconnection.  
Revision 2.0  
February 1998  
6
KM68V4000B, KM68U4000B Family  
CMOS SRAM  
TIMING WAVEFORM OF WRITE CYCLE(1) (WE Controlled)  
tWC  
Address  
tCW(2)  
tWR(4)  
CS  
tAW  
tWP(1)  
WE  
tAS(3)  
tDW  
tDH  
Data Valid  
Data in  
tWHZ  
tOW  
Data Undefined  
Data out  
TIMING WAVEFORM OF WRITE CYCLE(2) (CS Controlled)  
tWC  
Address  
tCW(2)  
tAS(3)  
tWR(4)  
CS  
tAW  
tWP(1)  
WE  
tDW  
tDH  
Data in  
Data Valid  
High-Z  
Data out  
High-Z  
NOTES (WRITE CYCLE)  
1. A write occurs during the overlap of a low CS and a low WE. A write begins at the latest transition among CS going Low and WE going  
low : A write end at the earliest transition among CS going high and WE going high, tWP is measured from the begining of write to the  
end of write.  
2. tCW is measured from the CS going low to end of write.  
3. tAS is measured from the address valid to the beginning of write.  
4. tWR is measured from the end of write to the address change. tWR applied in case a write ends as CS or WE going high.  
DATA RETENTION WAVE FORM  
CS controlled  
Data Retention Mode  
tSDR  
tRDR  
VCC  
3.0/2.7V  
2.2V  
VDR  
CS³ VCC - 0.2V  
CS  
GND  
Revision 2.0  
7
February 1998  
KM68V4000B, KM68U4000B Family  
CMOS SRAM  
Units : millimeter(inch)  
PACKAGE DIMENSIONS  
32 PIN PLASTIC SMALL OUTLINE PACKAGE (525mil)  
0~8°  
#32  
#17  
11.43±0.20  
0.450±0.008  
14.12±0.30  
0.556±0.012  
0.80±0.20  
0.031±0.008  
+0.10  
-0.05  
0.20  
#1  
#16  
2.74±0.20  
0.108±0.008  
+0.004  
20.87  
0.822  
0.008  
MAX  
-0.002  
3.00  
0.118  
MAX  
20.47±0.20  
0.806±0.008  
0.10 MAX  
0.004 MAX  
+0.100  
-0.050  
0.41  
0.71  
0.028  
1.27  
0.050  
+0.004  
-0.002  
(
)
0.05  
0.002  
0.016  
MIN  
Revision 2.0  
8
February 1998  
KM68V4000B, KM68U4000B Family  
PACKAGE DIMENSIONS  
CMOS SRAM  
Units : millimeter(inch)  
32 PIN THIN SMALL OUTLINE PACKAGE TYPE II (400F)  
0~8°  
0.25  
0.010  
(
)
#32  
#17  
0.45~0.75  
0.018 ~ 0.030  
11.76±0.20  
0.463±0.008  
#1  
#16  
0.50  
0.020  
(
)
+0.10  
-0.05  
+0.004  
-0.002  
0.15  
21.35  
0.841  
1.00±0.10  
0.039±0.004  
MAX  
0.006  
1.20  
0.047  
20.95±0.10  
0.825±0.004  
MAX  
0.10 MAX  
0.004 MAX  
0.05  
0.002  
MIN  
1.27  
0.050  
0.95  
0.037  
0.40±0.10  
0.016±0.004  
(
)
32 PIN THIN SMALL OUTLINE PACKAGE TYPE II (400R)  
0~8°  
0.25  
0.010  
(
)
#1  
#16  
0.45 ~0.75  
0.018 ~ 0.030  
11.76±0.20  
0.463±0.008  
#32  
#17  
0.50  
0.020  
(
)
+0.10  
-0.05  
+0.004  
-0.002  
0.15  
21.35  
0.841  
1.00±0.10  
0.039±0.004  
MAX  
0.006  
1.20  
0.047  
20.95±0.10  
0.825±0.004  
MAX  
0.10 MAX  
0.004 MAX  
1.27  
0.050  
0.95  
0.037  
0.05  
0.002  
0.40±0.10  
0.016±0.004  
(
)
MIN  
Revision 2.0  
9
February 1998  

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KM68U4000CLGI-10L

 Standard SRAM, 512KX8, 100ns, CMOS, PDSO32, 0.525 INCH, PLASTIC, SOP-32
SAMSUNG
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