KM718B90J-10 [SAMSUNG]
Cache SRAM, 64KX18, 10ns, BICMOS, PQCC52, PLASTIC, LCC-52;
| 型号： | KM718B90J-10 |
| 厂家： | 
SAMSUNG |
| 描述： | Cache SRAM, 64KX18, 10ns, BICMOS, PQCC52, PLASTIC, LCC-52 信息通信管理 静态存储器 |
| 文件： | 总12页 (文件大小：291K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PRELIMINARY
64Kx18 Synchronous SRAM
KM718B90
Document Title
64Kx18-Bit Synchronous Burst SRAM, 5V Power
Datasheets for 52PLCC
Revision History
Rev.No.
History
Draft Date
Remark
Rev. 1.0
- Final specification release
Final
- Change specification format.
Final
Rev. 1.1
April, 1997
No change was made in parameters.
The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to
change the specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions on the parameters of this
device. If you have any questions, please contact the SAMSUNG branch office near your office, call or contact Headquarters.
April 1997
- 1 -
Rev 1.1
PRELIMINARY
64Kx18 Synchronous SRAM
KM718B90
64Kx18-Bit Synchronous Burst SRAM
FEATURES
GENERAL DESCRIPTION
¡ Ü
Synchronous Operation.
On-Chip Address Counter.
Self-Timed Write Cycle.
On-Chip Address and Control Registers.
Single 5V±5% Power Supply.
Byte Writable Function.
Asynchronous Output Enable Control.
ADSP, ADSC, ADV Burst Control Pins.
The KM718B90 is a 1,179,648 bits Synchronous Static Random
Access Memory designed to support 66MHz of Intel secondary
caches.
It is organized as 65,536 words of 18bits. And it integrates
address and control registers, a 2-bit burst address counter and
high output drive circuitry onto a single integrated circuit for
reduced components counts implementation of high perfor-
mance cache RAM applications.
¡ Ü
¡ Ü
¡ Ü
¡ Ü
¡ Ü
¡ Ü
¡ Ü
¡ Ü
TTL-Level Three-State Output.
Write cycles are internally self-timed and synchronous.
The self-timed write feature eliminates complex off chip write
pulse shaping logic, simplifying the cache design and further
reducing the component count.
¡ Ü
3.3V I/O Compatible.
52-Pin PLCC Package.
¡ Ü
Burst cycle can be initiated with either the address status pro-
cessor(ADSP) or address status cache controller(ADSC) inputs.
Subsequent burst addresses are generated internally in the sys-
tem¢s burst sequence and are controlled by the burst address
advance(ADV) input.
FAST ACCESS TIMES
Parameter
Cycle Time
Symbol -8 -9 -10 -11 Unit
tCYC
tCD
15 15 17 20
ns
ns
ns
Clock Access Time
8
5
9
5
10 11
ZZ pin controls Power Down State and reduces Stand-by cur-
rent regardless of CLK.
Output Enable Access
tOE
5
6
The KM718B90 is implemented with SAMSUNG¢s high perfor-
mance BiCMOS technology and is available in a 52pin PLCC
package. Multiple power and ground pins are utilized to mini-
mize ground bounce.
PIN CONFIGURATION(TOP VIEW)
PIN NAME
Pin Name
A0 - A15
K
Pin Function
Address Inputs
7
6 5 4 3 2 1 52 51 50 49 48 47
Clock
I/O9
I/O10
VCC
I/O8
46
45
44
43
42
41
40
39
38
37
36
35
34
8
9
LW, UW
CS
Write Enable
Chip Selects
I/O7
I/O6
VCC
VSS
I/O5
I/O4
I/O3
I/O2
VSS
VCC
I/O1
I/O0
10
11
12
13
14
15
16
17
18
19
20
VSS
OE
Output Enable
Burst Address Advance
Address Status
Data Inputs/Outputs
+5V Power Supple
Ground
I/O11
I/O12
I/O13
I/O14
VSS
ADV
52-PLCC-SQ
ADSP, ADSC
I/O0~I/O17
VCC
VCC
I/O15
I/O16
I/O17
VSS
21 22 23 24 25 26 27 28 29 30 31 32 33
April 1997
Rev 1.1
- 2 -
PRELIMINARY
64Kx18 Synchronous SRAM
KM718B90
LOGIC BLOCK DIAGRAM
ADV
K
ADSC
64Kx18
MEMORY
ARRAY
BURST CONTROL
LOGIC
BURST
ADDRESS
COUNTER
A¢0~A¢1
ADSP
A0 ~ A1
A2~A15
ADDRESS
REGISTER
A0~A15
DATA-IN
REGISTER
CS
UW
LW
OUTPUT
BUFFER
CONTROL
LOGIC
OE
I/O0 ~ I/O17
FUNCTION DESCRIPTION
The KM718B90 is a synchronous SRAM designed to support the burst address accessing sequence of the Power microprocessor. All
inputs(with the exception of OE) are sampled on rising clock edges. The start and duration of the burst access is controlled by ADSP and
ADSC. The accesses are enabled with the chip select signals and output enable. Wait states are inserted into the access with ADV.
Read cycles are initiated with ADSP(regardless of LW, UW and ADSC) using the new external address clocked into the on-chip address
register whenever ADSP is sample low, The chip selects are sampled active, and the output buffer is enabled with OE, ADV is ignored
on the clock edge that samples ADSP asserted, but is sampled on the next and subsequent clock edges. The address is increased inter-
nally for the next access of the burst when LW, UW is sampled HIGH and ADV is sampled low.
Write cycles are performed by disabling the output buffers with OE and asserting LW, UW. LW, UW is ignored on the clock edge that
sampled ADSP low, but is sampled on the next and subsequent clock edges. The output buffers are disabled when LW, UW is sampled
low (regardless of OE). Data is clocked into the input register when LW, UW is sampled low. The address increases internally to the next
address of burst, if both LW, UW and ADV are sampled Low. Individual byte write cycles are performed sampling low only one byte write
enable signals(LW or LU)and LW controls I/O0~I/O7 and UW controls I/O8~I/O17.
Read or write cycles (depending on LW, LU)may also be initiated with ADSC, instead of ADSP. The differences between cycles initiated
with ADSC and ADSP are as follows;
ADSP must be sampled high when ADSC is sampled low to initiate a cycle with ADSC.
LW, UW is sampled on the same clock edge that sampled ADSC low(and ADSP high).
Addresses are generated for the burst accesses as shown below. The starting point of the burst sequence is provided by the external
address. The burst address counter wraps around to its initial state upon completion.
BURST SEQUENCE TABLE
(Linear Burst)
Case 4
Case 1
Case 2
Case 3
A1
A0
A1
A0
A1
A0
A1
A0
First Address
0
0
1
1
0
1
0
1
0
1
1
0
1
0
1
0
1
1
0
0
0
1
0
1
1
0
0
1
1
0
1
0
Fourth Address
April 1997
Rev 1.1
- 3 -
PRELIMINARY
64Kx18 Synchronous SRAM
KM718B90
TRUTH TABLES
SYNCHRONOUS TRUTH TABLE(See Notes 1 and 2)
CS
H
H
L
ADSP ADSC
ADV
X
LW/UW
K
•
Address Accessed
Operation
L
X
L
X
L
X
X
X
H
H
H
H
L
N/A
Not Selected
X
•
N/A
Not Selected
X
L
X
•
External Address
External Address
Next Address
Current Address
External Address
Next Address
Current Address
Begin Burst Read Cycle
Begin Burst Read Cycle
Continue Burst Read Cycle
Suspend Burst Read Cycle
Begin Burst Write Cycle
Continue Burst Write Cycle
Suspend Burst Write Cycle
L
H
H
H
H
H
H
X
•
X
X
L
H
H
L
L
•
H
•
X
•
X
X
H
H
L
•
H
L
•
NOTE1 : X means "Don¢t Care".
NOTE2 : The rising edge of clock is symbolized by • .
ASYNCHRONOUS TRUTH TABLE(See Notes 1 and 2)
OE
L
Operation
Read I/O0~I/O17
H
Output High-Z
X
Not Selected, Outputs High-Z
NOTE1 : X means "Don¢t Care".
NOTE2 : For write cycles that follow read cycles, the output buffers must be disabled with OE, otherwise data bus contention w ill occur.
ABSOLUTE MAXIMUM RATING*
Parameter
Voltage on VCC Supply Relative to VSS
Voltage on Any Other Pin Relative to VSS
Power Dissipation
Symbol
VCC
Rating
-0.5 to 7.0
-0.5 to 7.0
1.2
Unit
V
VIN
V
PD
W
Storage Temperature
TSTG
TOPR
TBIAS
-65 to 150
0 to 70
°C
°C
°C
Operating Temperature
Storage Temperature Range Under Bias
-10 to 85
*NOTE : Stresses greater than those listed under "Absolute Maximum Rating" may cause permanent damage to the device. This is a s tress rating only
and functional operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not
implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
April 1997
- 4 -
Rev 1.1
PRELIMINARY
64Kx18 Synchronous SRAM
KM718B90
OPERATING CONDITIONS(0°C£ TA £ 70°C)
Parameter
Supply Voltage
Ground
Symbol
Min
4.75
0
Typ.
5.0
0
Max
5.25
0
Unit
V
VCC
VSS
V
CAPACITANCE*(TA=25°C, f=1MHz)
Parameter
Symbol
Test Condition
VIN=0V
Min
Max
5
Unit
pF
Input Capacitance
CIN
-
-
Output Capacitance
COUT
VOUT=0V
8
pF
*NOTE : Sampled not 100% tested.
TEST CONDITIONS(TA=0 to 70°C, VDD=5V±5%, unless otherwise specified)
Parameter
Input Pulse Level
Value
0 to 3V
2ns
Input Rise and Fall Time(Measured at 0.3V and 2.7V)
Input and Output Timing Reference Levels
Output Load
1.5V
See Fig. 1
DC ELECTRICAL CHARACTERISTICS(TA=0 to 70°C, VDD=5V±5%)
Parameter
Input Leakage Current
Output Leakage Current
Symbol
Test Conditions
VDD=Max ; VIN=VSS to VCC
Output Disabled
Min
Max
+2
Unit
IIL
-2
-2
-
mA
mA
IOL
+2
15ns
17ns
20ns
270
260
250
VCC=Max IOUT=0mA
Cycle Time³ tCYC min
Operating Current
ICC
mA
-
-
Device deselected, IOUT=0mA, Min Cycle All
Inputs=VIH and VIL, VIH³ 3V and VIL=0V
Standby Current
ISB
-
90
mA
Output Low Voltage
Output High Voltage
Input Low Voltage
Input High Voltage
VOL
VOH
VIL
IOL = 8.0mA
IOH = -4.0mA
-
0.4
3.3
V
V
V
V
2.4
-0.5*
2.2
0.8
VIH
Vcc+5.5
* VIL(Min) = -3.0(Pulse Width£20ns)
April 1997
Rev 1.1
- 5 -
PRELIMINARY
64Kx18 Synchronous SRAM
KM718B90
AC TIMING CHARACTERISTICS(TA=0 to 70°C, VCC=5V±5%)
KM718B90-8
KM718B90-9
KM718B90-10
KM718B90-11
Parameter
Symbol
Unit
Min
Max
Min
Max
Min
Max
Min
Max
Cycle Time
tCYC
tCD
15
-
-
8
5
-
15
-
-
9
5
-
17
-
-
10
5
-
20
-
-
11
6
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Clock Access Time
Output Enable to Data Valid
Clock High to Output Low-Z
Output Hold from Clock High
Output Enable Low to Output Low-Z
Output Enable High to Output High-Z
Clock High to Output High-Z
Clock High Pulse Width
tOE
-
-
-
-
tLZC
tOH
6
6
6
6
3
-
3
-
3
-
3
-
tLZOE
tHZOE
tHZC
tCH
0
-
0
-
0
-
0
-
2
5
6
-
2
5
6
-
2
5
6
-
2
5
6
-
-
-
-
-
5
5
5
6
Clock Low Pulse Width
tCL
5
-
5
-
5
-
6
-
Address Setup to Clock High
Address Status Setup to Clock High
Data Setup to Clock High
tAS
2.5
2.5
2.5
2.5
2.5
2.5
0.5
0.5
0.5
0.5
0.5
0.5
-
2.5
2.5
2.5
2.5
2.5
2.5
0.5
0.5
0.5
0.5
0.5
0.5
-
2.5
2.5
2.5
2.5
2.5
2.5
0.5
0.5
0.5
0.5
0.5
0.5
-
2.5
2.5
2.5
2.5
2.5
2.5
0.5
0.5
0.5
0.5
0.5
0.5
-
tSS
-
-
-
-
tDS
-
-
-
-
Write Setup to Clock High
tWS
-
-
-
-
Address/Advance Setup to Clock
Chip Select Setup to Clock High
Address Hold from Clock High
Address Status Hold from Clock High
Data Hold from Clock High
tADVS
tCSS
tAH
-
-
-
-
-
-
-
-
-
-
-
-
tSH
-
-
-
-
tDH
-
-
-
-
Write Hold from Clock High
Address Advance Hold from Clock
Chip Select Hold from Clock High
tWH
tADVH
tCSH
-
-
-
-
-
-
-
-
-
-
-
-
NOTE : 1. All address inputs must meet the specified setup and hold times for all rising clock edges whenever ADSC and/or ADSP i s sampled low and
CS is sampled low. All other synchronous inputs must meet the specified setup and hold times whenever this device is chip select ed. Both
chip selects must be active whenever ADSC or ADSP is sampled low in order for this device to remain enabled.
Output Load(A)
Output Load(B)
(for tLZC, tLZOE, tHZOE& tHZC)
Dout
+5V
480W
Dout
Z0=50W
255W
RL=50W
VL=1.5V
* Including Scope and Jig Capacitance
5pF*
Fig. 1
April 1997
Rev 1.1
- 6 -
PRELIMINARY
64Kx18 Synchronous SRAM
KM718B90
April 1997
Rev 1.1
- 7 -
PRELIMINARY
64Kx18 Synchronous SRAM
KM718B90
April 1997
Rev 1.1
- 8 -
PRELIMINARY
64Kx18 Synchronous SRAM
KM718B90
April 1997
Rev 1.1
- 9 -
PRELIMINARY
64Kx18 Synchronous SRAM
KM718B90
April 1997
Rev 1.1
- 10 -
PRELIMINARY
64Kx18 Synchronous SRAM
KM718B90
April 1997
Rev 1.1
- 11 -
PRELIMINARY
64Kx18 Synchronous SRAM
KM718B90
April 1997
Rev 1.1
- 12 -
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