KM718S949H-67_技术文档

KM736S849

KM718S949

256Kx36 & 512Kx18 Pipelined NtRAM^TM

Document Title

256Kx36 & 512Kx18-Bit Pipelined NtRAM^TM

Revision History

History

Rev.No.

Draft Date

Remark

1. Initial document.

0.0

September. 1997

Preliminary

1. Changed speed bin from 167MHz to 150MHz

2. Changed DC Parameters;

0.1

November. 1997

Preliminary

ICC : from 400mA to 450mA , ISB : from 60mA to 20mA

ISB2 : from 50mA to 85mA

1. Changed speed bin from 150MHz to 167MHz

2. Changed Power from 3.3V to 2.5V

0.2

March. 11. 1998

Preliminary

3. Changed N.C pins to Power and ZZ Pin #14, #16, #64, #66

4. Changed some control pin names.

from CEN to CKE, from BWEx to BWx

5. Modify absolute maximum ratings

VDD ; from 4.0V to 3.6V, VIN ; from 4.6V to 3.6V

6. Changed DC parameters

ISB ; from 20mA to 80mA, ISB2 ; from 85mA to 10mA

VOL ; from 0.4V to 0.2V, VOH ; from 2.4V to 2.0V

VIL ; from 0.8V to 0.7V, VIH ; from 2.0V to 1.7V

7. ADD the sleep mode timing and characteristics

CKE controlled timing and CS controlled timing

1. Removed speed bin 167MHz

0.3

April. 11. 1998

Preliminary

2.Changed AC parameters

tHZOE ; from 4.0 to 3.5 , tHZC;from 4.0 to 3.5 at -75

tHZOE ; from 5.0 to 3.5 , tHZC;from 5.0 to 3.5 , tCL/H; 4.0 to 3.0 at -10

3.Modify Sleep Mode Waveform.

Changed Sleep Mode Electrical Characteristics .

tPDS ;from Max 2cycle to Min 2cycle

tPUS ; from Max 2cycle to Min 2cycle

1.Modify from ADV to ADV at timing.

0.4

0.5

June. 02. 1998

Aug. 19. 1998

Preliminary

2.ADD the Trade Mark( NtRAM^TM

)

1. Changed DC parameters

ISB1; from 10mA to 20mA, ISB2 ; from 10mA to 20mA

1. Changed tCD,tOE from 4.0ns to 4.2ns at -75.

0.6

0.7

Sep. 28. 1998

Nov. 10. 1998

Preliminary

1. Changed DC condition at Icc and parameters

ICC ; from 420mA to 320mA at -67 , from 370mA to 300mA at -75

from 300mA to 250mA at -10.

ISB ; from 70mA to 60mA at -67 , from 60mA to 50mA at -75

from 50mA to 40mA at -10.

1.Changed VOL Max value from 0.2V to 0.4V .

1. Add 119BGA(7x17 Ball Grid Array Package) .

1. Final spec release

0.8

0.9

1.0

2.0

Dec. 23. 1998

Mar. 03. 1999

April. 01. 1999

Oct. 30. 1999

Preliminary

Final

1. Add tCYC 167Mhz.

Final

The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the

specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions on the parameters of this device. If you have any ques-

tions, please contact the SAMSUNG branch office near your office, call or contact Headquarters.

- 1 -

November 1999

Rev 3.0

KM736S849

KM718S949

256Kx36 & 512Kx18 Pipelined NtRAM^TM

Document Title

256Kx36 & 512Kx18-Bit Pipelined NtRAM^TM

Revision History

History

Rev.No.

Draft Date

Remark

1. Remove 119BGA package .

3.0

Nov. 19. 1999

Final

The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the

specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions on the parameters of this device. If you have any ques-

tions, please contact the SAMSUNG branch office near your office, call or contact Headquarters.

- 2 -

November 1999

Rev 3.0

KM736S849

KM718S949

256Kx36 & 512Kx18 Pipelined NtRAM^TM

256Kx36 & 512Kx18-Bit Pipelined NtRAM^TM

FEATURES

GENERAL DESCRIPTION

• 2.5V ±5% Power Supply.

The KM736S849 and KM718S949 are 9,437,184 bits Synchro-

• Byte Writable Function.

nous Static SRAMs.

• Enable clock and suspend operation.

• Single READ/WRITE control pin.

• Self-Timed Write Cycle.

• Three Chip Enable for simple depth expansion with no data

contention .

• A interleaved burst or a linear burst mode.

• Asynchronous output enable control.

• Power Down mode.

• TTL-Level Three-State Outputs.

•100-TQFP-1420A .

The NtRAM^TM, or No Turnaround Random Access Memory uti-

lizes all the bandwidth in any combination of operating cycles.

Address, data inputs, and all control signals except output

enable and linear burst order are synchronized to input clock.

Burst order control must be tied "High or Low".

Asynchronous inputs include the sleep mode enable(ZZ).

Output Enable controls the outputs at any given time.

Write cycles are internally self-timed and initiated by the rising

edge of the clock input. This feature eliminates complex off-chip

write pulse generation

and provides increased timing flexibility for incoming signals.

For read cycles, pipelined SRAM output data is temporarily

stored by an edge triggered output register and then released

to the output buffers at the next rising edge of clock.

The KM736S849 and KM718S949 are implemented with SAM-

SUNG¢s high performance CMOS technology and is available

in 100pin TQFP packages. Multiple power and ground pins

minimize ground bounce.

FAST ACCESS TIMES

PARAMETER

Cycle Time

Symbol -60 -67 -75 -10 Unit

tCYC

tCD

6.0 6.7 7.5 10 ns

3.5 3.8 4.2 5.0 ns

Clock Access Time

Output Enable Access Time

tOE

LOGIC BLOCK DIAGRAM

LBO

BURST

ADDRESS

COUNTER

A¢0~A¢1

A [0:17]or

A [0:18]

A0~A1

256Kx36 , 512Kx18

MEMORY

ADDRESS

REGISTER

A2~A17 or A2~A18

ARRAY

WRITE

ADDRESS

REGISTER

DATA-IN

ADDRESS

CLK

K

REGISTER

CKE

DATA-IN

REGISTER

CS1

CS2

ADV

WE

CONTROL

LOGIC

OUTPUT

K

BWx

(x=a,b,c,d or a,b)

REGISTER

BUFFER

OE

ZZ

36 or 18

DQa0 ~ DQd7 or DQa0 ~ DQb8

DQPa ~ DQPd

NtRAM^TMand No Turnaround Random Access Memory are trademarks of Samsung,

and its architecture and functionalities are supported by NEC and Toshiba.

- 3 -

November 1999

Rev 3.0

KM736S849

KM718S949

256Kx36 & 512Kx18 Pipelined NtRAM^TM

PIN CONFIGURATION(TOP VIEW)

80

79

78

77

76

75

74

73

72

71

70

69

68

67

66

65

64

63

62

61

60

59

58

57

56

55

54

53

52

51

DQPb

DQb7

DQb6

VDDQ

VSSQ

DQb5

DQb4

DQb3

DQb2

VSSQ

VDDQ

DQb1

DQb0

VSS

DQPc

DQc0

DQc1

VDDQ

VSSQ

DQc2

DQc3

DQc4

DQc5

VSSQ

VDDQ

DQc6

DQc7

VDD

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

100 Pin TQFP

VDD

ZZ

VDD

VSS

(20mm x 14mm)

DQa7

DQa6

VDDQ

VSSQ

DQa5

DQa4

DQa3

DQa2

VSSQ

VDDQ

DQa1

DQa0

DQPa

DQd0

DQd1

VDDQ

VSSQ

DQd2

DQd3

DQd4

DQd5

VSSQ

VDDQ

DQd6

DQd7

DQPd

KM736S849(256Kx36)

PIN NAME

SYMBOL

PIN NAME

TQFP PIN NO.

SYMBOL

PIN NAME

TQFP PIN NO.

A0 - A17

Address Inputs

32,33,34,35,36,37,

VDD

Power Supply(+2.5V) 14,15,16,41,65,66,91

44,45,46,47,48,49,

VSS

Ground

17,40,67,90

50,81,82,83,99,100

N.C.

No Connect

38,39,42,43,84

ADV

WE

Address Advance/Load

Read/Write Control Input

Clock

Clock Enable

Chip Select

Byte Write Inputs

Output Enable

Power Sleep Mode

Burst Mode Control

85

88

89

87

98

97

92

DQa0~a7

DQb0~b7

DQc0~c7

DQd0~d7

DQPa~Pd

Data Inputs/Outputs

52,53,56,57,58,59,62,63

68,69,72,73,74,75,78,79

2,3,6,7,8,9,12,13

18,19,22,23,24,25,28,29

51,80,1,30

CLK

CKE

CS1

CS2

BWx

OE

93,94,95,96

VDDQ

VSSQ

Output Power Supply 4,11,20,27,54,61,70,77

(+2.5V)

Output Ground

86

64

31

ZZ

LBO

5,10,21,26,55,60,71,76

Notes : 1. The pin 84 is reserved for address bit for the 16Mb NtRAM.

2. A0 and A1 are the two least significant bits(LSB) of the address field and set the internal burst counter if burst is desired.

- 4 -

November 1999

Rev 3.0

KM736S849

KM718S949

256Kx36 & 512Kx18 Pipelined NtRAM^TM

PIN CONFIGURATION(TOP VIEW)

80

79

78

77

76

75

74

73

72

71

70

69

68

67

66

65

64

63

62

61

60

59

58

57

56

55

54

53

52

51

A10

N.C.

VDDQ

VSSQ

N.C.

DQb8

DQb7

VSSQ

VDDQ

DQb6

DQb5

VDD

1

2

3

4

5

6

7

8

N.C.

VDDQ

VSSQ

N.C.

DQa0

DQa1

DQa2

VSSQ

VDDQ

DQa3

DQa4

VSS

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

100 Pin TQFP

VDD

ZZ

VDD

VSS

(20mm x 14mm)

DQa5

DQa6

VDDQ

VSSQ

DQa7

DQa8

N.C.

VSSQ

VDDQ

N.C.

DQb4

DQb3

VDDQ

VSSQ

DQb2

DQb1

DQb0

N.C.

VSSQ

VDDQ

N.C.

KM718S949(512Kx18)

PIN NAME

SYMBOL

PIN NAME

TQFP PIN NO.

SYMBOL

PIN NAME

TQFP PIN NO.

A0 - A18

Address Inputs

32,33,34,35,36,37,

VDD

Power Supply(+2.5V) 14,15,16,41,65,66,91

44,45,46,47,48,49,50, VSS

Ground

17,40,67,90

80,81,82,83,99,100

85

88

N.C.

No Connect

1,2,3,6,7,25,28,29,30,

38,39,42,43,51,52,53,

56,57,75,78,79,84,95,96

ADV

WE

Address Advance/Load

Read/Write Control Input

Clock

Clock Enable

Chip Select

Byte Write Inputs

Output Enable

Power Sleep Mode

Burst Mode Control

CLK

CKE

CS1

CS2

BWx

OE

89

87

98

DQa0~a8

DQb0~b8

Data Inputs/Outputs 58,59,62,63,68,69,72,73,74

8,9,12,13,18,19,22,23,24

97

92

93,94

86

64

VDDQ

VSSQ

Output Power Supply 4,11,20,27,54,61,70,77

(+2.5V)

ZZ

LBO

Output Ground

5,10,21,26,55,60,71,76

31

Notes : 1. The pin 84 is reserved for address bit for the 16Mb NtRAM.

2. A0 and A1 are the two least significant bits(LSB) of the address field and set the internal burst counter if burst is desired.

- 5 -

November 1999

Rev 3.0

KM736S849

KM718S949

256Kx36 & 512Kx18 Pipelined NtRAM^TM

FUNCTION DESCRIPTION

The KM736S849 and KM718S949 are NtRAM^TMdesigned to sustain 100% bus bandwidth by eliminating turnaround cycle when

there is transition from Read to Write, or vice versa.

All inputs (with the exception of OE, LBO and ZZ) are synchronized to rising clock edges.

All read, write and deselect cycles are initiated by the ADV input. Subsequent burst addresses can be internally generated by the

burst advance pin (ADV). ADV should be driven to Low once the device has been deselected in order to load a new address for next

operation.

Clock Enable(CKE) pin allows the operation of the chip to be suspended as long as necessary. When CKE is high, all synchronous

inputs are ignored and the internal device registers will hold their previous values.

NtRAM^TMlatches external address and initiates a cycle, when CKE, ADV are driven to low and all three chip enables(CS1, CS2, CS2)

are active .

Output Enable(OE) can be used to disable the output at any given time.

Read operation is initiated when at the rising edge of the clock, the address presented to the address inputs are latched in the

address register, CKE is driven low, all three chip enables(CS1, CS2, CS2) are active, the write enable input signals WE are driven

high, and ADV driven low.The internal array is read between the first rising edge and the second rising edge of the clock and the data

is latched in the output register. At the second clock edge the data is driven out of the SRAM. Also during read operation OE must

be driven low for the device to drive out the requested data.

Write operation occurs when WE is driven low at the rising edge of the clock. BW[d:a] can be used for byte write operation. The pipe-

lined NtRAM^TMuses a late-late write cycle to utilize 100% of the bandwidth.

At the first rising edge of the clock, WE and address are registered, and the data associated with that address is required two cycle

later.

Subsequent addresses are generated by ADV High for the burst access as shown below. The starting point of the burst seguence is

provided by the external address. The burst address counter wraps around to its initial state upon completion.

The burst sequence is determined by the state of the LBO pin. When this pin is low, linear burst sequence is selected.

And when this pin is high, Interleaved burst sequence is selected.

During normal operation, ZZ must be driven low. When ZZ is driven high, the SRAM will enter a Power Sleep Mode after 2 cycles. At

this time, internal state of the SRAM is preserved. When ZZ returns to low, the SRAM normally operates after 2 cycles of wake up

time.

BURST SEQUENCE TABLE

(Interleaved Burst, LBO=High)

Case 4

Case 1

Case 2

Case 3

LBO PIN

HIGH

First Address

A1

A0

A1

A0

A1

A0

A1

A0

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

Fourth Address

BQ TABLE

(Linear Burst, LBO=Low)

Case 4

Case 1

Case 2

Case 3

LBO PIN

LOW

First Address

A1

A0

A1

A0

A1

A0

A1

A0

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

Fourth Address

Note : 1. LBO pin must be tied to High or Low, and Floating State must not be allowed.

- 6 -

November 1999

Rev 3.0

KM736S849

KM718S949

256Kx36 & 512Kx18 Pipelined NtRAM^TM

STATE DIAGRAM FOR NtRAM^TM

WRITE

READ

BEGIN

READ

BEGIN

WRITE

READ

DESELECT

BURST

READ

BURST

WRITE

BURST

COMMAND

DS

ACTION

DESELECT

READ

BEGIN READ

BEGIN WRITE

WRITE

BEGIN READ

BURST

BEGIN WRITE

CONTINUE DESELECT

Notes : 1. An IGNORE CLOCK EDGE cycle is not shown is the above diagram. This is because CKE HIGH only blocks the clock(CLK) input and does

not change the state of the device.

2. States change on the rising edge of the clock(CLK)

- 7 -

November 1999

Rev 3.0

KM736S849

KM718S949

256Kx36 & 512Kx18 Pipelined NtRAM^TM

TRUTH TABLES

SYNCHRONOUS TRUTH TABLE

CS1 CS2 CS2 ADV WE BWx OE

CKE CLK

ADDRESS ACCESSED

N/A

OPERATION

Not Selected

H

X

L

X

L

X

H

X

L

X

H

X

H

X

L

X

L

X

L

H

•

N/A

Not Selected

X

H

X

H

X

H

X

H

X

L

N/A

Not Selected

H

L

N/A

Not Selected Continue

Begin Burst Read Cycle

Continue Burst Read Cycle

NOP/Dummy Read

Dummy Read

External Address

Next Address

External Address

Next Address

External Address

Next Address

N/A

X

L

X

L

H

L

H

X

L

X

L

H

L

Begin Burst Write Cycle

Continue Burst Write Cycle

NOP/Write Abort

Write Abort

X

L

X

L

H

L

X

L

H

X

H

X

Next Address

Current Address

Ignore Clock

Notes : 1. X means "Don¢t Care".

2. The rising edge of clock is symbolized by (• ).

3. A continue deselect cycle can only be enterd if a deselect cycle is executed first.

4. WRITE = L means Write operation in WRITE TRUTH TABLE.

WRITE = H means Read operation in WRITE TRUTH TABLE.

5. Operation finally depends on status of asynchronous input pins(ZZ and OE).

WRITE TRUTH TABLE(x36)

WE

H

L

BWa

X

BWb

X

BWc

X

BWd

X

OPERATION

READ

L

H

WRITE BYTE a

WRITE BYTE b

WRITE BYTE c

WRITE BYTE d

WRITE ALL BYTEs

WRITE ABORT/NOP

L

H

L

H

L

H

L

H

L

H

L

H

Notes : 1. X means "Don¢t Care".

2. All inputs in this table must meet setup and hold time around the rising edge of CLK(• ).

WRITE TRUTH TABLE(x18)

WE

BWa

BWb

OPERATION

H

X

L

X

H

L

READ

L

WRITE BYTE a

WRITE BYTE b

WRITE ALL BYTEs

WRITE ABORT/NOP

L

H

L

H

Notes : 1. X means "Don¢t Care".

2. All inputs in this table must meet setup and hold time around the rising edge of CLK(• ).

- 8 -

November 1999

Rev 3.0

KM736S849

KM718S949

256Kx36 & 512Kx18 Pipelined NtRAM^TM

ASYNCHRONOUS TRUTH TABLE

Notes

Operation

ZZ

H

L

OE

X

I/O STATUS

1. X means "Don¢t Care".

2. Sleep Mode means power Sleep Mode of which stand-by current does

not depend on cycle time.

3. Deselected means power Sleep Mode of which stand-by current

depends on cycle time.

Sleep Mode

High-Z

DQ

L

Read

L

H

X

High-Z

Write

L

Din, High-Z

High-Z

Deselected

L

X

ABSOLUTE MAXIMUM RATINGS*

PARAMETER

Voltage on VDD Supply Relative to VSS

Voltage on Any Other Pin Relative to VSS

Power Dissipation

SYMBOL

VDD

RATING

-0.3 to 3.6

1.4

UNIT

V

VIN

V

PD

W

Storage Temperature

TSTG

TOPR

TBIAS

-65 to 150

0 to 70

°C

Operating Temperature

Storage Temperature Range Under Bias

-10 to 85

*Note : Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only

and functional operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not

implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.

OPERATING CONDITIONS(0°C £ TA £ 70°C)

PARAMETER

Supply Voltage

Ground

SYMBOL

MIN

2.375

0

Typ.

2.5

0

MAX

2.625

0

UNIT

VDD

V

VDDQ

VSS

*Note : VDD and VDDQ must be supplied with identical vlotage levels.

CAPACITANCE*(TA=25°C, f=1MHz)

TEST CONDI-

VIN=0V

PARAMETER

Input Capacitance

SYMBOL

CIN

MIN

MAX

UNIT

pF

-

6

8

Output Capacitance

COUT

VOUT=0V

pF

*Note : Sampled not 100% tested.

- 9 -

November 1999

Rev 3.0

KM736S849

KM718S949

256Kx36 & 512Kx18 Pipelined NtRAM^TM

DC ELECTRICAL CHARACTERISTICS(VDD=2.5V ±5%, TA=0°C to +70°C)

PARAMETER

SYMBOL

TEST CONDITIONS

VDD=Max ; VIN=VSS to VDD

MIN

MAX

+2

UNIT NOTES

Input Leakage Current(except ZZ)

Output Leakage Current

IIL

-2

-

mA

IOL

Output Disabled,

+2

-60

-67

-75

-10

-60

-67

-75

-10

350

320

300

250

70

-

VDD=Max IOUT=0mA

Operating Current

ICC

ISB

mA

1,2

Cycle Time ³ tCYC Min

-

Device deselected, IOUT=0mA,

ZZ£VIL, f=Max,

-

60

-

50

All Inputs£0.2V or ³ VDD-0.2V

-

40

Standby Current

Device deselected, IOUT=0mA, ZZ£0.2V, f=0,

ISB1

ISB2

-

20

mA

All Inputs=fixed (VDD-0.2V or 0.2V)

Device deselected, IOUT=0mA, ZZ³ VDD-0.2V,

f=Max, All Inputs£VIL or ³ VIH

Output Low Voltage

Output High Voltage

Input Low Voltage

Input High Voltage

VOL

VOH

VIL

IOL=1.0mA

-

0.4

V

IOH=-1.0mA

2.0

-0.3*

1.7

-

0.7

VIH

VDD+0.3**

3

Notes : 1. Reference AC Operating Conditions and Characteristics for input and timing.

2. Data states are all zero.

3. In Case of I/O Pins, the Max. VIH=VDDQ+0.3V

VIH

VSS

VSS-0.8V

20% tCYC(MIN)

TEST CONDITIONS

(TA=0 to 70°C, VDD=2.5V ±5%, unless otherwise specified)

PARAMETER

VALUE

0 to 2.5V

1.0V/ns

1.25V

Input Pulse Level

Input Rise and Fall Time(Measured at 20% to 80%)

Input and Output Timing Reference Levels

Output Load

See Fig. 1

- 10 -

November 1999

Rev 3.0

KM736S849

KM718S949

256Kx36 & 512Kx18 Pipelined NtRAM^TM

Output Load(A)

Output Load(B),

(for tLZC, tLZOE, tHZOE & tHZC)

Dout

RL=50W

+2.5V

VL=1.25V

1667W

30pF*

Dout

Zo=50W

1538W

5pF*

* Including Scope and Jig Capacitance

Fig. 1

AC TIMING CHARACTERISTICS

(VDD=2.5V ±5%, TA=0 to 70°C)

-60

-67

-75

-10

PARAMETER

SYMBOL

UNIT

MIN

6.0

-

MAX

MIN

6.7

-

MAX

MIN

7.5

-

MAX

MIN

10.0

-

MAX

Cycle Time

tCYC

tCD

-

ns

Clock Access Time

3.5

3.8

4.2

5.0

Output Enable to Data Valid

Clock High to Output Low-Z

Output Hold from Clock High

Output Enable Low to Output Low-Z

Output Enable High to Output High-Z

Clock High to Output High-Z

Clock High Pulse Width

tOE

-

3.5

-

3.8

-

4.2

-

5.0

ns

tLZC

tOH

1.5

0

-

1.5

0

-

1.5

0

-

1.5

0

-

ns

-

ns

tLZOE

tHZOE

tHZC

tCH

-

ns

-

2.7

-

3.0

-

3.5

-

3.5

ns

-

2.7

-

3.0

-

3.5

-

3.5

-

ns

2.2

1.5

0.5

2

2.5

1.5

0.5

2

3.0

1.5

0.5

2

3.0

1.5

0.5

2

ns

Clock Low Pulse Width

tCL

-

ns

Address Setup to Clock High

CKE Setup to Clock High

tAS

-

ns

tCES

tDS

-

ns

Data Setup to Clock High

-

ns

Write Setup to Clock High (WE, BWX)

Address Advance Setup to Clock High

Chip Select Setup to Clock High

Address Hold from Clock High

CKE Hold from Clock High

Data Hold from Clock High

Write Hold from Clock High (WE, BWEX)

Address Advance Hold from Clock High

Chip Select Hold from Clock High

ZZ High to Power Down

tWS

-

ns

tADVS

tCSS

tAH

-

ns

-

ns

-

ns

tCEH

tDH

-

ns

-

ns

tWH

tADVH

tCSH

tPDS

tPUS

-

ns

-

ns

-

ns

-

cycle

ZZ Low to Power Up

2

-

2

-

2

-

2

-

Notes : 1. All address inputs must meet the specified setup and hold times for all rising clock(CLK) edges when ADV is sampled low and CS is sampled

low. All other synchronous inputs must meet the specified setup and hold times whenever this device is chip selected.

2. Chip selects must be valid at each rising edge of CLK(when ADV is Low) to remain enabled.

3. A write cycle is defined by WE low having been registered into the device at ADV Low, A Read cycle is defined by WE High with ADV Low,

Both cases must meet setup and hold times.

4. To avoid bus contention, At a given voltage and temperature tLZC is more than tHZC.

The specs as shown do not imply bus contention because tLZC is a Min. parameter that is worst case at totally different test conditions

(0°C,2.625V) than tHZC, which is a Max. parameter(worst case at 70°C,2.375V)

It is not possible for two SRAMs on the same board to be at such different voltage and temperature.

- 11 -

November 1999

Rev 3.0

KM736S849

KM718S949

256Kx36 & 512Kx18 Pipelined NtRAM^TM

SLEEP MODE

SLEEP MODE is a low current, power-down mode in which the device is deselected and current is reduced to ISB2. The duration of

SLEEP MODE is dictated by the length of time the ZZ is in a High state.

After entering SLEEP MODE, all inputs except ZZ become disabled and all outputs go to High-Z

The ZZ pin is an asynchronous, active high input that causes the device to enter SLEEP MODE.

When the ZZ pin becomes a logic High, ISB2 is guaranteed after the time tZZI is met. Any operation pending when entering SLEEP

MODE is not guaranteed to successful complete. Therefore, SLEEP MODE (READ or WRITE) must not be initiated until valid pend-

ing operations are completed. similarly, when exiting SLEEP MODE during tPUS, only a DESELECT or READ cycle should be given

while the SRAM is transitioning out of SLEEP MODE.

SLEEP MODE ELECTRICAL CHARACTERISTICS

(VDD,VDDQ=2.5V ±5%)

DESCRIPTION

Current during SLEEP MODE

CONDITIONS

SYMBOL

ISB2

MIN

MAX

UNITS

mA

ZZ ³ VIH

10

ZZ active to input ignored

tPDS

2

cycle

tPUS

ZZ inactive to input sampled

ZZ active to SLEEP current

tZZI

2

ZZ inactive to exit SLEEP current

tRZZI

0

SLEEP MODE WAVEFORM

K

tPDS

ZZ setup cycle

tPUS

ZZ recovery cycle

ZZ

tZZI

Isupply

ISB2

tRZZI

All inputs

(except ZZ)

Deselect or Read Only

Normal

operation

cycle

Outputs

(Q)

High-Z

DON¢T CARE

- 12 -

November 1999

Rev 3.0

KM736S849

KM718S949

256Kx36 & 512Kx18 Pipelined NtRAM^TM

- 13 -

November 1999

Rev 3.0

KM736S849

KM718S949

256Kx36 & 512Kx18 Pipelined NtRAM^TM

- 14 -

November 1999

Rev 3.0

KM736S849

KM718S949

256Kx36 & 512Kx18 Pipelined NtRAM^TM

- 15 -

November 1999

Rev 3.0

KM736S849

KM718S949

256Kx36 & 512Kx18 Pipelined NtRAM^TM

- 16 -

November 1999

Rev 3.0

KM736S849

KM718S949

256Kx36 & 512Kx18 Pipelined NtRAM^TM

- 17 -

November 1999

Rev 3.0

KM736S849

KM718S949

256Kx36 & 512Kx18 Pipelined NtRAM^TM

PACKAGE DIMENSIONS

Units ; millimeters/Inches

100-TQFP-1420A

22.00 ±0.30

20.00 ±0.20

0~8°

+ 0.10

- 0.05

0.127

16.00 ±0.30

0.10 MAX

14.00 ±0.20

(0.83)

0.50 ±0.10

#1

0.65

(0.58)

0.30 ±0.10

0.10 MAX

1.40 ±0.10

1.60 MAX

0.05 MIN

0.50 ±0.10

- 18 -

November 1999

Rev 3.0


型号：	KM718S949H-67
厂家：	SAMSUNG
描述：	ZBT SRAM, 512KX18, 3.8ns, CMOS, PBGA119, BGA-119 静态存储器
文件：	总18页 (文件大小：398K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

KM718S949H-67 [SAMSUNG]

相关型号：

KM718S949H-75T

KM718S949T-60

KM718V087H-10

KM718V087H-80000

KM718V087T-80000

KM718V089

KM718V089H-54

KM718V089H-60

KM718V089H-72

KM718V089P-60

KM718V089P-67

KM718V089P-72