KM718V889-85 [SAMSUNG]
Cache SRAM, 256KX18, 4ns, CMOS, PQFP100, 20 X 14 MM, TQFP-100;
| 型号： | KM718V889-85 |
| 厂家： | 
SAMSUNG |
| 描述： | Cache SRAM, 256KX18, 4ns, CMOS, PQFP100, 20 X 14 MM, TQFP-100 静态存储器 |
| 文件： | 总15页 (文件大小：427K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
KM718V889
256Kx18 Synchronous SRAM
Document Title
256Kx18-Bit Synchronous Pipelined Burst SRAM
Revision History
REMARK
Rev. No. History
Draft Date
Preliminary
Preliminary
Preliminary
Preliminary
0.0
0.1
0.2
0.3
Initial draft
May . 15. 1997
Change 7.5 bin to 7.2
January . 13 . 1998
February. 02. 1998
Change speed symbol 6.0/6.7/7.2/8.5 to 60/67/72/85
Change DC characteristics VDD condition from VDD=3.3V+10%/-5% Change February. 12. 1998
Input/output leackage currant for ±1mA to ±2mA
Modify Read timing & Power down cycle timing.
Change ISB2 value from 30mA to 20mA.
Remove DC characteristics ISB1 - L ver.& ISB2 - L ver .
Remove Low power version.
Preliminary
0.4
Change Undershoot spec
April. 14. 1998
from -3.0V(pulse width£20ns) to -2.0V(pulse width£tCYC/2)
Add Overshoot spec 4.6V((pulse width£tCYC/2)
Change VIH max from 5.5V to VDD+0.5V
Preliminary
Preliminary
0.5
0.6
Change ISB2 value from 20mA to 30mA.
Change VDD condition from VDD=3.3V+10%/-5% to VDD=3.3V+0.3V/-0.165V.
May.13. 1998
May.14. 1998
Modify DC characteristics( Input Leakage Current test Conditions)
form VDD=VSS to VDD to Max.
Final
Final
Final
1.0
2.0
3.0
Final spec Release
May 15. 1998
Oct. 23. 1998
Feb.10. 1999
Add 119BGA(7x17 Ball Grid Array Package) .
Remove 119BGA(7x17 Ball Grid Array Package) .
The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the
specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions on the parameters of this device. If you have any ques-
tions, please contact the SAMSUNG branch office near your office, call or contact Headquarters.
Feb. 1999
Rev 3.0
- 1 -
KM718V889
256Kx18 Synchronous SRAM
256Kx18-Bit Synchronous Pipelined Burst SRAM
FEATURES
GENERAL DESCRIPTION
• Synchronous Operation.
• 2 Stage Pipelined Operation With 4 Burst.
• On-Chip Address Counter.
The KM718V889 is a 4,718,592 bits Synchronous Static Ran-
dom Access Memory designed for high performance second
level cache of pentium and Power PC based system.
It is organized as 256K words of 18 bits. And it integrates
address and control registers, a 2-bit burst address counter and
added some new functions for high performance cache RAM
applications; GW, BW, LBO, ZZ.
• Self-Timed Write Cycle.
• On-Chip Address and Control Registers.
• VDD=3.3V+0.3V/-0.165V Power Supply.
• 5V Tolerant Inputs except I/O Pins.
• Byte Writable Function.
Write cycles are internally self-timed and synchronous.
Full bus-width write is done by GW, and each byte write is per-
formed by the combination of WEx and BW when GW is high.
And with CS1 high, ADSP disable to support address pipelin-
ing.
• Global Write Enable Controls a full bus-width write.
• Power Down State via ZZ Signal.
• LBO Pin allows a choice of either a interleaved burst or a lin-
ear burst.
• Three Chip Enables for simple depth expansion with No Data
Contention ; 2 cycle Enable, 1 cycle Disable.
• Asynchronous Output Enable Control.
• ADSP, ADSC, ADV Burst Control Pins.
• TTL-Level Three-State Output.
Burst cycle can be initiated with either the address status pro-
cessor(ADSP) or address status cache controller(ADSC)
inputs. Subsequent burst addresses are generated internally in
the system¢s burst sequence and are controlled by the burst
address advance(ADV) input.
• 100-TQFP-1420A.
LBO pin is DC operated and determines burst sequence (linear
or interleaved).
FAST ACCESS TIMES
ZZ pin controls Power Down State and reduces Stand-by cur-
rent regardless of CLK.
Parameter
Cycle Time
Symbol 60 67 72 85 Unit
The KM718V889 is fabricated using SAMSUNG¢s high perfor-
mance CMOS technology and is available in a 100pin TQFP
package. Multiple power and ground pins are utilized to mini-
mize ground bounce.
tCYC
tCD
6.0 6.7 7.2 8.5 ns
3.5 3.8 4.0 4.0 ns
3.5 3.8 4.0 4.0 ns
Clock Access Time
Output Enable Access Time
tOE
LOGIC BLOCK DIAGRAM
CLK
LBO
256Kx18
BURST CONTROL
LOGIC
BURST
MEMORY
ADDRESS
ADV
ADSC
A¢0~A¢1
ARRAY
COUNTER
A0~A1
A2~A17
ADDRESS
REGISTER
A0~A17
ADSP
DATA-IN
REGISTER
CS1
CS2
CS2
GW
BW
OUTPUT
REGISTER
CONTROL
LOGIC
BUFFER
WEa
WEb
OE
ZZ
DQa0 ~ DQb7
DQPa ~ DQPb
Feb. 1999
Rev 3.0
- 2 -
KM718V889
256Kx18 Synchronous SRAM
PIN CONFIGURATION(TOP VIEW)
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
A10
N.C.
N.C.
N.C.
VDDQ
VSSQ
N.C.
1
2
3
4
5
6
7
8
N.C.
N.C.
VDDQ
VSSQ
N.C.
DQPa
DQa7
DQa6
VSSQ
VDDQ
DQa5
DQa4
VSS
N.C.
DQb0
DQb1
VSSQ
VDDQ
DQb2
DQb3
N.C.
VDD
N.C.
VSS
DQb4
DQb5
VDDQ
VSSQ
DQb6
DQb7
DQPb
N.C.
VSSQ
VDDQ
N.C.
N.C.
N.C.
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
100 Pin
TQFP
N.C.
VDD
ZZ
DQa3
DQa2
VDDQ
VSSQ
DQa1
DQa0
N.C.
N.C.
VSSQ
VDDQ
N.C.
N.C.
N.C.
(20mm x 14mm)
PIN NAME
SYMBOL
PIN NAME
TQFP PIN NO.
SYMBOL
PIN NAME
TQFP PIN NO.
A0 - A17
Address Inputs
32,33,34,35,36,37,
44,45,46,47,48,49,
50,80,81,82,99,100
83
VDD
VSS
N.C.
Power Supply(+3.3V) 15,41,65,91
Ground
17,40,67,90
No Connect
1,2,3,6,7,14,16,25,28,29,
30,38,39,42,43,51,52,53,
56,57,66,75,78,79,95,96
ADV
ADSP
ADSC
CLK
CS1
CS2
CS2
WEx
OE
GW
BW
ZZ
LBO
Burst Address Advance
Address Status Processor 84
Address Status Controller
Clock
Chip Select
85
89
98
97
92
93,94
86
88
87
DQa0~a7
DQb0~b7
DQPa, Pb
Data Inputs/Outputs
58,59,62,63,68,69,72,73
8,9,12,13,18,19,22,23
74,24
Chip Select
Chip Select
Byte Write Inputs
Output Enable
Global Write Enable
Byte Write Enable
Power Down Input
Burst Mode Control
VDDQ
VSSQ
Output Power Supply 4,11,20,27,54,61,70,77
(+3.3V)
Output Ground
5,10,21,26,55,60,71,76
64
31
Feb. 1999
Rev 3.0
- 3 -
KM718V889
256Kx18 Synchronous SRAM
FUNCTION DESCRIPTION
The KM718V889 is a synchronous SRAM designed to support the burst address accessing sequence of the Pentium and Power PC
based microprocessor. All inputs(with the exception of OE, LBO and ZZ) are sampled on rising clock edges. The start and duration of
the burst access is controlled by ADSP, ADSC, ADV and Chip Select pins.
The accesses are enabled with the chip select signals and output enabled signals. Wait states are inserted into the access with ADV.
When ZZ is pulled high, the SRAM will enter a Power Down State. At this time, internal state of the SRAM is preserved. When ZZ
returns to low, the SRAM normally operates after 2 cycles of wake up time. ZZ pin is pulled down internally.
Read cycles are initiated with ADSP(regardless of WEx and ADSC) using the new external address clocked into the on-chip address
register whenever ADSP is sampled low, the chip selects are sampled active, and the output buffer is enabled with OE. In read oper-
ation the data of cell array accessed by the current address, registered in the Data-out registers by the positive edge of CLK, are car-
ried to the Data-out buffer by the next positive edge of CLK. The data, registered in the Data-out buffer, are projected to the output
pins. ADV is ignored on the clock edge that samples ADSP asserted, but is sampled on the subsequent clock edges. The address
increases internally for the next access of the burst when WEx are sampled High and ADV is sampled Low. And ADSP is blocked to
control signals by disabling CS1.
All byte write is done by GW (regardless of BW and WEx.), and each byte write is performed by the combination of BW and WEx
when GW is High.
Write cycles are performed by disabling the output buffers with OE and asserting WEx. WEx are ignored on the clock edge that sam-
ples ADSP Low, but are sampled on the subsequent clock edges. The output buffers are disabled when WEx are sampled
Low(regaedless of OE). Data is clocked into the data input register when WEx sampled Low. The address increases internally to the
next address of burst, if both WEx and ADV are sampled Low. Individual byte write cycles are performed by any one or more byte
write enable signals(WEa or WEb) sampled low. The WEa controls DQa0 ~ DQa7 and DQPa, WEb controls DQb0 ~ DQb7 and DQPb.
Read or write cycle may also be initiated with ADSC, instead of ADSP. The differences between cycles initiated with ADSC and
ADSP as are follows;
ADSP must be sampled high when ADSC is sampled low to initiate a cycle with ADSC.
WEx are sampled on the same clock edge that sampled ADSC low(and ADSP high).
Addresses are generated for the burst access as shown below, The starting point of the burst sequence is provided by the external
address. The burst address counter wraps around to its initial state upon completion. The burst sequence is determined by the state
of the LBO pin. When this pin is Low, linear burst sequence is selected. And when this pin is High, Interleaved burst sequence is
selected.
BURST SEQUENCE TABLE
(Interleaved Burst)
Case 4
Case 1
Case 2
Case 3
LBO PIN
HIGH
First Address
A1
A0
A1
A0
A1
A0
A1
A0
0
0
1
1
0
1
0
1
0
0
1
1
1
0
1
0
1
1
0
0
0
1
0
1
1
1
0
0
1
0
1
0
Fourth Address
BURST SEQUENCE TABLE
(Linear Burst)
Case 1
Case 2
Case 3
Case 4
LBO PIN
LOW
First Address
A1
A0
A1
A0
A1
A0
A1
A0
0
0
1
1
0
1
0
1
0
1
1
0
1
0
1
0
1
1
0
0
0
1
0
1
1
0
0
1
1
0
1
0
Fourth Address
NOTE : 1. LBO pin must be tied to High or Low, and Floating State must not be allowed.
Feb. 1999
Rev 3.0
- 4 -
KM718V889
256Kx18 Synchronous SRAM
TRUTH TABLES
SYNCHRONOUS TRUTH TABLE
CS1
H
L
CS2
X
L
CS2 ADSP ADSC ADV WRITE CLK
Address Accessed
N/A
Operation
X
X
H
X
H
L
X
L
L
X
X
L
X
X
X
X
X
X
X
X
L
X
X
X
X
X
X
L
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Not Selected
N/A
Not Selected
L
X
L
L
N/A
Not Selected
L
X
X
L
N/A
Not Selected
L
X
H
H
H
X
X
X
X
X
X
X
X
L
N/A
Not Selected
L
X
L
External Address
External Address
External Address
Next Address
Next Address
Next Address
Next Address
Current Address
Current Address
Current Address
Current Address
Begin Burst Read Cycle
Begin Burst Write Cycle
Begin Burst Read Cycle
Continue Burst Read Cycle
Continue Burst Read Cycle
Continue Burst Write Cycle
Continue Burst Write Cycle
Suspend Burst Read Cycle
Suspend Burst Read Cycle
Suspend Burst Write Cycle
Suspend Burst Write Cycle
L
L
H
H
H
X
H
X
H
X
H
X
L
L
L
H
H
H
L
X
H
X
H
X
H
X
H
X
X
X
X
X
X
X
X
H
H
H
H
H
H
H
H
L
L
L
L
H
H
H
H
H
H
L
L
NOTE : 1. X means "Don¢t Care".
2. The rising edge of clock is symbolized by • .
3. WRITE = L means Write operation in WRITE TRUTH TABLE.
WRITE = H means Read operation in WRITE TRUTH TABLE.
4. Operation finally depends on status of asynchronous input pins(ZZ and OE).
WRITE TRUTH TABLE
GW
H
BW
H
L
WEa
X
WEb
X
Operation
READ
H
H
H
READ
H
L
L
H
WRITE BYTE a
WRITE BYTE b
WRITE ALL BYTEs
WRITE ALL BYTEs
H
L
H
L
H
L
L
L
L
X
X
X
NOTE : 1. X means "Don¢t Care".
2. All inputs in this table must meet setup and hold time around the rising edge of CLK(• ).
ASYNCHRONOUS TRUTH TABLE
(See Notes 1 and 2):
NOTE
Operation
ZZ
H
L
OE
X
I/O Status
High-Z
1. X means "Don¢t Care".
2. ZZ pin is pulled down internally
Sleep Mode
3. For write cycles that following read cycles, the output buffers must be
disabled with OE, otherwise data bus contention will occur.
4. Sleep Mode means power down state of which stand-by current does
not depend on cycle time.
5. Deselected means power down state of which stand-by current
depends on cycle time.
L
DQ
Read
L
H
X
High-Z
Write
L
Din, High-Z
High-Z
Deselected
L
X
Feb. 1999
Rev 3.0
- 5 -
KM718V889
256Kx18 Synchronous SRAM
PASS-THROUGH TRUTH TABLE
Previous Cycle
Present Cycle
CS1 WRITE
Next Cycle
Operation
WRITE
Operation
OE
Initiate Read Cycle
All L Address=An
Write Cycle, All bytes
Address=An-1, Data=Dn-1
Read Cycle
Data=Qn
L
H
L
Data=Qn-1 for all bytes
Write Cycle, All bytes
Address=An-1, Data=Dn-1
No new cycle
Data=Qn-1 for all bytes
No carryover from
previous cycle
All L
All L
H
H
H
H
L
Write Cycle, All bytes
Address=An-1, Data=Dn-1
No new cycle
Data=High-Z
No carryover from
previous cycle
H
Initiate Read Cycle
One L Address=An
Data=Qn-1 for one byte
Write Cycle, One byte
Address=An-1, Data=Dn-1
Read Cycle
Data=Qn
L
H
H
L
L
Write Cycle, One byte
Address=An-1, Data=Dn-1
No new cycle
Data=Qn-1 for one byte
No carryover from
previous cycle
One L
H
NOTE : 1. This operation makes written data immediately available at output during a read cycle preceded by a write cycle.
ABSOLUTE MAXIMUM RATINGS*
Parameter
Voltage on VDD Supply Relative to VSS
Voltage on VDDQ Supply Relative to VSS
Voltage on Input Pin Relative to VSS
Voltage on I/O Pin Relative to VSS
Power Dissipation
Symbol
VDD
Rating
-0.3 to 4.6
VDD
Unit
V
VDDQ
VIN
V
-0.3 to 6.0
-0.3 to VDDQ + 0.5
1.6
V
VIO
V
PD
W
°C
°C
°C
Storage Temperature
TSTG
TOPR
TBIAS
-65 to 150
0 to 70
Operating Temperature
Storage Temperature Range Under Bias
-10 to 85
*NOTE : Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only
and functional operation of the device at these or any other conditions above those indicated in the operating sections of this specification is
not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
OPERATING CONDITIONS(0°C £ TA £ 70°C)
Parameter
Supply Voltage
Ground
Symbol
Min
3.135
3.135
0
Typ.
3.3
3.3
0
Max
3.6
3.6
0
Unit
V
VDD
VDDQ
VSS
V
V
CAPACITANCE*(TA=25°C, f=1MHz)
Parameter
Symbol
Test Condition
VIN=0V
Min
Max
5
Unit
pF
Input Capacitance
CIN
-
-
Output Capacitance
COUT
VOUT=0V
7
pF
*NOTE : Sampled not 100% tested.
Feb. 1999
Rev 3.0
- 6 -
KM718V889
256Kx18 Synchronous SRAM
DC ELECTRICAL CHARACTERISTICS(TA=0 to 70°C, VDD=3.3V+0.3V/-0.165V)
Parameter
Symbol
Test Conditions
Min
Max
+2
Unit
mA
Input Leakage Current(except ZZ)
Output Leakage Current
IIL
VDD=Max ; VIN=VSS to VDD
-2
-2
-
IOL
Output Disabled, VOUT=VSS to VDDQ
+2
mA
-60
-67
-72
-85
-60
-67
-72
-85
425
400
375
350
130
120
110
110
ICC
Device Selected, IOUT=0mA, ZZ£VIL,
All Inputs=VIL or VIH
-
Operating Current
mA
mA
-
Cycle Time ³ tCYC min
-
-
Device deselected, IOUT=0mA,
ZZ£VIL, f=Max,
-
ISB
-
All Inputs £ 0.2V or ³ VDD-0.2V
-
Standby Current
Device deselected, IOUT=0mA, ZZ£0.2V,
ISB1
ISB2
-
-
30
30
mA
mA
f = 0, All Inputs=fixed (VDD-0.2V or 0.2V)
Device deselected, IOUT=0mA,
ZZ³ VDD-0.2V, f=Max, All Inputs£VIL or ³ VIH
Output Low Voltage
Output High Voltage
Input Low Voltage
Input High Voltage
VOL
VOH
VIL
IOL=8.0mA
IOH=-4.0mA
-
0.4
V
V
V
V
2.4
-0.5*
2.0
-
0.8
VIH
VDD+0.5**
*
VIL(Min)=-2.0(Pulse Width £ tCYC/2)
** VIH(Max)=4.6(Pulse Width £ tCYC/2)
** In Case of I/O Pins, the Max. VIH=VDDQ+0.5V
TEST CONDITIONS(TA=0 to 70°C, VDD=3.3V+0.3V/-0.165V, unless otherwise specified)
Parameter
Value
Input Pulse Level
0 to 3V
2ns
Input Rise and Fall Time(Measured at 0.3V and 2.7V)
Input and Output Timing Reference Levels
1.5V
Output Load
See Fig. 1
Output Load(A)
Output Load(B)
(for tLZC, tLZOE, tHZOE& tHZC)
+3.3V
Dout
RL=50W
319W
VL=1.5V
Dout
30pF*
Z0=50W
353W
5pF*
* Including Scope and Jig Capacitance
* Capacitive Load consists of all components of
the test environment.
Fig. 1
Feb. 1999
Rev 3.0
- 7 -
KM718V889
256Kx18 Synchronous SRAM
AC TIMING CHARACTERISTICS
(VDD=3.3V+0.3V/-0.165V, TA=0 to 70°C)
-60
-67
-72
-85
Parameter
Symbol
Unit
Min
6.0
-
Max
Min
6.7
-
Max
Min
7.2
-
Max
Min
8.5
-
Max
Cycle Time
tCYC
tCD
-
-
-
-
ns
ns
Clock Access Time
3.5
3.8
4.0
4.0
Output Enable to Data Valid
Clock High to Output Low-Z
Output Hold from Clock High
Output Enable Low to Output Low-Z
Output Enable High to Output High-Z
Clock High to Output High-Z
Clock High Pulse Width
tOE
-
3.5
-
3.8
-
4.0
-
4.0
ns
tLZC
tOH
0
-
0
-
0
-
0
-
ns
1.5
0
-
1.5
0
-
1.5
0
-
1.5
0
-
ns
tLZOE
tHZOE
tHZC
tCH
-
-
-
-
ns
-
3.5
-
3.5
-
3.8
-
3.8
ns
1.5
2.4
2.4
1.5
1.5
1.5
1.5
1.5
1.5
0.5
0.5
0.5
0.5
0.5
0.5
2
6.0
-
1.5
2.6
2.6
1.5
1.5
1.5
1.5
1.5
1.5
0.5
0.5
0.5
0.5
0.5
0.5
2
6.7
-
1.5
2.8
2.8
1.5
1.5
1.5
1.5
1.5
1.5
0.5
0.5
0.5
0.5
0.5
0.5
2
7.2
-
1.5
3.4
3.4
1.5
1.5
1.5
1.5
1.5
1.5
0.5
0.5
0.5
0.5
0.5
0.5
2
7.5
-
ns
ns
Clock Low Pulse Width
tCL
-
-
-
-
ns
Address Setup to Clock High
Address Status Setup to Clock High
Data Setup to Clock High
tAS
-
-
-
-
ns
tSS
-
-
-
-
ns
tDS
-
-
-
-
ns
Write Setup to Clock High (GW, BW, WEX)
Address Advance Setup to Clock High
Chip Select Setup to Clock High
Address Hold from Clock High
Address Status Hold from Clock High
Data Hold from Clock High
tWS
-
-
-
-
ns
tADVS
tCSS
tAH
-
-
-
-
ns
-
-
-
-
ns
-
-
-
-
ns
tSH
-
-
-
-
ns
tDH
-
-
-
-
ns
Write Hold from Clock High (GW, BW, WEX)
Address Advance Hold from Clock High
Chip Select Hold from Clock High
ZZ High to Power Down
tWH
tADVH
tCSH
tPDS
tPUS
-
-
-
-
ns
-
-
-
-
ns
-
-
-
-
ns
-
-
-
-
cycle
cycle
ZZ Low to Power Up
2
-
2
-
2
-
2
-
NOTE : 1. All address inputs must meet the specified setup and hold times for all rising clock edges whenever ADSC and/or ADSP is sampled low and
CS is sampled low. All other synchronous inputs must meet the specified setup and hold times whenever this device is chip selected.
2. Both chip selects must be active whenever ADSC or ADSP is sampled low in order for the this device to remain enabled.
3. ADSC or ADSP must not be asserted for at least 2 Clock after leaving ZZ state.
Feb. 1999
Rev 3.0
- 8 -
KM718V889
256Kx18 Synchronous SRAM
Feb. 1999
Rev 3.0
- 9 -
KM718V889
256Kx18 Synchronous SRAM
Feb. 1999
Rev 3.0
- 10 -
KM718V889
256Kx18 Synchronous SRAM
Feb. 1999
Rev 3.0
- 11 -
KM718V889
256Kx18 Synchronous SRAM
Feb. 1999
Rev 3.0
- 12 -
KM718V889
256Kx18 Synchronous SRAM
Feb. 1999
Rev 3.0
- 13 -
KM718V889
256Kx18 Synchronous SRAM
APPLICATION INFORMATION
DEPTH EXPANSION
The Samsung 256Kx18 Synchronous pipelined Burst SRAM has two additional chip selects for simple depth expansion.
This permits easy secondary cache upgrades from 256K depth to 512K depth without extra logic.
I/O[0:71]
Data
Address
A[0:18]
A[18]
A[0:17]
A[18]
A[0:17]
Address Data
CS2
Address Data
CS2
CLK
CS2
CLK
ADSC
WEx
OE
CS2
CLK
ADSC
WEx
OE
Microprocessor
256Kx18
SPB
SRAM
256Kx18
SPB
SRAM
Address
CLK
(Bank 0)
(Bank 1)
Cache
Controller
CS1
CS1
ADV ADSP
ADV ADSP
ADS
INTERLEAVE READ TIMING (Refer to non-interleave write timing for interleave write timing)
(ADSP CONTROLLED , ADSC=HIGH)
Clock
tSS
tSH
ADSP
tAS
tAH
A2
A1
ADDRESS
[0:n]
tWS
tWH
WRITE
CS1
tCSS
tCSH
Bank 0 is selected by CS2, and Bank 1 deselected by CS2
An+1
ADV
OE
Bank 0 is deselected by CS2, and Bank 1 selected by CS2
tADVS
tADVH
tOE
tHZC
tLZOE
Data Out
(Bank 0)
Q1-1
Q1-2
Q1-3
Q1-4
tCD
tLZC
Data Out
(Bank 1)
Q2-1
Q2-2
Q2-3
Q2-4
*NOTES n = 14 32K depth, 15 64K depth, 16 128K depth, 17 256K depth
Don¢t Care
Undefined
Feb. 1999
Rev 3.0
- 14 -
KM718V889
256Kx18 Synchronous SRAM
PACKAGE DIMENSIONS
100-TQFP-1420A
Units:millimeters/inches
22.00 ±0.30
20.00 ±0.20
0~8°
+ 0.10
- 0.05
0.127
16.00 ±0.30
0.10 MAX
14.00 ±0.20
(0.83)
0.50 ±0.10
#1
0.65
(0.58)
0.30 ±0.10
0.10 MAX
1.40 ±0.10
1.60 MAX
0.05 MIN
0.50 ±0.10
Feb. 1999
Rev 3.0
- 15 -
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