KM718V987H-7 [SAMSUNG]
Cache SRAM, 512KX18, 7.5ns, CMOS, PBGA119, BGA-119;
| 型号： | KM718V987H-7 |
| 厂家： | 
SAMSUNG |
| 描述： | Cache SRAM, 512KX18, 7.5ns, CMOS, PBGA119, BGA-119 时钟 静态存储器 内存集成电路 |
| 文件： | 总21页 (文件大小：575K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
KM736V887
KM718V987
256Kx36 & 512Kx18 Synchronous SRAM
Document Title
256Kx36 & 512Kx18-Bit Synchronous Burst SRAM
Revision History
Rev.No.
History
Draft Date
Remark
0.0
Initial draft
April. 10 . 1998
Preliminary
0.1
Change DC Characteristics.
Aug. 31. 1998
Preliminary
ISB value from 60mA to 90mA at -8
ISB value from 50mA to 80mA at -9
ISB value from 40mA to 70mA at -10
ISB1 value from 10mA to 30mA
ISB2 value from 10mA to 30mA
0.2
1. Changed tCD from 8.0ns to 8.5ns at -8
2. Changed tCYC from 13.0ns to 12.0ns at -10
3. Changed DC condition at Icc and parameters
ICC ; from 300mA to 350mA at -8,
from 260mA to 300mA at -9,
Sep. 09. 1998
Preliminary
from 220mA to 260mA at -10,
ISB ; from 90mA to 130mA at -8,
from 80mA to 120mA at -9,
from 70mA to 110mA at -10,
0.3
1. ADD 119BGA(7x17 Ball Grid Array Package) .
2. ADD x32 organization.
Oct. 15. 1998
Preliminary
0.4
0.5
1.0
Add VDDQ Supply voltage( 2.5V )
Dec. 10. 1998
Dec. 23. 1998
Jan. 29. 1999
Preliminary
Preliminary
Final
Changed VOL Max value from 0.2V to 0.4V at 2.5V I/O.
1. Final Spec Release.
2. Remove x32 organization.
2.0
3.0
1. Remove VDDQ supply voltage(2.5V)
Feb. 25. 1999
Mar. 30. 1999
Final
Final
1. Changed ICC from 350mA to 330mA at -8.
2. Add bin -7. (tCD 7.5ns).
4.0
5.0
1. Add VDDQ supply voltage(2.5V)
May. 13. 1999
Nov. 19. 1999
Final
Final
1. Changed tCYC from 12ns to 10ns at -9.
The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the
specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions on the parameters of this device. If you have any ques-
tions, please contact the SAMSUNG branch office near your office, call or contact Headquarters.
November 1999
- 1 -
Rev 5.0
KM736V887
KM718V987
256Kx36 & 512Kx18 Synchronous SRAM
256Kx36 & 512Kx18-Bit Synchronous Burst SRAM
FEATURES
GENERAL DESCRIPTION
• Synchronous Operation.
• On-Chip Address Counter.
• Self-Timed Write Cycle.
The KM736V887 and KM718V987 are 9,437,184-bit Synchro-
nous Static Random Access Memory designed for high perfor-
mance second level cache of Pentium and Power PC based
System.
• On-Chip Address and Control Registers.
• 3.3V+0.165V/-0.165V Power Supply.
• I/O Supply Voltage 3.3V+0.165V/-0.165V for 3.3V I/O
or 2.5V+0.4V/-0.125V for 2.5V I/O
• 5V Tolerant Inputs Except I/O Pins.
• Byte Writable Function.
• Global Write Enable Controls a full bus-width write.
• Power Down State via ZZ Signal.
• LBO Pin allows a choice of either a interleaved burst or a lin-
ear burst.
• Three Chip Enables for simple depth expansion with No Data
Contention only for TQFP.
• Asynchronous Output Enable Control.
• ADSP, ADSC, ADV Burst Control Pins.
• TTL-Level Three-State Output.
It is organized as 256K(512K) words of 36(18) bits and inte-
grates address and control registers, a 2-bit burst address
counter and added some new functions for high performance
cache RAM applications; GW, BW, LBO, ZZ. Write cycles are
internally self-timed and synchronous.
Full bus-width write is done by GW, and each byte write is per-
formed by the combination of WEx and BW when GW is high.
And with CS1 high, ADSP is blocked to control signals.
Burst cycle can be initiated with either the address status pro-
cessor(ADSP) or address status cache controller(ADSC)
inputs. Subsequent burst addresses are generated internally in
the system¢s burst sequence and are controlled by the burst
address advance(ADV) input.
• 100-TQFP-1420A /119BGA(7x17 Ball Grid Array Package)
LBO pin is DC operated and determines burst sequence(linear
or interleaved).
FAST ACCESS TIMES
ZZ pin controls Power Down State and reduces Stand-by cur-
rent regardless of CLK.
The KM736V887 and KM718V987 are fabricated using SAM-
SUNG¢s high performance CMOS technology and is available
in a 100pin TQFP and 119BGA package. Multiple power and
ground pins are utilized to minimize ground bounce.
PARAMETER
Cycle Time
Symbol -7 -8 -9 -10 Unit
tCYC
tCD
8.5 10 10 12 ns
7.5 8.5 9.0 10.0 ns
3.5 3.5 3.5 3.5 ns
Clock Access Time
Output Enable Access Time
tOE
LOGIC BLOCK DIAGRAM
CLK
LBO
256Kx36 , 512Kx18
BURST CONTROL
LOGIC
BURST
MEMORY
ADDRESS
COUNTER
ADV
ADSC
A¢0~A¢1
ARRAY
A0~A1
A2~A17
or A2~A18
A
0
~A17
ADDRESS
REGISTER
or A
0~A18
ADSP
DATA-IN
REGISTER
CS
CS
CS
1
2
2
GW
BW
OUTPUT
BUFFER
CONTROL
LOGIC
WEx
(x=a,b,c,d or a,b)
OE
ZZ
DQa
0
~ DQd
7
or DQa0 ~ DQb7
DQPa,DQPb
DQPa ~ DQPd
November 1999
Rev 5.0
- 2 -
KM736V887
KM718V987
256Kx36 & 512Kx18 Synchronous SRAM
PIN CONFIGURATION(TOP VIEW)
DQPc
1
DQPb
DQb7
DQb6
VDDQ
VSSQ
DQb5
DQb4
DQb3
DQb2
VSSQ
VDDQ
DQb1
DQb0
VSS
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
DQc0
2
DQc1
3
VDDQ
VSSQ
5
DQc2
DQc3
7
DQc4
DQc5
9
VSSQ
VDDQ
11
DQc6
DQc7
13
N.C.
4
6
8
10
12
100 Pin TQFP
14
VDD
15
N.C.
VDD
ZZ
(20mm x 14mm)
N.C.
16
VSS
17
DQd0
18
DQd1
VDDQ
20
VSSQ
DQd2
22
DQd3
DQd4
24
DQd5
VSSQ
26
VDDQ
DQd6
28
DQd7
DQa7
DQa6
VDDQ
VSSQ
DQa5
DQa4
DQa3
DQa2
VSSQ
VDDQ
DQa1
DQa0
DQPa
KM736V887(256Kx36)
19
21
23
25
27
29
DQPd
30
PIN
SYMBOL
PIN NAME
Address Inputs
TQFP PIN NO.
SYMBOL
PIN NAME
TQFP PIN NO.
A0 - A17
32,33,34,35,36,37,43 VDD
44,45,46,47,48,49,50 VSS
Power Supply(+3.3V) 15,41,65,91
Ground
17,40,67,90
81,82,99,100
83
Address Status Processor 84
Address Status Controller 85
N.C.
No Connect
14,16,38,39,42,66
ADV
ADSP
ADSC
CLK
CS1
Burst Address Advance
DQa0~a7
DQb0~b7
DQc0~c7
DQd0~d7
DQPa~Pd
VDDQ
Data Inputs/Outputs
52,53,56,57,58,59,62,63
68,69,72,73,74,75,78,79
2,3,6,7,8,9,12,13
18,19,22,23,24,25,28,29
51,80,1,30
Clock
89
98
97
92
Chip Select
Chip Select
Chip Select
CS2
CS2
Output Power Supply 4,11,20,27,54,61,70,77
(2.5V or 3.3V)
WEx(x=a,b,c,d) Byte Write Inputs
93,94,95,96
OE
Output Enable
86
88
87
64
31
VSSQ
Output Ground
5,10,21,26,55,60,71,76
GW
BW
ZZ
Global Write Enable
Byte Write Enable
Power Down Input
Burst Mode Control
LBO
Notes : 1. A0 and A1 are the two least significant bits(LSB) of the address field and set the internal burst counter if burst is desired.
2. The pin 42 is reserved for address bit for the 16Mb .
November 1999
Rev 5.0
- 3 -
KM736V887
KM718V987
256Kx36 & 512Kx18 Synchronous SRAM
PIN CONFIGURATION(TOP VIEW)
A10
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
N.C.
N.C.
N.C.
VDDQ
VSSQ
N.C.
1
2
3
4
5
6
7
8
N.C.
N.C.
VDDQ
VSSQ
N.C.
DQPa
DQa7
DQa6
VSSQ
VDDQ
DQa5
DQa4
VSS
N.C.
DQb0
DQb1
VSSQ
VDDQ
DQb2
DQb3
N.C.
VDD
N.C.
VSS
DQb4
DQb5
VDDQ
VSSQ
DQb6
DQb7
DQPb
N.C.
VSSQ
VDDQ
N.C.
N.C.
N.C.
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
100 Pin TQFP
(20mm x 14mm)
N.C.
VDD
ZZ
DQa3
DQa2
VDDQ
VSSQ
DQa1
DQa0
N.C.
N.C.
VSSQ
VDDQ
N.C.
N.C.
N.C.
KM718V987(512Kx18)
PIN NAME
SYMBOL
PIN NAME
TQFP PIN NO.
SYMBOL
PIN NAME
TQFP PIN NO.
A0 - A18
Address Inputs
32,33,34,35,36,37,43 VDD
44,45,46,47,48,49,50 VSS
Power Supply(+3.3V) 15,41,65,91
Ground
17,40,67,90
80,81,82,99,100
83
Address Status Processor 84
N.C.
No Connect
1,2,3,6,7,14,16,25,28,29,
30,38,39,42,51,52,53,56,
57,66,75,78,79,95,96
ADV
ADSP
ADSC
CLK
CS1
CS2
CS2
WEx
OE
Burst Address Advance
Address Status Controller
Clock
Chip Select
Chip Select
Chip Select
85
89
98
97
92
93,94
86
DQa0 ~ a7
DQb0 ~ b7
DQPa, Pb
VDDQ
Data Inputs/Outputs
58,59,62,63,68,69,72,73
8,9,12,13,18,19,22,23
74,24
Output Power Supply
(2.5V or 3.3V)
Output Ground
4,11,20,27,54,61,70,77
Byte Write Inputs
Output Enable
VSSQ
5,10,21,26,55,60,71,76
GW
BW
ZZ
LBO
Global Write Enable
Byte Write Enable
Power Down Input
Burst Mode Control
88
87
64
31
Notes : 1. A0 and A1 are the two least significant bits(LSB) of the address field and set the internal burst counter if burst is desired.
2. The pin 42 is reserved for address bit for the 16Mb .
November 1999
Rev 5.0
- 4 -
KM736V887
KM718V987
256Kx36 & 512Kx18 Synchronous SRAM
119BGA PACKAGE PIN CONFIGURATIONS(TOP VIEW)
KM736V887(256Kx36)
1
2
A
3
A
4
ADSP
ADSC
VDD
NC
5
A
6
A
7
A
B
C
D
E
F
VDDQ
NC
VDDQ
NC
CS2
A
A
A
A
NC
A
A
A
NC
DQc
DQc
VDDQ
DQc
DQc
VDDQ
DQd
DQd
VDDQ
DQd
DQd
NC
DQPc
DQc
DQc
DQc
DQc
VDD
DQd
DQd
DQd
DQd
DQPd
A
VSS
VSS
VSS
WEc
VSS
NC
VSS
WEd
VSS
VSS
VSS
LBO
A
VSS
VSS
VSS
WEb
VSS
NC
VSS
WEa
VSS
VSS
VSS
NC
A
DQPb
DQb
DQb
DQb
DQb
VDD
DQa
DQa
DQa
DQa
DQPa
A
DQb
DQb
VDDQ
DQb
DQb
VDDQ
DQa
DQa
VDDQ
DQa
DQa
NC
CS1
OE
G
H
J
ADV
GW
VDD
CLK
NC
K
L
M
N
P
R
T
BW
A1*
A0*
VDD
A
NC
NC
NC
ZZ
U
VDDQ
NC
NC
NC
NC
NC
VDDQ
Note : * A0 and A1 are the two least significant bits(LSB) of the address field and set the internal burst counter if burst is desired.
PIN NAME
SYMBOL
PIN NAME
SYMBOL
PIN NAME
Power Supply(+3.3V)
A
Address Inputs
VDD
VSS
A0, A1
Burst Count Address
Ground
ADV
Burst Address Advance
Address Status Processor
Address Status Controller
Clock
Chip Select
Chip Select
N.C.
No Connect
ADSP
ADSC
CLK
CS1
CS2
DQa
DQb
DQc
DQd
Data Inputs/Outputs
Data Inputs/Outputs
Data Inputs/Outputs
Data Inputs/Outputs
Data Inputs/Outpus
WEx
Byte Write Inputs
DQPa~Pd
(x=a,b,c,d)
VDDQ
Output Power Supply
(2.5V or 3.3V)
OE
Output Enable
GW
BW
ZZ
Global Write Enable
Byte Write Enable
Power Down Input
Burst Mode Control
LBO
November 1999
Rev 5.0
- 5 -
KM736V887
KM718V987
256Kx36 & 512Kx18 Synchronous SRAM
119BGA PACKAGE PIN CONFIGURATIONS(TOP VIEW)
KM718V987(512Kx18)
1
2
A
3
A
4
ADSP
ADSC
VDD
NC
5
A
6
A
7
A
B
C
D
E
F
VDDQ
NC
VDDQ
NC
CS2
A
A
A
A
NC
A
A
A
NC
DQb
NC
NC
VSS
VSS
VSS
WEb
VSS
NC
VSS
VSS
VSS
VSS
VSS
LBO
A
VSS
VSS
VSS
VSS
VSS
NC
VSS
WEa
VSS
VSS
VSS
NC
A
DQPa
NC
DQa
NC
DQa
VDD
NC
DQa
NC
DQa
NC
A
NC
DQb
NC
CS1
OE
DQa
VDDQ
DQa
NC
VDDQ
NC
G
H
J
DQb
NC
ADV
GW
VDD
CLK
NC
DQb
VDDQ
NC
VDD
DQb
NC
VDDQ
DQa
NC
K
L
DQb
VDDQ
DQb
NC
M
N
P
R
T
DQb
NC
BW
A1*
VDDQ
NC
DQPb
A0*
DQa
NC
NC
VDD
NC
A
A
NC
A
ZZ
U
VDDQ
NC
NC
NC
NC
NC
VDDQ
Note : * A0 and A1 are the two least significant bits(LSB) of the address field and set the internal burst counter if burst is desired.
PIN NAME
SYMBOL
PIN NAME
SYMBOL
PIN NAME
Power Supply(+3.3V)
A
A0,A1
Address Inputs
VDD
VSS
Burst Count Address
Ground
ADV
Burst Address Advance
Address Status Processor
Address Status Controller
Clock
N.C.
No Connect
ADSP
ADSC
CLK
DQa
DQb
DQPa~Pb
Data Inputs/Outputs
Data Inputs/Outputs
Data Inputs/Outpus
CS1
Chip Select
CS2
Chip Select
WEx
(x=a,b)
Byte Write Inputs
VDDQ
Output Power Supply
(2.5V or 3.3V)
OE
Output Enable
GW
BW
ZZ
Global Write Enable
Byte Write Enable
Power Down Input
Burst Mode Control
LBO
November 1999
Rev 5.0
- 6 -
KM736V887
KM718V987
256Kx36 & 512Kx18 Synchronous SRAM
FUNCTION DESCRIPTION
The KM736V887 and KM718V987 are synchronous SRAM designed to support the burst address accessing sequence of the Power
PC based microprocessor. All inputs (with the exception of OE, LBO and ZZ) are sampled on rising clock edges. The start and dura-
tion of the burst access is controlled by ADSC, ADSP and ADV and chip select pins.
The accesses are enabled with the chip select signals and output enabled signals. Wait states are inserted into the access with
ADV.
When ZZ is pulled high, the SRAM will enter a Power Down State. At this time, internal state of the SRAM is preserved. When ZZ
returns to low, the SRAM normally operates after 2cycles of wake up time. ZZ pin is pulled down internally.
Read cycles are initiated with ADSP(or ADSC) using the new external address clocked into the on-chip address register when both
GW and BW are high or when BW is low and WEa, WEb, WEc, and WEd are high. When ADSP is sampled low, the chip selects are
sampled active, and the output buffer is enabled with OE. the data of cell array accessed by the current address are projected to the
output pins.
Write cycles are also initiated with ADSP(or ADSC) and are differentiated into two kinds of operations; All byte write operation and
individual byte write operation.
All byte write occurs by enabling GW(independent of BW and WEx.), and individual byte write is performed only when GW is high
and BW is low. In KM736V887, a 256Kx36 organization, WEa controls DQa0 ~ DQa7 and DQPa, WEb controls DQb0 ~ DQb7 and
DQPb, WEc controls DQc0 ~ DQc7 and DQPc and WEd controls DQd0 ~ DQd7 and DQPd.
CS1 is used to enable the device and conditions internal use of ADSP and is sampled only when a new external address is loaded.
ADV is ignored at the clock edge when ADSP is asserted, but can be sampled on the subsequent clock edges. The address
increases internally for the next access of the burst when ADV is sampled low.
Addresses are generated for the burst access as shown below, The starting point of the burst sequence is provided by the external
address. The burst address counter wraps around to its initial state upon completion. The burst sequence is determined by the state
of the LBO pin. When this pin is Low, linear burst sequence is selected. And this pin is High, Interleaved burst sequence is selected.
BURST SEQUENCE TABLE
(Interleaved Burst)
Case 4
Case 1
Case 2
Case 3
LBO PIN
HIGH
First Address
A1
A0
A1
A0
A1
A0
A1
A0
0
0
1
1
0
1
0
1
0
0
1
1
1
0
1
0
1
1
0
0
0
1
0
1
1
1
0
0
1
0
1
0
Fourth Address
BQ TABLE
(Linear Burst)
Case 1
Case 2
Case 3
Case 4
LBO PIN
LOW
First Address
A1
A0
A1
A0
A1
A0
A1
A0
0
0
1
1
0
1
0
1
0
1
1
0
1
0
1
0
1
1
0
0
0
1
0
1
1
0
0
1
1
0
1
0
Fourth Address
Note : 1. LBO pin must be tied to High or Low, and Floating State must not be allowed.
November 1999
Rev 5.0
- 7 -
KM736V887
KM718V987
256Kx36 & 512Kx18 Synchronous SRAM
TRUTH TABLES
SYNCHRONOUS TRUTH TABLE
CS1
H
L
CS2
X
L
CS2 ADSP ADSC ADV WRITE CLK
ADDRESS ACCESSED
N/A
OPERATION
Not Selected
X
X
H
X
H
L
X
L
L
X
X
L
X
X
X
X
X
X
X
X
L
X
X
X
X
X
X
L
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
N/A
Not Selected
L
X
L
L
N/A
Not Selected
L
X
X
L
N/A
Not Selected
L
X
H
H
H
X
X
X
X
X
X
X
X
L
N/A
Not Selected
L
X
L
External Address
External Address
External Address
Next Address
Next Address
Next Address
Next Address
Current Address
Current Address
Current Address
Current Address
Begin Burst Read Cycle
Begin Burst Write Cycle
Begin Burst Read Cycle
Continue Burst Read Cycle
Continue Burst Read Cycle
Continue Burst Write Cycle
Continue Burst Write Cycle
Suspend Burst Read Cycle
Suspend Burst Read Cycle
Suspend Burst Write Cycle
Suspend Burst Write Cycle
L
L
H
H
H
X
H
X
H
X
H
X
L
L
L
H
H
H
L
X
H
X
H
X
H
X
H
X
X
X
X
X
X
X
X
H
H
H
H
H
H
H
H
L
L
L
L
H
H
H
H
H
H
L
L
Notes : 1. X means "Don¢t Care".
2. The rising edge of clock is symbolized by • .
3. WRITE = L means Write operation in WRITE TRUTH TABLE.
WRITE = H means Read operation in WRITE TRUTH TABLE.
4. Operation finally depends on status of asynchronous input pins(ZZ and OE).
WRITE TRUTH TABLE( x36)
GW
H
BW
H
L
WEa
X
WEb
X
WEc
X
WEd
X
OPERATION
READ
H
H
H
H
H
READ
H
L
L
H
H
H
WRITE BYTE a
WRITE BYTE b
WRITE BYTE c and d
WRITE ALL BYTEs
WRITE ALL BYTEs
H
L
H
L
H
H
H
L
H
H
L
L
H
L
L
L
L
L
L
X
X
X
X
X
Notes : 1. X means "Don¢t Care".
2. All inputs in this table must meet setup and hold time around the rising edge of CLK(• ).
WRITE TRUTH TABLE(x18)
GW
H
BW
H
L
WEa
X
WEb
X
OPERATION
READ
H
H
H
READ
H
L
L
H
WRITE BYTE a
WRITE BYTE b
WRITE ALL BYTEs
WRITE ALL BYTEs
H
L
H
L
H
L
L
L
L
X
X
X
Notes : 1. X means "Don¢t Care".
2. All inputs in this table must meet setup and hold time around the rising edge of CLK(• ).
November 1999
Rev 5.0
- 8 -
KM736V887
KM718V987
256Kx36 & 512Kx18 Synchronous SRAM
ASYNCHRONOUS TRUTH TABLE
Operation
ZZ
H
L
OE
X
I/O STATUS
Notes
Sleep Mode
High-Z
DQ
1. X means "Don¢t Care".
2. ZZ pin is pulled down internally
3. For write cycles that following read cycles, the output buffers must be
disabled with OE, otherwise data bus contention will occur.
4. Sleep Mode means power down state of which stand-by current does
not depend on cycle time.
L
Read
L
H
X
High-Z
Write
L
Din, High-Z
High-Z
5. Deselected means power down state of which stand-by current
depends on cycle time.
Deselected
L
X
ABSOLUTE MAXIMUM RATINGS*
PARAMETER
Voltage on VDD Supply Relative to VSS
Voltage on VDDQ Supply Relative to VSS
Voltage on Input Pin Relative to VSS
Voltage on I/O Pin Relative to VSS
Power Dissipation
SYMBOL
VDD
RATING
-0.3 to 4.6
VDD
UNIT
V
VDDQ
VIN
V
-0.3 to 4.6
-0.3 to VDDQ+0.5
1.4
V
VIO
V
PD
W
°C
°C
°C
Storage Temperature
TSTG
TOPR
TBIAS
-65 to 150
0 to 70
Operating Temperature
Storage Temperature Range Under Bias
-10 to 85
*Notes : Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only
and functional operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not
implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
OPERATING CONDITIONS at 3.3V I/O(0°C £ TA £ 70°C)
PARAMETER
Supply Voltage
Ground
SYMBOL
VDD
MIN
3.135
3.135
0
Typ.
3.3
3.3
0
MAX
3.465
3.465
0
UNIT
V
V
V
VDDQ
VSS
OPERATING CONDITIONS at 2.5V I/O(0°C £ TA £ 70°C)
PARAMETER
Supply Voltage
Ground
SYMBOL
VDD
MIN
3.135
2.375
0
Typ.
3.3
2.5
0
MAX
3.465
2.9
UNIT
V
V
V
VDDQ
VSS
0
CAPACITANCE*(TA=25°C, f=1MHz)
PARAMETER
Input Capacitance
SYMBOL
TEST CONDITION
VIN=0V
MIN
MAX
UNIT
CIN
-
-
6
8
pF
pF
Output Capacitance
COUT
VOUT=0V
*Note : Sampled not 100% tested.
November 1999
Rev 5.0
- 9 -
KM736V887
KM718V987
256Kx36 & 512Kx18 Synchronous SRAM
DC ELECTRICAL CHARACTERISTICS(VDD=3.3V+0.165V/-0.165V, TA=0°C to +70°C)
Parameter
Symbol
Test Conditions
VDD=Max ; VIN=VSS to VDD
Min
Max
+2
Unit
mA
Notes
Input Leakage Current(except ZZ)
Output Leakage Current
IIL
-2
-2
-
IOL
Output Disabled, Vout=VSS to VDDQ
+2
mA
-7
-8
350
330
300
260
140
130
120
120
-
Device Selected, IOUT=0mA,
Operating Current
ICC
ISB
mA
mA
1,2
ZZ£VIL , Cycle Time ³ tCYC Min
-9
-
-10
-7
-
-
Device deselected, IOUT=0mA,
ZZ£VIL, f=Max, All Inputs£0.2V or
³ VDD-0.2V
-8
-
-9
-
-10
-
Standby Current
Device deselected, IOUT=0mA, ZZ£0.2V, f=0,
ISB1
ISB2
-
-
30
30
mA
mA
All Inputs=fixed (VDD-0.2V or 0.2V)
Device deselected, IOUT=0mA, ZZ³ VDD-0.2V,
f=Max, All Inputs£VIL or ³ VIH
Output Low Voltage(3.3V I/O)
Output High Voltage(3.3V I/O)
Output Low Voltage(2.5V I/O)
Output High Voltage(2.5V I/O)
Input Low Voltage(3.3V I/O)
Input High Voltage(3.3V I/O)
Input Low Voltage(2.5V I/O)
Input High Voltage(2.5V I/O)
VOL
VOH
VOL
VOH
VIL
IOL=8.0mA
IOH=-4.0mA
IOL=1.0mA
IOH=-1.0mA
-
0.4
V
V
V
V
V
V
V
V
2.4
-
-
0.4
-
2.0
-0.3*
2.0
-0.3*
1.7
0.8
VIH
VDD+0.5**
0.7
3
3
VIL
VIH
VDD+0.5**
Notes : 1. Reference AC Operating Conditions and Characteristics for input and timing.
2. Data states are all zero.
3. In Case of I/O Pins, the Max. VIH=VDDQ+0.3V
VIH
VSS
VSS-1.0V
20% tCYC(MIN)
TEST CONDITIONS
(VDD=3.3V+0.165V/-0.165V,VDDQ=3.3V+0.165/-0.165V or VDD=3.3V+0.165V/-0.165V,VDDQ=2.5V+0.4V/-0.125V, TA=0to70°C)
PARAMETER
VALUE
0 to 3.0V
0 to 2.5V
1.0V/ns
1.0V/ns
1.5V
Input Pulse Level(for 3.3V I/O)
Input Pulse Level(for 2.5V I/O)
Input Rise and Fall Time(Measured at 20% to 80% for 3.3V I/O)
Input Rise and Fall Time(Measured at 20% to 80% for 2.5V I/O)
Input and Output Timing Reference Levels for 3.3V I/O
Input and Output Timing Reference Levels for 2.5V I/O
Output Load
VDDQ/2
See Fig. 1
November 1999
Rev 5.0
- 10 -
KM736V887
KM718V987
256Kx36 & 512Kx18 Synchronous SRAM
Output Load(A)
Output Load(B),
(for tLZC, tLZOE, tHZOE & tHZC)
+3.3V for 3.3V I/O
/+2.5V for 2.5V I/O
RL=50W
Dout
VL=1.5V for 3.3V I/O
319W / 1667W
VDDQ/2 for 2.5V I/O
30pF*
Dout
Zo=50W
353W / 1538W
5pF*
* Including Scope and Jig Capacitance
Fig. 1
AC TIMING CHARACTERISTICS(VDD=3.3V+0.165V/-0.165V, TA=0°C to +70°C)
-7
-8
-9
-10
PARAMETER
SYMBOL
UNIT
MIN
8.5
-
MAX
MIN
10
-
MAX
MIN
10
-
MAX
MIN
12
-
MAX
Cycle Time
tCYC
tCD
-
-
-
-
ns
ns
Clock Access Time
7.5
8.5
9.0
10
Output Enable to Data Valid
tOE
-
3.5
-
3.5
-
3.5
-
3.5
ns
Clock High to Output Low-Z
tLZC
tOH
2.5
2.5
0
-
2.5
2.5
0
-
2.5
2.5
0
-
2.5
2.5
0
-
ns
Output Hold from Clock High
Output Enable Low to Output Low-Z
Output Enable High to Output High-Z
Clock High to Output High-Z
Clock High Pulse Width
-
-
-
-
ns
tLZOE
tHZOE
tHZC
tCH
-
-
-
-
ns
ns
-
3.5
-
3.5
-
3.5
-
4.0
-
4.0
-
-
5.0
-
-
5.0
-
-
6.0
-
ns
2.5
2.5
2.0
2.0
2.0
2.0
2.0
2.0
0.5
0.5
0.5
0.5
0.5
0.5
2
3.0
3.0
2.0
2.0
2.0
2.0
2.0
2.0
0.5
0.5
0.5
0.5
0.5
0.5
2
3.0
3.0
2.0
2.0
2.0
2.0
2.0
2.0
0.5
0.5
0.5
0.5
0.5
0.5
2
3.0
3.0
2.0
2.0
2.0
2.0
2.0
2.0
0.5
0.5
0.5
0.5
0.5
0.5
2
ns
Clock Low Pulse Width
tCL
-
-
-
-
ns
Address Setup to Clock High
Address Status Setup to Clock High
Data Setup to Clock High
tAS
-
-
-
-
ns
tSS
-
-
-
-
ns
tDS
-
-
-
-
ns
Write Setup to Clock High (GW, BW, WEX)
Address Advance Setup to Clock High
Chip Select Setup to Clock High
Address Hold from Clock High
Address Status Hold from Clock High
Data Hold from Clock High
tWS
-
-
-
-
ns
tADVS
tCSS
tAH
-
-
-
-
ns
-
-
-
-
ns
-
-
-
-
ns
tSH
-
-
-
-
ns
tDH
-
-
-
-
ns
Write Hold from Clock High (GW, BW, WEX)
Address Advance Hold from Clock High
Chip Select Hold from Clock High
ZZ High to Power Down
tWH
tADVH
tCSH
tPDS
tPUS
-
-
-
-
ns
-
-
-
-
ns
-
-
-
-
ns
-
-
-
-
cycle
cycle
ZZ Low to Power Up
2
-
2
-
2
-
2
-
Notes : 1. All address inputs must meet the specified setup and hold times for all rising clock edges whenever ADSC and/or ADSP is sampled low and
CS is sampled low. All other synchronous inputs must meet the specified setup and hold times whenever this device is chip selected.
2. Both chip selects must be active whenever ADSC or ADSP is sampled low in order for the this device to remain enabled.
3. ADSC or ADSP must not be asserted for at least 2 Clock after leaving ZZ state.
November 1999
- 11 -
Rev 5.0
KM736V887
KM718V987
256Kx36 & 512Kx18 Synchronous SRAM
November 1999
- 12 -
Rev 5.0
KM736V887
KM718V987
256Kx36 & 512Kx18 Synchronous SRAM
November 1999
- 13 -
Rev 5.0
KM736V887
KM718V987
256Kx36 & 512Kx18 Synchronous SRAM
November 1999
- 14 -
Rev 5.0
KM736V887
KM718V987
256Kx36 & 512Kx18 Synchronous SRAM
November 1999
- 15 -
Rev 5.0
KM736V887
KM718V987
256Kx36 & 512Kx18 Synchronous SRAM
November 1999
- 16 -
Rev 5.0
KM736V887
KM718V987
256Kx36 & 512Kx18 Synchronous SRAM
November 1999
- 17 -
Rev 5.0
KM736V887
KM718V987
256Kx36 & 512Kx18 Synchronous SRAM
APPLICATION INFORMATION
DEPTH EXPANSION
The Samsung 256Kx36 Synchronous Burst SRAM has two additional chip selects for simple depth expansion.
This permits easy secondary cache upgrades from 256K depth to 512K depth without extra logic.
I/O[0:71]
Data
Address
A[0:18]
A[18]
A[0:17]
A[18]
A[0:17]
Address Data
CS
CS
Address Data
CS
CS
CLK
2
2
2
2
256Kx36
SB
SRAM
CLK
ADSC
WEx
OE
256Kx36
SB
SRAM
CLK
ADSC
WEx
OE
Microprocessor
Address
CLK
(Bank 0)
(Bank 1)
Cache
Controller
CS1
CS1
ADV ADSP
ADV ADSP
ADS
INTERLEAVE READ TIMING (Refer to non-interleave write timing for interleave write timing)
(ADSP CONTROLLED , ADSC=HIGH)
CLOCK
tSS
tSH
ADSP
tAS
tAH
A1
A2
ADDRESS
[0:n]
tWS
tWH
WRITE
CS1
tCSS
tCSH
Bank 0 is selected by CS2, and Bank 1 deselected by CS2
An+1
ADV
OE
Bank 0 is deselected by CS2, and Bank 1 selected by CS2
tADVS
tADVH
tOE
tLZOE
tHZC
Data Out
(Bank 0)
Q1-1
Q1-2
Q1-3
Q1-4
tCD
tLZC
Data Out
(Bank 1)
Q2-1
Q2-2
Q2-3
Q2-4
Don¢t Care
*Notes : n = 14 32K depth ,
15 64K depth
16 128K depth , 17 256K depth
18 512K depth
Undefined
November 1999
Rev 5.0
- 18 -
KM736V887
KM718V987
256Kx36 & 512Kx18 Synchronous SRAM
APPLICATION INFORMATION
DEPTH EXPANSION
The Samsung 512Kx18 Synchronous Burst SRAM has two additional chip selects for simple depth expansion.
This permits easy secondary cache upgrades from 512K depth to 1M depth without extra logic.
I/O[0:71]
Data
Address
A[19]
A[19]
A[0:18]
A[0:18]
A[0:19]
Address Data
Address Data
CS
CS
CLK
2
CS2
2
CS2
Microprocessor
512Kx18
SB
SRAM
CLK
ADSC
WEx
OE
512Kx18
SB
SRAM
CLK
ADSC
WEx
OE
Address
CLK
(Bank 0)
(Bank 1)
Cache
Controller
CS
1
CS1
ADV ADSP
ADV ADSP
ADS
INTERLEAVE READ TIMING (Refer to non-interleave write timing for interleave write timing)
(ADSP CONTROLLED , ADSC=HIGH)
CLOCK
tSS
tSH
ADSP
tAS
tAH
A1
A2
ADDRESS
[0:n]
tWS
tWH
WRITE
CS1
tCSS
tCSH
Bank 0 is selected by CS2, and Bank 1 deselected by CS2
An+1
ADV
OE
Bank 0 is deselected by CS2, and Bank 1 selected by CS2
tADVS
tADVH
tOE
tLZOE
tHZC
Data Out
(Bank 0)
Q1-1
Q1-2
Q1-3
Q1-4
tCD
tLZC
Data Out
(Bank 1)
Q2-1
Q2-2
Q2-3
Q2-4
Don¢t Care
*Notes : n = 14 32K depth ,
15 64K depth
16 128K depth , 17 256K depth
18 512K depth , 19 1M depth
Undefined
November 1999
Rev 5.0
- 19 -
KM736V887
KM718V987
256Kx36 & 512Kx18 Synchronous SRAM
PACKAGE DIMENSIONS
100-TQFP-1420A
Units ; millimeters/Inches
22.00 ±0.30
20.00 ±0.20
0~8°
+ 0.10
- 0.05
0.127
16.00 ±0.30
0.10 MAX
14.00 ±0.20
(0.83)
0.50 ±0.10
#1
0.65
(0.58)
0.30 ±0.10
0.10 MAX
1.40 ±0.10
1.60 MAX
0.05 MIN
0.50 ±0.10
November 1999
Rev 5.0
- 20 -
KM736V887
KM718V987
256Kx36 & 512Kx18 Synchronous SRAM
119BGA PACKAGE DIMENSIONS
1.27
1.27
14.00±0.10
22.00±0.10
Indicator of
Ball(1A) Location
20.50±0.10
C0.70
C1.00
0.750±0.15
1.50REF
0.60±0.10
0.60±0.10
NOTE :
1. All Dimensions are in Millimeters.
2. Solder Ball to PCB Offset : 0.10 MAX.
3. PCB to Cavity Offset : 0.10 MAX.
12.50±0.10
November 1999
- 21 -
Rev 5.0
相关型号：
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